Accelerating Redisedge with CCIX Jeff Defilippi Director Product Management Arm

Accelerating RedisEdge with CCIX Jeff Defilippi Director Product Management Arm

Massive Amounts 5G of Data Critical Data Edge Trillions Cloud Data Edge Centers of Devices Edge

Analyze & Store Filter & React Local Decisions

Latency Requirements for Emerging Applications Robotics / Medical V2X Control Smart City, IoT Control 2.2ms 10ms 15-20ms

300 All Internet Data 250 278

228 200 186 150 151

EXABYTES/MONTH 100 122 96

0 2016 2017 2018 2019 2020 2021

Source: Cisco Visual Networking Index 2016-2021

300

250

200 208 CDN + Managed IP services 150 166 133 EXABYTES/MONTH 100 104 81 61 50 Remaining bandwidth (to Cloud) 35 41 47 54 63 70 0 2016 2017 2018 2019 2020 2021

500M HD image sensors 329EB/ 300 month

250

200 208 Visual positioning – 150 166 100M driving hrs/day 133 6EB/month EXABYTES/MONTH 100 104 81 Voice UI for 61 50 50% of cellphone subscribers – 35 41 47 54 63 70 1EB/month 0 2016 2017 2018 2019 2020 2021

…….Faster and faster general-purpose compute used to be good enough for all workloads…

general purpose compute

…….Faster and faster general-purpose compute used to be good enough for all workloads…

general purpose network storage security ml/ai graphics compute ... … heterogenous, intelligent & optimized compute is the only way to keep up

Cloud native deployments Edge

Stack Engines

Multi-tenancy, virtualized, secured Analytics

SQL/NoSQL Data

Network Services Network

Network PredictionNetwork Filter / React / / React Store Filter/

Containers / Hypervisor Diverse, heterogenous systems HW Acceleration

RUNTIME SECURITY SERVICESSECURITY RUNTIME Arm Neoverse Platform

Root of Trust Arm PSA

Redis high performance, fast in-memory database • <1ms latency for real-time processing Redis with Streams + Modules • RedisTimeSeries, RedisAI, RedisGears

Tunable data persistence • Ensure recovery of critical data Small footprint • <5MB for resource constrained deployments (<8 cores)

https://github.com/RedisGears/EdgeRealtimeVideoAnalytics

Hyperscale Edge Edge Datacenter Compute Access

150W and beyond 35W-105W 15W-65W 64-128 core 16-64 core 8-32 core

Neoverse N1 offers hyperscale performance with industry leading power/area efficiency for more applications

4x Neoverse N1 CPUs at speeds up to 3 GHz Cutting-edge TSMC 7nm manufacturing process Silicon interoperability proof of N1 platform with Cadence’s PCIe/CCIX Gen4/3 and DDR4/3 IP Demonstrate performant cache-coherent integration of accelerators using Xilinx’s Alveo (U280) CCIX accelerator card Benchmark performance of cloud-native workloads and optimize open-source software

Application Processor software Compute Subsystem Supervisory firmware

Distro & grub Secure Partition Application Supervisory SCP firmware bootloader Under development CPUs compute (Cortex-M) Open Source firmware for N1SDP for system initialization Linux Kernel power control and SCP UEFI/EDK2 MCP Firmware MCP SoC level system management Trusted Firmware-A SoC (Interconnect, IO) • Open source firmware for CPU initialization & system management • Secure runtime interface

https://community.arm.com/developer/tools-software/oss-platforms/w/docs/440/neoverse-n1-sdp

16nm Cloud Deployable UltraScale™ Architecture

Off-Chip Memory Support Cloud ↔ On-Premise • Max Capacity: 8GB Mobility • Max Bandwidth: 460 GB/s

Ecosystem of Applications Internal SRAM • Many available today • Max Capacity: 43MB • More on the way • Max Bandwidth: 37TB/s

PCIe Gen3x16, Gen4x8, Server OEM Support • Major OEMs in Qualification CCIX

Accelerate Any Application • IDE for compiling, debugging, profiling • Supports C/C++, RTL, and OpenCL

Cache Coherent Interface for Xcellerators (CCIX)

• Accelerates heterogeneous computing • Builds on PCIe standard and infrastructure • Adds cache coherency protocol

Supports PCIe Gen 4.0 (16GT/s) and Gen 5.0 (32GT/s)

• Includes intermediate speeds, 20GT/s, 25GT/s

Processor Processor

Processor CCIX CCIX Processor Processor

CCIX CCIX CCIX CCIX CCIX CCIX CCIX

Switch Accel Accel

CCIX CCIX

CCIX CCIX CCIX CCIX CCIX CCIX Accelerator Memory

Accelerator Memory CCIX CCIX

CCIX CCIX

Accel Accel

Direct attached, daisy chain, mesh and switched topologies

CCIX CCIX CCIX CCIX

SW DMA Engine: Clean and copy data PCIe != on-chip Processor Require software to move data Accelerator CPU CPU PCIe Special driver for each accelerator On-chip bus System Bus CPU CPU Requires skilled kernel developers Private Accel Memory Long term maintenance required Memory

OS Virtual Memory Reduced ability to leverage high level languages and tools

Shared Virtual Memory

‘Driverless’ model, it’s all memory Processor Accelerator CPU CPU CCIX On-chip = multichip

On-chip bus Cache Eliminates bespoke DMA driver CPU CPU

Enables, cache coherent fine grain Accel Memory data sharing Memory

Shared Data Structures

Access to CCIX resources from virtual Guest App Guest App machines and containers CCIX VF0 CCIX CCIX Guest VMs/ VF1 VF2 Containers Capable of creating CCIX Virtual Functions (VF) in any SW language Hypervisor

Simple R/W access to any memory region CCIX ext PCIe SW Model OS Kernel

Processor Mem Accel Mem

CCIX: Cache Coherent Interface for Xccelerators

• Symmetrical coherency for scale-up and heterogeneous compute-to-compute

• Ability to create a network of coherent devices enabled devices (tree, mesh, etc)

• Accelerator-to-accelerator data movement CXL: Compute Express Link

• CXL 1.1 specification available, built on PCIe Gen5

• Simple, asymmetrical coherency model

• Focus on accelerator and memory attach to server compute Arm investment within CCIX and CXL

• Focus on enabling innovation for emerging use-cases and workloads • Unify the software stack between CCIX and CXL • Support PCIe, CCIX, CXL on Neoverse CMN IP for both server and accelerator SoC designs

Time RedisEdge = Redis + Streams + + AI + Gears Series

1. Persistent memory expansion

2. Acceleration function offload

Periodic back-up (every second) of a log file (AOF) and checkpoint file (RDB) 2 Redis database application Arm N1 SDP

works out of memory SSD PCIe 1 3 DDR Memory If crash occurs, database is restored and rebuilt

Replace SSD with CCIX persistent memory

Arm N1 SDP Xilinx U280 2x better performance by eliminate

processing for log/checkpoint

CCIX CCIX

No risk of critical data loss DDR Memory 1 PMEM

Application works directly on Instantaneous restart NVMe PMEM

Off-line acceleration - regression, analytics, etc Add in-line or off-line custom acceleration to offload critical CPU cycles Arm N1 SDP Xilinx U280

2 CCIX In-line acceleration: add on the path to CCIX memory such as crypto and compression 1

DDR Memory PMEM Off-line acceleration: add an off-line module that runs directly on the accelerator In-line acceleration - crypto, compression, etc

Support for both event driven and batch operations

Develop routines in C or Python

Port modules to accelerator without kernel changes • On-chip or off-chip accelerators

Arm N1 SDP Xilinx U280

CCIX CCIX

DDR Memory PMEM

RedisEdge: purpose-built data service platform for the AI edge

Arm Neoverse N1: secure, hyperscale compute in edge power budget

Xilinx Alveo U280: accelerate any workload

CCIX: seamless, driverless, efficient data movement

Copyright © 2019 Arm TechCon, All rights reserved. 33 Trademark and copyright statement The trademarks featured in this presentation are Thank You! registered and/or unregistered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners.