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Dissertation Matthias Klein
Beschreibung der Modellbildung des Thermokompressions-Bondvorganges an galvanisch abgeschiedenen Strukturen vorgelegt von Diplom-Physiker Matthias Klein aus Lübeck von der Fakultät IV – Elektrotechnik und Informatik der Technischen Universität Berlin zur Erlangung des akademischen Grades Doktor der Ingenieurwissenschaften - Dr.-Ing.- genehmigte Dissertation Promotionsausschuss: Vorsitzender: Prof. Dr.-Ing. H. Klar Berichter: Prof. Dr.-Ing. Dr.-Ing. E.h. H. Reichl Berichter: Prof. Dr.-Ing. M. Nowottnick Tag der wissenschaftlichen Aussprache: 19.11.2010 Berlin 2010 D 83 ii Zusammenfassung Das Thermokompressions-Bonden ist ein Kontaktierungsverfahren der Aufbau- und Verbindungs- technik für die Mikroelektronik. Es findet hauptsächlich beim Flip-Chip-, TAB- und Wafer-zu- Wafer-Bonden Anwendung. Obwohl das TC-Bonden vielfältig genutzt wird, ist die Wirkungs- weise der Bondparameter Druck und Temperatur und der Mechanismus der Verbindungsbildung unter Einbeziehung der Bumpgeometrie bisher nur unzureichend analysiert worden. In dieser Ar- beit wurden daher erstmals umfangreiche Untersuchungen zum TC-Bonden auf Basis galvanisch abgeschiedener Goldkontakte für die Flip-Chip-Kontaktierung durchgeführt. Die beim Bonden in der Verbindungszone auftretenden Verschiebungen der zwei Goldflächen zueinander wurden detailliert untersucht. Diese Verschiebungen konnten als notwendige Voraussetzung für eine Ver- bindungsbildung identifiziert werden, da sie zu einem Aufreißen der Kontaminationsschichten auf den Goldoberflächen führen. Erst durch diese partielle, im Randbereich der Kontakte auftretende Reinigung der Goldoberflächen kann eine Interdiffusion der dann reinen Metallflächen erfolgen. Eine thermo-mechanische Simulation des TC-Bondens wurde durchgeführt, um die Verschie- bungen der Goldoberflächen in der Verbindungszone zu bestimmen. Es zeigte sich, dass sich die Breite dieser Zone proportional zur Höhe des Goldkontaktes im Ausgangszustand verhält. In der Folge ist die Scherfestigkeit, die beim TC-Bonden erzielt wird, abhängig vom Aspektverhältnis des Kontaktes im Ausgangszustand. -
A Comparative Simulation Study of 3D Through Silicon Stack Assembly Processes
2013 IEEE 63rd Electronic Components and Technology Conference (ECTC 2013) Las Vegas, Nevada, USA 28 – 31 May 2013 Pages 1-806 IEEE Catalog Number: CFP13ECT-POD ISBN: 978-1-4799-0233-0 1/3 TABLE OF CONTENTS 0: Modeling and Simulation Challenges in 3D Systems Chairs: Yong Liu, Fairchild Semiconductor Dan Oh, Altera A Comparative Simulation Study of 3D Through Silicon Stack Assembly Processes ............................ 1 Kamal Karimanal, Cielution LLC Thermo Mechanical Challenges for Processing and Packaging Stacked Ultrathin Wafers .................... 7 Mario Gonzalez, IMEC; Bart Vandevelde, IMEC; Antonio La Manna, IMEC; Bart Swinnen, IMEC; Eric Beyne, IMEC Signal and Power Integrity Analysis of a 256-GB/s Double-Sided IC Package with a Memory Controller and 3D Stacked DRAM ....................................................................................... 13 Wendemagegnehu Beyene, Rambus, Inc.; Hai Lan, Rambus, Inc.; Scott Best, Rambus, Inc.; David Secker, Rambus, Inc.; Don Mullen, Rambus, Inc.; Ming Li, Rambus, Inc.; Tom Giovannini, Rambus, Inc. Optimization of 3D Stack for Electrical and Thermal Integrity ................................................................... 22 Rishik Bazaz, Georgia Institute of Technology; Jianyong Xie, Georgia Institute of Technology; Madhavan Swaminathan, Georgia Institute of Technology 1: 3D Assembly and Reliability Chairs: John Knickerbocker, IBM Corporation Sam Karikalan, Broadcom Corporation Reliability Studies on Micro-Bumps for 3-D TSV Integration .................................................................... -
Sponsored By: Supported By: Welcome from the Mayor of Las Vegas
Sponsored by: Supported by: Welcome from the Mayor of Las Vegas 2 WELCOME FROM ECTC GENERAL AND PROGRAM CHAIRS On behalf of the Program Committee and Executive Committee, it is my pleasure to welcome you to the 63rd Electronic Components and Technology Conference (ECTC) at The Cosmopolitan of Las Vegas, Nevada, USA. This premier international conference is sponsored by the IEEE Components, Packaging and Manufacturing Technology Society (CPMT). The ECTC Program Committee represents a wide range of disciplines and expertise from the electronics industry around the world. We have selected more than 300 high-quality papers to be presented at the conference in 36 oral sessions, four interactive presentation sessions, and one student posters session. The 36 oral sessions cover papers on 3D/TSV, embedded devices, LEDs, Co-Design, RF packaging, and electrical and mechanical modeling, in addition to topics such as advanced packaging technologies, all types and levels of interconnections, materials, assembly manufacturing, system packaging, optoelectronics, reliability, MEMS, and sensors. The program committee strives to address new trends as well as ongoing technological challenges. Four Interactive Presentation sessions feature technical presentations in a format that enhances and encourages interaction. One student poster session focuses on research conducted in academia presented by the emerging scientists. Authors from companies, research institutes, and universities from over 25 countries will present at the ECTC, making it a truly diverse and global conference. In addition to the technical sessions, panel and special sessions focusing on crucial topics presented by industry experts enhance the technical program. In the special session titled “The Role of Wafer Foundries in Next Generation Packaging,” held Tuesday, May 28, at 10 a.m., session chair Sam Karikalan will gather a panel of experts to present and discuss their proposed business models and strategies for embracing the next generation packaging needs of the industry. -
Reliable Fine-Pitch Chip-To-Substrate Copper Interconnections with High-Throughput Assembly and High Power-Handling
RELIABLE FINE-PITCH CHIP-TO-SUBSTRATE COPPER INTERCONNECTIONS WITH HIGH-THROUGHPUT ASSEMBLY AND HIGH POWER-HANDLING A Dissertation Presented to The Academic Faculty by Ninad Makarand Shahane In Partial Fulfillment of the Requirements for the Degree Doctorate of Philosophy in the School of Material Science and Engineering Georgia Institute of Technology August 2018 COPYRIGHT © 2018 BY NINAD MAKARAND SHAHANE RELIABLE FINE-PITCH CHIP-TO-SUBSTRATE COPPER INTERCONNECTIONS WITH HIGH-THROUGHPUT ASSEMBLY AND HIGH POWER-HANDLING Approved by: Dr. Rao R. Tummala, Advisor Dr. Pulugurtha Raj Markondeya School of Electrical and Computer School of Electrical and Computer Engineering Engineering Georgia Institute of Technology Georgia Institute of Technology Dr. Antonia Antoniou, Co-Advisor Dr. Preet Singh School of Mechanical Engineering School of Material Science Engineering Georgia Institute of Technology Georgia Institute of Technology Dr. Naresh Thadhani Dr. Vanessa Smet School of Material Science Engineering School of Electrical and Computer Georgia Institute of Technology Engineering Georgia Institute of Technology Date Approved: June 18, 2018 Dedicated to my parents, Makarand and Seema And to my love, Damini ACKNOWLEDGEMENTS I would like to express my sincere gratitude to my advisor, Professor Rao R. Tummala for his vision and ambition, his close guidance towards interdisciplinary research, and for providing extraordinary opportunities of close cooperation with industry partners. I would also like to thank my co-advisor Prof. Antonia Antoniou for exceptional guidance. Her constant push towards deep scientific inquiry encouraged and inspired me towards completing this Ph.D. thesis. I also thank my committee members, Professor Naresh Thadhani, Professor Preet Singh, Dr. Vanessa Smet and Dr. -
Integrated Power Electronic Module
International Journal of Electrical and Electronics Engineers ISSN- 2321-2055 (E) http://www.arresearchpublication.com IJEEE, Vol. No.6, Issue No. 02, July-Dec., 2014 INTEGRATED POWER ELECTRONIC MODULE Hansa Gupta EEE, Department, Kurukshetra University, (India) ABSTRACT IPEM(Integrated Power Electronic Module) targets to develop a packaging technology which provides three- dimensional planar packaging including a unique package resistance, better thermal transfer, lower parasitic problem and ultra-fast switching performance which is the major problem faced in creating a electronic circuit contains IGBT, MOSFET , SOD etc (Power electronic devices) . It also meets the increased requirements towards ampacity and heat dissipation, Increasing power levels and power density for multiple end products, not only in new but also in already established packages. It overcome the given package limitations and provides an easy way to cool the devices and to connect them to the outer circuit. It provides a very compact and efficient way to design an electronic circuit. Keyword: IPEM, IGBT, MOSFET, DCB, PCB I. INTRODUCTION The fundamental approach to power conversion has steadily moved toward high-frequency synthesis resulting in important reductions in converter performance, size, weight and cost. However, in some high frequency power conversion technologies ,fundamental limits are being reached that will not be overcome without a radical change in the design and implementation of power electronics systems. It is well recognized within the industrial sector that the performance of power electronics systems were driven by improvements in semiconductor components over the last decades. Moving from bipolar to MOSFET technology has resulted in speed increases that, today, test the limits of packaging inductance and thermal handling. -
Parts, Materials, and Processes Experience Summary
NASA SP-6507 PARTS, MATERIALS, AND PROCESSES EXPERIENCE SUMMARY Volume II NATIONAL AERONAUTICS AND SPACE ADMINISTRATION NASA SP-6507 PARTS, MATERIALS, * • .-! ' AND PROCESSES EXPERIENCE SUMMARY Volume II Prepared under contract for NASA by Lockheed Missiles & Space Company Scientific and Technical Information Office 1973 NATIONAL AERONAUTICS AND SPACE ADMINISTRATION Washington, D.C. For sale by the National Technical Information Service Springfield, Virginia 22151 Price - Domestic, $5.25; Foreign, $7.75 FOREWORD Scientific and engineering organizations within the National Aeronautics and Space Administration, the Department of Defense, and throughout the aerospace industry are greatly concerned about the impact of system failures related to parts, materials, and processes. Establishment of the NASA ALERT reporting program in 1964, expanded in 1968 to include participants of the Government-Industry Data Exchange Program (GIDEP), provided the means for sharing and benefiting from each other's experience with these types of failures. Extensive data accumulated from ALERT reports have proved a valuable method of communicating problems and providing assistance in avoiding or minimizing recurrences. In order that this accumulated experience be made readily available, this publication, Parts, Materials, and Processes Experience Summary, condenses and catalogs ALERT and other information on basic design, reliability, quality and application, problems. Designers, engineers, failure analysts and other reliability and quality personnel will find the answers to many application and problem-avoidance questions. This publication was developed under contract NAS2-6060 by the Lockheed Missiles & Space Company, Inc., Sunnyvale, Calif., under the leadership of W.L. Finch, W. Geller, and S. Ognibene. The contract was administered under the technical direction of NASA's Ames Research Center, Moffett Field, Calif., with G.E.