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0784085 Patrickdeenen Eindhoven University of Technology MASTER Optimizing wafer allocation for back-end semiconductor production Deenen, Patrick C. Award date: 2018 Link to publication Disclaimer This document contains a student thesis (bachelor's or master's), as authored by a student at Eindhoven University of Technology. Student theses are made available in the TU/e repository upon obtaining the required degree. The grade received is not published on the document as presented in the repository. The required complexity or quality of research of student theses may vary by program, and the required minimum study period may vary in duration. General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain Manufacturing Systems Engineering Department of Mechanical Engineering De Rondom 70, 5612 AP Eindhoven P.O. Box 513, 5600 MB Eindhoven The Netherlands www.tue.nl Author P.C. Deenen Optimizing wafer allocation for 0784085 back-end semiconductor production Committee members I.J.B.F. Adan A.E. Akçay C.A.J. Hurkens DC 2018.101 Master Thesis Report Company supervisors J. Adan J. Stokkermans Date November 29, 2018 Where innovation starts Optimizing wafer allocation for back-end semiconductor production Patrick Deenena,b,∗ aEindhoven University of Technology, Department of Mechanical Engineering, Eindhoven, The Netherlands bNexperia, Industrial Technology and Engineering Centre, Nijmegen, The Netherlands Abstract This paper discusses the development of an efficient and practical algorithm that minimizes overproduction in the allocation of wafers to customer orders prior to assembly at a semiconductor production facility. This study is motivated by and tested on Nexperia's assembly and test facilities, but its potential applications extend to many manufacturers in the semiconductor industry. The problem that is considered in this paper, has an additional element that has not been taken into account in previous studies. That is, there are some wafers which contain dies with different electrical properties, used for multiple different end products. Inspired by the classic bin covering problem, the wafer allocation problem is formulated as multiple integer linear programs (ILPs). A novel heuristic is proposed, referred to as the multi-start swap algorithm, which is compared to current practice, other existing heuristics and a commercial optimization solver. Experi- ments show that the proposed solution method significantly outperforms current practice and other existing heuristics, and that the overall performance is generally close to optimal. Furthermore, some data processing steps and heuristics are presented to make the ILPs applicable to the real-world application at Nexperia and able to interact with other stages of the existing back-end scheduling environment. Keywords: Wafer allocation, production planning, lot-to-order matching, bin covering, integer linear programming, heuristic, semiconductor 1. Introduction This research is motivated by the problem of allocating semiconductor wafers to customer orders in the back-end production process of integrated circuits (ICs) at Nexperia's assembly and test facilities. The back- end sites work with a make-to-order policy, in which customer orders have to be made with wafers which are stored in a warehouse waiting to be assembled. It is a challenging task to allocate these wafers to the orders prior to assembly. An inadequate allocation will cause more produced finished goods than requested by the customer orders, i.e. overproduction. This overproduction has a severe impact on the company's profit, since it will consume more expensive material, produce excess inventory and occupy manufacturing machines longer. Thus, in the $412.2 billion semiconductor industry1, which is still growing every year, improving the wafer allocation process to minimize overproduction, is highly valuable. The reader is referred to Frederix and Florent [2] for an elaborate overview of the manufacturing process of ICs, but it can basically be divided into the following four steps. The first one is wafer fabrication, where many ICs are fabricated on a blank disk of semiconducting material (such as silicon) using photo-lithography techniques. A single IC on a wafer is called a die. The second step is wafer testing, where the dies are probed on their electrical properties and can be identified as a good or bad die. For some wafer types, the good dies are also categorized in different classes based on their quality. The first two steps, wafer fabrication ∗Corresponding author Email address: [email protected] (Patrick Deenen) 1The annual world-wide sales of the semiconductor industry in 2017 was $412.2, according to the Semiconductor Industry Association (SIA) [1] Preprint submitted to Journal of Manufacturing Systems November 29, 2018 and wafer testing, are carried out in the front-end wafer fabs, whereafter the wafers are transported to the back-end assembly and test facilities for the third step. Here, the good dies are cut out of the wafers and assembled into a package. In the fourth and final step, these packaged ICs receive a full final functional test after which the ones which pass the tests can be sold. The manufacturing process at the back-end facilities is prone to overproduction, because underproduction is not allowed and once a wafer is allocated to an order the complete wafer has to be used. Also, the amount of good dies on a wafer, referred to as the die yield, differs for each wafer. This causes that the realized production quantities often do not exactly match the required order quantities. The task of allocating wafers to customer orders prior to assembly is called the wafer allocation problem. This problem has received significant attention by researchers and is also known as the lot-to-order matching problem. However, the current problem has an additional element which was not taken into account in previous studies. That is, there are many different die types, each type having a unique IC lay-out. Generally, all the dies on a single wafer are from the same type. However, dies from the same type may still vary in their electrical properties. At the wafer testing stage in the front-end fabs the dies are probed and categorized into the so-called die classes. Each die class is defined by bounds on certain electrical properties. Specific orders may require dies from specific types and additionally of specific classes only which makes the wafer allocation problem becomes more complex. The problem including these die classes has not been studied before. Although the problem in this paper is motivated by Nexperia, its potential applications extend to many manufacturers in the semiconductor industry, since different die classes (used for different end products) on a single wafer are very common. The reason for this is that process variability is inherent in the manufacturing process of wafers, and customers demand tight bounds on the electrical specifications of their end products. Therefore, it is often not possible to manufacture a wafer which is completely suited for a single end product. Three variations of the problem will be considered: (1) the wafer allocation problem (WAP), (2) the class-constrained wafer allocation problem (CWAP) and (3) the flexible class-constrained wafer allocation problem (FCWAP). The WAP considers the problem without differentiating between die classes, i.e. all dies on a single wafer can be used for the same order. The CWAP does take into account different die classes on a single wafer. If an order needs dies from specific classes, and a wafer is allocated to such an order, then only the dies from the feasible classes can be used to fill that order. However, allocated wafers must always be completely assembled, also the dies from the infeasible classes. As a result, ICs will be created that cannot be used for that order and which will be considered to be overproduction. Finally, the FCWAP is an extension of the CWAP. The policy of the FCWAP allows dies from different classes on the same wafer to be allocated to separate orders, in contrast to the CWAP where only complete wafers can be allocated to orders. A wafer still has to be completely assembled if at least one group of dies corresponding to one of the die classes on that wafer is allocated to an order, even if the dies of other classes are unallocated. The current situation at Nexperia corresponds to a combination of WAPs and CWAPs. FCWAP is not yet applicable at Nexperia, but is considered to explore the potential benefits of a more flexible allocation policy, which could be implemented in the future. Several methods are proposed to decide which wafers to allocate to which orders prior to the assembly process. The main objective is to minimize overproduction while fulfilling a given set of orders. Important to note is that the wafer allocation problem, which is a variation of the bin covering problem, is NP-complete (Non-deterministic polynomial-time) and therefore it is {for moderately sized problems{ often not possible to provide an exact optimal solution within a reasonable time limit [3]. This justifies the use of heuristics. Two existing heuristics from the lot-to-order matching problem are adapted to make them suitable for the WAP: a First-Fit-Decreasing (FFD) policy and a First-In-First-Out with Improved End Game policy (FIFO-IEG). Also, a novel Multi-Start Swap (MS-Swap) algorithm, suitable for the WAP and the CWAP, is proposed. MS-Swap uses multiple initial solutions complemented with a smart swapping mechanism.
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