Eindhoven University of Technology

MASTER

Optimizing wafer allocation for back-end semiconductor production

Deenen, Patrick C.

Award date: 2018

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Department of Mechanical Engineering De Rondom 70, 5612 AP Eindhoven P.O. Box 513, 5600 MB Eindhoven The Netherlands www.tue.nl

Author P.C. Deenen Optimizing wafer allocation for 0784085 back-end semiconductor production Committee members I.J.B.F. Adan A.E. Akçay C.A.J. Hurkens DC 2018.101 Master Thesis Report Company supervisors J. Adan J. Stokkermans Date November 29, 2018

Where innovation starts Optimizing wafer allocation for back-end semiconductor production

Patrick Deenena,b,∗

aEindhoven University of Technology, Department of Mechanical Engineering, Eindhoven, The Netherlands bNexperia, Industrial Technology and Engineering Centre, Nijmegen, The Netherlands

Abstract This paper discusses the development of an efficient and practical algorithm that minimizes overproduction in the allocation of wafers to customer orders prior to assembly at a semiconductor production facility. This study is motivated by and tested on Nexperia’s assembly and test facilities, but its potential applications extend to many manufacturers in the semiconductor industry. The problem that is considered in this paper, has an additional element that has not been taken into account in previous studies. That is, there are some wafers which contain dies with different electrical properties, used for multiple different end products. Inspired by the classic bin covering problem, the wafer allocation problem is formulated as multiple integer linear programs (ILPs). A novel heuristic is proposed, referred to as the multi-start swap algorithm, which is compared to current practice, other existing heuristics and a commercial optimization solver. Experi- ments show that the proposed solution method significantly outperforms current practice and other existing heuristics, and that the overall performance is generally close to optimal. Furthermore, some data processing steps and heuristics are presented to make the ILPs applicable to the real-world application at Nexperia and able to interact with other stages of the existing back-end scheduling environment. Keywords: Wafer allocation, production planning, lot-to-order matching, bin covering, integer linear programming, heuristic, semiconductor

1. Introduction

This research is motivated by the problem of allocating semiconductor wafers to customer orders in the back-end production process of integrated circuits (ICs) at Nexperia’s assembly and test facilities. The back- end sites work with a make-to-order policy, in which customer orders have to be made with wafers which are stored in a warehouse waiting to be assembled. It is a challenging task to allocate these wafers to the orders prior to assembly. An inadequate allocation will cause more produced finished goods than requested by the customer orders, i.e. overproduction. This overproduction has a severe impact on the company’s profit, since it will consume more expensive material, produce excess inventory and occupy manufacturing machines longer. Thus, in the $412.2 billion semiconductor industry1, which is still growing every year, improving the wafer allocation process to minimize overproduction, is highly valuable. The reader is referred to Frederix and Florent [2] for an elaborate overview of the manufacturing process of ICs, but it can basically be divided into the following four steps. The first one is wafer fabrication, where many ICs are fabricated on a blank disk of semiconducting material (such as silicon) using photo-lithography techniques. A single IC on a wafer is called a die. The second step is wafer testing, where the dies are probed on their electrical properties and can be identified as a good or bad die. For some wafer types, the good dies are also categorized in different classes based on their quality. The first two steps, wafer fabrication

∗Corresponding author Email address: [email protected] (Patrick Deenen) 1The annual world-wide sales of the semiconductor industry in 2017 was $412.2, according to the Semiconductor Industry Association (SIA) [1]

Preprint submitted to Journal of Manufacturing Systems November 29, 2018 and wafer testing, are carried out in the front-end wafer fabs, whereafter the wafers are transported to the back-end assembly and test facilities for the third step. Here, the good dies are cut out of the wafers and assembled into a package. In the fourth and final step, these packaged ICs receive a full final functional test after which the ones which pass the tests can be sold. The manufacturing process at the back-end facilities is prone to overproduction, because underproduction is not allowed and once a wafer is allocated to an order the complete wafer has to be used. Also, the amount of good dies on a wafer, referred to as the die yield, differs for each wafer. This causes that the realized production quantities often do not exactly match the required order quantities. The task of allocating wafers to customer orders prior to assembly is called the wafer allocation problem. This problem has received significant attention by researchers and is also known as the lot-to-order matching problem. However, the current problem has an additional element which was not taken into account in previous studies. That is, there are many different die types, each type having a unique IC lay-out. Generally, all the dies on a single wafer are from the same type. However, dies from the same type may still vary in their electrical properties. At the wafer testing stage in the front-end fabs the dies are probed and categorized into the so-called die classes. Each die class is defined by bounds on certain electrical properties. Specific orders may require dies from specific types and additionally of specific classes only which makes the wafer allocation problem becomes more complex. The problem including these die classes has not been studied before. Although the problem in this paper is motivated by Nexperia, its potential applications extend to many manufacturers in the semiconductor industry, since different die classes (used for different end products) on a single wafer are very common. The reason for this is that process variability is inherent in the manufacturing process of wafers, and customers demand tight bounds on the electrical specifications of their end products. Therefore, it is often not possible to manufacture a wafer which is completely suited for a single end product. Three variations of the problem will be considered: (1) the wafer allocation problem (WAP), (2) the class-constrained wafer allocation problem (CWAP) and (3) the flexible class-constrained wafer allocation problem (FCWAP). The WAP considers the problem without differentiating between die classes, i.e. all dies on a single wafer can be used for the same order. The CWAP does take into account different die classes on a single wafer. If an order needs dies from specific classes, and a wafer is allocated to such an order, then only the dies from the feasible classes can be used to fill that order. However, allocated wafers must always be completely assembled, also the dies from the infeasible classes. As a result, ICs will be created that cannot be used for that order and which will be considered to be overproduction. Finally, the FCWAP is an extension of the CWAP. The policy of the FCWAP allows dies from different classes on the same wafer to be allocated to separate orders, in contrast to the CWAP where only complete wafers can be allocated to orders. A wafer still has to be completely assembled if at least one group of dies corresponding to one of the die classes on that wafer is allocated to an order, even if the dies of other classes are unallocated. The current situation at Nexperia corresponds to a combination of WAPs and CWAPs. FCWAP is not yet applicable at Nexperia, but is considered to explore the potential benefits of a more flexible allocation policy, which could be implemented in the future. Several methods are proposed to decide which wafers to allocate to which orders prior to the assembly process. The main objective is to minimize overproduction while fulfilling a given set of orders. Important to note is that the wafer allocation problem, which is a variation of the bin covering problem, is NP-complete (Non-deterministic polynomial-time) and therefore it is –for moderately sized problems– often not possible to provide an exact optimal solution within a reasonable time limit [3]. This justifies the use of heuristics. Two existing heuristics from the lot-to-order matching problem are adapted to make them suitable for the WAP: a First-Fit-Decreasing (FFD) policy and a First-In-First-Out with Improved End Game policy (FIFO-IEG). Also, a novel Multi-Start Swap (MS-Swap) algorithm, suitable for the WAP and the CWAP, is proposed. MS-Swap uses multiple initial solutions complemented with a smart swapping mechanism. Finally, these algorithms are benchmarked with the best solution retrieved by the Gurobi Optimizer, which is a commercial optimization solver, in the same solution time. The main contributions of this paper are threefold. Firstly, the not yet studied problems, the CWAP and the FCWAP, are introduced and formulated as integer linear programming (ILP) problems. Secondly, a novel heuristic is proposed to solve the WAP and the CWAP. And lastly, the Gurobi Optimizer is used to 2 solve the WAP, CWAP and the FCWAP as well as to benchmark existing (FFD and FIFO-IEG) heuristics and the novel heuristic. The remainder of this paper is organized as follows. The related literature is discussed in Section 2. In Section 3, mathematical formulations are given for the researched problems. The proposed algorithms to solve the problems are discussed in Section 4. The application is explained in Section 5 and the results of this are shown in Section 6. Finally, the conclusions and recommendations are given in Section 7.

2. Literature review The bin covering problem is a dual version of the bin packing problem and it belongs to the packing problems. The literature on packing problems (which includes bin packing, bin covering and knapsack problems) is very broad and one can find many heuristics to approximately solve the problem. A comparison between heuristics has been done by Bischoff et al. [4]. The main conclusion of this comparison is that the performance of these heuristics is very domain-dependent, and their performance may vary with the number and relative size of the different items. Especially when the number of bins (orders) is small and the average size of the items (wafers) is large, it is more difficult to pack each bin effectively. More recently Coffman Jr. et al. [5] give a survey and classification of many approximation algorithms for the bin packing problem. Assigning wafers to customers orders, often referred to as lot-to-order matching, at back-end facilities is obviously a part of the complete semiconductor supply chain. A recent survey of M¨onch et al. [6] gives an overview of the literature in all the areas of this supply chain. In the framework of the so-called supply chain matrix of Meyr et al. [7], lot-to-order matching is part of the short-term demand fulfillment. There are two bodies of literature that deal with the wafer allocation problem, one concerning the front-end fabs where the wafers still have to be produced and the other at the back-end assembly sites where the wafers are waiting to be assembled in the warehouse. For the back-end case, Knutson et al. [8] decompose the problem into two integer linear programs and solve them sequentially with heuristics. The two sub problems are the choice of orders to be filled given a capacity-constrained factory (order selection), followed by filling these orders with available wafers (wafer allocation). Coffman Jr. et al. [5] showed that the FFD policy had one of the best characteristics with respect to worst case as well as average case behaviour for the bin packing problem and therefore this policy is also used in solving the wafer allocation part of [8], outperforming the FIFO policy significantly. Fowler et al. [9] and Carlyle et al. [10] proposed additional heuristics for the same problem, where FFD1(Si), which is an algorithm that combines a search routine with a priority rule system, eventually had the best average performance. Boushall et al. [11] extended the problem to a class-constrained lot-to-order matching problem, where there are two different classes of end products: high- and low speed integrated circuits. However, these two classes do not overlap, which in essence creates two disjoint subsets of wafer-order combinations and can be treated similarly as two independent lot to order matching problems. Also, The FIFO and FFD algorithms have been extended with the improved endgame (IEG), in which FIFO-IEG seemed to perform the best. NG et al. [12] consider the lot to order matching problem with uncertain lot sizes and look at under- or over-filling the customer orders with robust optimization. Sun et al. [13] study a generalized version of the problem that allows downward product substitution when demand exceeds supply. The CWAP and the FCWAP introduced in this work are an extension on the second part of the lot to order matching problem of [8, 9, 10]. The addition of having different die classes on a wafer based on the electrical properties of a die, is very common in the current industry, but is not included in previous mentioned literature. Only Boushell et. al [11] consider two die classes (i.e. low- and high speed circuits), but these die classes could be treated as two disjoint problems. In contrast, in this work there are many die-classes having a lot of overlap in their relations which makes it not possible to split it into disjoint problems.

3. Problem description and formulation Three variations on the wafer allocation problem are introduced in this section, each of them is formulated as an integer linear programming problem. To start with, the classic bin covering problem formulation will 3 be given. After that, the WAP, which is similar to the lot to order matching problem as studied in [8, 9, 10], is presented. Next, the CWAP formulation is introduced by replacing some constraints of the WAP. Finally, the complete model formulation of FCWAP is given, which has additional constraints and some different variables.

3.1. Classic bin covering The wafer allocation problem has many similarities to the well-known variable-sized bin covering problem (VSBCP), which is a variation on the classic bin covering problem. The classic bin covering problem is a dual version of the bin packing problem. As is done in [14], it can be described as follows: given is a set I = {a1, a2, ..., an} of items, size s(ai) > 0 for each item ai, and a threshold T > 0, where the threshold is the size of the bin (all bins are of the same size). There is an infinite supply of bins. The objective is to determine the maximum number m such that I can be partitioned into sets I1, ..., Im where each set Ii has total size s(I ) = P s(a ) ≥ T . i α∈Ii i The VSBCP has a finite set of variable sized bins B = {b1, b2, ..., bm} with size s(bi) > 0 for each bin bi, where the cumulative size of all bins is bigger than the cumulative size of all items. Now the objective is to cover, with the given list of items, a set of bins with the largest total size.

3.2. The wafer allocation problem (WAP) The bins and items in the classic bin covering problem are considered to be orders and wafers respectively in the wafer allocation problem. The total set of orders is denoted by O and the total set of wafers by W . The size of order i is Si with i ∈ O and the total size of wafer j is Lj with j ∈ W , both expressed in die quantities. Using this notation the model formulation of the WAP is given as follows:   X X min  δijLj − Si , (1) δ i∈O j∈W subject to

X δijLj ≥ Si ∀ i ∈ O (2) j∈W X δij ≤ 1 ∀ j ∈ W (3) i∈O where  1 if wafer j allocated to order i δ = ij 0 otherwise.

The objective function (1) minimizes the cumulative overproduction. Constraints (2) ensure that all orders are covered and constraints (3) ensure that a wafer can only be allocated to at most one order. Generally, the set of orders O is selected such that there is sufficient supply of wafers to cover all orders. However, this cannot be ensured beforehand and therefore the problem can still be infeasible. If it is infeasible, one or more orders will be removed from the set of orders until the problem becomes feasible. This will be discussed more elaborately in Section 5.2.

3.3. The class-constrained wafer allocation problem (CWAP) The class-constrained wafer allocation problem has the additional element, compared to the WAP, of dies from different classes on a single wafer. This categorization into classes is based on the electrical properties of each die. Due to specific requirements on the electrical specifications only certain die classes are feasible for each order and the set of feasible die classes differs per order. C denotes the set of all die classes, and Ci is the set of feasible die classes to fill order i with Ci ⊂ C. ljk denotes the quantity of dies in class k on 4 P wafer j, such that Lj = k∈C ljk. The CWAP model is obtained by taking the model formulation of the WAP and replacing constraints (2) with the following:

X X δijljk ≥ Si ∀ i ∈ O (4)

j∈W k∈Ci

Only the feasible die classes Ci can be used to fulfill order i. Thus, only the die quantities of matching classes are considered in constraints (4). However if a wafer is allocated to an order, the complete wafer has to be manufactured, also the infeasible die classes. Therefore, the complete die quantity of a wafer is still considered in the objective function (1).

3.4. The flexible class-constrained wafer allocation problem (FCWAP) The flexible class-constrained wafer allocation problem includes the policy that the groups of dies from different classes on a wafer can be allocated to separate orders, whereas the previous problem solely allows the complete wafer to be allocated to at most one order. Hence, a die class k of wafer j can be allocated to order i and the set of all order-wafer-class combinations is denoted by Ω = {(i, j, k) | i ∈ O ∧ j ∈ W ∧ k ∈ C}. As mentioned before, not all die classes are eligible for all orders. Ωe and Ωne denote, respectively, the set of eligible combinations and non-eligible combinations with Ωe ⊂ Ω, Ωne ⊂ Ω and Ωe ∩ Ωne = ∅. Using similar notation as in previous sections, the complete FCWAP formulation is given as follows: X X min ΛjLj − Si, (5) δ,Λ j∈W i∈O subject to

X X δijkljk ≥ Si ∀ i ∈ O (6) j∈W k∈C X δijk ≤ 1 ∀ j ∈ W, ∀ k ∈ C (7) i∈O

δijk ∈ {0, 1} ∀ (i, j, k) ∈ Ωe (8)

δijk = 0 ∀ (i, j, k) ∈ Ωne (9)

δijk ≤ Λj ∀ i ∈ O, ∀ j ∈ W, ∀ k ∈ C (10) where   1 if die class k of wafer j allocated δijk = to order i  0 otherwise.

Constraints (6) and (7), have the same functionality as in the previous problems, except that the decision variable δijk allows each die class k on a wafer to be allocated individually to at most one order. The eligibility constraints, such that orders will be filled with feasible die classes, are captured in (8) and (9). Furthermore, Λj is introduced and constraints (10) ensure that Λj  X X  0 if δijk = 0 Λj = i∈O k∈C  1 otherwise.

If at least one of the die classes on wafer j is allocated, the complete wafer quantity Lj has to be manufactured, even if other die classes are unallocated. Hence, in that case, Λj will be one, and Lj is added in the objective function (5). 5 4. Solution methods In this section, several approaches will be considered to solve the wafer allocation problems. First, the FFD and FIFO-IEG policy, suitable for the WAP, are discussed. After that, a novel heurstic called the MS-Swap, is introduced. MS-Swap uses multiple initial solutions with random initialization complemented with a smart swapping mechanism. MS-Swap is suitable for both the WAP and the CWAP. Finally, the commercial solver used for benchmarking called Gurobi Optimizer is shortly discussed. It was not in the scope of this work to develop a heuristic which is capable of solving the FCWAP. Instead, the Gurobi Optimizer is used to solve the FCWAP, which is sufficient to explore the potential benefits of the different allocation policy of FCWAP compared CWAP.

4.1. First-Fit-Decreasing policy The First-Fit-Decreasing (FFD) policy is applicable to the WAP and it originates from bin packing problem. In the bin packing problem items have to be packed inside the bin and may not exceed the size of the bin, i.e. all the items have to fit in the bin. Recall that in the bin covering problem, which is a dual version of the bin packing problem, the items have to cover the bin, i.e. the cumulative size of the allocated items have to be equal to or exceed the size of the bin. To make the FFD policy applicable to the bin covering problem and therefore also for the WAP, the Left quantity is introduced. Left is defined as the sum of the unallocated order quantity and the smallest unallocated wafer quantity. The yet-to-be-allocated wafer has to fit in Left. The complete FFD policy for the WAP is described below. FFD for wafer allocation: 1. Sort the orders in non-increasing size. 2. Sort the wafers in non-increasing size. 3. If all the orders are covered, go to Step 11. 4. Select the first uncovered order i. 5. Determine the size of the smallest unallocated wafer. 6. Define Left as the sum of the unallocated order quantity and the smallest wafer quantity. 7. If the first unallocated wafer j is smaller than Left, select this wafer j and go to Step 9. 8. Search the list of unallocated wafers and select the first wafer j which is smaller than Left. 9. Allocate wafer j to order i. 10. If order i is covered, go to Step 3 – else go to Step 5. 11. Stop.

Over- Left allocation

Left 2 2 Total size

1 2 3 4 5 1 3 4 5 1 3 5

Order Wafers Order Wafers Order Wafers (a) (b) (c)

Figure 1: Illustrative example which shows 3 stages of the allocation process using the FFD policy

An illustrative example is given in Figure 1. In Figure 1(a), the wafers are clearly sorted in non-increasing order, after which wafer 1 and 2 are allocated to the order. In Figure 1(b), wafer 3, 4 and 5 are unallocated and wafer 3 will be selected. However, wafer 3 does not fit in Left, so therefore wafer 4 is selected, which does fit in Left and will be allocated to fill the order. Figure 1(c) shows the final allocation of wafer 1, 2 and 4, where a part of wafer 4 accounts for the overallocation. 6 4.2. First-In-First-Out with Improved End Game The First-In-First-Out with Improved End Game (FIFO-IEG) policy is also applicable to the WAP. The FIFO-IEG policy starts to assign wafers in FIFO order: the wafer with the nearest expiration date first. This policy has practical benefits, since it prevents wafers to expire in the warehouse. After a wafer has been allocated, the policy always checks whether the largest unallocated wafer can fill the order. If so, the policy enters the Improved End Game (IEG), where it will search through all unallocated wafers to find the wafer which causes the least overallocation while still covering the order. The complete FIFO-IEG policy is described below FIFO-IEG for wafer allocation: 1. Sort the orders in non-increasing size. 2. Sort the wafers by expiration date, with the earliest expiration date first. 3. If all the orders are covered, go to Step 10. 4. Select the first uncovered order i. 5. If any wafer can cover order i, go to Step 7 6. Select the first unallocated wafer j, go to Step 8 7. Select the smallest wafer j which can cover order i. 8. Allocate wafer j to order i. 9. If order i is filled, go to Step 3 – else go to Step 5. 10. Stop.

Over- allocation

Total 1 1 size

2 2 1 4 5 3 2 4 5 3 4 3

Order Wafers Order Wafers Order Wafers (a) (b) (c)

Figure 2: Illustrative example which shows 3 stages of the allocation process using the FIFO-IEG policy

The FIFO-IEG policy is illustrated in Figure 2, using the same order and set of wafers as in the example of previous section. In Figure 2(a), the wafers are ordered by expiration date. Wafer 2 expires first, hence it is allocated to the order first. After that, none of the wafers is able to cover the order, so it will not enter the IEG. Instead, it will allocate the next wafer with first expiration date: wafer 1. In Figure 2(b), there are wafers which can cover the order, so it will enter the IEG. At this point, the allocated wafers and unallocated wafers are similar to the example of the FFD policy as shown in Figure 1(b). The IEG policy searches for the wafer which causes the least overallocation while still covering the order, so it allocates wafer 5, in contrast to the FFD policy which would have allocated wafer 4 in the similar situation, resulting in In Figure 2(c). The IEG can also be combined with FFD, which would result in FFD-IEG. However, Boushell et al. [11] showed that FIFO-IEG clearly outperforms FFD-IEG, because the FIFO policy maintains a greater range of unallocated wafer sizes than the FFD policy. This greater range of wafer sizes causes the IEG to perform better, since it is more likely to find wafers that cover the order with less overallocation. For that reason, FFD-IEG is not considered in this work.

7 4.3. Multi-start Swap Algorithm In contrast to the FFD and FIFO-IEG heuristics, which are only applicable to the WAP, the multi-start swap (MS-Swap) algorithm proposed here can also be applied to the CWAP. Although, certain specific features are necessary to deal with the complexity of different die classes on the same wafer, in either case, the proposed method follows the same main procedure as is shown in Algorithm 1. It starts with the generation of the set of initial solutions, Sall, followed by attempts to find improvements for each initial solution s via iterations over local search (LocalSearch(s)) and 0-cost moves (ZeroCostMoves(s)). The latter search methods are both based on swap moves, i.e. the exchange of two wafers. The number of times the algorithm iterates over the sequential local search and 0-cost moves, is determined by parameter R. If the resulting objective of solution s (ObjectiveOf(s)) is smaller than the current best objective (Obest), the solution s and its objective are saved.

Algorithm 1 Multi-Start Swap (MS-Swap) algorithm

1: Obest ← ∞ 2: Sall ← GenerateInitialSolutions(); . See Algorithm 2 3: 4: for each solution s ∈ Sall do 5: ireps ← 0; 6: while ireps < R do . See Table 6.2 for parameter R 7: LocalSearch(s); . See Algorithm 3 8: ZeroCostMoves(s); . See Algorithm 5 9: ireps ← ireps + 1; 10: end while 11: 12: if ObjectiveOf(s) < Obest then . ObjectiveOf(s) calculates the objective of solution s 13: Obest ← ObjectiveOf(s); 14: sbest ← s; 15: end if 16: end for

A schematic overview of the components of the MS-Swap algorithm and the flow between them is shown in Figure 3. The algorithm starts with the initialization, in which multiple solutions are generated. Each solution requires a specified number of wafers in each order, the so-called configuration. Then, the solutions are randomly filled with wafers according to their configuration. After that, attempts are made to find improvements by iterating over a local search mechanism and 0-cost moves. Finally, the solution with the best objective is chosen. In the subsequent sections the components of the proposed MS-Swap algorithm are described in more detail.

4.3.1. Initialization and random fill Inherently, swap moves do not alter the number of wafers allocated to each order as well as the number of unallocated wafers. Thus, the number of wafers in each order is dictated by the initial solution. Consequently, since an optimal solution contains a certain number of wafers for each order, it may not be reached from certain initial solutions. For this reason, multiple initial solutions are generated, each with a different number of wafers per order. Given the required die quantity of a order together with the available wafers, it is rather straightforward to determine the minimum and maximum number of allocated wafers for each order. The total number of initial solutions with a different number of wafers for each order then equals,

i=I Y max min (|W |i − |W |i ) i=0 min max where |W |i and |W |i are the minimum and maximum number of allocated wafers to order i respec- tively. When the variation of die quantity among wafers is relatively small, this number remains small as 8 Initialization Random fill Legend Solution 3 Solution 3 Order Solution 2 Solution 2 Solution 1 Solution 1 Allocated wafer Unallocated wafer

23 2 4 23 2 4 Configuration Configuration

Unallocated wafers Unallocated wafers

0-Cost Moves Local Search Solution 3 Solution 3 Solution 2 Solution 2 Solution 1 Solution 1 Best Solution sbest

Unallocated wafers Unallocated wafers

Figure 3: Illustrative example which show the different components of the MS-Swap algorithm: initialization, random fill, local search and zero-cost moves. Finally, the solution is chosen with the best objective.

9 well. However, since this is not necessarily the case for every problem, it is not scalable to evaluate all possible configurations. Instead, the set of initial solutions, Sall, is generated as in Algorithm 2. First, the configuration with a minimum number of wafers for each order, cmin, is determined. Then, solution smin is generated through a random assignment of a certain number of wafers per order, defined by cmin. After that, another series of initial solutions is generated where the allocated number of wafers is increased by 1 for each order separately. This procedure continues until a certain maximum is reached, specified by a parameter K. Each new generated configuration cnew is checked on feasibility, i.e., the total number of allocated wafers may not exceed the total number of available wafers. Furthermore, due to the random assignment of wafers it can happen that the initial solutions contain orders which are not filled. However, the subsequent local search will attempt to solve this.

Algorithm 2 Initialization for MS-Swap 1: procedure GenerateInitialSolutions 2: min 3: cmin ← MinConfiguration(|W | ); . Configuration cmin uses min. amount of wafers per order 4: smin ← RandomAllocateWafers(cmin); . Solution s is generated 5: Add s to set Sall; .Sall is set of all initial solutions 6: 7: for each order i ∈ Oall do 8: kinc ← 0; 9: while kinc < K do . See Table 6.2 for parameter K 10: cnew ← Increase order i in configuration cmin with kinc; 11: if configuration cnew is feasible then 12: s ← RandomAllocateWafers(cnew); . Allocates wafers to all orders according to configuration cnew 13: Add s to set Sall 14: end if 15: kinc ← kinc + 1; 16: end while 17: end for 18: 19: return Sall

4.3.2. Swap Moves Once a random initial solution is generated, attempts are made to find improvements by means of swap moves. As mentioned, a swap move is based on the exchange of two wafers. The swap neighborhood is searched as described in Algorithm 3. The search propagates through each order as follows: at first, an allocated wafer, wi, is selected. Then, swap moves with all unallocated wafers, wj ∈ WUA, are evaluated. Finally, the move that results in the largest improvement is accepted, i.e. steepest descent. This move is implemented by ImplementSwap(BestMove). Among preliminary experiments with different acceptance strategies, e.g. any descent, the strategy of steepest descent yielded the best results in terms of computational efficiency. The search for feasible swap moves continues until no more improvements are found. Then, the search continues with the next order. The structure of the local search is identical for the WAP and CWAP. The only difference between both problems is in the acceptance criterion of a swap move, dictated by DetermineIfImprovement which is shown in Algorithm 4. An order can either be in underallocation or overallocation, i.e., the total allocated quantity is smaller or larger, respectively, than the total required quantity. If order i is in overallocation, the swap move between two wafers, wi and wj, has to satisfy following three conditions: (1) the swap move has to decrease the overallocation, (2) the swap move has to be better than currently best found swap move (BestSwap) and (3) order i has to stay filled after the swap move. For the WAP, the third condition is checked by considering the complete wafer quantities, while for the CWAP, merely the quanities of the 10 feasible die classes for order i are considered. If order i is in underallocation, the following two conditions have to be satisfied: (1) the move has to decrease the underallocation and (2) the swap move has to be better than currently best found swap move (BestSwap). Again, for the first condition only the quantities of feasible die classes are considered for the CWAP, but complete wafer quantities for the WAP.

Algorithm 3 Local search for MS-Swap 1: procedure LocalSearch(solution s) 2: 3: for each order i ∈ O do .O is the set of all orders 4: ImprovementFound ← true; 5: while ImprovementFound = true do 6: ImprovementFound ← false; 7: for each allocated wafer wi in order i do 8: for each unallocated wafer wj ∈ WUA do .WUA is the set of all unallocated wafers 9: if DetermineIfImprovement(BestSwap, i, wi, wj) = true then . See Algorithm 4 10: BestSwap ← SaveSwap(wi, wj); 11: ImprovementFound ← true; 12: end if 13: end for 14: end for 15: if ImprovementFound = true then 16: ImplementSwap(BestSwap); 17: end if 18: end while 19: end for

Algorithm 4 Acceptance criterion of local search

1: procedure DetermineIfImprovement(BestSwap, order i, allocated wafer wi, unallocated wafer wj) 2: 3: if order i is in overallocation then 4: if Swap(wi, wj) decreases overallocation and Swap(wi, wj) is better than BestSwap and order i stays filled after Swap(wi, wj) then 5: return true; 6: end if 7: end if 8: 9: if order i is in underallocation then 10: if Swap(wi, wj) decreases underallocation and Swap(wi, wj) is better than BestSwap then 11: return true; 12: end if 13: end if 14: 15: return false;

After the first local search iteration, the infeasible solutions, i.e. solutions containing orders which are not filled, are deleted. Only feasible solutions will considered for the remainder of the algorithm. Since the objective is to minimize the total overallocation, swapping wafers among orders in many cases moves the overallocation from one order to another. Since these moves do not improve the objective they are referred to as 0-cost moves. Nevertheless, these moves can diversify the search. Capua et al. [15] reported 11 that these moves have a significant contribution to the search performance. In the method proposed in Algorithm 5, 0-cost moves are considered between all possible combinations of two orders i and j. For each order combination, all possible combinations of two allocated wafers wi and wj are checked on feasibility, i.e. whether both orders stay filled after the swap move. If the swap between wi and wj is feasible, it is accepted with probability P and implemented by ImplementSwap(wi, wj).

Algorithm 5 0-cost moves for MS-Swap 1: procedure ZeroCostMoves(solution s) 2: 3: for each order i ∈ O do 4: for each order j ∈ O do 5: if i 6= j then 6: for each allocated wafer wi in order i do 7: for each allocated wafer wj in order j do 8: if both orders stay filled after swap then 9: ImplementSwap(wi, wj) with probability P. See Table 6.2 for parameter P 10: end if 11: end for 12: end for 13: end if 14: end for 15: end for

4.4. Gurobi Optimizer Gurobi Optimizer is a commercial optimization solver for mathematical programming problems, such as the integer linear programming (ILP) problem introduced in section 3. To solve ILP problems it uses a linear-programming based branch-and-bound algorithm. For a more elaborate description of this algorithm the reader is referred to [16].

5. Application

As mentioned before, the solution method proposed in this paper is applied to one of Nexperia’s back-end assembly and test facilities located in Malaysia. Their product portfolio is large and the considered back-end site assembles approximately 900 unique products, using more than 1000 different wafer types. This section will give more insight in how the matching of wafers interacts with other parts of the back-end scheduling process. Furthermore, the translation of the data into the wafer allocation problems is described as well as the translation of the solutions of the problems to the production orders, which can be communicated to the rest of the back-end facility. Finally, the current practice of wafer allocation is discussed and what the main problems are of this way of working.

5.1. Back-end scheduling environment Wafer allocation is merely a link in the chain of the entire scheduling processes in the back-end facilities. To fully understand the scheduling environment, a complete overview is shown in Figure 4. Customer orders are received from the mid-term master planning on a weekly basis, called planned orders. Wafers are received daily from the front-end fabs and are waiting to be assembled in the back-end’s wafer inventory. Generally the front-end fabs ensure that the wafer supply matches the requested wafer types of the planned orders. These planned orders and wafers go into the wafer allocation stage, which will be elaborately discussed in Section 5.2, where the wafers are matched to (groups of) planned orders. These orders with allocated wafers are the so-called preprocess orders. Next, the preprocess orders are scheduled on the machines, which is done by a hybrid genetic algorithm proposed by Adan et al. in [17]. This scheduling process is called

12 machine allocation. Finally these so-called process orders – consisting of planned orders, allocated wafers and allocated machines – are sent to assembly and test.

Order Planned Preprocess Process release orders orders orders FGTO Wafer Machine Assembly FGTS allocation allocation & Testing Wafer FGTW inventory Wafers

Figure 4: Back-end scheduling flow

After testing, the finished goods (FGs) can be divided into three categories: (1) FGs sent To an Order (FGTO), (2) overproduced FGs sent To the Warehouse (FGTW) and (3) FGs which do not pass the final tests: FGs sent To Scrap (FGTS). The main goal of optimizing the wafer allocation process, is minimizing FGTW and maximizing FGTO. The FGTS, caused by electrical or mechanical failures, are inherent to the assembly process and cannot be influenced by wafer allocation.

5.2. Pre- and postprocessing of data This section discusses the pre- and post-processing steps in the wafer allocation block of Figure 4. The pre-processing steps translate the incoming planned orders and wafers into multiple WAPs and (F)CWAPs. Subsequently, these ILPs are solved by one of the proposed solution methods. After that, the post-processing steps translate the solutions into pre-process orders (groups of planned orders with allocated wafers), which are then passed to the next scheduling step of machine allocation. All these steps can be seen in Figure 5 and each of them will be discusses separately in following sections.

Wafer Allocation Planned Filtered WAPs & Matching matching (F)CWAPs Algorithm Pre-process orders groups solutions orders Combine Order groups Translate Matching Translate and group selection to ILPs algorithm to PPOs Wafers If infeasible

Figure 5: Back-end scheduling flow

For the experiments in this work, a stand-alone database is set up, such that it did not directly interfere with the back-end facility. The database received the same planned orders and wafers as the back-end facility. To find a more description of the database the reader is referred to Appendix A.

5.2.1. Combine and group As can be seen in Table 1, each planned order has a requested quantity for a specified finished good type (FG type). Each FG type has a different recipe which determines how many dies from which wafer type have to be used. At Nexperia, this can vary from single-die, double-die, triple-die to quad-die products, using at most two different wafer types. For example, orders O1 and O2 are both for FG type A, which is a double-die product where both dies are from wafer type 1. This means that the required die quantity of that wafer should be twice the requested FG quantity. However, this quantity is slightly higher, because it also takes into account that a certain percentage of all the FGs will be damaged during assembly and have to be scrapped after the final tests. This is called the estimated scrap factor and this differs for each FG type. Order O3 has a different FG-type than O1 and O2 and therefore it requires different wafers. Order O3 has FG-type D, which is a double-die product with two different dies, one from wafer type 2 and the other one from wafer type 3. Therefore, the required die quantity for both wafer 2 and wafer 3 are the same 13 and equal to the FG quantity plus the estimated amount of scrap. Order O4 is a quad-die product, with two dies from wafer type 4 and two from wafer type 5 and the corresponding required die quantities are calculated in similar manner. Furthermore, a FG type can request specific die classes, which means that it can only be made with dies from these specified classes; e.g. order O4 can only be filled with classes 21 and 22 from wafer type 4 and 5. Orders O1, O2 and O3 do not require specific classes.

Planned orders ID FG type FG qty Waf type Req qty Waf type Req qty Due date Classes O1 A 182.000 1 364.498 -- 18-10-18 - O2 A 76.000 1 155.548 -- 23-10-18 - O3 D 400.000 2 424.500 3 424.500 21-10-18 - O4 E 300.000 4 606.600 5 606.600 22-10-18 21,22 O5 F 120.000 4 129.000 5 129.000 23-10-18 22,23,24 ......

Table 1: Illustrative sample of planned orders. For each order the unique ID number, the finished-good type (FG type), finished goods quantity (FG qty), wafer type (waf type) and corresponding required die quantity (req qty), the due date and the required classes are given.

The wafers are tested in the front-end fabs and therefore the total quantity of good dies (Tot qty) is known. For the wafer types, which are used for FG types requiring specific classes, also the amount of dies in each of these classes is known, as can be seen for wafer W11 and W13 in Table 2.

Wafers Classes ID Waf type Exp date Tot qty No class 21 22 23 ... W11 4 18-10-19 43.820 - 40.502 0 2.140 ... W12 1 20-08-19 24.405 24.405 - - - ... W13 5 21-12-18 112.097 - 320 100.284 5.245 ......

Table 2: Illustrative sample of available wafers in the warehouse. For each wafer the wafer type (waf type), expiration date (exp date), total die quantity on that wafer (tot qty) and the die quantity per class is given.

Planned orders, which require the same materials and have the same assembly processes can be combined in one preprocess order. For the illustrative example, it is assumed that all planned orders with the same FG type can be combined. All wafers from the same type are also grouped in batches of wafers. Then the order-wafer relations are mapped in a bipartite graph. The bipartite graph resulting from the planned orders in Table 1 is shown Figure 6. FG type A needs wafer type 1. FG type B needs wafer type 1 and 2, while FG type D uses the same wafer type 2 and different wafer type 3 and so forth. Clearly two disjoint groups, G1 and G2, can be found with batches of orders and wafers. These disjoint groups are called matching groups and are passed along to the next stage of order selection.

5.2.2. Order selection Although the front-end fabs try to match the wafer supply with the order demand, it often happens that there is insufficient wafer supply to cover all the orders. In that case, the ILP problem in Section 3 would become infeasible. To prevent this, the matching groups go through the order selection stage, which categorizes all the orders into selected and unselected planned orders. This results in matching groups with merely the selected planned orders, so-called filtered matching groups, as can be seen in Figure 7. The order selection stage has many similarities with the bin packing problem. For the complete formu- lation of the classic bin packing problem the reader is referred to Baker [18]. Recall that the bin packing 14 G1 G2 Batch of all planned ABCDEF X orders from type X

Batch of wafers 1 2 3 4 5 Y from type Y

Figure 6: A bipartite graph to illustrate the order-wafer relations of the planned orders in Table 1. This graph decomposes into two disjoint groups, so-called matching groups, G1 and G2.

G1 G2 Batch of selected planned ABCDEF X orders from type X

Batch of wafers 1 2 3 4 5 Y from type Y Batch of unselected planned A C D E X orders from type X

Figure 7: Filtered matching groups with selected and unselected planned orders problem is a dual version of the bin covering problem. The order selection procedure is slightly different for non-class-constrained groups (WAPs) and class-constrained groups (CWAPs or FCWAPs). Therefore, both procedures will be described separately.

Selected Unselected

If order does not fit If order Yet to allocate Sum qty fits O3 of all O1 O2 wafers Req OX 1 2 3 12 3 1 wafer Order X needs qty Y Z wafer type Y Bins per wafer type Planned orders and Z

Figure 8: Schematic overview of the workings of the FIFO-Fist-Fit heuristic for order selection for WAPs. For this example, the non-class-constrained group G1 shown in Figure 6 with corresponding the planned orders from Table 1 is used.

To start with the order selection problem for WAPs, this is illustrated in Figure 8, for matching group G1 of Figure 6 and corresponding planned orders of Table 1. There is one bin per wafer type and each bin’s capacity is the sum of the total die quantities of all wafers of that wafer type. Each planned order creates one or two items which can only be used to fill the bin with the corresponding wafer type. For example, in Figure 8, order O1 (for FG type A) only needs wafer type 1 and has therefore just 1 item of which the size corresponds to the requested quantity in dies. Order O3 (for FG type D) needs wafer type 2 and 3, so this corresponds to two items. Thus, if O3 is selected, one of the items will fill bin 2 and the other item fills bin 3. The objective of the order selection part is threefold: (1) to make the ILP problem (WAP, CWAP or FCWAP) in following scheduling stages feasible, (2) to maximize the fulfilled planned orders with given wafer supply and (3) to meet the due dates of the planned orders as much as possible. The latter two are conflicting objectives, for which a novel heuristic is proposed, called the FIFO-First-Fit policy. Aforementioned heuristic sufficiently satisfies both objectives for this application. However, the policy does not suffice to ensure the first objective of feasibility of the ILPs, but this will be discussed later. The FIFO-First-Fit policy for WAPs 15 is described below. FIFO-First-Fit for order selection for WAPs: 1. For each wafer type: sum all wafer quantities and set this as the capacity of the corresponding bin. 2. For each planned order: translate the total FG quantity to the required quantities for the corresponding wafers. 3. Add all planned orders to yet to allocate group. 4. Sort the planned orders by due date, nearest due date first. 5. Select first planned order in yet to allocate group. 6. Check if planned order fits for all corresponding wafer types. If it does not fit, go to Step 8. 7. Move order to the selected group and allocate order to bins of corresponding wafer types, go to Step 9 8. Move order to the unselected group. 9. If yet to allocate group contains wafers, go to Step 5. 10. Stop.

Selected Unselected

Wafer Wafer If order does not fit type 4 type 5 Yet to allocate If O5 order O4 Sum qty fits 21 21 22 22 OX of all 23 23 Req Order X 22 22 00 00 wafers 24 24 wafer needs class qty 01 01 00 or 01 21 23 21 22 23 4 5 4 5 from wafer Bins per die class per wafer type Planned orders Y Z type Y and Z

Figure 9: Schematic overview of the workings of the FIFO-Fist-Fit heuristic for order selection for CWAPs or FCWAPs. For this example, the class-constrained group G2 shown in Figure 6 with corresponding the planned orders from Table 1 is used.

For CWAPs or FCWAPs, the order selection problem is illustrated in Figure 9, for matching group G2 of Figure 6 and corresponding planned orders of Table 1. There is one bin per die class per wafer type. Each bin’s capacity is the sum of the total dies which have that die class and are from that wafer type. Each planned order creates one or two items which can only be used to fill the bin with the corresponding wafer type and one of the corresponding die classes. For example, in Figure 9, order O4 (for FG type E) needs die classes 21 or 22 from wafer type 4 and 5 and O5 (for FG type F) needs die classes 22, 23 or 24 from wafer type 4 and 5. The FIFO-First-Fit policy for CWAPs or FCWAPs is described below. FIFO-First-Fit for order selection for CWAPs or FCWAPs: 1. For each die class of each wafer type: sum all quantities and set this as the capacity of the corresponding bin. 2. For each planned order: translate the total FG quantity to the required quantities for the corresponding die classes and wafer types. 3. Add all planned orders to yet to allocate group. 4. Sort the planned orders by due date, nearest due date first. 5. Select first planned order in yet to allocate group. 6. Check if planned order fits for all corresponding items. If it does not fit, go to Step 8. 7. Move planned order to the selected group and allocate items of each order to bins of corresponding die classes and wafer types. If multiple die classes are possible, allocate it in the bin with largest unallocated quantitiy. Go to Step 11 16 8. Check if allocated items can be moved to bins of die classes which are not feasible for currently selected planned order. If so, move these items to other bins, otherwise go to Step . 9. Check again if selected planned order fits for all corresponding items. If it fits, go to Step 7. 10. Move order to the unselected group. 11. If yet to allocate group contains planned orders, go to Step 5. 12. Stop. Even though the sums of the requested wafer quantity of the selected planned orders will not exceed the available wafer quantities, the ILPs can still be infeasible. This will be noticed at the matching algorithm stage, see Figure 5, and in that case it will feed the matching groups back to the stage of order selection. The wafer types (corresponding to the bins in Figure 8) which cause it to be infeasible are identified and the order with the latest due date in that bin is removed. If this order has a linked item in another bin, then this item is also removed from that bin. For example, if wafer type 2 causes the problem to be infeasible and order O4 is the latest order in that bin, then O2 is removed from bin 2. In addition, the item belonging to O4 in bin 1 is also removed. This procedure is repeated until all the ILPs become feasible.

5.2.3. Translate to ILPs The filtered matching groups require some translation to obtain the WAP, CWAP and FCWAP formu- lations. Each unique wafer type creates one problem formulation. A matching group is class-constrained if any of the orders require specific die classes and it is non-class-constrained if none of the orders do so. Class-constrained groups are formulated as either CWAPs or FCWAPs and non-class-constrained groups always become WAPs. For example, filtered matching group G1 (see Figure 7) is non-class-constrained and has three wafer types: 1, 2 and 3. Thus, three separate WAP formulations are created: WAP1, WAP2 and WAP3, see Figure 10. Order type B needs dies from wafer type 1 and wafer type 2. Therefore, the batch of orders of FG type B will decompose in two separate orders B1 and B2 for respectively WAP1 and WAP2. The size of order B1 and B2 is the sum of the requested die quantities for, respectively, wafer type 1 and wafer type 2 from all selected planned orders of FG type B. In conclusion, the set of orders O in WAP1 is {A1, B1} and the set of wafers W consists of all wafers with wafer type 1.

WAP1 WAP2 WAP3 CWAP1 CWAP2 Single (C)WAP A1 B1B2 C2D2 D3E4 F4 E5 F5 X0 order

Batch of wafers 1 2 3 4 5 Y from type Y

Figure 10: Schematic overview of the WAPs and CWAPs corresponding to the filtered matching groups of Figure 7, resulting from planned orders in Table 1 and wafers in Table 2.

Matching group G2 is a class-constrained group and can be formulated as a CWAP or a FCWAP. Recall that, to mimic the current way of working of the back-end facilities of Nexperia, the problems are formulated as CWAPs. To explore the potential gains of using a different allocation policy in the future compared to the current policy, the problems are formulated as FCWAPs. In case of a CWAP formulation, it is very similar to the WAP formulation, resulting in CWAP1 and CWAP2 of Figure 10. In case of a FCWAP formulation, the set of items which can be allocated individually to orders does not consist of complete wafers as in the WAP and CWAP. Instead, each group of dies from the same class on one wafer is a separate item in the FCWAP. For FCWAPs, an item is considered to be a group of dies from one wafer with the same die class. For instance, wafer W11 (see Table 2) is of type 4 and has dies from both classes 21 and 23. Therefore, it will be treated as two separate items in the FCWAP formulation with according sizes. The batch of dies from class 21 are the first item and belong to 4.21 in Figure 11 and the batch of dies from class 23 are the second item and belong to 4.23. Thus, wafer W11 appears in two batches of items: 4.21 and 4.23. Order E4 can be filled with items from either 4.21 or 4.22, but does not necessarily need both. This order-wafer relation is marked with a dashed line in Figure 11. 17 WAP1 WAP2 WAP3 FCWAP1 FCWAP2 Single (FC)WAP X0 order A1 B1B2 C2D2 D3 E4 F4 E4 F4 Batch of wafers X from type Y 1 2 3 4.21 4.22 4.23 4.24 5.21 5.22 5.23 5.24 Batch of items X.0 from class 0 and type X

Figure 11: Schematic overview of the WAPs and FCWAPs corresponding to the filtered matching groups of Figure 7, resulting from planned orders in Table 1 and wafers in Table 2. CWAP1 and CWAP2 from Figure 10 are replaced by FCWAP1 and FCWAP2. In contrast to the CWAPs, the order-wafer relations which are dashed are optional, i.e. order E4 can be filled with items from class 21 and 22 but does not necessarily need both. An item is considered to be a group of dies from one wafer with the same die class.

5.2.4. Matching algorithm The matching algorithm phase solves the WAPs, CWAPs and FCWAPs with the proposed solution methods of Section 4. These solutions consists of orders with allocated wafers belonging to specific orders and will be translated to process orders in the next stage.

5.2.5. Translate to PPOs Finally the solutions from the matching algorithm have to be translated into process orders, which will be communicated to the downstream scheduling stages in the back-end facility. Each unique product type creates one process order, and the decomposed parts will be merged again. For example, orders B1 and B2 from the WAP formulation, are merged into one process order which contains the corresponding planned orders and both the allocated wafers from B1 and B2.

5.3. Assembly line configuration The machine configuration of the assembly line on which the ICs are assembled, influences the wafer allocation process. Therefore, some background information about the assembly lines and the influence it has on the wafer allocation, will be given in this section. A schematic overview of the back-end processes is shown in Figure 12. Unassembled wafers, which are produced in the front-end fabs, arrive at the back-end assembly and test facility and are stored in a warehouse. Once a wafer is allocated to an order which is going to be produced, the wafer goes to the sawing phase. Sawing, also referred to as dicing, refers to the mechanical process by which the wafer is separated into individual dies. Subsequently, during die bonding, these dies are bonded on a (metal) support structure, the so-called lead frame. Wire bonding is the process of making interconnections between the semiconductor device (the die) and a specific location on the lead frame. Molding refers to the encapsulation of the device by a molding compound to protect it from the outside environment. At last, trim and form is the process where the individual leads of the leadframe are separated from the lead frame strip and where the device is mechanically formed in the specified shape.

Sawing Die Bonding Wire Bonding Molding Trim & Form

BIM line or STS line

Figure 12: Back-end assembly process consists of sawing, die bonding, wire bonding, molding. A part of it happens either on BIM-lines or on STS-machines.

For die bonding, wire bonding and moulding, two types of assembly processes are possible: (1) on strip- to-strip (STS) machines or (2) on a breakthrough-in-manufacturing line (BIM). STS machines are separate machines for each assembly process and one order will only be processed by one machine at the same time. The strips of leadframe are transported from one machine to another between each process. In contrast, a

18 BIM-line consists of multiple machines in series, which perform all three aforementioned processes, and a long roll of leadframe flows through all the machines in the BIM-line. An illustration of a BIM-line is shown in Figure 13. BIM-lines often contain multiple tracks of leadframe and multiple machines for each assembly step. For example, a frequently used configuration are four die bond machines, four wire bond machines and one mould machine in series.

EMC

DB Mould

Figure 13: Illustration of a BIM-line with die-bond (DB) machine, wire bond (WB) machine and moulding machine in series. On the DB the sawed wafer is loaded, on the WB a roll of wire is loaded and the Mould uses EMC-shielding material to form an encapsulation for the IC. The leadframe flows through all machines and is shown in the figure between each machine.

After sawing, wafers are loaded onto the die-bond machines, where each die is moved from the wafer and placed on the leadframe. Since there are multiple die-bond machines in a BIM-line, wafers have to be loaded on the assembly line in multiple places. Each machine places a die on a different location on the lead frame, as is shown in Figure 14. In this example, there are two tracks of leadframe and four die bond machines. A double-die product, indicated with one blue and one orange die per product, is assembled. The loading on each machine has to be balanced to avoid incomplete products or wasted leadframe. At Nexperia’s back-end facility there are BIM-lines with two or four die bond machines. Wafers can also be split in halves or in quarters to balance the machines’ loading. However, this lowers the overall production speed, since the halved or quartered wafers have to be replaced more frequently. Hence, if an order is assembled on a BIM-line, the wafer allocation process should not only consider the total required quantity, but also the BIM-line configuration. Currently, the planners who manually allocate the wafers, use following policy: for BIM-line orders two separate groups of wafers, such that total quantities of both groups match as good as possible, to improve balanced loading and restrain split wafers. Similar policy is used in the proposed solution methods in this work. However, it is acknowledged that there might be potentially more beneficial policies to deal with this.

19 DB DB DB DB

1 2 3 4

Figure 14: Illustration of four die-bond (DB) machines in series. Two tracks of leadframe flow through all the machines. A double die-product, illustrated with one blue and one orange die, is assembled on both tracks.

Certain FG-types are always produced on STS lines and others always on BIM lines. In case of a BIM- line, this is taken into account at the wafer allocation process in following manner. It is ensured that each BIM-line order type consists of two separate orders in the (C)WAP formulations. For example, if order A and B in Figure 10 are BIM-line orders, this will result in Figure 15. Initially, order type A consisted of just one order in the WAP formulations: A1. Therefore, another A1 order is created in Figure 15, and each A1 order has half of the quantity of the original A1 order. Order type B already consisted of two orders in the WAPs: B1 and B2. In case of a BIM-line configuration of 2 die-bond machines, each separate order can be used to load one single machine. In case of 4 die-bond machines, each order has to be balanced over 2 machines. Either way, for the example of two orders A1, balanced machine loading is improved compared to just considering one single order A1. Also, this way will mostly resemble the current way of work of the planners.

WAP1 WAP2 WAP3 CWAP1 CWAP2 Single (C)WAP A1 A1 B1B2 C2D2 D3E4 F4 E5 F5 X0 order

Batch of wafers 1 2 3 4 5 Y from type Y

Figure 15: Schematic overview of the same WAPs and CWAPs as in Figure 10, but now order A and B have to be produced on a BIM-line. Originally order A has merely one order in the WAP formulation (A1) , each having halve of the total quantity of the original order A1.

6. Computational results

This section discusses the computational results of the proposed solution methods based on several data sets of a back-end assembly and test facility of Nexperia. For a fair comparison, all algorithms are coded in C# 6.0 and all experiments are run on a computer with an Intel Core i7-5600U processor running at 2.60 GHz and 8 GB of RAM memory. First, the size of the data instances and how this influences the solvability is discussed. Secondly, the performance of all solution methods are analyzed by comparing the resulting percentage of overallocation. Thirdly, the computation time of all algorithms is evaluated. Finally, two similar data sets are formulated both as CWAPs and FCWAPs, and the resulting performances are compared.

20 6.1. Data instances Since the bin covering problem is considered to be NP-complete, the set of all possible solutions – the so-called solution space – greatly influences computational time and solvability. The data instances of these experiments are real-life production data sets which consist of all the planned orders and wafers from one entire back-end facility. One data set contains the orders of one week, since the facility currently receives the planned orders on a weekly frequency. The experiments are done on 4 different data sets of subsequent weeks: 39 to 42. One average weekly data set consists of approximately 300 orders and 20.000 wafers in total, which can be decomposed into approximately 80 disjoint groups. Each disjoint group is either class-constrained, if it contains orders which need specific die-classes, or non-class-constrained if it contains none of these orders. A non-class-constrained groups is formulated as a WAP and class-constrained group can be formulated as either a CWAP or a FCWAP. The disjoint groups differ greatly in size, the largest groups have up to 15 orders and 2000 wafers, whereas the smallest groups have only 1 order and 40 wafers. Out of the 80 disjoint groups, roughly 70 groups are non-class-constrained and 10 groups are class-constrained. The size of each problem, and thus the solvability, is mainly influenced by following three factors: (1) the number of wafers, (2) the number of orders and (3) the demand/supply ratio. A larger number of wafers and orders, increases the number of all possible allocation configurations and therefore it makes the problem bigger. The demand/supply ratio is defined as the total requested die quantity divided by the sum of all available wafer quantities. Due to the order selection in the pre-processing of the data, it is ensured that the demand is always smaller than the supply, i.e. this ratio is between zero and one. If this ratio is closer to one, the set of all feasible solutions is smaller and the problems can generally be solved in less computation time. Similarly, if the ratio is closer to zero, the problem gets bigger and requires more computation time. To make a fair comparison between the different algorithms, the planned orders in the data sets are selected such that all the algorithms are able to find feasible solutions for the same set of planned orders. This is done by running the complete back-end scheduling flow for each algorithm as in Figure 5, which includes the order selection heuristic explained in Section 5.2.2. Then, the selected planned orders of each run are compared and the smallest set of planned orders is chosen. This chosen set of planned orders is then used for all solution methods.

6.2. Parameter settings For the experiments in this work, the parameter settings shown in Table 6.2 are used. The parameters for MS-Swap are chosen based on preliminary experiments, showing that these settings yield good results within acceptable computational time for these data sets. The purpose of each of the MS-Swap’s parameters is elaborately discussed in Section 4.3. For the Gurobi solver, all parameters are set to default, as recommended in [16], except for Tlim and Ifeas. Tlim is chosen to be 60 seconds per disjoint group, such that the computational time is acceptable for this application. For many groups Gurobi found the optimal solution within Tlim and for the groups it did not find an optimal solution within Tlim, increasing the available time did often not yield better objective values. Instead, it used the extra time to prove optimality, i.e. the lower bound was increased, while the incumbent remained constant. Furthermore, an integrality constraint is satisfied in Gurobi if the variable’s value is less than Ifeas from the nearest integer value.. This tolerance is chosen to be tight enough (1e-8), such that the value of the found objective did correspond to the same value of the calculated overallocation using the allocated wafers. Loosening this tolerance slightly reduces the runtime, but allows larger integrality violations, which caused errors in the objective.

21 Parameter settings Algorithm Parameter Function Value The maximum increase in number of wafers in K 3 each order at initialization. MS-Swap P Acceptance probability of 0-cost moves. 0.5 Number of iterations through the sequence R 2 of local search and 0-cost moves. Limits the total runtime (in seconds) of the T 60 Gurobi lim solver per disjoint group. Integrality restriction on a variable is considered Ifeas satisfied when the variable’s value is less than 1e-8 Ifeas from the nearest integer value.

Table 3: Parameter settings for MS-Swap and Gurobi Optimizer.

6.3. Overallocation performance As formulated in the linear programming problems, the objective is to minimize overallocation. Over- allocation is defined as the portion of the total allocated dies, which will result in overproduction and is computed according to equation (11) where the allocated die quantity is the sum of dies on each allocated wafer and the required die quantity is the sum of requested die quantities of all the orders. Allocated die quantity − Required die quantity Overallocation (OA) = · 100% (11) Allocated die quantity Table 2 shows the performance results in terms of overallocation of all the proposed solution methods. The actual overallocation at Nexperia’s back-end facility resulting from the current practice of wafer alloca- tion is shown under Manual. For the Gurobi Optimizer, the Incumbent (Inc) and the Lower Bound (LB) are shown. The incumbent is the best feasible solution found within the set time limit. The bound LB is a lower bound on the optimal objective. The difference between the incumbent and the lower bound is known as the Gap. Thus, if the gap is zero, then the optimal solution is found. For an elaborate description of the branch- and-bound algorithm used by Gurobi, the reader is referred to [16]. Three different results are shown: only considering the non-class constrained groups (WAPs), only considering the non-class-constrained groups (CWAPs) and considering both groups, i.e. the complete data set (All: WAPs and CWAPs). Since the FFD and FIFO-IEG are suitable for solely WAPs, there are no results shown for these algorithms in the CWAPs and All part. Furthermore, the manual performance could only be obtained of the complete data set, because the decomposition into WAPs and CWAPs was difficult to make with the obtained data sets of current practice. Several observations can be made from these results:

– MS-Swap clearly outperforms both FFD and FIFO-IEG in terms of mean OA, but also for every individual disjoint group. This result was expected, since FFD and FIFO-IEG are relatively simple heuristics, which fill orders sequentially until the order is filled. In contrast, MS-Swap considers all the orders at the same time and also attempts to find improvements after all orders are already filled. Therefore, MS-Swap is computationally more expensive, but will yield better results. – In many disjoint groups, Gurobi found the optimal solution, and in groups where it did not find the optimal solution, the gap between the incumbent and lower bound was often very small. Therefore, the obtained total OA by Gurobi was nearly optimal. – The performance of MS-Swap nearly matches Gurobi’s performance and for many disjoint groups it did find the exact same objective. This shows that both parts – initialization and swap moves – of

2Hided for confidentiality reasons. 22 Overallocation performance of all algorithms Gurobi Manual FFD FIFO-IEG MS-Swap Inc LB Week Req die qty OA (%) OA (%) OA (%) OA (%) OA (%) OA (%) WAPs 39 [...]2 - 6.1603 6.1163 3.7731 3.7730 3.7730 40 [...]2 - 6.2068 5.5635 3.2773 3.2605 3.2605 41 [...]2 - 6.2351 6.2037 3.6831 3.6707 3.6704 42 [...]2 - 6.2359 6.1553 4.0572 4.0575 4.0572

Mean [...]2 - 6.2095 6.0097 3.6977 3.6904 3.6903 CWAPs 39 [...]2 - - - 7.6642 7.6506 7.6505 40 [...]2 - - - 6.3741 6.2880 6.2878 41 [...]2 - - - 15.9545 15.9519 15.9517 42 [...]2 - - - 20.7012 20.6976 20.6975

Mean [...]2 - - - 12.6735 12.6470 12.6470 All: WAPs and CWAPs 39 [...]2 [...]2 - - 3.9737 3.9728 3.9727 40 [...]2 [...]2 - - 3.8004 3.6788 3.6788 41 [...]2 [...]2 - - 5.5364 5.5259 5.3754 42 [...]2 [...]2 - - 5.9748 5.9744 5.7689

Mean [...]2 [...]2 - - 4.8213 4.7880 4.6990

Table 4: The overallocation performance (OA) of all algorithms: First-Fit-Decreasing (FFD), First-In-First-Out with Improved End Game (FIFO-IEG), MS-Swap and the Gurobi solver. For Gurobi, both the incumbent (Inc) and the lower bound (LB) are shown. Manual represents the current practice at Nexperia’s back-end facility. Three results are shown: only for the non-class-constrained groups (WAPs), only for the class-constrained groups (CWAPs) and for both groups, i.e. the complete data set (All: WAPs and CWAPs). The required die quantity (Req die qty) is the sum of requested die quantities of all the orders in that data set.

23 the MS-Swap algorithm perform well. Recall that swap moves inherently do not alter the number of wafers allocated to each order. Hence, if MS-Swap finds the optimal solution this means that the set of initial solutions which are generated by MS-Swap contains a solution which has the same number of wafers in each order as the optimal solution. Subsequently, the swap moves successfully improve this initial solution towards the optimal objective.

– The difference between MS-Swap and Gurobi compared to Manual is substantial, more than [...]2 difference in terms of mean OA. Thus, there are significant potential gains possible for Nexperia by implementing the method of wafer allocation proposed in this work. This difference can be explained by several elements of the manual allocation done by the planners at the back-end facility. First of all, the proposed solution method combines planned orders (see Section 5.2.1) generally into bigger batches than is done manually, each one of these batches is a single order in the (C)WAP formulation. A few big orders will cause less cumulative overallocation than many small orders. Furthermore, the planners allocate the orders sequentially with no knowledge on the yet-to-allocate orders. Finally, it is often too difficult (or very labor-intensive) to find the optimal wafer allocation manually, since the number of possible allocation combinations is extensive. For this reason, planners choose an allocation where the OA is acceptably low, but it can still be far from the optimal allocation.

6.4. Computation time The computation time per algorithm is shown in Table 6.4 for the data set of week 41. The other weeks have similar performance in terms of computation time. The first observation is that the heuristics FFD and FIFO-IEG need significantly less time to solve the problems than MS-Swap and Gurobi. This is as expected, since FFD and FIFO-IEG are simple heuristics, which are relatively computational inexpensive compared to MS-Swap or the Gurobi solver. Furthermore, the MS-Swap algorithm requires more time than Gurobi, but one should not that in this work, the main focus was on the performance of the proposed MS-Swap and not on the computational efficiency. Also, recall that the time limit Tlim of Gurobi is set to 60 seconds per disjoint group. Increasing this time will yield more computation time. However, the overallocation performance will (practically) not improve by doing so. Finally, in terms of computation time, all algorithms are well suited for this application. The wafer allocation scheduling process for an entire week of the complete back-end facility takes less than 5 minutes for MS-Swap and even less for the other algorithms. This is very acceptable, since it only has to run once a week. Even if the scheduling process has to run on a daily basis, the computation time would still be tolerable.

Computation time FFD FIFO-IEG MS-Swap Gurobi (s) (s) (s) (s) WAPs 0.7 2.6 225.8 113.7 CWAPs - - 23.2 5.9 Total - - 249.0 119.6

Table 5: Computation time of each algorithm for the data set of week 41.

6.5. CWAP versus FCWAP Using two identical filtered data sets, merely containing the class-constrained groups, the first one is formulated as CWAPs and the second one as FCWAPs. Both are solved with Gurobi and the results are shown in table 6.5. Recall that in the FCWAP formulation each group of dies corresponding to a specific die class is considered to be an individual item to allocate, as opposed to allocating complete wafers in the CWAP. For example, a wafer containing dies from three different classes, is considered to be one item to allocate in the CWAP formulation, but will be three separate items in the FCWAP formulation. Therefore, compared to CWAPs there are three main differences in terms of the available items: (1) FCWAPs will 24 contain more items, (2) each item will be smaller in size and (3) each item will contain dies from one die class only. The results show that the FCWAP formulations yield a significant better performance than CWAP formulations with a mean OA which is almost 7% lower. This is mainly caused by the three previously mentioned differences in items to allocate. The first difference of having more items, gives more possible allocation configurations and therefore, it is easier to find a lower objective of overallocation. The second difference that the items are smaller (and the orders are of similar size), will also yield more allocation configurations with less overallocation. The third difference of having dies from one die class only in each item, makes each allocated item completely utilizable. In contrast, in CWAPs, partial wafers can not be used for their corresponding order if the wafer contains dies from die classes not feasible for that order. The results also show that Gurobi has more difficulties in finding the optimal solution within the time limit as set for the FCWAPs, since the average Gap is significantly larger. This is mainly due to the increased number of available items, which gives more possible allocation configurations and therefore the solution space of FCWAPs is bigger than for CWAPs.

Overallocation performance of CWAPs versus FCWAPs CWAPs FCWAPs Gurobi Gurobi Nr of Inc Lb Gap Nr of Inc Lb Gap Req die qty items OA (%) OA (%) (%) items OA (%) OA (%) (%) 39 [...]2 1,074 7.6506 7.6504 0.0021 1,851 3.2373 2.2885 29.3079 40 [...]2 1,777 6.2880 6.2878 0.0032 2,652 0.8896 0.2992 66.3707 41 [...]2 1,985 15.9519 15.9517 0.0008 3,026 8.7705 5.4515 37.8432 42 [...]2 1,914 20.6976 20.6975 0.0006 2,836 10.4637 8.7960 15.9377

Mean [...]2 1,688 12.6470 12.6469 0.0017 2,591 5.8403 4.2088 37.3649

Table 6: Comparison in overallocation (OA) performance between CWAPs and FCWAPs. The data sets consist of all class- constrained orders of that week. Both are solved with the Gurbobi solver, using the same parameter settings. The required die quantity (Req die qty) is the sum of requested die quantities of all the orders and the Nr of items is the sum of available items. For CWAPs, an item corresponds to a complete wafer, for FCWAPs, an item is considered to be a group of dies from one wafer with the same die class. Gurobi is used to solve the problems and the incumbent (Inc), lower bound (LB) and the Gap are shown.

7. Conclusions

In this work, a solution method is presented, which successfully solves the problem of allocating wafers to customer orders prior to assembly at a semiconductor production facility. The objective of the solution method is minimizing the overallocation. This is important for the industrial application, because the overproduced products have to be stored as inventory and can be sold to future customer orders. Some products even expire and have to be disposed. Also, less overproduction implies that more products are made which can be sold immediately , in other words, the effective capacity increases. Thus, more customer orders will be delivered on time. All in all, the reduction of overproduced products has following three main advantages: (1) less inventory has to be stored, (2) less material and time is wasted on products which will be disposed and (3) more customer orders can be delivered on time. The considered problem includes an additional element which has not been taken into account in previous studies. That is, some of the wafers contain dies from several different die classes used for multiple different end products. This makes the problem more complex, because if a wafer is allocated to an order, the complete wafer has to be manufactured, even if it contains dies from classes which can not be used for that order. The dies from infeasible classes will therefore be overproduction. In this paper, the complete problem from the real-world, consisting of batches of orders and wafers which have to be produced in a time frame of a week, is decomposed in many smaller disjoint groups which are solved one at a time. Some groups are

25 class-constrained, i.e. the group contains wafers with dies from different classes, or non-class constrained, i.e. the group solely contains wafers where all dies are from the same class. The non-class constrained groups are formulated as WAPs, which is the well-studied problem without the additional element. For the class-constrained groups, a novel model formulation, the CWAP, is introduced, which is an extension of the WAP to incorporate different classes of dies. Both problem formulations are ILPs. No heuristic existed in the literature to solve the CWAP and therefore a novel heuristic is proposed, which uses multiple initial solutions complemented with a smart swapping mechanism, called the Multi-Start Swap (MS-Swap) algorithm. Since MS-Swap is applicable to both WAPs and CWAPs, it is benchmarked against existing heuristics (the FFD and FIFO-IEG policy) for WAPs and with a commercial optimization solver, Gurobi, for both WAPs and CWAPs. In experiments it is shown that, in terms of overallocation performance, MS-Swap outperformed both existing heuristics but even more so the current practice at Nexperia’s back- end facilities. Also, by using Gurobi as a benchmark, it is shown that, for the data instances used in these experiments, the solution resulting from MS-Swap was nearly optimal. The average overallocation at Nexperia’s back-end facilities with current practice was approximately 8.2% and can be decreased to approximately [...]3 using MS-Swap or Gurobi, which means that the overproduction is reduced by roughly [...]3. In terms of computation time, Gurobi outperformed MS-Swap in the considered test cases. However, both solution methods are suitable for the practical application, since the corresponding computation times are sufficiently fast with respect to the wafer allocation process which only needs to be done on a weekly (or possibly daily) basis. For the industrial application, MS-Swap might be more attractive than a commercial solution such as Gurobi, because (1) it is cheaper, (2) it is not dependent on a ‘black-box’ solver from an external party and (3) there is still improvement possible for the computation time of MS-Swap, since this work was mainly focused on the overallocation performance. Furthermore, it is investigated what the potential benefits would be, in terms of overallocation, if it is possible to allocate groups of dies (of different classes) from a single wafer to different orders, as opposed to allocating complete wafers to at most one order. Therefore, the CWAP formulation is extended to the FCWAP formulation which is a more flexible allocation policy which might be used in the future. FCWAP is compared to CWAP with similar data sets and both are solved with Gurobi. The experiments show that the CWAP may significantly improve the overallocation performance, with an average overallocation of 12.6% for CWAPs versus 5.8% for FCWAPs. Since the FCWAP considers groups of dies as to-be-allocated items, instead of entire wafers, there are more items to allocate than in CWAP. This increases the problem size, and therefore computation time gets longer and it is more difficult to solve it to optimality. Also, it is acknowledged that implementing the more flexible allocation policy of FCWAP, creates some practical challenges in different areas of the back-end facility.

8. Recommendations

The main focus in this work was on overallocation performance, not on computation time. Therefore, the proposed MS-Swap algorithm may be further enhanced in terms of computational efficiency. Additionally, it would be interesting to test the MS-Swap algorithm on more data sets with a large variation in problem sizes. This way, one can examine the scalability of the algorithm and how this influences both the quality of the solutions as well as the computational costs. Furthermore, the parameters of the MS-Swap algorithm are set manually through trial-and-error. As a result, the chosen parameter setting in this work, may not give desirable results in terms of computational time or optimality for other data sets with different wafer and order sizes. Therefore, a more structural way to calibrate these parameters may be beneficial, e.g. by means of a Design of Experiments (DOE). Considering FCWAPs, the scope of this project was merely to explore potential benefits of this allocation policy and as such these problems have only been solved using Gurobi. In future work, a heuristic may be proposed to solve FCWAP, which can either be an extension of the MS-Swap algorithm or a completely

3Hided for confidentiality reasons. 26 different heuristic. Also, attempts can be made, by tuning Gurobi’s parameter settings, to find solutions which are closer to optimality when using Gurobi. From a practical point of view, it would be interesting to examine whether the potential benefits of implementing the FCWAP instead of the current CWAP, outweigh the practical challenges. One of the challenges is that, since wafers have to be assembled completely once they are loaded onto the machine, multiple customer orders must be produced simultaneously on one machine and finished goods have to be sorted after assembly. Additionally, for the BIM assembly lines, it may be valuable to give more attention to balanced machine loading as opposed to solely minimizing total overallocation. This can be incorporated, for example, by using multi-objective optimization where a measure for both balancing and overallocation are included in the objective function.

References

[1] Semiconductor industry association (sia), global billings report history, https://www.semiconductors.org/resources/, accessed: 2018-09-25. [2] F. Frederix, Planning and scheduling multi-site semiconductor production chains: a survey of needs, current practices and integration issues, 1996. [3] M. R. Garey, D. S. Johnson, Computers and Intractability; A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, USA, 1990. [4] E. E. Bischoff, M. D. Marriott, A comparative evaluation of heuristics for container loading, European Journal of Opera- tional Research 44 (2) (1990) 267 – 276, cutting and Packing. doi:https://doi.org/10.1016/0377-2217(90)90362-F. [5] E. G. Coffman Jr., J. Csirik, G. Galambos, S. Martello, D. Vigo, Bin Packing Approximation Algorithms: Survey and Classification, Springer New York, New York, NY, 2013, pp. 455–531. doi:10.1007/978-1-4419-7997-1_35. [6] L. M¨onch, R. Uzsoy, J. W. Fowler, A survey of semiconductor supply chain models part iii: master planning, production planning, and demand fulfilment, International Journal of Production Research 56 (13) (2018) 4565–4584. doi:10.1080/ 00207543.2017.1401234. [7] H. Meyr, M. Wagner, J. Rohde, Structure of Advanced Planning Systems, Springer Berlin Heidelberg, Berlin, Heidelberg, 2015, pp. 99–106. doi:10.1007/978-3-642-55309-7_5. [8] K. Knutson, K. Kempf, J. Fowler, M. Carlyle, Lot-to-order matching for a semiconductor assembly and test facility, IIE Transactions 31 (11) (1999) 1103–1111. doi:10.1080/07408179908969911. [9] J. Fowler, K. Knutson, M. Carlyle, Comparison and evaluation of lot-to-order matching policies for a semiconductor assem- bly and test facility, International Journal of Production Research 38 (8) (2000) 1841–1853. doi:10.1080/002075400188627. [10] M. Carlyle, K. Knutson, J. Fowler, Correspondence, Bin covering algorithms in the second stage of the lot to order matching problem, Journal of the Operational Research Society 52 (11) (2001) 1232–1243. [11] T. G. Boushell, J. W. Fowler, A. B. Keha, K. R. Knutson, D. C. Montgomery, Evaluation of heuristics for a class- constrained lot-to-order matching problem in semiconductor manufacturing, International Journal of Production Research 46 (12) (2008) 3143–3166. doi:10.1080/00207540601001650. [12] T. S. Ng, Y. Sun, J. Fowler, Semiconductor lot allocation using robust optimization, European Journal of Operational Research 205 (3) (2010) 557 – 570. doi:https://doi.org/10.1016/j.ejor.2010.01.021. [13] Y. Sun, J. W. Fowler, D. L. Shunk, Policies for allocating product lots to customer orders in semiconductor manufacturing supply chains, Production Planning & Control 22 (1) (2011) 69–80. doi:10.1080/09537287.2010.490020. [14] S. Assmann, D. Johnson, D. Kleitman, J.-T. Leung, On a dual version of the one-dimensional bin packing problem, Journal of Algorithms 5 (4) (1984) 502 – 525. doi:https://doi.org/10.1016/0196-6774(84)90004-X. [15] R. Capua, Y. Frota, L. S. Ochi, T. Vidal, A study on exponential-size neighborhoods for the bin packing problem with conflicts, Journal of Heuristics 24 (4) (2018) 667–695. doi:10.1007/s10732-018-9372-2. [16] Gurobi optimization,gurobi optimizer reference manual, 2018, URL: http://www. gurobi. com. [17] J. Adan, , A. Akcay, R. Van den Dobbelsteen, J. Stokkermans, A hybrid genetic algorithm for parallel machine scheduling at semiconductor back-end production., in: ICAPS, 2018, pp. 298–302. [18] B. S. Baker, A new proof for the first-fit decreasing bin-packing algorithm, Journal of Algorithms 6 (1) (1985) 49 – 70. doi:https://doi.org/10.1016/0196-6774(85)90018-5.

Author biographies

Patrick Deenen is a M.Sc. student at the Department of Mechanical Engineering of Eindhoven University of Technology, following the Master’s program Manufacturing Systems Engineering. He conducted this re- search as part of his Master’s thesis combined with an internship at Nexperia. His current research interests are in the area of modeling, design and control of manufacturing systems, manufacturing optimization and supply chain. His email address is [email protected].

27 Appendix A. Database architecture To not interfere with the back-end facility, the required data was obtained on a daily basis and saved on a stand-alone database. This database was used to carry out the experiments. Besides the planned orders and wafer inventory, it also contained all other necessary information to allocate the wafers in a correct manner. An schematic overview of the data flow can be seen in Figure A.17. The majority of the data is obtained from a database called SAP, which is an Enterprise Resource Program (ERP). Other information has been obtained manually from the planners on-site. All data is loaded into the stand-alone database, for which MySQL is used. MySQL is an open source relational database management system. This database interacts with the Wafermatcher, which selects and combines planned orders, and allocates to these orders resulting in preprocess orders.

SAP .csv files MySQL Database Wafermatcher Preprocess orders Manual Excel files

Figure A.16: Overview of the data flow.

The enhanced entity-relationship (EER) diagram of the data model is shown in Figure A.17. This diagram shows the relation between the different entities, which can either be identifying (solid lines) or non-identifying (dashed lines). In this model, identifying relations are mandatory, while non-identifying are optional. Each data entity is explained separately next. - Process orders are the final orders which are sent to production. Therefore, these orders are used to analyze the performance of current practice at the back-end facility. One process order contains multiple planned orders and a planned order can be split over multiple process orders. Thus, planned orders and process orders have a m:n relationship. To map these relations in the database the inter- mediate data entity plannedprocessLink is made. In similar way, process orders and wafers have a 1:m relationship and processwaferLink maps the relations between these two entities. - Planned orders are the customer orders received by the back-end site on a weekly basis for the products which have to assembled. These orders contain information about the FG (finished good) type, the requested quantity and the due date. - Wafers contain information about all wafers available the inventory at that time. Each wafer has a linked item in waferpretestdata which contains the die quantity in each separate class, in case the wafer is part of a class-constrained matching group. The size of the wafer is saved in wafersizes and it used to determine on which BIM line is can be manufactured. Wafers with different sizes can therefore not be combined in the same process order. - Product information is an independent entity and contains all information per FG type, such as, which wafer types have to be used, how many dies per product are used, what the estimated scrap factor is and whether the products needs dies from specific classes. - Packing and orientation is used to determine which planned orders can be combined in one process order. Planned orders for the same FG type can always be combined. In some cases different FG types can also be combined, if the die orientation is the same. That information is provided by this data entity. To make a fair comparison between current practice and the Wafermatcher presented in this work, all process orders are considered per week. These process orders contain planned orders with allocated wafers. From this, the overallocation performance can be analyzed. Then, similar planned orders, together with all wafers available at the inventory during that week, are used as the input for the Wafermatcher. Finally, these preprocess orders given by the Wafermatcher also yield an overallocation performance and this can be compared to the overallocation of current practice. 28 Figure A.17: An overview of the enhanced entity-relationship (EER) diagram in MySQL.

29