RapidIO® Interconnect for Integrated DeviceTechnology Servers and Supercomputing

ANALOG AND RF | INTERFACE AND CONNECTIVITY | MEMORY AND LOGIC | POWER MANAGEMENT | TIMING AND SYNCHRONIZATION

RAPIDIO FOR AND SUPERCOMPUTING • Scalability - Peer-to-peer, “any-to-any” topologies from 1Gbps to 20 Gbps with native processor interface - Mesh, star, dual star, hypercube, etc. - Scales to 64k processing nodes, 66 bit memory addressing - 3-layer protocol terminated in hardware with no software intervention - Direct processor interface up to 20 Gbps with NO NIC - Smallest form factor with 1/10th footprint per Gflop in ARM based server vs. x 86 with NIC. RapidIO for Multi Processor Systems • Latency - 100 ns cut through latency for switches RapidIO is the interconnect that was developed for peer-to-peer inter-processor communication - End-to-end sub microsecond packet termination between devices on a board, between boards across a and between chassis through latency with reliable transmission, orders of cabling. RapidIO is optimized for low latency, low power interconnect in embedded systems where magnitude better than ethernet thousands of processors need to communicate in a system with “any-to-any” traffic. RapidIO’s largest • Power market was in wireless bases station where it is used to connect large number of processing nodes - Typical power approximately 300 mW per with up to 20 Gbps interconnect directly on processors without NICs, adaptors and software interven- 10 Gbps in switch tion. This provides a uniform interconnect inside the system in very tight small form factors. All of these - No additional power from NICs meaning attributes have emerged as major requirements in both servers and supercomputing systems today. approximately 1/10th the power required for RapidIO also addresses the overall energy requirements of both data centers and supercomputing. scale out with Ethernet systems requiring NICs - Lowest power per payload bit vs. other RapidIO: the Ideal Scalable Interconnect for Servers and Super Computing interconnect protocols Historically, a server was a connected to an ethernet network with network interface con- troller. Over time this LAN topology was pushed inside the rack with large quantities of processors all PROTOCOL COMPARISON connected to a top-of-rack switch through NIC’s. This in effect collapses a LAN based topology into a rack, but carries all the drawbacks of the historic architecture. RapidIO has solved the multi processor 48 SRIO 10xN 4 x 10.3125G problem by addressing the interconnect problem from the processor to processor angle rather than the SRIO 4 x 6.25G 40 PCI Express 2 4 x 5G processor to “network” angle. RapidIO-connected servers and can use both back- 10G Ethernet UDP plane based and top-of-rack-based switching with latencies as low as 100ns through switches and less 16 than 1 microsecond end-to-end between processing nodes.

18 The New Wave: , ARM and PowerPC based Servers with RapidIO Bandwidth (Gbps ) 16 Servers can be designed with processors from all vendors, either with native RapidIO interface or with external connect with IDT PCIe® to S-RIO bridging devices. ARM and PowerPC based processors are 8 available in the industry with 20 Gbps RapidIO interfaces. This allows for highly dense scalable serv-

0 er systems with low power and small form factors for x86 based RapidIO servers. Supercomputing 110 100 1000 10000 PDU Size (Bytes) systems based on RapidIO and ARM processors are leading the industry for energy efficiency with Up to 20 Gbps per port with native processor products that are as high as twice the energy efficiency of the top tier of the Green 500. interface • Highest protocol efficiency in embedded systems Interconnect: Scalability-Latency-Hardware Termination with 94% payload versus header efficiency HARDWARE GUARANTEED • Serial RapidIO standard supports arbitrary system SCALABILITY LOW LATENCY TERMINATED DELIVERY topology with true peer-to-peer networking Ethernet • Twice the performance per link compared to Ethernet PCIe PCIe 10 Gb Ethernet in s/w only • RapidIO messaging support for transfers of large blocks of data, superior to PCIe and 10 GbE in target applications RapidIO interconnect combines the best attributes of PCIe and Ethernet in a multi-processor fabric

IDT | INTEGRATED DEVICE TECHNOLOGY RAPIDIO FOR SERVERS AND SUPER COMPUTING PRODUCT BRIEF 1 RapidIO® Interconnect for Servers and Supercomputing Integrated DeviceTechnology ANALOG AND RF | INTERFACE AND CONNECTIVITY | MEMORY AND LOGIC | POWER MANAGEMENT | TIMING AND SYNCHRONIZATION

RAPIDIO GEN2 FEATURES • 20 Gbps per port with native Processor interface on integrated SoC’s • 300 mW per 10 Gbps PCIe- S-RIO X86 NIC CPU • 2W for PCIe2 to S-RIO2 NIC Server • Production switching and bridging porfolio with RapidIO over 6 million devices shipped connecting over Switch PPC 30 million processing nodes CPU • 100ns cut through latency through switches ARM CPU • Sub microsecond latency for end-to-end transactions 40Gbps S-RIO • 100 cm long reach per lane over 2 connector Per port to front panel across @ 6.25 Gbaud • Top-of-rack scalable RapidIO switch devices available from industry with 20 Gbps per port Scalable Server Design with multiple processor options: X86, PowerPC, ARM • Built-in reliable transmission • Extensive portfolio of switches and bridging products in production.

RAPIDIO 10xN TECHNOLOGY ENHANCEMENTS

ARM ARM ARM ARM • 40 Gbps per port with native Processor interface CPU CPU CPU CPU on integrated SoC’s ARM ARM RapidIO • Large Lane Count 40 Gbps backplane switching CPU CPU Backplane ARM ARM • PCIe 3 to S-RIO 10xN NICs CPU RAPIDIO CPU Switch ARM SWITCH ARM 20-40Gbps • 100 cm long reach over 2 connector across CPU CPU backplanes @ 10.3125 Gbaud per Port ARM 40Gbps S-RIO ARM CPU CPU • 64/67 encoding for greater efficiency over Per port to front panel ARM ARM ARM ARM 8b/10b encoding CPU CPU CPU CPU TARGET APPLICATIONS ! • Super Computer ARM based Server with Rapid IO • Blade Server • Micro Server RapidIO vs. Ethernet Processor Access • Top-of-Rack RapidIO switching

• X86, ARM, PowerPC based servers PCI Express Gen2@ 10Gb Ethernet Ethernet Processor PCI Express South 16Gbps Ethernet LAN X86 Gen2 Bridge NIC Interconnect 35 x 35 27 X 27 25 x 25 RapidIO vs. Ethernet Processor Acccess Form Factor 10x

Integrated Long Latency Path PCI Express Rapid IO 10 Gb PCI Express Gen2 @ 16 Ethernet Latency Board IncrementalEt hInterconnecternet Ethernet Processor 20G Gbpsen2 South DensityGbps Discrete Power LAN Rapid IO (ns) Direct Processor X86 RapidIO Bridge factor Devices NIC(w) Interconnect Processor35x35 27x27 25x25 Interconnect ARM RapidIO Ethernet >1000 10x 2 ~10 Discover what IDT know-how Integrated can do for you: RapidForm IO Fact<100or 10x 1x 0 >0.25 Short Latency Path www.IDT.com/go/rapidio Footprint, latency, power comparisonLong Latency with Pax86th + Ethernet Server Latency Board Incremental Interconnect RapidIO 202 Gbps (ns) Density Discrete Power

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O factor Devices (W) Processor t Rapip dIO I a r Processor id g DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. AllA informationRM in thisp document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters e t

of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customerIn products.terc Theonn informationect contained herein is provided without representationRa or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied In Ethernet >1000 10x 2 ~10 warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs,F areor them propertyfa cof toIDT orr their1x respective third party owners. © Copyright 2010. All rights reserved. PB_RapidIO_SERVERS_REVA_0913 IDT | INTEGRATED DEVICE TECHNOLOGY RAPIDIO FORRap SERVERSidIO AND<10 SUPER0 1COMPUTINGx 0 PRODUCT >BRIEF0.25 2 Short Latency Path

This is why is pushing Ethernet out of the Box Too many adaptors, too much latency, too much power

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