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Crusoe Power Management CrusoeCrusoe PoPowerwer Management:Management: CuttingCutting x86x86 OperatingOperating PowerPower ThroughThrough LongRunLongRun MarcMarc FleischmannFleischmann Director,Director, LowLow PowerPower ProgramsPrograms TransmetaTransmeta CorporationCorporation Crusoe, LongRun and Code Morphing are trademarks of Transmeta Corp. Pentium, Pentium Pro, Pentium II and Pentium III 12th Hot Chips Symposium - August 15, 2000 are registered trademarks of Intel Corp. 1 OverviewOverview u Key Challenges for Mobile Computing u “Portability” (weight) and “Ease of Use” (battery life) u Power consumption is the key limiting factor u Solution - Crusoe Processor u Full compatibility with x86 power management model u Significantly lower power u LongRun u Transmeta’s new invention to drive power savings Ø Adaptive Power Control (performance on demand) Ø Advanced Thermal Control (thermal budget expansion) 12th Hot Chips Symposium - August 15, 2000 2 PoPowerwer DensityDensity TheThe FundamentalFundamental ProblemProblem 1000 Not too long to reach W/cm2 Nuclear Reactor 100 Surpassed Pentium III® Hot Plate Pentium II® 10 Pentium Pro® Pentium® i386 i486 1 1.5µ 1µ 0.7µ 0.5µ 0.35µ 0.25µ 0.18µ 0.13µ 0.1µ 0.07µ “Time” Source: Fred Pollack, Intel. New Microprocessor Challenges in the Coming Generations of CMOS Technologies, Micro32 12th Hot Chips Symposium - August 15, 2000 3 X86X86 PowerPower ManagementManagement StatesStates AA QuickQuick PrimerPrimer ACPI Definition Mobile x86 Mobile x86 Power States Solution Processor Advanced Communication and 650 / 500 MHz Power Interface Specification 1.6 / 1.35 V Normal (C0) • The CPU is actively executing instructions. 14.0 / 8.0 W AutoHALT (C1) • CPU executes a low power instruction (x86: HLT). 1.7 / 1.1 W • CPU kills internal clocks (driven by South Bridge Quick Start (C2) via STPCLK#). 1.3 / 0.8 W • CPU maintains cache coherence (caches must be snooping). • South Bridge kills external clock input to the CPU. • Deep Sleep (C3) Maximum power savings w/o losing CPU context. 0.5 / 0.3 W • System enforces cache coherence (caches don’t need to snoop). 12th Hot Chips Symposium - August 15, 2000 4 TheThe SolutionSolution -- IncreaseIncrease EfficiencyEfficiency × 22 × PPowerower == CCapacitanceapacitance ×VVoltageoltage ×FFrequencyrequency u Transmeta Innovation - Code Morphing Software (CMS) u Effect - Replace Millions of Logic Transistors with Software u … and transistors translate into capacitance u Benefit - Significantly Reduces Power Consumption of x86 Power States 12th Hot Chips Symposium - August 15, 2000 5 LongRunLongRun AdaptiveAdaptive PowerPower ControlControl MaximizeMaximize BatteryBattery LifeLife WithWith PerformancePerformance onon DemandDemand 2 ×× 2 ×× Watt 133 MHz, 3.3 V Power = c v f 6.0 Power = c v f 125 MHz, 2.5 V 633 MHz, 1.6 V 5.0 u Dynamically adapt both 4.0 frequency and voltage to Linear: I/O (DDR, SDRAM) performance demands 3.0 u Mechanisms in hardware 2.0 Ø Cubic: Fully programmable 1.0 Core + Northbridge u Policies in CMS 0.0 Normal 12.5% 25.0% 37.5% 50.0% 62.5% 75.0% 87.5% u Adapt f to demand SDR 0.5 0.4 0.4 0.3 0.2 0.2 0.2 0.2 u Reduce v proportionally DDR 0.5 0.4 0.4 0.3 0.3 0.3 0.3 0.3 Core+NB 5.5 3.8 2.3 1.7 1.3 1.0 1.0 1.0 Ø Cubic power savings! 12th Hot Chips Symposium - August 15, 2000 6 LongRunLongRun AdaptiveAdaptive PowerPower ControlControl vsvs.. TraditionalTraditional PowerPower ManagementManagement 633 MHz, 1.6 V 6 Crusoe TM5400 5 Power [W] 4 3 LongRun Normal ⇔⇔ Sleep alternation 2 300 MHz, 1.2 V 1 0 Normal 12.5% 25.0% 37.5% 50.0% 62.5% 75.0% 87.5% C3 Idle Time LongRun 6.0 4.2 2.7 2.0 1.6 1.4 1.4 1.4 1.4 Power C3 6.0 5.3 4.5 3.8 3.0 2.3 1.5 0.8 0.0 Notes 1 Power numbers include Northbridge 2 DDR-only configuration 12th Hot Chips Symposium - August 15, 2000 7 LongRunLongRun AdaptiveAdaptive PowerPower ControlControl CrusoeCrusoePowerPower ProfileProfile 6 Crusoe TM5400 5 Power [W] 4 3 LongRun 2 Normal ⇔⇔ Sleep alternation 1 0 Normal 12.5% 25.0% 37.5% 50.0% 62.5% 75.0% 87.5% C3 Idle Time TM5400 6.0 4.2 2.7 2.0 1.6 1.2 0.8 0.4 0.0 Power Notes 1 Power numbers include Northbridge 2 DDR-only configuration 12th Hot Chips Symposium - August 15, 2000 8 TheThe LongRunLongRun EffectEffect PowerPower ProfilesProfiles 16 A/C 650 MHz, 1.6 V 14 Conventional Multimedia (DVD) 12 Power Mobile x86 10 Battery > 4x [W] 500 MHz, 1.35 V 8 633 MHz, 1.6 V 6 4 300 MHz, 1.2 V Crusoe 2 TM5400 0 Normal 12.5% 25.0% 37.5% 50.0% 62.5% 75.0% 87.5% C3 TM5400+NB 6.0 4.2 2.7 2.0 1.6 1.2 0.8 0.4 0.0 A/C 16.0 14.2 12.4 10.6 8.8 6.9 5.1 3.3 1.5 Battery 10.0 8.6 7.2 5.8 4.3 2.9 1.5 Notes 1 Power numbers include Northbridge 2 DDR-only configuration 12th Hot Chips Symposium - August 15, 2000 9 SystemSystem ArchitectureArchitecture StandardStandard ApplicationsApplications NoNo changes changes required required Closed loop StandardStandard OperatingOperating SystemSystem NoNo changes changes required required Closed loop StandardStandard BIOSBIOS NoNo changes changes required required Closed loop CrusoeCrusoeTM5400TM5400 processorprocessor featuringfeaturing TransmetaTransmeta LongRunLongRuntechnologytechnology CodeCode Morphing Morphing software software monitors monitors system system activity activity and and dynamicallydynamically adapts adapts LongRun LongRun performance performance levels levels 12th Hot Chips Symposium - August 15, 2000 10 PerformancePerformance onon DemandDemand DutyDuty CycleCycle ððEffectiveEffective PerformancePerformance LevelLevel Performance 630 MHz LongRun: < 50% frequency reduction 330 MHz Sleep 50% duty cycle Residual Sleep states Power 6.0 W LongRun: > 50% power reduction 1.5 W 50mW 40mW Normal Sleep LongRun: Low voltage Sleep 12th Hot Chips Symposium - August 15, 2000 11 TransitionTransition DynamicsDynamics FastFast Frequency/VoltageFrequency/Voltage ScalingScaling Frequency 566 MHz 500 MHz Pseudo Deep Sleep: < 20 µ s Voltage 1.5 V 1.3 V ~ 20 µ s per step 0 µ s 100 µ s Time CMS/LongRun LongRun scales voltage asynchronously policy decision Stepping: > 1.3 V: 50mV, < 1.3 V: 25 mV; max. ramping time: < 300 µ s (1.6V to 1.1V) Crusoe resumes x86 execution LongRun trips clock change 12th Hot Chips Symposium - August 15, 2000 12 TransitionTransition DetailsDetails VoltageVoltage ScalingScaling u TM5400 Core Voltage is Fully Voltage Under Software Control 1.5 V u CMS directly controls voltage regulator pins (via internal processor register) 1.3 V u OEM configurable Interrupt-driven voltage regulator programming Ø CPU output pin/voltage mapping Ø Voltage settling interval Voltage u CMS Schedules Interrupts to Select Asynchronously Ramp Voltage VoltageVoltage RegulatorRegulator u Allows sustained x86 forward progress during voltage ramping Core Voltage 12th Hot Chips Symposium - August 15, 2000 13 TransitionTransition DetailsDetails FrequencyFrequency ScalingScaling --Establish/commitEstablish/commit controlcontrol ClockClock Control Control ShadowShadow Core: 400 [MHz] Clock Control PSR Core: 400 [MHz] Clock Control PCI:PCI: 3333 [MHz] [MHz] Core:Core: 400400 [MHz] [MHz] Data To PLL DDR:DDR: 100100 [MHz] [MHz] PCI:PCI: 3333 [MHz] [MHz] SDR:SDR: 6666 [MHz] [MHz] DDR:DDR: 100100 [MHz] [MHz] Commit:Commit: 00 SDR:SDR: 6666 [MHz] [MHz] EnableEnable EnableEnable PLLPLL Counter Counter Wake event PSR Master Control Data Master Control Global Clock StopCore: 0 Control Logic StopCore: 0 Enable EnableEnable 12th Hot Chips Symposium - August 15, 2000 14 ProgrammingProgramming InterfaceInterface ProcessorProcessor andand NorthbridgeNorthbridge Adaptive Power Control Advanced Thermal Control CPU interface Northbridge interface CPUID 8086 0001h Function 0, Register A8h EDX:0 LongRun supported Bit 4 Thermal Management ECX Nominal core frequency enabled CPUID 8086 0007h Bit 1:3 Power reduction level EAX Current core frequency Bits Mode 000 Reserved EBX Current core voltage 001 Reserved ECX Current performance 010 75.0% percentage 011 62.5% 100 50.0% MSR 8086 8010h 101 37.5% 110 25.0% EDX Upper boundary 111 12.5% (% of max. performance) EAX Lower boundary Bit 0 LongRun supported (% of max. performance) 12th Hot Chips Symposium - August 15, 2000 15 EnergyEnergy EfficiencyEfficiency SuperiorSuperior PerformancePerformance inin SmallSmall FormForm FactorsFactors 60 CPUmark99 Cooling Barrier Passive Active (fan) A/C 50 Crusoe All-Day Battery 40 TM5600 Computing 30 TM5400 Conventional Mobile x86 20 10 0 1 3 56 7 9 11 13 15 17 Power [W] 12th Hot Chips Symposium - August 15, 2000 16 TheThe LongRunLongRun AdvantageAdvantage DVDDVD PlaybackPlayback --PerformancePerformance onon DemandDemand 12th Hot Chips Symposium - August 15, 2000 17 PoPowerwer ComparisonComparison SubstantialSubstantial PowerPower Reduction,Reduction, DeliveredDelivered byby CrusoeCrusoe Conventional Crusoe TM5400 Mobile x86 Solution Integrated North Bridge Processor North Total LongRun 650 / 500 MHz Bridge 650 / 500 MHz 633 ó 300 MHz ó 1.6 / 1.35 V 3.3 V 1.6 / 1.35 V 1.6 1.2 V Normal (C0) 14.0 / 8.0 2.0 16.0 / 10.0 6.5 ó 1.5 Watts AutoHALT (C1) 1.7 / 1.1 2.0 3.7 / 3.1 0.9 ó 0.3 Watts Quick Start (C2) 1.3 / 0.8 2.0 3.3 / 2.8 0.6 ó 0.2 Watts Deep Sleep (C3) 0.5 / 0.3 ~1.0 1.5 / 1.3 0.05 ó 0.05 Watts u Crusoe plays Soft-DVD at the same power that conventional mobile x86 processors use in Deep Sleep! 12th Hot Chips Symposium - August 15, 2000 18 TheThe LongRunLongRun AdvantageAdvantage DVDDVD PlaybackPlayback --ThermalThermal ComparisonComparison Conventional Mobile x86 Crusoe TM5400 Processor Processor with LongRun 105.5º C 221.9º F 48.2º C 118.8º F Active thermal solution required Passive thermal solution (Fan or overload protection) (No fan or overload protection) 12th Hot Chips Symposium - August 15, 2000 19 SummarySummary u Crusoe Supports the x86 Power Management Model with Significantly Reduced Power Consumption u Sleep: 4× (C1) - 30× (C3) power savings u Crusoe Leverages Code Morphing Software to Drive Performance on Demand - LongRun u Normal: 2× - 10× power savings u Crusoe Leverages LongRun to Expand the Thermal Budget u Crusoe’s Innovative Low-Power Technology Portfolio u Enables a whole new class of battery-powered devices u The full PC and Internet experience - Anywhere and Anytime 12th Hot Chips Symposium - August 15, 2000 20 12th Hot Chips Symposium - August 15, 2000 21.
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