A Bond Graph Approach for the Modeling and Simulation of a Buck Converter

Journal of Low Power Electronics and Applications

Article A Bond Graph Approach for the Modeling and Simulation of a Buck Converter

Rached Zraﬁ *, Sami Ghedira * and Kamel Besbes

Microelectronics and Instrumentation Laboratory, University of Monastir, Monastir 5000, Tunisia; [email protected] * Correspondence: rachedzraﬁ@yahoo.fr (R.Z.); [email protected] (S.G.)

Received: 19 November 2017; Accepted: 23 January 2018; Published: 25 January 2018

Abstract: This paper deals with the modeling of bond graph buck converter systems. The bond graph formalism, which represents a heterogeneous formalism for physical modeling, is used to design a sub-model of a power MOSFET and PiN diode switchers. These bond graph models are based on the device’s electrical elements. The application of these models to a bond graph buck converter permit us to obtain an invariant causal structure when the switch devices change state. This paper shows the usefulness of the bond graph device’s modeling to simulate an implicit bond graph buck converter.

Keywords: Bond graph modeling; PiN diode; power MOSFET; buck converter

1. Introduction A bond graph is a physics-based modeling tool that provides an energy-based topological framework for the modeling of physical systems [1]. It enhances the visual understanding of these systems through the visual indication of the cause and effect relationships of the energy transfer between the subsystem variables. A bond graph, as a powerful modeling tool, has known great development and enjoyed a well-deserved popularity in many engineering disciplines. Regarding the power converter modeling discipline, recent research has begun to overcome the problem of switching and state discontinuities. In [2], a new bond graph element to represent an ideal switch was proposed. In this method, the switching operation is handled by sending, on a junction, zero flow when the switch is ON and zero effort when the switch is OFF. This method needs a reconfiguration of the causality whenever the position of the switchers changes. An extension of this method is the causality resistor technique [3] that suggests the addition of a resistor to the switch port. The adaptation of the causality of this resistor according to the ideal switch state leads to unchanged causality for the rest of the bond graph diagram. Other models use the modulated transformer (MTF) [4,5], where a modulation parameter m is set to 1 for the closed switch state and to 0 for the open switch state, but the causality must be reassigned. An extension of this technique [3], taking account of the resistance of the switcher during the ON mode, consists in combining a Ron resistor to the MTF to represent the non-linear characteristics of the switcher. This method allows for the definition of a single bond graph model that holds for all switch positions. Another method that implies invariant causalities during the different switch modes is the switched power junction [5]. Here, more than one bond can decide the effort at a 0-junction and the flow at a 1-junction at mutual time instants. These techniques, however, do not show the dynamic internal comportment of the switch devices during their switching mode. In this respect, there are some works [6–8] where the authors developed new switcher component models based on the bond graph formalism for a better modeling of the internal physical behavior of these devices. In this paper, we present the dynamic models, by a bond graph formalism, of the power MOSFET transistor and the PiN diode and their

J. Low Power Electron. Appl. 2018, 8, 2; doi:10.3390/jlpea8010002 www.mdpi.com/journal/jlpea J. Low Power Electron. Appl. 2018, 8, x 2 of 11 application in a buck converter circuit. The use of these switcher models leads to unchanged causality during the different transition states, and to a better simulation of the dynamic comportment of the buck converter and the switcher devices. To analyze the transfer of energy and the performance in a converter system against input or J. Low Power Electron. Appl. 2018, 8, 2 2 of 11 load changes, a PWM regulator block is always used. Therefore, the bond graph package was developed in the VHDL-AMS language. This is to design bond graph schema mixed with digital application in a buck converter circuit. The use of these switcher models leads to unchanged causality control blocks.during This the differentpackage transition was integrated states, and to into a better the simulation graphical of modeling the dynamic tool comportment SystemVision of the in order to explore rapidbuck converter prototyping and the switcherand the devices. visual design facilities. VHDL-AMSTo analyze is a new the transfer mixed-signal of energy and modelling the performance language in a converter based system on againstthe VHDL input or language. load It is designed tochanges, support a PWM mixed-signal regulator block systems is always that used. cont Therefore,ain digital the bond elements graph package and analog was developed elements and to in the VHDL-AMS language. This is to design bond graph schema mixed with digital control blocks. allow the Thisinteraction package was between integrated them. into the It graphical allows modeling for hierarchy tool SystemVision description in order toand explore the rapidsimulation of continuousprototyping and discrete and theevents visual [9,10]. design facilities. This articleVHDL-AMS is organized is a new as mixed-signal follows. Section modelling 2 language introduces based the on the bond VHDL graph language. theory. It is Section 3 describes thedesigned buck tobond support graph mixed-signal design systemsmethodology that contain using digital a power elements MOSFET and analog and elements a PiN and diode bond to allow the interaction between them. It allows for hierarchy description and the simulation of graph sub-model.continuous Section and discrete 4 presents events [9, 10the]. simulation results. Finally, the last section provides some conclusions andThis suggestions article is organized for future as follows. work. Section 2 introduces the bond graph theory. Section3 describes the buck bond graph design methodology using a power MOSFET and a PiN diode bond 2. The Bondgraph Graph sub-model. Theory Section 4 presents the simulation results. Finally, the last section provides some conclusions and suggestions for future work. A bond graph is an engineering tool based on the description of physical systems by analyzing 2. The Bond Graph Theory the exchange of energy within [1]. This exchange determines the dynamic behavior of the systems. A bond graph is an engineering tool based on the description of physical systems by analyzing Bond graphthe modeling exchange of involves energy within devices, [1]. This their exchange connections, determines thedirected dynamic power behavior transfers, of the systems. and causality strokes. TheBond power graph or modeling the energy involves flow devices, is represente their connections,d by a half directed arrow power called transfers, a power and causality bond. Each bond is associatedstrokes. with The two power variables: or the energy effort flow and is represented flow. The by adirection half arrow calledof the a powerflow bond.variable Each is bond given by the causality information.is associated with Graphically, two variables: the effort causality and flow. is The indicated direction of by the putting flow variable a stroke is given near by the the element causality information. Graphically, the causality is indicated by putting a stroke near the element which controlswhich the controls flow the as flow shown as shown in Figure in Figure 1.1.

FigureFigure 1. The 1. The general general conventions conventions of of bond bond causality. causality.

The energyThe flow energy in flow a system in a system is described is described at at any time time by by the the value value of the of power, the whichpower, is the which is the product of the effort variable by the flow variable. Therefore, a bond graph can represent systems product offrom the differenteffort variable domains inby a unifiedthe flow way. variab Table1 showsle. Therefore, the effort and a bond the flow graph variables can of therepresent main systems from differentphysical domains domains. in a unified way. Table 1 shows the effort and the flow variables of the main physical domains. Table 1. Effort and flow variables of the main physical domains.

TablePhysical 1. Effort Domain and flow variables Flow Variable of the mainEffort physical Variable domains. Electrical Current Voltage PhysicalMechanical Domain Flow Velocity Variable Effort Force Variable ElectricalHydraulic VolumeCurrent ﬂow PressureVoltage Thermal Entropy ﬂow Temperature Mechanical Velocity Force Hydraulic Volume flow Pressure Thermal Entropy flowTemperature

3. The Buck Bond Graph Model The buck converter to simulate is pictured in Figure 2. It consists of a switch-regulated buck converter, where the values of its components have been chosen as: voltage E = 9 Volts, L = 50 µH, C = 50 µF, and R = 4 Ohms. The switcher Sw1 represents the power MOSFET IRF740 and Sw2 represents the PiN diode STTA81200. In this example, the buck converter is chosen to operate in continuous conduction mode.

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3. The Buck Bond Graph Model The buck converter to simulate is pictured in Figure2. It consists of a switch-regulated buck converter, where the values of its components have been chosen as: voltage E = 9 Volts, L = 50 µH, C = 50 µF, and R = 4 Ohms. The switcher Sw1 represents the power MOSFET IRF740 and Sw2 represents the PiN diode STTA81200. In this example, the buck converter is chosen to operate in continuous J. Low Power Electron. Appl. 2018, 8, x 3 of 11 conduction mode.

FigureFigure 2. Circuit 2. Circuit diagram diagram of of the regulated regulated buck buck converter. converter.

To deriveTo the derive buck the bond buck bondgraph graph schema, schema, we we desi designedgned the the switchers’ bond bond graph graph sub-model sub-model and added themand addedto the thembuck to bond the buckgraph bond model graph with model respect with respectto the tosequential the sequential causality causality assignment assignment procedure. procedure. 3.1. Power MOSFET Bond Graph Sub-Model Description 3.1. Power MOSFETFigure3 shows Bond the Graph cross-section Sub-Model of the Description power MOSFET (VDMOS). The basic electrical components to satisfy its dynamic behavior are [11]: Figure 3 shows the cross-section of the power MOSFET (VDMOS). The basic electrical components• Theto satisfy capacitances its dynamicCds, Cgd andbehaviorCgs that are simulate [11]: the drain-source, gate-source, and gate-drain capacitances, respectively;

• The resistances Rd, Rg and Rs that represent the equivalent resistance of the drain, gate, and • The capacitances Cds, Cgd and Cgs that simulate the drain-source, gate-source, and gate-drain source, respectively; capacitances, respectively; • The resistance Rds that represents the total resistance between the drain and the source • The resistances(the body-drain Rd, R diode);g and andRs that represent the equivalent resistance of the drain, gate, and source,• respectively;The controlled current source Ids, whose associated equations are: • The resistance Rds that represents the total resistance between the drain and the source (the body- Ids = 0i f Vgs < vt (1) drain diode); and 2 kplinVds • Vgs − vt Vds − The controlled current source Ids, whose associated2kpsat equations are: kpsat Ids = kpsat i f Vds ≤ Vgs − vt (2) 1 + θ Vgs − vt kplin =0 < (1) 2 Vgs − vt kpsat Ids = kpsat i f Vds > Vgs − vt . (3) 2 1 + θ Vgs −vt kplin − − 2 Therefore, an equivalent bond graph model for the power MOSFET can be derived from these (2) = ≤ − basic components. 1+ − To derive the bond graph model of the power MOSFET, we used the 0-junction to represent the Kirchoff’s current law (the 0-junction is inserted− at each node and between elements that have the same potential) and the 1-junction = to represent Kirchoff’s voltage law> (the 1-junction− is inserted. between (3) the 0-junctions). For the assignment21+ of the causality − (Figure4), we applied the sequential causality assignment procedure [1] in order to transfer the effort value (that is the voltage) from the drain and Therefore, an equivalent bond graph model for the power MOSFET can be derived from these basic components. To derive the bond graph model of the power MOSFET, we used the 0-junction to represent the Kirchoff’s current law (the 0-junction is inserted at each node and between elements that have the same potential) and the 1-junction to represent Kirchoff’s voltage law (the 1-junction is inserted between the 0-junctions). For the assignment of the causality (Figure 4), we applied the sequential causality assignment procedure [1] in order to transfer the effort value (that is the voltage) from the drain and the source to the flow source element Ids. The value of the effort Vgs used on the flow source Ids is obtained from a voltage-to-quantity converter, placed at the gate bond, via an information link. Table 2 shows the values of the Power MOSFET IRF740 parameters.

Table 2. The Power MOSFET IRF740 Parameters.

Parameters Description Values Unity Teta Transverse electric field factor of the MOSFET 3.5 Kplin Linear transconductance 9.0 A/V Kpsat Saturation transconductance 15.0 A/V

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vt Threshold voltage 3.5 V

d J. Low PowerR Electron. Appl. 2018, Equivalent8, x resistance of the drain 0.02 Ω4 of 11 Rs Equivalent resistance of the source 0.038 Ω Rg vt EquivalentThreshold resistance voltage of the gate 3.50.09 V Ω Rds Rd ResistanceEquivalent between resistance the drain of theand drain the source 0.021.5 × 106 Ω Ω Rs Equivalent resistance of the source 0.038 Ω Cds0 Drain-source capacity at zero level polarization 5.2 × 10−9 F Rg Equivalent resistance of the gate 0.09 Ω Is0 Saturation current of the body-drain diode 4.0 × 10−9 A Rds Resistance between the drain and the source 1.5 × 106 Ω PB Potential of the MOSFET base 0.8 V Cds0 Drain-source capacity at zero level polarization 5.2 × 10−9 F MJ Gradient coefficient 1.0 – J. Low PowerIs0 Electron. Appl. Saturation8 current of the body-drain diode 4.0 × 10−9 A 2018, , 2 4 of 11 B 21 m N PB ConcentrationPotential of in the the MOSFET MOSFET base base 5.40.8 × 10 V −9 Coxd MJ GateGradient oxide coefficient capacity 0.0451.0 × 10 – F the source to the ﬂow source element Ids. The value of the effort Vgs used on the ﬂow source−6 Ids is Agd NB EquivalentConcentration surface in of the the MOSFET gate-drain base area 5.44.0 × 10 ×21 10 m m obtained from a voltage-to-quantity converter, placed at the gate bond, via an information link. Table2 Coxd Gate oxide capacity 0.045 × 10−9 −9 F showsCgs the values of the PowerGrid-source MOSFET equivalent IRF740 parameters. capacity 0.4 × 10 F Agd Equivalent surface of the gate-drain area 4.0 × 10−6 m Cgs Grid-source equivalent capacity 0.4 × 10−9 F

FigureFigure 3.Figure (a) 3. Cross-Section ( 3.a) (Cross-Sectiona) Cross-Section of Powerof of Power Power MOSFET MOSFET MOSFET showing showing the thethe principal principal principal electrical electrical electrical elements; elements; elements; (b) ( equivalentb) equivalent (b) equivalent electricalelectricalelectrical schema schema schema of the of of thePower the Power Power MOSFET. MOSFET. MOSFET.

FigureFigure 4. 4. BondBond graph graph sub-model ofof the the power power MOSFET. MOSFET.

Figure 4. Bond graph sub-model of the power MOSFET.

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Table 2. The Power MOSFET IRF740 Parameters.

Parameters Description Values Unity −1 Teta Transverse electric ﬁeld factor of the MOSFET 3.5 V 2 Kplin Linear transconductance 9.0 A/V 2 Kpsat Saturation transconductance 15.0 A/V vt Threshold voltage 3.5 V Rd Equivalent resistance of the drain 0.02 Ω Rs Equivalent resistance of the source 0.038 Ω Rg Equivalent resistance of the gate 0.09 Ω 6 Rds Resistance between the drain and the source 1.5 × 10 Ω −9 Cds0 Drain-source capacity at zero level polarization 5.2 × 10 F −9 Is0 Saturation current of the body-drain diode 4.0 × 10 A PB Potential of the MOSFET base 0.8 V MJ Gradient coefﬁcient 1.0 – 21 −3 NB Concentration in the MOSFET base 5.4 × 10 m −9 Coxd Gate oxide capacity 0.045 × 10 F −6 2 Agd Equivalent surface of the gate-drain area 4.0 × 10 m −9 Cgs Grid-source equivalent capacity 0.4 × 10 F

3.2. PiN Diode Bond Graph Model Description The Pin diode consists of a wide and lightly doped central region delimited by two generally much thinner and more highly doped lateral regions P+ and N+ (Figure5). To model the dynamic comportment of the PiN diode, we use the following electrical components [12]:

• The current junction source Ij deﬁned by the following equation: 2Ve Ij = Ise exp − 1 (4) Ut

where Ve is the junction voltage and Ut is the thermal voltage. • The current base source Ib, whose relations are as follows:

qe − qb Ib = (5) TM

where qe is the injected charge level at the junction and qb is the total charge in the central region, where: Ve qe = Istau exp − 1 (6) Ut and dq q b = I − b . (7) dt b tau

• The voltage base source Vb, equal to:

Ut TM RM0 I Vb = . (8) qb RM0 + Ut TM

• The junction capacitance Cj • The equivalent resistance Rs

Based on the same procedure used in the case of the power MOSFET, we can derive the bond graph PiN diode sub-model as represented below in Figure6. The parameters of the PiN diode STTA81200 are reported in Table3. J. Low Power Electron. Appl. 2018, 8, x 5 of 11

3.2. PiN Diode Bond Graph Model Description The Pin diode consists of a wide and lightly doped central region delimited by two generally much thinner and more highly doped lateral regions and (Figure 5). To model the dynamic comportment of the PiN diode, we use the following electrical components [12]: • The current junction source Ij defined by the following equation:

2 = −1 (4)

where is the junction voltage and is the thermal voltage. • The current base source Ib, whose relations are as follows:

− = (5)

where is the injected charge level at the junction and is the total charge in the central region, where:

= −1 (6) and

= − . (7)

• The voltage base source Vb, equal to:

= . (8) +

• The junction capacitance Cj J. Low Power Electron. Appl. 2018, 8, 2 6 of 11 • The equivalent resistance Rs

FigureFigure 5.5. ((aa)) Cross-SectionCross-Section ofof PiNPiN diodediode showingshowing thethe principalprincipal electricalelectrical elements;elements; (b(b)) equivalentequivalent J. Low Powerelectricalelectrical Electron. schema schema Appl. 2018 of of the the, 8 PiN, PiNx diode. diode. 6 of 11

Based on the same procedure used in the case of the power MOSFET, we can derive the bond graph PiN diode sub-model as represented below in Figure 6. The parameters of the PiN diode STTA81200 are reported in Table 3.

Figure 6. Bond graph sub-model of the PiN diode. Figure 6. Bond graph sub-model of the PiN diode.

TableTable 3. 3. TheThe PiN PiN diode STTA81200 Parameters. Parameters.

ParametersParameters DescriptionDescription Values Unity Unity

s −3−3 RsR SerialSerial resistance resistance 30.0 30.0× ×10 10 Ω Ω −23 Ise Ise Recombination current current 1.01.0×10× 10 −23 A A × −9 TMTM CarriersCarriers transit transit time time 8.2 8.2 ×10 10−9 nsns −7 TAU Carriers lifetime 1.3 × 10 ns TAU Carriers lifetime 1.3 × 10−7 ns RM0 Initial resistance 0.1 Ω MRM0 GradientInitial coefﬁcientresistance 0.55 0.1 Ω – −9 Cj0M JunctionGradient capacitance coefficient 3.0 × 0.5510 – F I Saturation current × −12 A sCj0 Junction capacitance 1.0 3.0 ×10 10−9 F Is Saturation current 1.0 × 10−12 A 3.3. Derivation of the Buck Bond Graph Model 3.3. DerivationBy applying of the the Buck bond Bond graph Graph sub-model Model of the power MOSFET transistor and the PiN diode, and withBy respect applying to the the sequential bond graph causality sub-model assignment of the procedure,power MOSFET the resulting transistor buck and bond the graph PiN diode, model isand withas shownrespect in to Figure the sequential7. causality assignment procedure, the resulting buck bond graph model is as shownThe implementation in Figure 7. of the power-MOSFET, PiN diode, and the buck bond-graph model in SystemVision is achieved via the graphical and user-friendly interface (Figures8–10). In SystemVision, The implementation of the power-MOSFET, PiN diode, and the buck bond-graph model in the designer can draw the bond graph model on the screen by using the basic bond graph library SystemVision is achieved via the graphical and user-friendly interface (Figures 8–10). In written in the VHDL-AMS language. For more information about the combination of bond graph SystemVision, the designer can draw the bond graph model on the screen by using the basic bond theory and mixed language programming, the reader can refer to [13–15], and [15–17] for more detail graph library written in the VHDL-AMS language. For more information about the combination of about the implementation of the basic bond graph elements in VHDL-AMS. bond graph theory and mixed language programming, the reader can refer to [13–15], and [15–17] for more detail about the implementation of the basic bond graph elements in VHDL-AMS.

Figure 7. Bond graph buck converter schema.

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Figure 6. Bond graph sub-model of the PiN diode.

Table 3. The PiN diode STTA81200 Parameters.

Parameters Description Values Unity Rs Serial resistance 30.0 × 10−3 Ω Ise Recombination current 1.0×10−23 A TM Carriers transit time 8.2 × 10−9 ns TAU Carriers lifetime 1.3 × 10−7 ns RM0 Initial resistance 0.1 Ω M Gradient coefficient 0.55 – Cj0 Junction capacitance 3.0 × 10−9 F Is Saturation current 1.0 × 10−12 A

3.3. Derivation of the Buck Bond Graph Model By applying the bond graph sub-model of the power MOSFET transistor and the PiN diode, and with respect to the sequential causality assignment procedure, the resulting buck bond graph model is as shown in Figure 7. The implementation of the power-MOSFET, PiN diode, and the buck bond-graph model in SystemVision is achieved via the graphical and user-friendly interface (Figures 8–10). In SystemVision, the designer can draw the bond graph model on the screen by using the basic bond graph library written in the VHDL-AMS language. For more information about the combination of bond graph theory and mixed language programming, the reader can refer to [13–15], and [15–17] J. Low Power Electron. Appl. 2018, 8, 2 7 of 11 for more detail about the implementation of the basic bond graph elements in VHDL-AMS.

J. Low Power Electron. Appl. 2018, 8, x Figure 7. Bond graph buck converter schema. 7 of 11

Figure 8. ImplementationImplementation of the power MOSFET bo bondnd graph sub-model in SystemVision.

Figure 9. Implementation of the PiN diode bond graph sub-model in SystemVision.

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J. Low Power Electron. Appl. 2018, 8, 2 8 of 11 Figure 8. Implementation of the power MOSFET bond graph sub-model in SystemVision.

Figure 9. Implementation of the PiN diode bond graph sub-model in SystemVision. J. Low PowerFigure Electron. 9. Implementation Appl. 2018, 8, x of the PiN diode bond graph sub-model in SystemVision. 8 of 11

FigureFigure 10. 10.Screen Screen of of SystemVisionSystemVision showing the the buck buck bond bond graph graph model. model.

4. Simulation Results 4. Simulation Results The simulation results of the bond graph buck model are displayed in Figures 11–13. To show theThe output simulation voltage resultsregulation, of the we bond perturbed graph the buck input model voltage are displayed(Figure 11) inand Figures the resistive 11–13. charge To show the(Figure output 12) voltage at various regulation, times during we perturbed the simulation. the input As a result voltage of these (Figure perturbations, 11) and the we resistive can see chargethat (Figurethe output 12) at voltage various is times regulated during to thethe simulation.reference volt Asage a result(4.5 V). of In these Figure perturbations, 13, we can see we the can inverse see that thecurrent output of voltage the PiN is diode regulated during to its the reverse reference recovery voltage. Therefore, (4.5 V). Inthe Figure simulation 13, we results can see of the the bond inverse graph buck model present satisfactory switching operation results.

Figure 11. Time evolution of the output voltage Vout(t) and the inductor current IL(t) during the Vin(t) jump and drop with an amplitude of 3 V at t = 5 ms and t = 7 ms.

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Figure 10. Screen of SystemVision showing the buck bond graph model.

4. Simulation Results The simulation results of the bond graph buck model are displayed in Figures 11–13. To show the output voltage regulation, we perturbed the input voltage (Figure 11) and the resistive charge (FigureJ. Low 12) Power at Electron.various Appl. times2018 during, 8, 2 the simulation. As a result of these perturbations, we can9 ofsee 11 that the output voltage is regulated to the reference voltage (4.5 V). In Figure 13, we can see the inverse currentcurrent of the of thePiN PiN diode diode during during its its reverse reverse recovery recovery.. Therefore,Therefore, the the simulation simulation results results of the of bondthe bond graphgraph buck buck model model present present satisfactory satisfactory switching switching operationoperation results. results.

FigureFigure 11. 11.TimeTime evolution evolution of of the outputoutput voltage voltage Vout(t) Vout(t and) theand inductor the inductor current current IL(t) during IL(t) the during Vin(t) the Vin(t) jump and drop with an amplitude of 3 V at t = 5 ms and t = 7 ms. J. Lowjump Power and Electron. drop withAppl. 2018 an amplitude, 8, x of 3 V at t = 5 ms and t = 7 ms. 9 of 11

Figure 12. Time evolution of the output voltage Vout(t) and the inductor current IL(t) during the R Figure 12. Time evolution of the output voltage Vout(t) and the inductor current IL(t) during the R load drop and jump from 4 ohm to 2 ohm at t = 25 ms and back to 4 ohm at t = 27 ms. load drop and jump from 4 ohm to 2 ohm at t = 25 ms and back to 4 ohm at t = 27 ms.

Figure 13. Time evolution of the STTA81200 voltage and current during the Vin(t) jump with an amplitude of 3 V at t = 5 ms.

In addition, the bond graph buck model operates at the different switching modes without any modification on the model schema. Therefore, the use of a bond graph sub-model, based on the electrical components for the switcher devices, provides an unchanged causality of the buck bond

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J. Low PowerFigure Electron. 12. Time Appl. evolution2018, 8, 2 of the output voltage Vout(t) and the inductor current IL(t) during the R 10 of 11 load drop and jump from 4 ohm to 2 ohm at t = 25 ms and back to 4 ohm at t = 27 ms.

FigureFigure 13. 13.Time Time evolutionevolution of the the STTA81200 STTA81200 voltage voltage and and current current during during the Vin(t) the Vin(t) jump jumpwith an with anamplitude of of 3 3 V V at at t t= =5 5ms. ms.

In addition, the bond graph buck model operates at the different switching modes without any modificationIn addition, on the the bond model graph schema buck. Therefore, model operates the use at of the a differentbond graph switching sub-model, modes based without on the any modificationelectrical components on the model for the schema. switcher Therefore, devices, pr theovides use ofan aunchanged bond graph causality sub-model, of the basedbuck bond on the electrical components for the switcher devices, provides an unchanged causality of the buck bond graph schema for the different switching states. The commutation of the switcher devices is ensured mainly through the controlled flow element Ids for the power MOSFET IRF740 and the controlled flow elements Ij and Ib for the simple diode STTA81200.

5. Conclusions In this paper, we present a methodology using the uniﬁed formalism of a bond graph to model a buck converter circuit. This approach allows us to model a bond graph buck converter very well at all switching modes. Thus, the use of a bond graph sub-model, based on the electrical elements for the switcher devices, allows for the maintenance of a causality invariant. The design of the buck converter is realised using a bond graph package developed in the VHDL-AMS language and under the SystemVision environment. This is to achieve a rapid prototyping of the target design and to explore the graphics facility. In future work, we will add the thermal effect within the switcher devices.

Acknowledgments: This work was supported by the Microelectronics and Instrumentation Laboratory. Author Contributions: Rached Zrafi is the main author of the paper. Sami Ghedira and Kamel Besbes was responsible for the supervising of the paper. Conflicts of Interest: The authors declare no conflict of interest.

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