Cell-Aware Analysis for Small-Delay Effects and Production Test Results from Different Fault Models

Cell-aware Analysis for Small-delay Effects and Production Test Results from Different Fault Models

2011 International Test Conference

Friedrich Hapke 1, Michael Reese 2, Jason Rivers 2, Jeff Rearick2, Janusz Rajski1, Wilfried Redemund1, Juergen Schloeffel1, Andreas Glowatz1 Purpose

• To evaluate the effectiveness of the Cell-aware and other fault models on a large number of tested ICs in a production environment

• To analyze cell-internal Bridge defects causing Small-delay effects

2 Outline

• Introduction – Standard fault models, very short intro to Cell-aware

• Production Test Results from different fault models – Test Program Flow 45nm IC , Test Results , Test Costs

• Cell-aware Analysis for Small-delay defects – Analysis Flow 32nm Library, Defect Types & Results – Latest Production Test Results achieved after ITC 2011

• Summary & Future Work

3 Introduction

• Quality of delivered IC itdis not good enoug h. There are too many customer returns

• This means , state -of- the-art ATPG tools do not target real defects sufficiently

• This paper will focus • Stuck-At & Transition Which • N-Detection fault models on imppgroving this • Gate-Exhaustive shall we • Cell-Aware use situation 4 Previous Work

• Many papers have been published in the past addressing the pro blem for improv ing the de fec t coverage

• 2007/2008 the EMD method was introduced ((,ITC 2007, paper 30.3; ITC 2008, paper 20.1)

• 2009 Cell-Aware the Basic methodology was presented (ITC 2009, paper 1.2)

• 2010 Cell-Aware the Gross-delay methodology for cell- internal Bridges and Opens (ITC 2010, paper 10.1)

• 2011 Gate-Exhaustive versus Cell-Aware pattern sets for Industrial Desigg(ns (VLSI-DAT 2011,,p pa per w22 )

5 Overview of Standard Fault Models z Stuck-At z TitiTransition We exactly know what z Timing-Aware we do, but we also know that these tests z Path-Delay are not sufficient z Interconnect Bridges We don ‘t know what we z N-Detect do, but if we do it often z Embedded-Multi-Detect enough it becomes better z Gate-Exhaustive We don‘t know what are good patterns, therefore we apply all 6 The Cell-Aware Methodology

Library Characterization Flow

Layout Analog Fault Cell-Aware Extraction Simulation Fault Model Reports Cell SPICE Defect Generation Layout parasitics Matrix GDS2 netlist Cell-Aware defects Model

Normal Cell-Aware Test Synthesis ATPG System RTL .V .STIL

Normal Design Flow

The new defect-oriented Cell-Aware method addresses cell-internal defects explicitly and forces the ATPG to deterministically target these defects. 7 Production Test Results

Effectiveness of different Fault Models

8 Production Test Design

• AMD notebook processor Core1 Core2 • Cores: two x86 cores, each with a 1ML2 cac he an d 128-bit FPU

• Process: 45 nm silicon-on-insulator (SOI) , 11 layers of copper

• Transistors: 230 Analyzed Fault Models million

• Stuck-At & Transition • Power: 65 Watts • Gate-Exhaustive (Slow-speed) • Frequency: 3.1 GHz • CllCell-A(SlAware (Slow-speed) at 1.3 V • Transition N-Detect5 (At-speed) 9 Test Program Flow

AMD Notebook processor 45nm technology TR fail exit At-speed pass

SA fail Slow-speed continue on fail topoff pass log fails

GE CA TR N-det5 Slow-speed Slow-speed At-speed log fails

log fails log fails log fails

Normal Production Test Fault Model Experiment

10 Detailed Production Test Results

Venn Diagram 600,000 ICs - 45nm Design Pattern Type #fails #pat DPPM total Cell-aware 32 4k 55 Slow-speed 32 fails Gate-exhaustive 23 8k 40 4k pat 55 ppm Slow-speed TR N-Detect5 98 40k 162 Cell-aware At-speed total Slow-speed total 23 fails 98 fails 12 40 ppm 162 ppm N-detect5 is an At-speed test with 10X more pattern than 1 11 Cell-aware Slow-speed 8 Î too costly for production Gate- Transition exhaustive N-detect5 We expect that the Cell- Slow-speed 9 At-speed aware At-speedtd test will 5 70 outperform the Transition N-detect5 test 8k pat 40k pat

11 Test Cost Comparison

10.0 9.0 On average On average 9.8 over 10 designs over 10 designs 808.0 1-cycle Slow-speed 2-cycle At-speed 7.0 Gate-Exhaustive Gate-Exhaustive

Costs versus versus

t 6.0

ss Cell-Aware Cell-Aware Te 5.0 4X higher 12X higher 4.0 lative ee 3.0 R 2.0 2.0 1.0 101.0 0.0 Cell-awareCA Gate-exhaustiveGE TRTR‐ Ndet5N-detect5 slowslow-s‐speedpeed slowslow-s‐speedpeed atat‐speed-speed

12 Effectiveness of Fault Models Resu lts a fter 600, 000 tes te d IC

14 13.4 12 10 8 6 5.0 4 414.1 2 0 Cell Aware Gate Exhaustive N‐Detect5 Slow‐speed Slow‐speed At‐speed

Effectiveness in [dppm] per 1000 pattern

13 How to replace the costly Transition N-detect At-speed patterns ?

Venn Diagram 600,000 ICs - 45nm Design total 32 fails 4k pat 55 ppm Cell-aware total Slow-speed total 23 fails 98 fails 12 40 ppm 162 ppm

1 11 8 Gate- Transition exhaustive N-detect5 Slow-speed 9 At-speed 5 70

8k pa t 40k pat

14 Cell-aware Analysis for Small-delay defects

15 Small-delay Analysis Flow

Library Characterization Flow

Layout Analog Fault Cell-Aware Extraction Simulation Fault Model Reports Cell SPICE Defect Generation Layout parasitics Matrix GDS2 netlist Cell-Aware defects Model

1-cycle SPICE 2-cycle SPICE Analog Netlist Analog Netlist Fault Creation for Fault Creation for Simulation 2-cycle FS Simulation SPICE 1-cycle FS SPICE Gross SPICE Defect parasitics faultsim Delay faultsim Matrix netlist netlist Detection netlist

loop over all loop over all input combinations input combinations 16 Cell-internal Defect Type1

D1 vdd 175 Ω 175 Ω 175 Ω Tboth M16 M17 M18 A 90 Ω M13 M14 M15 B M10 M11 M12

C Z

M7 M8 M9

gnd Max. load capacitor M4 M5 M6

M1 M2 M3

gnd

[V] 1.0 (Tboth) D1 Defect Type D1 Tboth Gross- 0.8 delay (Tboth) D1 test 0.6 defects that influence

0.4 Fault-free both the P and N waveform FF at the cell transistors 0.2 ouput Z t4= gross delay 0.0 0.1 V t0 t1 t2 t3 t4 t5 strobe time 17 Cell-internal Defect Type2

vdd 175 Ω 175 Ω 175 Ω M16 M17 M18 A 90 Ω M13 M14 M15 B D2 Ton M10 M11 M12 C Z

M7 M8 M9

gnd Max. load capacitor M4 M5 M6

M1 M2 M3

gnd

[V] 1.0 Defect Type D2 Ton 0.8

0.6 defects that switch a (Ton) D2 transistor on when it Fault-free 0.4 Small- waveform FF (Ton) D2 delay should be switched off at the cell 0.2 (Ton) D2 test ouput Z t3= small delay 0.0 0.1 V t0 t1 t2 t3 t4 t5 strobe time 18 Cell-internal Defect Type3

vdd 175 Ω 175 Ω 175 Ω M16 M17 M18 A D3 90 Ω M13 M14 M15 Toff B M10 M11 M12

C Z

M7 M8 M9

gnd Max. load capacitor M4 M5 M6

M1 M2 M3

gnd

[V] 1.0 Defect Type D3 Toff 0.8 Small- delay 0.6 test defects that switch a

0.4 Fault-free transistor off when it waveform FF at the cell should be switched on 0.2 ouput Z (Toff) D3 0.0 0.1 V t0 t1 t2 t3 t4 t5 19 Cell-internal Defect Types

D1 vdd Tboth 175 Ω 175 Ω 175 Ω M16 M17 M18 D3 A Toff 90 Ω M13 M14 M15 B D2 M10 M11 M12 Ton C Z

M7 M8 M9

gnd Max. load capacitor M4 M5 M6

M1 M2 M3

gnd

[V] 1.0 (Tboth) D1 3 Major Defect Types Gross- 0.8 delay (Tboth) D1 test 0.6 D1 Tboth = gross delay (Ton) D2 0.4 Fault-free D2 Ton = small delay waveform FF (Ton) D2 Small- at the cell delay (Ton) D2 0.2 ouput Z test D3 Toff = small delay (Toff) D3 0.0 0.1 V t0 t1 t2 t3 t4 t5 20 Results from a 32nm Cell Library Pattern Count – Small & Gross-delay

28% #S# Sma ll-dldelay 4674

#Gross# Gross-delay 12,204

72%

21 Results from a 32nm Cell Library Detectable Rate [%] per Library Cell

100%

90% Gross‐Delay Test

] 80%

%% Small‐Delay Test [ 70% Rate 60% le bb DtDetect tblRtable Rate 50% is improved 40% significantly Detecta ee 30%

Bridg 20%

10%

0% Cell # 0 200 400 600 800 1000 1200 1400 1600 1800

22 Latest Results Achieved after ITC 2011

23 Latest Results: 32nm Production Test

• AMD notebook processor • ~220mm² 1.5B transistors • 4CPU4 CPU cores – Power gating & clock gating – 35M transistors/core – ~10mm²/core • 1MB L2 cache Analyzed Fault Models • DDR3 memory • Stuck-at (Slow-speed) • DirectX® 11 GPU • Transition (At-speed ND5) • Cell-aware (Slow-speed) • 822M tittransistors

• Cell-aware (At-speed) 24 Test Program Flow – 32nm Experiment

TR N-det5 fail exit At-speed pass SA Slow-speed fail topoff continue on fail

pass CA-2 CA-1 Slow-speed At-speed topoff

Normal Production Test Cell-aware Experiment

25 Production Test Results – 32nm Experiment

Venn Diagram 800, 000 ICs - 32nm Design

total Total 699 fails = 885 PPM total 231 fails 609 fails 292 ppm 771 ppm

Slow-speed At-speed

90 141 468 fails fails fails

26 Summary & Future Work

• 45nm production test results from 600,000 ICs tested with different f ault models have been presented • As expected, Cell-aware patterns are most efficient for reducing PPM rates, GE & TR N-detect too costly • Small-delay defects have been analyzed for 1900 cells from a 32nm library, detectability up to +30% • At ITC2011 we expected that At-speed CA patterns will detect more defects than At-speed TR N-detect • Latest 32nm results have proven our expectation. A total defect rate reduction of 885 PPM has been achieved with an efficient Cell-aware pattern set 27 Questions & Answers

28 Why more Cell-aware fails than Gate-Exhaustive fails?

Gate-Exhaustive Cell-Aware

Stimuli (example) Fault D0 D1 D2 S1 S2 F1 0 - - 0 0 F2 1 - - 0 0 F3 0 1 - 0 0 F4 1 0 - 0 0 Stimuli F5 0 - 1 0 0 Fault D0 D1 D2 S1 S2 F6 1 - 0 0 0 F1 0 0 0 0 0 F7 - 0 - 0 1 F2 1 0 0 0 0 F8 - 1 - 0 1 F3 0 1 0 0 0 Many faults still F9 1 0 - 0 1 F10 0 1 - 0 1 ALL exhaustive faults F4 1 0 1 0 0 can be detected F5 0 0 1 0 0 F11 - 0 1 0 1 are undetected F6 1 1 0 0 0 F12 - 1 0 0 1 F13 - - 0100 1 0 (because D2 can’t be F7 1 0 0 0 1 Only those which need F8 0 1 0 0 1 F14 - - 1 1 0 assigned to 0 or 1) . . . an assignment at D2 F15 1 - 0 1 0 F32 1 1 1 1 1 F16 0 - 1 1 0 remain undetected F17 - 1 0 1 0 F18 - 0 1 1 0

Reference: K.Y. Cho, S. Mitra, and E.J. McCluskey, “Gate Exhaustive Testing”, in Proc. of IEEE Int'l Test Conf., ITC, 2005, paper 31.3 29