Efficient Utilization of Vector Extensions in Microprocessors

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Efficient Utilization of Vector Extensions in Microprocessors Efficient Utilization of Vector Extensions in Microprocessors vorgelegt von Dipl.-Ing. Angela Pohl an der Fakultät IV - Elektrotechnik und Informatik der Technischen Universität Berlin zur Erlangung des akademischen Grades Doktor der Ingenieurwissenschaften - Dr.-Ing.- genehmigte Dissertation Promotionsausschuss: Vorsitzende: Prof. Dr. Begüm Demir Gutachter: Prof. Dr. Ben Juurlink Gutachterin: Prof. Dr. Sabine Glesner Gutachter: Prof. Dr. Biagio Cosenza Gutachter: Prof. Dr. Jeronimo Castrillon Tag der wissenschaftlichen Aussprache: 15. Oktober 2020 Berlin 2020 To My Parents Abstract Since the early 1990s, microprocessors have been enhanced with vector exten- sions to exploit data-level parallelism in applications. Programs are sped up by applying the same instruction to multiple data elements, grouped in a vector, in parallel. Up to this day, efficient utilization of such vector extensions remains challenging, however. While manually transforming code to exploit vector reg- isters and vector instructions yields high performance gains, the effort is signifi- cant. Automated approaches, such as those deployed by compilers, on the other hand, struggle to identify parallelism in applications or fail to find profitable code transformations. In this thesis, we present enhancements to auto-vectorizing compilers in or- der to close the performance gap between manually and automatically vector- ized code. Our enhancements increase the number of automatically vectoriz- able code patterns, offer alternative transformation options that achieve higher performance than state of the art, and enable a comparison of different vector- ization options. We thereby improve all steps of the vectorization process: the transformation of vectorizable code patterns, the mapping of abstract interme- diate code to low-level instructions, and the profitability analysis of the transfor- mation. Our first contribution is a different vector packing strategy for nested loops whose inner loops only perform few iterations. By changing the way vector ele- ments are grouped together, we enable full vector utilization even for large vec- tors. Applying our approach to the two most compute-intense filters of the Ver- satile Video Codec decoder shows improvements of 24% on average over state- of-the-art auto-vectorization. The second contribution is a proposal for the vec- torization of loops with control flow. We offer an alternative implementation for architectures that do not support masked store instructions, and introduce a technique to remove predicates from masked load instructions. While both approaches introduce overhead, we demonstrate their benefit for more than 10 loop kernels. For masked load instructions, the overhead is mitigated by the vec- torized calculation and evaluation of the control flow condition. For masked store instruction, our solution outperforms state of the art for single-threaded applications, and is profitabel for multi-threaded programs when a minimum vectorization factor—depending on the arithmetic intensity of the kernel—is met. As a third contribution, we present an platform-independent cost model to as- iii iv sess the benefit of code vectorization. Its accurate performance prediction allows for the comparison of different vectorization options, and the compiler refrains from transforming code that will exhibit slowdowns after vectorization. Applying our cost model to three different evaluation platforms, we are able to show im- provements with respect to the precision of the speedup prediction, the number of classification errors, and their impact on overall execution time. For exam- ple, our cost model improves the correlation between predicted and measured speedup of 99 loop kernels by 13% on an Intel AVX2 platform, thereby reducing the number of mispredictions by 46% and the total execution time by 3%. Overall, we are able to increase the performance of auto-vectorizing com- pilers by incrasing their vectorization rate, improving their vectorization quality, and reducing the number of mispredictions during their transformation prof- itability analysis. At the same time, we exploit the automatic and platform in- dependent nature of compilers, thereby keeping the effort of code vectorization at a minimum. All of our approaches have been verified for compatibility with vector-length agnostic code generation, ensuring applicability to the program- ming model of future vector extensions. Zusammenfassung Seit Beginn der 90er Jahre werden Vektorerweiterungen in Mikroprozessoren ein- gesetzt, um Parallelität auf Datenebene in Programmen auszunutzen. Durch die gleichzeitige Verarbeitung mehrerer Daten mit derselben Instruktion erhofft man, die Ausführung des Programms zu beschleunigen. Allerdings werden die vorhan- denen Vektorerweiterungen oft nicht effizient genutzt. Entweder muss Quellco- de von Hand umgeschrieben werden, um die speziellen Register und Befehle zu verwenden, oder der vom Compiler erzeugte Code nutzt das Potential der Hard- ware nicht aus. In dieser Doktorarbeit wird untersucht, wie man die Rechenleistung von han- doptimiertem Code erzielen kann, ohne jedoch den damit einhergehenden Auf- wand spendieren zu müssen. Dabei erweitern wir die Vektorisierungsalgorith- men in Compilern derart, dass mehr Codemuster automatisch vektorisiert wer- den können und der transformierte Code eine höhere Rechenleistung erzielt. Außerdem ermöglichen wir den Vergleich unterschiedlicher Transformationsop- tionen. Unsere Erweiterungen verbessern alle Verarbeitungsschritte der Code- Vektorisierung: die Transformation von skalaren in vektoriellen Code, das Ab- bilden der abstrakten Programmdarstellung auf Maschinensprache, sowie die Kosten-Nutzen-Analyse der vorgenommenen Vektorisierung. Insgesamt präsentieren wir in dieser Arbeit drei Compilererweiterungen für die automatische Code-Vektorisierung. Die erste Erweiterung beschäftigt sich mit der Vektorisierung von verschachtelten Schleifen, deren innere Schleifen nur wenige Durchläufe ausführen. Bei der automatischen Vektorisierung dieser Co- demuster werden insbesondere große Vektoren, die viele Datenelemente parallel speichern und verarbeiten können, bislang nicht ausreichend ausgelastet. Wir ändern daher die Art und Weise, wie Datenelemente in diesen Vektoren ange- ordnet werden. Die Vektorisierung der zwei rechenintensivsten Filter des Deko- dierers des Versatile Video Codec zeigt, dass die Ausführungszeit des Programms mit unserem Ansatz im Durchschnitt um 24% verringert werden kann. Die zwei- te Erweiterung, die wir präsentieren, verbessert die Vektorisierung von Schlei- fen, die Kontrollstrukturen enthalten. Wir stellen eine alternative Möglichkeit vor, die bedingte Befehlsausführung für Speicherinstruktionen in Maschinen- sprache zu implementieren. Außerdem zeigen wir, wie die Lesezugriffsrechte für alle Datenelemente eines Vektor zur Laufzeit sichergestellt werden können. Die Evaluierung unserer Methoden bestätigt, dass der Mehraufwand, der durch die v vi Überprüfung der Lesezugriffsrechte zur Laufzeit entsteht, durch die parallele Be- trachtung mehrerer Datenelemente aufgehoben wird. Bei der Betrachtung von 10 Schleifen mit Kontrollstrukturen zeigt sich außerdem, dass Schreibzugriffe um ein Vielfaches beschleunigt werden können, wenn ein Mindestanzahl an par- allelen Datenelementen garantiert werden kann (VF > 4). Die dritte Erweiterung ist ein neues Kostenmodell für die Kosten-Nutzen-Analyse von Vektorisierun- gen. Durch die genaue Vorhersage der zu erwartenden Beschleunigung wird es dem Compiler ermöglicht, verschiedene Transformationsoptionen miteinander zu vergleichen. Außerdem verhindert es die Umsetzung von Transformationen, die die Rechenleistung negativ beeinflussen. Unser Kostenmodell wurde auf drei unterschiedlichen Plattformen untersucht und auf allen dreien wurden Verbes- serungen erzielt. Diese Verbesserungen betreffen die Genauigkeit der Beschleu- nigungsvorhersage, die Anzahl der fehlerhaften Vorhersagen, sowie die Ausfüh- rungszeit. Zum Beispiel konnten wir auf einer Intel AVX2 Hardware die Korre- lation zwischen vorhergesagter und gemessener Beschleunigung von 99 Testco- des um 13% verbessern, wodurch sich die Anzahl der falsch vorhergesagten Be- schleunigungen um 46% und die Ausführungszeit um 3% verringerte. Insgesamt können durch die vorgestellten Erweiterungen mehr Codemus- ter besser vektorisiert werden. Gleichzeitig vermeiden wir fehlerhafte Prognosen bezüglich der zu erwartenden Beschleunigung und ermöglichen den Vergleich unterschiedlicher Vektorisierungsoptionen. Der Aufwand zur Nutzung unserer Verbesserungen ist für den Programmierer minimal, da die Erweiterungen au- tomatisch während des Kompilierens angewendet werden. Zusätzlich sind alle vorgestellten Ansätze auch für die Generierung von vector-length agnostic Code geeignet, der für die effiziente Ausnutzung von Vektorerweiterungen der nächs- ten Generation benötigt wird. Contents 1 Introduction 1 1.1 Proposed Solution............................4 1.2 Motivation................................6 1.3 Pre-Published Work...........................8 1.4 Thesis Organization........................... 11 2 Background 13 2.1 Vector Extensions............................ 14 2.1.1 Structure.............................. 14 2.1.2 Terminology Overview...................... 23 2.1.3 Evolution.............................. 24 2.2 Code Vectorization Techniques.................... 28 2.2.1 Explicit Code Vectorization................... 28 2.2.2 Implicit Code Vectorization................... 30 2.2.3 Vector-Length Agnostic Programming...........
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