ISL6334EVAL1Z User Guide Board Specifications 1

Technical Brief 486

ISL6334EVAL1Z User Guide Board Specifications 1. Intel VR11.1 compliant. 2. 4-Phase, 130W, 400kHz, Load Line = 0.8mΩ. 3. Socket: LGA1366, die sensing, can be configured for motherboard sensing. 4. 6 Layer Board: Top/Bottom - 0.5oz plated, 1.5oz finished; Internal Layer – 1oz. 5. Dual footprint for Intersil 12V (ISL6612A, ISL6622) and 5V drivers (ISL6596/ISL6620) for cost or FIGURE 3. efficiency optimization. With minor re-work, the board can also operate 12V drive for high-side MOSFET and 5V drive for low-side MOSFET. VR Enable Switch 6. Dual footprint for PowerPak and DPAK MOSFET for One switch (SW2) is provided for EN_VTT signal control. cost or efficiency optimization. In “OFF” position, EN_VTT signal is shorted to ground and ISL6334 is disabled. Place SW2 in the “ON” position ISL6334EVAL1Z Board Brief to enable operation. Description Control Power Supply There are two ways to provide 5VDC to this evaluation board: through ATX power connectors (J21) or Banana connectors (J5 and J0). SW1 is used to control the ATX silver box power supply.

FIGURE 4.

PGOOD Indicator and Test Points CR2 is used to indicate the status of VR_RDY (PGOOD) signal. When VR_RDY is high, the LED in CR2 will be OFF (no light); otherwise the red LED in CR2 will be on once 5V is applied. FIGURE 1. Test points are provided for VR_RDY, IMON, VR_HOT and Input Power Supply and External Load VR_FAN signals. Connector 12VDC input power supply can be connected to the board through the 4-pin ATX connector J4. Two test points, TPVIN and TPGND, are provided for input voltage measurement. Two connectors (J1 and J2) are provided for external load.

FIGURE 5.

FIGURE 2.

July 7, 2010 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. TB486.0 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Technical Brief 486

VID (Figure 7) Phase Count Control VID code can be generated from Demo board R1P, R2P, R3P, RW2, RW3, and RW4 are used to set the (JP9 = DEMO) or VTT tool (JP9 = VTT). phase count, as shown in Table 1. If phase count is different than 4, R1 and R5 must be adjusted accordingly PSI for stability and correct load line. Dynamic PSI signal can be generated from LGA1366 VTT or external function generator. Static, fixed PSI operation TABLE 1. can be set through SW5. Placing the 0 switch in the “N” R3P R2P R1P RW4 RW3 RW2 position, leads to the circuit operating in PSI mode. 4-Phase DNP DNP DNP 0Ω 0Ω 0Ω

3-Phase 0Ω DNP DNP DNP 0Ω 0Ω 2-Phase X 0Ω DNP DNP DNP 0Ω

1-Phase X X 0Ω DNP DNP DNP NOTE: X = Don’t care.

Available Design Assist Tools

1Layout Check list.

2 VR Design Worksheet.

3VCORE and IMON TOB Calculator. 4 Schematic is available in OrCAD format.

5 Layout is available in Allegro format. FIGURE 6. Contact Intersil’s local office or field support for the latest available information.

FIGURE 7.

2 July 7, 2010 TB486.0 Technical Brief 486 D C B A C PWM3 PWM2 VCORE VCORE CW2 VCORE VCORE of CW3 13 DNP DNP CI or SI connection RSI4 RCI4 RSI2 0 RCI2 RSI1 RSI3 RCI1 1 RCI3 Intersil Corporation Somerville, NJ 08876 1 DNP 0 65 Readington Road DNP 0 0 RW2 PWM4 0 Ohm DNP ISEN4- DNP ISEN2- PWM1 ISEN1- ISEN3- RW3 DNP 0 Ohm Placement needs correction VCORE4 RP4 VCORE3 1.82k VCORE2 ISL6334 Burnside - 130W Rev C Board VCORE1 Title Title DNP 0 Ohm 0 Ohm RP2 1.82k RW4 RP3 RP1 1.82k 1.82k Thursday, December 20, 2007 R1P DNP 0 Ohm 0 Ohm DNP DNP DNP CF2 B R2P and R3P their traces should not be close to any current sensing network. CC30 CF3 CC40 CF4 Size Rev 470n 470n 470n Size Rev 0.15u 0.15u 0.15u CC10 0.15u Date: Sheet Date: Sheet CF1 470n CC20 CW4 0 R2P DNP DNP RW2 0 Ohm RT2 221 DNP 221 RT1 RT3 RT4 221 221 0 X RW3 R3P DNP 0 Ohm 0 R1P DNP RW4 2 ~27ns RC Time Constant 2 CT1 120p 120p 120p 120p CT2 CT3 CT4 Vc5 CW1 3-PHASE 2-PHASE 1-PHASE X X 0 Ohm DNP DNP DNP 4-PHASE X = DON'T CARE Droop (R1+R5) and compensation network must be adjusted accordingly. Number of Operating Phases Configuration DNP Intersil Confidential Vc5 R2P DNP R3P DNP DNP DNP TO Vc5 TO Vc5 RFS2 100k R6 R7 9.31k R24 R11 R17 R28 20k VCC12 49.9k 0.1u C66 49.9k 1k TP6 RFS1 DNP DNP 6.8k RN2 TO GND TO GND EN_VTT TP5 VR_FAN VR_HOT 3 3 37 18 32 39 28 22 29 23 38 33 27 21 30 24 26 20 31 25 R27 DNS TM DNP DNP RSS2 PWM1 PWM2 PWM3 PWM4 ISEN1- ISEN2- ISEN3- ISEN4-

TO Vc5 TO Vc5 ISEN1+ ISEN2+ ISEN3+ ISEN4+ TCOMP

EN_VTT VR_FAN

VR_HOT EN_PWR GND 41 ISL6334 VCC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI# VR_RDY RGND VSEN VDIFF FB COMP/FB REF DAC IMON OFS FS SS U1 RSS1 DNP DNP 1 2 3 4 5 6 7 8 9 TO GND TO GND 19 40 36 16 17 15 14 13 12 11 10 34 35 100k RSS1 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Vc5 62k RFS1 SI - 1P SI - 2P CI - 1P CI - 2P RGND VSEN TP29 Phase Dropping Decoding RN2 = Vishay, NTHS0805N02N6801 SI = Un-couppled Inductor CI = Couppled Inductor R344 PSI# VCC5 Csen DNP 2.2 R8 26.1k ROFS CVC RSS2 0.1u RFS2 DNP 1.30k 4 4 DNP PSI# Vc5 901k RMOFS 33nF C14 TP7 VR_RDY R346 C5 1n 0 RED 0 R90 FIGURE 8.FIGURE CONTROLLER CIRCUIT BOARD, C 130W REV - BURNSIDE ISL6334 VCC5 VR_RDY 10.2k RMON 2k R10 VCC5 R9 GREEN DNP CR2 Q24 2N7002 DNP C15 DNP VR_RDY R91 R88 0 C3 R3 C2 R345 12pF Place this close to the socket 249 390pF 5 TP15 IMON 5 DNP Expose these traces on external layers 237 R5 R1 1k R2 12.1k C1 150pF ISENSE ISENSE_DN SET R5+R1=R334; Average OC=100uA IMON OC Trip = 1.12V VSS_SENSE_DIE Controller circuit D C B A ISL6334EVAL1Z Schematics

3 July 7, 2010 TB486.0 Technical Brief 486 D C B A C J2 GND J1 V_CORE of 1 1 23 CO46 DNP Rail4 CO18 22u CO27 DNP CO9 22u Rail4 VCORE 1 1 CO45 DNP Rail4 Intersil Corporation Somerville, NJ 08876 CO26 22u 65 Readington Road CO17 22u CO8 22u CO44 22u CO34 DNP CO25 22u CO16 22u CO7 22u TP100 GND CO43 DNP CO24 22u CO47 330u CO15 22u CO6 22u CO33 330u ISL6334 Burnside - 130W Rev C Board Rail5 Title Title CO42 DNP CO23 22u CO14 22u CO5 22u CO32 330u TP50 GND CO38 330u Wednesday, December 05, 2007 CO41 DNP CO22 22u CO4 22u CO13 22u B Size Rev Size Rev Date: Sheet Date: Sheet CO37 330u CO31 330u CO12 22u CO21 22u CO40 22u CO3 22u 2SEPC330MW TP10 GND Place these hoods on different positions for scope probe ground CO36 330u CO30 330u CO20 DNP CO11 22u CO39 22u CO2 22u Rail2 CO10 DNP Rail1 CO35 330u CO1 22u CO19 DNP CO28 DNP Rail3 CO29 DNP 2 2 L2 ISEN3- ISEN4- L1 160nH L4 160nH ISEN2- 160nH ISEN1- Intersil Confidential L3 160nH C26 DNP C28 680uF C27 680uF C33 DNP RPS4 0 RPS2 0 C44 4.7u C46 4.7u C64 4.7u RPS3 0 C78 4.7u RPS1 0 C67 4.7u C70 4.7u C68 4.7u C79 4.7u C22 4.7u C30 DNP R46 2.2 C24 4.7u C32 DNP R47 2.2 C23 4.7u C31 DNP R71 2.2 C75 DNP R73 2.2 C76 4.7u Need new footprint and use bigger hole for T-core; Expose output copper for Coupled Inductors 3 3 PHASE1

PHASE3 PHASE2 PHASE4

QLT22 QUB1 QLT12 QUB3 QLT32 QUB2 QUB4 QLT42

2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 VCC12 VCC12 VCC12 VCC12 1 1 1 1 1 1 1 1 PHASE1 PHASE3 PHASE2 PHASE4

QLT11 UG2 QLT21 UG4 QLT41

UG3

UG1 2 3 2 3 2 3 3 QLT31 2 LG1 LG3 LG2 1 1 1 1 LG4 UG1 LG1 UG3 LG3 UG2 LG2 LG4 UG4 RPH4 0 RPH2 0 RPH1 0 RPH3 0 CB4 CB2 CB1 CB3 (Continued) 0.1u 0.1u 0.1u 0.1u 2 2 2 2 11 11 11 11 10 10 10 10 6 6 6 6 1 1 1 1 4 4 EP EP EP EP

BOOT BOOT BOOT BOOT

LGATE LGATE LGATE LGATE PHASE PHASE PHASE PHASE UGATE UGATE UGATE UGATE

GND/4 GND/4 GND/4 GND

5 5 5 5 FIGURE 9. STAGE POWER BOARD, REV C 130W - BURNSIDE ISL6334 CC1 1u CC4 1u CC3 1u CC2 1u ISL6622CR/12CR ISL6622CR/12CR ISL6622CR/12CR ISL6622CR/12CR VCC/PVCC UVCC/NC LVCC/VCC PWM GDV/NC VCC/PVCC UVCC/NC LVCC/VCC PWM GDV/NC VCC/PVCC UVCC/NC LVCC/VCC PWM GDV/NC VCC/PVCC UVCC/NC LVCC/VCC PWM GDV/NC UD1 UD3 UD2 UD4 9 8 7 4 3 9 8 7 4 3 9 8 7 4 3 9 8 7 4 3 Follow Intel Burside ATX Layout Guideline for Power Stage and LGA1366 Socket as well as Input Bus Line (1080 pre-preg stackup, 6 layers) Dual footprint for SI and CI - Expose Output Inductor Copper Dual footprint - LFPAK/DPAK for High-side (T/B) and Low-Side (B/T) CI: Phase1 (Thermistor) + Phase3 ; Phase2 Phase4 Default - 12VUG, LDO=LG. Hardware Options: 12VUG5VLG; LDO=UGLG; 5V DRIVER RGV1 DNP RGV3 DNP RGV2 DNP RGV4 DNP 0 0 0 0 RDU1 RDU3 RDU2 RDU4 PWM1 PWM3 PWM2 PWM4 1u 1u 1u 1u DNP CL1 CL3 CL2 CL4 RDL1 RDL3 RDL2 RDL4 0 0 0 5 5 R4V12 10 R2V12 10 R1V12 10 R3V12 10 VCC12 DNP RV5 VCC5 Power Stage D C B A ISL6334EVAL1Z Schematics

4 July 7, 2010 TB486.0 Technical Brief 486 D C B A C TPVIN Vin VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 of 4 3 VCC12 33 TP23 VID3 TP27 VID7

12V

+12V

5 5 TP22 VID2 TP26 VID6 1 Intersil Corporation Somerville, NJ 08876 1 65 Readington Road GND GND0 TP21 VID1 TP25 VID5 J4 2x2 Power Connector 1 2 TP20 VID0 TP24 VID4 RD7 10k TPGND Vin_GND ISL6334 Burnside - 130W Rev C Board RD6 10k Title Title RD5 10k 1 Tuesday, January 08, 2008 SW1 RD4 10k B

Size Rev Size Rev

Date: Sheet Date: Sheet

RD3 10k 2 4 RD2 10k J0 Increase Resistor Value to improve LL efficiency. 3 RD1 10k VCC5 VCC5 8 20 16 3 14 5 7 15 17 18 19 24 VCC5 C107 0.1u C108 0.1u RD0 10k NC -12V GND 2 2

GND0 GND1 GND2 GND3 GND4 GND5 GND6

16 16 5 5 15 15 6 6 3 8 13 18 3 8 13 18 25 PS_ON# 25 PWR_OK nc nc VEE VEE VCC VCC GND GND COM1 COM2 COM3 COM4 COM1 COM2 COM3 COM4 +3.3V +3.3VA +3.3VB +3.3VC +5V +5VA +5VB +5VC +5VD +5VSB +12V1A +12V1B J21 ATX 24-Pin Connector NC1 NC2 NC3 NC4 NO1 NO2 NO3 NO4 EN1 EN2 EN3 EN4 NC1 NC2 NC3 NC4 NO1 NO2 NO3 NO4 EN1 EN2 EN3 EN4 U6 ISL43240 U7 ISL43240 1 2 4 6 9 12 13 21 22 23 10 11 4 7 2 9 1 4 7 2 9 1 14 17 12 19 10 11 20 14 17 12 19 10 11 20 0 Intersil Confidential R101 VTT_VID0 VTT_VID1 VTT_VID2 VTT_VID3 VTT_VID4 VTT_VID5 VTT_VID6 VTT_VID7 J5 10u C99 VCC5 EN_VTT C106 10n Use Intersil/VTT Interposer for DCLL Measurement TP28 ENABLE 3 3 2 SW2

R78 10k

1 3 VSEN RGND VCC5 VSEN RGND TP8 TP9 VR_RDY EN_VTT JP9 6 4 VCC5 R74 10k SW3 SW DIP-8 VSS_SENSE_DIE VID Code VTT C12 DNS DEMO R62 DNP R66 DNP RDIEP RDIEN C37 DNP C41 DNP R100 R99 0 0 R61 DNP R65 DNP DNS 100 C36 DNP C40 DNP DNS VCORE LG2 LG4 RLCP 100 RLCN (Continued) R64 DNP R60 DNP C39 DNP C35 DNP FIGURE 10.FIGURE BURNSIDE - 130W REV C BOARD ISL6334 VTTPWRGOOD Add via on AR18 and AR17 for test points R63 DNP 4 R59 DNP VCC_SENSE_DIE VSS_SENSE_DIE 4 C38 DNP C34 DNP VID generator, LGA1366 socket and input connectors LG3 LG1 Per Intel Request, but not needed AR7 AR9 AR8 NEED BNC FOOTPRINT VSS VCC AB35 AR18 AR17 LG3

QLB32

LG4

4 PSI

QLB42 TP68

5 3 4

2 5 3

1 UG4 2

UG3 1 LG3 UG4 QLB31

LG4 4 LGA1366_SOCKET

QUT4 QLB41

UG3 4 5 3 4

QUT3

4 5 3 2 5 3

5 3 1 2 VCC12 2

PHASE3 AP7 AL10 AL9 AN9 AM10 AN10 AP9 AP8 AN8 AK8 AK7 2 1 VCC12 1 1 U100 PHASE4 PHASE3 PHASE4 PHASE3 LG1

QLB12

UG2 LG2 R79 100k

4 PHASE4

UG1 QLB22

5 3 4

VTT_VID0 VTT_VID1 VTT_VID2 VTT_VID3 VTT_VID4 VTT_VID5 VTT_VID6 VTT_VID7 ISENSE 2 5 3

VCC5 1 2

QUT1

ISENSE_DN

UG1 UG2 1 5 4 5

QUT2

5 3 4

LG1 5 3 VCC12 2 DEMO

QLB11

LG2 2 4 1 VCC12

QLB21

1 5 3 4

2 5 3

1 SW5 SW DIP-4 1 PHASE2 PHASE1 Place These FETs on Top Side for Intel Burnside CRB Design PHASE2 0 1 BNC VTT PHASE1 ONLY 1 "ON" code allowed PHASE2 PHASE1 PHASE2 Place These FETs on Bottom Side for Intel Burnside CRB Design (Depending Upon the Layout, we might drop this) PHASE1 PSI# D C B A ISL6334EVAL1Z Schematics

5 July 7, 2010 TB486.0 Technical Brief 486 D C B A A Rev Rev VSS of 55 VSS Intersil Corporation C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 LGA1366 SOCKET PIN OUT VSS VSS VSS VSS VSS Title Title

A4 A5 A6 A7 A8 A9 A10 A14 A15 A16 A17 A18 A19 A20 A24 A25 A26 A27 A28 A29 A30 A31 A35 A36 A37 A38 A39 A40 A41

D20 D21

Tuesday, January 08, 2008

C20

VSS VSS VSS D22 VSS VSS

C19 D23

C18 D24 Custom

Size

Date: Sheet Date: Sheet C17 D25

C16 D26

C15 D27

1 1 C14 D28

C13 D29

C12 D30

MN8 C11 D31

C10 D32

VSS

C9 D33 MN7 U100-6

C8 1366LGA_6 D34

MN6 C7 D35

C6 U100-7 D36

VSS

C5 D37

1366LGA_6 MN5

VSS C4 D38

MN4 C3 D39

C2 D40

MN3 D41

D42

VSS MN2 D43 MN1 VSS VSS VSS VSS E1 E2 E3 E4 E5 E6 E7 E8 E9 VSS VSS VSS E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 E41 E42 E43 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 VSS VSS

AC39 AC40 AC41 AC42 AC43 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AD33 AD34 AD35 AD36 AD37 AD38 AD39 AD40 AD41 AD42 AD43 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AE33 AE34 AE35 AE36 AE37 AE38 AE39 AE40 AE41 AE42 AE43 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11

AF33

VSS AF34 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS AF35

AC38 AF36

AC37 AF37

VSS VSS AC36 AF38

AC35 AF39

AC34 AF40

VSS F38 F39 F40 F41 F42 F43 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 G41 G42 G43 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 AC33 AF41

AF42

AB11 AF43

VSS VSS VSS VSS VSS VSS VSS VSS VSS

AB10 AF11

F37

AB9 AF10

F36

AB8 AF9

F35 H22

VSS

VSS AB7 AF8

F34 H23

AB6 AF7

F33 H24

AB5 AF6

F32 H25

VSS VSS

AB4 AF5

F31 H26

AB3 AF4

F30 H27

AF3

VSS F29 H28

AF2

F28 H29

AB43 AF1

VSS F27 H30

VSS

AB42

F26 H31

2 VSS 2 AB41 AG43

H32

VSS

AB40 AG42

F25 H33

AB39 AG41

F24 H34

AB38 AG40

VSS

F23 H35

VSS

AB37 AG39

F22 H36

AB36 AG38

F21 H37

VTTPWRGOOD

AB35 AB35 AG37

F20 H38

AB34 AG36

F19 H39

PROCHOT#

AB33 AG35

VSS F18 H40

AG34

F17 H41

VSS

AA11 AG33

F16 H42

VSS

AA10 AG11

F15 H43

VSS

AA9 AG10

F14

VSS

AA8 AG9

VSS F13 J43

AA7 AG8

F12 J42

AA6 AG7

F11 J41

AA5 AG6

F10 J40

AA4 AG5

VSS

F9 J39

VSS

AA3 AG4

VSS

F8 J38

VSS

AG3

F7 J37

AG2

F6 J36

AG1

F5 J35

VSS

F4 J34

AA41 AH43

VSS F3 J33

AA40 AH42

F2 J32

VSS

AA39 AH41

F1 J31

VSS

AA38 AH40

J30

VSS AA37 AH39

AA36 AH38

VSS

AA35

AH37 VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

AA34 AH36

U100-5

AA33

AH35 J1 J2 J3 J4 J5 J6 J7 J8 J9

K9 K8 K7 K6 K5 K4 K3 K2 K1 1366LGA_6

J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29

VSS K43 K42 K41 K40 K39 K38 K37 K36 K35 K34 K33 K32 K31 K30 K29 K28 K27 K26 K25 K24 K23 K22 K21 K20 K19 K18 K17 K16 K15 K14 K13 K12 K11 K10 AH34

VCC AH33

VCC AH11

AH10

AH9

AH8

VSS AH7

AH6

AH5

AH4

AH3

AH2

VSS AH1 VCC VCC VCC VSS VSS VCC VSS VCC VSS VSS VCC VCC VSS VCC VSS VCC VSS VCC VSS ISENSE_DN ISENSE VCC VSS VCC VCC VCC VSS VCC VCC VSS VSS VSS VSS VCC VSS VSS VSS U100-3 1366LGA_6 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AJ10 AJ11 AJ33 AJ34 AJ35 AJ36 AJ37 AJ38 AJ39 AJ40 AJ41 AJ42 AJ43 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38 AK39 AK40 AK41 AK42 AK43 AK7 AK8 VSS VCC 3 3 AP7 AP8 AP9 AN8 AN9 AN10 VSS AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 AN40 AN41 AN42 AN43 AP1 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34 AP35 AP36 AP37 AP38 AP39 AP40 AP41 AP42 AP43 VSS VSS VSS VSS VSS VSS VSS VSS VSS

VCC VCC VCC VCC VCC VSS VCC VCC VCC VSS VID5 VSS VID2 VID4 VCC VCC VCC VSS VCC VSS VCC VCC VSS VSS VID6 VCC VSS VCC VSS VCC VCC VCC VCC VCC VCC VCC VSS VID7 VCC VCC VSS VSS VSS VCC VSS VSS VSS VCC VSS VSS VCC VSS VSS VSS VCC VCC

PSI #

AR43 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 M34 M35 M36 M37 M38 M39 M40 M41 M42 M43 N33 N34 N35 N36 N37 N38 N39 N40 N41 N42 N43 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43

AM43 AR42

AM42 AR41

VSS

VSS VCC VSS VSS VSS VSS VSS VSS VCC VSS VCC VSS VSS VSS VSS VCC VCC VCC

AM41

AR40 VSS

VCC

VSS

M23 P11 AM40 AR39

VSS

M22 P10 AM39 AR38

VCC

M21 P9 AM38 AR37

VSS VSS

VSS M20 P8 AM37 AR36

VCC

VSS M19 P7

AM36 AR35

VSS

VSS VCC

M18 P6 AM35 AR34

VCC VCC

M17 P5 AM34 AR33

VSS

VCC M16 P4 AM33 AR32

VCC VSS

VSS VCC

M15 P3

AM32 AR31

VSS

VCC

M14 P2 AM31 AR30

VCC

VCC VSS M13 P1

AM30 AR29 VSS

VCC VSS M12 AM29 AR28

VCC VCC M11 R43 AM28 AR27

VCC VSS

M10 R42 AM27 AR26

VSS

VSS VCC M9 R41 AM26 AR25

VCC VCC

M8 R40 AM25 AR24

VSS

VCC VSS M7 R39 AM24 AR23

VSS VSS M6 R38 AM23 AR22

VSS VCC

M5 R37

AM22 AR21

VSS 11.FIGURE PINOUT SOCKET LGA1366

VCC VSS M4 R36 AM21 AR20

VSS VCC

M3 R35 AM20 AR19

VSS

VCC VCC_NORTH

M2 R34 AM19 AR18

VCC

VCC VSS_NORTH M1 R33

AM18 AR17

VCC

VSS VCC R11 AM17 AR16

VCC VCC R10 AM16 AR15

VSS VCC L43 R9 AM15 AR14

VSS L42 R8 VCC AM14 AR13

VCC

VCC L41 R7 AM13 AR12

VSS

VCC VSS

L40 R6 AM12 AR11

VSS

VCC VSS L39 R5 AM11 AR10

VID3 VCC_SENSE L38 R4 AM10 AM10 AR9

VSS VSS_SENSE L37 R3 AM9 AR8

VR_READY L36 R2

AM8 AR7

(Continued) VSS

L35 R1 AM7 AR6

VSS

L34 AM6 AR5

VSS L33 T43 AM5 AR4

VSS L32 T42 AM4 AR3

VSS L31 T41 AM3 AR2

L30 T40

AM2 AR1

VSS

L29 T39 AM1

L28 T38 AT43

L27 T37 AT42

VSS L26 T36 AL43 AT41

VSS

L25 T35 AL42 AT40

VSS

L24 T34 AL41 AT39

4 AR17 AR18 VCC 4

VSS AR7 AR8 AR9

L23 T33 AL40 AT38

VCC

L22 T11 AL39 AT37

L21 T10 AL38 AT36

VSS

VSS VSS L20 T9 AL37 AT35

VCC VSS L19 T8 AL36 AT34

VSS VCC L18 T7 AL35 AT33

VSS VCC L17 T6 AL34 AT32

VCC VCC

L16 T5 AL33 AT31

VSS

VCC VSS L15 T4 AL32 AT30

VSS VCC L14 T3 AL31 AT29

VCC VCC L13 T2 AL30 AT28

VSS VCC L12 T1 AL29 AT27

VCC VSS L11 AL28 AT26

VCC VCC

L10 U43 AL27 AT25

VSS VSS

VSS VCC L9 U42 AL26 AT24

VSS VCC L8 U41 AL25 AT23

VSS VCC L7 U40 AL24 AT22

VCC VSS L6 U39 AL23 AT21

VSS VSS

L5 U38 AL22 AT20

VSS VSS

VCC VCC L4 U37 AL21 AT19

VCC VSS L3 U36 AL20 AT18

VSS L2 U35 VCC AL19 AT17

VCC VCC L1 U34 AL18 AT16

VCC VSS U33 AL17 AT15

VSS VCC AL16 AT14

VCC VCC AL15 AT13

VCC VSS AL14 AT12

VSS VSS VSS VSS VSS VSS VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS

VSS VCC VSS U100-4 1366LGA_6 AL13 AT11

VCC VCC AL12 AT10

Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9

V1 V2 V3 V4 V5 V6 V7 V8 V9 VSS VCC U1 U2 U3 U4 U5 U6 U7 U8 U9

AL11 AT9 W1 W2 W3 W4 W5 W6 W7 W8 W9

Y10 Y11 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y41 V10 V11 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43

U10 U11

W10 W11 W33 W34 W35 W36 W37 W38 W39 W40 W41 W42 W43

AL10 VID0 VSS AL10 AT8

VID1 VSS AL9 AL9 AT7

AL8 AT6

VSS AL7 AT5

AL6 AT4

AL5 AT3

AL4 AT2

AL3 AT1

VSS AL2

VSS AL1 VSS VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS VSS VCC VSS VCC VCC VSS VSS VSS VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS AV1 AV2 AV3 AV4 AV5 AV6 AV7 AV8 AV9 U100-2 AU1 AU2 AU3 AU4 AU5 AU6 AU7 AU8 AU9 AV10 AV11 AV12 AV13 AV14 AV15 AV16 AV17 AV18 AV19 AV20 AV21 AV22 AV23 AV24 AV25 AV26 AV27 AV28 AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AV37 AV38 AV39 AV40 AV41 AV42 AV43 AU10 AU11 AU12 AU13 AU14 AU15 AU16 AU17 AU18 AU19 AU20 AU21 AU22 AU23 AU24 AU25 AU26 AU27 AU28 AU29 AU30 AU31 AU32 AU33 AU34 AU35 AU36 AU37 AU38 AU39 AU40 AU41 AU42 AU43 1366LGA_6 VCC VSS VCC 5 5

AW36 AW35 AW34 AW33 AW32 AW31 AW30 AW29 AW28 AW27 AW26 AW25 AW24 AW23 AW22 AW21 AW20 AW19 AW18 AW17 AW16 AW15 AW14 AW13 AW12 AW11 AW10 AW9 AW8 AW7 AW6 AW5 AW4 AW3 AW2 AW1 AY42 AY41 AY40 AY39 AY38 AY37 AY36 AY35 AY34 AY33 AY32 AY31 AY30 AY29 AY28 AY27 AY26 AY25 AY24 AY23 AY22

AW37

AW38 VCC VSS VCC VCC VCC VSS VCC VSS VSS VCC VSS VSS VSS VCC VSS VCC VCC VCC VSS VSS VCC VCC VSS VSS VSS VCC VSS VSS VSS VSS VSS VCC VSS VCC VSS

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

AW39

VCC AW40 AY21

VSS AW41 AY20

VCC AW42 AY19 1366LGA_6 VCC VSS VCC VCC VSS VCC VCC VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VSS VSS VCC VSS VSS VCC VCC VSS VCC VSS VCC VSS VSS VSS VCC VSS VCC U100-1 AY2 AY3 AY4 AY5 AY6 AY7 AY8 AY9 BA3 BA4 BA5 BA6 BA7 BA8 BA9 AY10 AY11 AY12 AY13 AY14 AY15 AY16 AY17 AY18 BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 BA24 BA25 BA26 BA27 BA28 BA29 BA30 BA35 BA36 BA37 BA38 BA39 BA40 VCC D C B A ISL6334EVAL1Z Schematics

6 July 7, 2010 TB486.0 Technical Brief 486

ISL6334EVAL1Z Board Layout

FIGURE 12. TOP SILKSCREEN

7 July 7, 2010 TB486.0 Technical Brief 486