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|MO NAMAN ANTARA MARIAUS009773561B1 DEL MAI MARI ACTUAL UN ATTEN (12 ) United States Patent ( 10) Patent No. : US 9 ,773 ,561 B1 Um ( 45 ) Date of Patent : Sep . 26 , 2017 (54 ) NONVOLATILE MEMORY DEVICE AND ( 58) Field of Classification Search DATA STORAGE DEVICE INCLUDING THE CPC ...... G11C 16 / 16 ;G11C 16 / 14 ;G11C 16 /3445 SAME USPC ...... 365/ 185. 29 ( 71) Applicant : SK hynix Inc ., Gyeonggi- do (KR ) See application file for complete search history . (72 ) Inventor : Gi Pyo Um , Gyeonggi- do (KR ) (56 ) References Cited (73 ) Assignee : SK Hynix Inc ., Gyeonggi -do (KR ) U .S . PATENT DOCUMENTS ( * ) Notice : Subject to any disclaimer, the term of this 6 ,331 , 953 BIB1 * 12/ 2001 Wang ...... GIIC 11/ 5671 patent is extended or adjusted under 35 365 / 185 . 29 U . S .C . 154 (b ) by 0 days. * cited by examiner ( 21 ) Appl. No. : 15 / 609, 540 Primary Examiner — Jason Lappas (22 ) Filed : May 31 , 2017 ( 74 ) Attorney , Agent, or Firm — IP & T Group LLP Related U . S . Application Data ABSTRACT (63 ) Continuation of application No . 15 /081 , 306 , filed on (57 ) Mar. 25 , 2016 , now Pat . No . 9 ,697 , 903. A data storage device includes a nonvolatile memory device ; and a controller suitable for providing a normal erase ( 30 ) Foreign Application Priority Data command or a fine erase command to the nonvolatile memory device , wherein the nonvolatile memory device Dec . 30 , 2015 (KR ) ...... 10 - 2015 - 0189481 performs a first normal erase loop in which a first normal erase voltage and an erase verify voltage are applied to erase (51 ) Int. Ci. target memory cells , according to the normal erase com G11C 16/ 16 ( 2006 .01 ) mand , and performs a first fine erase loop in which a first fine GIIC 16 / 14 (2006 . 01 ) erase voltage and the erase verify voltage are applied to the GIIC 16 / 34 ( 2006 . 01 ) erase target memory cells , according to the fine erase (52 ) U .S . CI. command . CPC ...... GIIC 16 / 14 ( 2013 . 01 ) ; GIIC 16 /3445 ( 2013 .01 ); GIIC 16 / 16 ( 2013 .01 ) ; GIIC 16 / 34 ( 2013 .01 ) 6 Claims, 11 Drawing Sheets

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NONVOLATILE MEMORY DEVICE AND in which the voltage generator is controlled such that a first DATA STORAGE DEVICE INCLUDING THE normal erase voltage and an erase verify voltage are applied SAME to erase target memory cells among the memory cells , according to a normal erase command provided from an CROSS -REFERENCES TO RELATED 5 external device, and perform a first fine erase loop in which APPLICATION the voltage generator is controlled such that a first fine erase voltage and the erase verify voltage are applied to the erase This application is a continuation of U . S . patent applica - target memory cells , according to a fine erase command tion Ser. No. 15 / 081, 306 filed on Mar. 25 , 2016 , which provided from the external device . claims priority under 35 U . S .C . $ 119( a ) to Korean applica - 10 According to the embodiments , it is possible to densely tion number 10 - 2015 -0189481 , filed on Dec . 30 , 2015 , in the form an erased state distribution of memory cells included in Korean Intellectual Property Office. The disclosure of each a nonvolatile memory device. of the foregoing application is incorporated herein by ref erence in its entirety . BRIEF DESCRIPTION OF THE DRAWINGS 15 BACKGROUND FIG . 1 is a block diagram of a nonvolatile memory device , according to an embodiment of the invention . 1 . Technical Field FIG . 2 is a diagram illustrating an example of threshold Various embodiments generally relate to a data storage voltage distributions of memory cells included in a memory device including a nonvolatile memory device and , more 20 cell array of the nonvolatile memory device of FIG . 1 . particularly, to a data storage device capable of densely FIG . 3 is a diagram illustrating an example of threshold forming an erased state distribution of memory cells voltage distributions of memory cells included in a memory included in a nonvolatile memory device . cell array of the nonvolatile memory device of FIG . 1 . 2 . Related Art FIGS. 4 and 5 are diagrams illustrating a stepwise erase The paradigm for the computer environment has shifted 25 method , according to an embodiment of the invention . into ubiquitous computing so that computer systems can FIGS . 6 to 8 are diagrams illustrating a normal erase now be used anywhere and at any time. As a result , use of operation and a fine erase operation , according to an portable electronic devices , such as mobile phones, digital embodiment of the invention . cameras, and notebook computers has rapidly increased . FIG . 9 is a block diagram of a data storage device , Generally , such portable electronic devices use a data stor - 30 according to an embodiment of the invention . age device comprising a memory device . The data storage FIG . 10 is a diagram illustrating an example of a firmware device is typically used as an auxiliary memory device of the or a software to be driven in a random access memory of the portable electronic devices . data storage device of FIG . 9 . A data storage device using amemory devicemay provide FIG . 11 is a block diagram of a data processing system excellent stability and durability , high information access 35 including a data storage device , according to an embodiment speed , and low power consumption , since there is no of the invention . mechanical driving part. Data storage devices having such FIG . 12 is a block diagram of a data processing system advantages include a universal serial bus (USB ) memory including a solid state drive ( SSD ) , according to an embodi device, memory cards having various interfaces, and a solid ment of the invention . state drive (SSD ). 40 FIG . 13 is a block diagram of an example of an SSD For portable electronic devices to be able to play large controller of the solid state drive of FIG . 12 . files such as music or video files , data storage devices having FIG . 14 is a block diagram of an example of a computer large storage capacity are required . High storage capacity system including a data storage device , according to an data storage devices employ, as storage media , memory embodiment of the invention . devices having high integration degree in memory cells , 45 such as, for example , flash memory devices . DETAILED DESCRIPTION SUMMARY The present invention , advantages, features and methods thereof will become more apparent after a reading of the Various embodiments are directed to a data storage device 50 following exemplary embodiments in conjunction with the capable of densely forming an erased state distribution of drawings . The present invention may , however, be embodied memory cells included in a nonvolatile memory device . in different forms and should not be construed as being In an embodiment, a data storage device may include : a limited to the embodiments set forth herein . Rather, these nonvolatile memory device ; and a controller configured to embodiments describe the present invention in sufficient provide a normal erase command or a fine erase command 55 detail to allow a person skilled in the relevant art to practice to the nonvolatile memory device , wherein the nonvolatile the present invention . memory device performs a first normal erase loop in which It is to be understood that embodiments of the present a first normal erase voltage and an erase verify voltage are invention are not limited to the particulars shown in the applied to erase target memory cells , according to the drawings, that the drawings are not necessarily to scale , and , normal erase command , and performs a first fine erase loop 60 in some instances , proportions may have been exaggerated in which a first fine erase voltage and the erase verify voltage in order to more clearly depict certain features of the are applied to the erase target memory cells, according to the invention . While particular terminology is used herein , it is fine erase command . to be appreciated that the terminology used is for the purpose In an embodiment, a nonvolatile memory device may of describing particular embodiments only and is not include : memory cells ; a voltage generator configured to 65 intended to limit the scope of the present invention . generate voltages to be provided to the memory cells ; and a As used herein , the term “ and /or ” includes any and all control logic configured to perform a first normal erase loop combinations of one or more of the associated listed items . US 9 ,773 ,561 B1 It will be understood that when an element is referred to as correspond to respective bit lines BL1 to BLn with data being “ on ," " connected to ” or “ coupled to ” another element, input/ output lines or data input/ output buffers (not shown ), it may be directly on , connected or coupled to the other based on a decoded address . element or intervening elements may be present. As used The voltage generator 150 may generate voltages to be herein , a singular form is intended to include plural forms as 5 used in internal operations of the nonvolatile memory device well , unless the context clearly indicates otherwise . It will be 100 , according to control of the control logic 160 . The further understood that the terms “ includes ” “ including, " voltages generated by the voltage generator 150 may be " comprises, " " comprising, " " has, ” “ having ” and the like applied to the memory cells of the memory cell array 110 . when used in this specification , specify the presence of at For example, in a program operation , a program voltage and least one recited feature , step , operation , and / or elements , 10 a program verify voltage may be applied to a word line of but do not preclude the presence or addition of one or more memory cells for which the program operation is to be other un -recited features , steps , operations , and / or elements . performed . For another example , in an erase operation , an Hereinafter , a nonvolatile memory device, a data storage erase voltage may be applied to an area of memory cells for device including the same, and other embodiments of the which the erase operation is to be performed , and an erase invention will be described below with reference to the 15 verify voltage may be applied to word lines ofmemory cells accompanying drawings . for which the erase operation is to be performed . For still FIG . 1 is a block diagram illustrating a representation of another example , in a read operation , a read voltage may be an example of a nonvolatile memory device according to an applied to a word line ofmemory cells for which the read embodiment. operation is to be performed . Referring to FIG . 1 , a nonvolatile memory device 100 , 20 The control logic 160 may control general operations of according to an embodiment of the invention , may include the nonvolatile memory device 100 , based on control signals a memory cell array 110 , a row decoder 120 , a column provided from an external device . For example , the control decoder 130 , a data read /write block 140 , a voltage genera logic 160 may control main operations of the nonvolatile tor 150 , and a control logic 160 . memory device 100 , such as read , program and erase The memory cell array 110 may include memory cells 25 operations of the nonvolatile memory device 100 . MC arranged at areas where word lines WL1 to WLm and The control logic 160 may control two erase modes . In bit lines BL1 to BLn intersect with each other. The memory other words, the control logic 160 may control a normal cells may be grouped into different access units for erase and erase mode and a fine erase mode according to an erase program (write ) or read operations . For example , the command provided from the external device . memory cells may be grouped into an access unit , such as a 30 For instance , if a normal erase command is provided from memory block as an erase unit and a page as a program and the external device , the control logic 160 may perform a read unit . normal erase operation for memory cells of the memory cell The row decoder 120 may be coupled with the memory array 110 which are requested to be erased . In order to cell array 110 through the word lines WL1 to WLm . Opera - perform the normal erase operation , the control logic 160 tion of the row decoder 120 may be controlled by the control 35 may control the voltage generator 150 to generate an erase logic 160 . The row decoder 120 may decode an address voltage and an erase verify voltage to be used in the normal provided from an external device (not shown ) . The row erase operation . decoder 120 may select one of the word lines WL1 to WLm F or another instance, if a fine erase command is provided and drive the selected one and the unselected word lines, from the external device , the control logic 160 may perform based on a decoded address . The row decoder 120 may 40 a fine erase operation for memory cells of the memory cell provide word line voltages provided from the voltage gen - array 110 which are requested to be erased . In order to erator 150 , to the word lines WL1 to WLm as may be perform the fine erase operation , the control logic 160 may neneeded . control the voltage generator 150 to generate an erase The data read /write block 140 may be coupled with the voltage and an erase verify voltage to be used in the fine memory cell array 110 through the bit lines BL1 to BLn . The 45 erase operation . data read /write block 140 may include a plurality of read ! The normal and the fine erase operations will be described write circuits RW1 to RWn corresponding to the bit lines below in more detail . BL1 to BLn , respectively. The data read /write block 140 FIG . 2 is a diagram illustrating an example of threshold may operate according to control of the control logic 160 . voltage distributions of memory cells included in the The data read /write block 140 may operate as a write driver 50 memory cell array 110 of the memory device 100 of FIG . 1 . or a sense amplifier according to an operation mode . For As shown in FIG . 2 , each memory cell may be a single example , in a write operation , the data read /write block 140 level cell (SLC ) type. Each SCL type memory cell may be may operate as a write driver which stores data provided erased to have a threshold voltage of an erased state E , and from the external device , in the memory cell array 110 . For may be programmed to have a threshold voltage of a another example, in a read operation , the data read /write 55 programmed state P . block 140 may operate as a sense amplifier which reads out In a read operation , a read voltage Vrd _ P having a voltage data from the memory cell array 110 . level between the erased state E and the programmed state An operation of storing data in the memory cell array 110 Pmay be applied to memory cells . If the read voltage Vrd _ P may be referred to as a write operation or a program is applied , a memory cell having a threshold voltage of the operation . For the sake of convenience in explanation , 60 erased state E may be identified as an on cell which stores hereafter, an operation of storing data in the memory cell data “ 1 , " and a memory cell having a threshold voltage of array 110 will be referred to as a program operation . the programmed state P may be identified as an off cell Operation of the column decoder 130 may be controlled which stores data " 0 ." by the control logic 160 . The column decoder 130 may In a program operation , in order to determine whether decode an address provided from an external device (not 65 memory cells are completely programmed , a program verify shown ) . The column decoder 130 may couple the read /write voltage Vvf _ P having a voltage level higher than the read circuits RW1 to RWn of the data read /write block 140 which voltage Vrd _ P may be applied to the memory cells . If the US 9 , 773 ,561 B1 program verify voltage Vvf_ P is applied , a memory cell higher than the program verify voltage Vvf_ P1 may be which has a threshold voltage lower than or equal to the identified as an off cell which stores data “ 0 , " that is , a program verify voltage Vvf_ P may be identified as an on cell memory cell which is completely programmed . which stores data “ 1, " that is , a memory cell which is not If the program verify voltage Vvf_ P2 is applied to completely programmed , and a memory cell which has a 5 memory cells which should be programmed to the second threshold voltage higher than the program verify voltage programmed state P2 . a memory cell which has a threshold Vvf_ P may be identified as an off cell which stores data “ O ," voltage lower than or equal to the program verify voltage that is , a memory cell which is completely programmed . In an erase operation , in order to determine whether Vvf_ P2 may be identified as an on cell which stores data memory cells applied with an erase voltage are completely 10 “ 1 ,” that is , a memory cell which is not completely pro erased , an erase verify voltage Vvf_ E may be applied to the grammed , and a memory cell which has a threshold voltage memory cells . If the erase verify voltage Vvf _ E is applied , higher than the program verify voltage Vvf_ P2 may be a memory cell which has a threshold voltage lower than or identified as an off cell which stores data “ O , ” that is , a equal to the erase verify voltage Vvf _ E may be identified as memory cell which is completely programmed . an on cell which stores data “ 1 , " that is, a memory cell which 15 If the program verify voltage Vvf_ P3 is applied to is completely erased , and a memory cell which has a memory cells which should be programmed to the third threshold voltage higher than the erase verify voltage Vyf E programmed state P3 , a memory cell which has a threshold may be identified as an off cell which stores data “ O ,” that voltage lower than or equal to the program verify voltage is , a memory cell which is not completely erased . Vvf_ P3 may be identified as an on cell which stores data FIG . 3 is a diagram illustrating a representation of an 20 “ 1, ” that is, a memory cell which is not completely pro example of threshold voltage distributions of memory cells grammed , and a memory cell which has a threshold voltage included in the memory cell array 110 of FIG . 1 . higher than the program verify voltage Vvf _ P3 may be As shown in FIG . 3 , each memory cell may be a 2 - bit identified as an off cell which stores data “ 0 ,” that is , a multi -level cell (MLC ) type . Each memory MLC type cell memory cell which is completely programmed . may be erased to have a threshold voltage of an erased state 25 In an erase operation , in order to determine whether E , and may be programmed to have a threshold voltage of memory cells applied with an erase voltage are completely any one among a plurality of programmed states P1 , P2 and erased , an erase verify voltage Vvf _ E may be applied to the P3 . memory cells . If the erase verify voltage Vvf _ E is applied , In a read operation , any one of a first read voltage Vrd _ P1 a memory cell which has a threshold voltage lower than or having a voltage level between the erased state E and a first 30 equal to the erase verify voltage Vvf_ E may be identified as programmed state P1 , a second read voltage Vrd _ P2 having an on cell which stores data “ 1, ” that is , a memory cell which a voltage level between the first programmed state P1 and a is completely erased , and a memory cell which has a second programmed state P2 , and a third read voltage threshold voltage higher than the erase verify voltage Vvf _ E Vrd _ P3 having a voltage level between the second pro - may be identified as an off cell which stores data “ 0 , ” that grammed state P2 and a third programmed state P3 may be 35 is , a memory cell which is not completely erased . applied to memory cells . FIGS . 4 and 5 are diagrams illustrating a stepwise erase If the second read voltage Vrd _ P2 is applied , memory method , according to an embodiment of the invention . cells having threshold voltages of the erased state E and the As shown in FIGS . 4 and 5 , in order to reduce the time first programmed state P1 may be identified as on cells required for an erase operation and make threshold voltage which store LSB data “ 1 , " and memory cells having thresh - 40 distributions denser, memory cells may be erased using a old voltages of the second programmed state P2 and the third programmed state P3 may be identified as off cells which According to the stepwise erase method , an erase voltage store LSB data “ O . ” Vera of one pulse may be applied to a block area ofmemory If the first read voltage Vrd _ P1 is applied , a memory cell cells , and thereafter , an erase verify voltage Vvf_ E may be having a threshold voltage of the erased state E may be 45 applied to verify whether or not all of the memory cells are identified as an on cell which stores MSB data “ 1 , " and a erased . Namely, the erase verify voltage Vvf _ E may be memory cell having a threshold voltage of the first pro - applied each time the erase voltage Vera of one pulse is grammed state P1 may be identified as an off cell which applied to memory cells . An erase operation of applying the stores MSB data “ 0 .” erase voltage Vera and an erase verify operation of applying If the third read voltage Vrd _ P3 is applied , a memory cell 50 the erase verify voltage Vvf_ E may constitute an erase loop having a threshold voltage of the second programmed state EL . P2 may be identified as an on cell which stores MSB data After an erase verify operation of a first erase loop EL1 is “ 0 , " and a memory cell having a threshold voltage of the performed , when it is determined that at least one memory third programmed state P3 may be identified as an off cell cell which is not completely erased exists , the erase voltage which stores MSB data “ 1 ." 55 Vera may be increased by an increment AV , and a second In a program operation , in order to determine whether erase loop EL2 may be performed . That is to say, the erase memory cells are completely programmed , program verify loop EL may be repeated with the erase voltage VERA being voltages Vvf_ P1 , Vvf _ P2 and Vvf _ P3 having voltage levels increased in a stepwise manner each time by an increment higher than the read voltages Vrd _ P1, Vrd _ P2 and Vrd _ P3, AV until all the memory cells are erased to threshold respectively , may be applied to the memory cells . 60 voltages lower than or equal to the erase verify voltage If the program verify voltage Vvf _ P1 is applied to Vvf _ E . If not all the memory cells are erased to the erased memory cells which should be programmed to the first state E even though the erase loop EL has been performed programmed state P1, a memory cell which has a threshold a maximum number of times , the erase operation may be voltage lower than or equal to the program verify voltage ended as a “ fail. ” Vvf_ P1 may be identified as an on cell which stores data 65 FIGS. 6 to 8 are diagrams illustrating a normal erase “ 1 , " that is , a memory cell which is not completely pro - operation and a fine erase operation , according to an grammed , and a memory cell which has a threshold voltage embodiment of the invention . We note that in FIGS. 6 and US 9 , 773 ,561 B1 7 , symbols including “ _ N ” denote the normal erase opera and thereafter , the erase verify voltage Vvf_ E may be tion , whereas including “ _ F ” denote the fine erase operation applied to verify whether or not all of the memory cells are As shown in FIG . 7 , while the normal erase operation is erased . performed , normal erase loops EL1 _ N , EL2 _ N , EL3 _ When the fine erase loops EL1 _ F , EL2 _ F , EL3 _ F , . . . are N , . . .may be performed in a stepwise manner . For the sake 5 performed in a stepwise manner , as in threshold voltage of convenience in explanation , memory cells for which an distributions E1 _ F , E2 _ F , . . . shown in FIG . 6 , the threshold erase operation is to be performed , that is , erase target voltages of the memory cells may be gradually shifted from memory cells , will be referred to as memory cells . the programmed state P toward a fine erased state E _ F . When a first normal erase loop EL1 _ N is performed , a Finally , all of the memory cells may be erased to have first normal erase voltage V _ N may be applied to a block " threshold voltages of the fine erased state E F . area of the memory cells, and thereafter , an erase verify The voltage level of the first normal erase voltage V _ N voltage Vvf_ E may be applied to verify whether or not all applied to the memory cells while an initial erase loop ( that of the memory cells are erased . When it is determined that is , the first normal erase loop EL1 N ) of the normal erase not all of the memory cells are erased by the first normal 16 loops is performed may be higher than the voltage level of erase loop EL1 _ N , a second normal erase loop EL2 _ N may the first fine erase voltage V _ F applied to the memory cells be performed . while an initial erase loop ( that is , the first fine erase loop When the second normal erase loop EL2 _ N is performed , EL1 _ F ) of the fine erase loops is performed . a second normal erase voltage V _ N + AV _ N increased by an The erase voltage increment AV _ N added to the erase increment AV _ N from the first normal erase voltage V _ N 20 voltage each time the normal erase loop EL1 _ N , EL2 _ N , may be applied to the block area of the memory cells . EL3 _ N , . . . is repeated in a stepwise manner may be larger Thereafter , the erase verify voltage Vvf_ E may be applied to than the erase voltage increment AV _ F added to the fine verify whether or not the memory cells are erased . When it erase voltage each time the fine erase loop EL1 _ F , EL2 _ F , is determined that not all of the memory cells are erased by EL3_ F , . . . is repeated in a stepwise manner. the second normal erase loop EL2_ N , a third normal erase 25 Since the initial normal erase voltage V _ N of the normal loop EL3 _ N may be performed . erase operation is higher than the initial fine erase voltage When the third normal erase loop EL3 _ N is performed , a V _ F of the fine erase operation , and the erase voltage third normal erase voltage V N A V N increased by the increment AV _ N of the normal erase operation is larger than the erase voltage increment AV _ F of the fine erase opera increment AV _ N from the second normal erase voltage 30 tion , a threshold voltage shift amount S1 _ N due to a single V _ N +AV _ N may be applied to the block area of the memory normal erase loop may be larger than a threshold voltage cells , and thereafter, the erase verify voltage Vvf_ E may be shift amountSi _ F due to a single fine erase loop . This may applied to verify whether or not all of thememory cells are mean that a threshold voltage shift amount may be more erased . finely adjusted when the fine erase operation is performed . When the normal erase loops EL1 _ N , EL2 _ N , EL3 _ 35 . As a consequence , the erased state E _ F of the memory cells N , . . . are performed in a stepwise manner, as in threshold for which the fine erase operation is performed may be voltage distributions E1 _ N , E2 _ N , . . . shown in FIG . 6 , the denser than the erased state E _ N of the memory cells for threshold voltages of the memory cells may be gradually which the normal erase operation is performed . shifted from a programmed state P toward a normal erased FIG . 9 is a block diagram of a data storage device , state E _ N . Finally , the memory cells may be erased to have 40 according to an embodiment of the invention . threshold voltages of the normal erased state EN . Referring to FIG . 9 , a data storage device 300 may store As shown in FIG . 8 , while the fine erase operation is data to be accessed by a host device (not shown ), such as a performed , fine erase loops EL1_ F , EL2 _ F , EL3 _ F , . . .may mobile phone , an MP3 player , a laptop computer, a desktop be performed in a stepwise manner . For the sake of conve computer , a game player , a TV, an in -vehicle infotainment nience in explanation memory cells for which an erase 45 system , and the like . The data storage device 300 may also operation is to be performed , that is , erase target memory be referred to as a memory system . cells , will be referred to as memory cells . The data storage device 300 may be manufactured as any When a first fine erase loop EL1 _ F is performed , a first one of various kinds of storage devices according to the fine erase voltage V F may be applied to the block area of protocol of an interface which is electrically coupled with the memory cells , and thereafter, the erase verify voltage 50 the host device. For example , the data storage device 300 Vvf_ E may be applied to verify whether or not all of the may be configured as any one of various kinds of storage memory cells are erased . When it is determined that not all devices , such as a solid state drive (SSD ), a multimedia card of the memory cells are erased by the first fine erase loop in the form of an MMC , an eMMC , an RS -MMC and a EL1 _ F , a second fine erase loop EL2 _ F may be performed . micro -MMC , a secure digital card in the form of an SD , a When the second fine erase loop EL2 _ F is performed , a 55 mini- SD and a micro - SD , a universal serial bus (USB ) second fine erase voltage V _ F + AV _ F increased by an incre storage device, a universal flash storage (UFS ) device, a ment AV _ F from the first fine erase voltage V _ F may be Personal Computer Memory Card International Association applied to the block area of thememory cells, and thereafter , (PCMCIA ) card type storage device , a peripheral compo the erase verify voltage Vvf _ E may be applied to verify n ent interconnection (PCI ) card type storage device, a PCI whether or not all of the memory cells are erased . When it 60 express (PCI - E ) card type storage device , a compact flash is determined that not all of the memory cells are erased by (CF ) card , a smart media card , a memory stick , and the like . the second fine erase loop EL2 _ F , a third fine erase loop The data storage device 300 may be manufactured as any EL3 _ F may be performed . one of various kinds of package types . For example , the data When the third fine erase loop EL3 _ F is performed , a storage device 300 may be manufactured as any one of third fine erase voltage V _ F + 2 * AV _ F increased by the 65 various kinds of package types, such as a package -on increment AV _ F from the second fine erase voltage V _ F + package (POP ) , a system - in -package ( SIP ) , a system -on AV _ F may be applied to the block area of the memory cells , chip (SOC ), a multi- chip package (MCP ) , a chip -on -board US 9 , 773 ,561 B1 10 ( COB ), a wafer - level fabricated package (WFP ) , a wafer - collection module GC , a bad block management module BB , level stack package (WSP ) and the like . an erase operation control module EC , and so forth . The data storage device 300 may include a nonvolatile In the case where the host device accesses the data storage memory device 100 . The nonvolatile memory device 100 device 300 ( for example , requests a read operation or a may operate as a storage medium of the data storage device 5 program operation ), the host device may provide a logical 300 . The nonvolatile memory device 100 may be configured address to the data storage device 300 . The flash translation layer FTL may translate the provided logical address into a by the nonvolatile memory device 100 shown in FIG . 1 . The physical address of the nonvolatile memory device 100 , and nonvolatile memory device 100 may be configured by any perform a requested operation by referring to the converted one of various types ofnonvolatile memory devices , such asde 10 physical address. In order for such an address translation a NOR flash memory device , a ferroelectric random access operation , address translation data , that is, the address map memory ( FRAM ) using a ferroelectric capacitor, a magnetic ping table MAP may be included in the flash translation random access memory (MRAM ) using a tunneling mag layer FTL . neto -resistive ( TMR ) layer, a phase change random access The wear- leveling module WL may manage wear levels memory (PRAM ) using a chalcogenide alloy , a resistive 15 for memory blocks of the nonvolatile memory device 100 . random access memory (RERAM ) using a transition metal Memory cells of the nonvolatile memory device 100 may be oxide and the like . aged by program and erase operations. Aged memory cells , The data storage device 300 may include a controller 200 . that is , worn -out memory cells may cause fails ( for example , The controller 200 may include a control unit 210 and a physical defects ) . The wear - leveling module WL may man random access memory 230 . 20 age the program - erase counts of respective memory blocks The control unit 210 may control general operations of the in such a way as to be leveled , in order to prevent a certain controller 200 . The control unit 210 may analyze and memory block from being worn out earlier than the other process a signal or a request which is inputted from the host memory blocks . device . To this end , the control unit 210 may decode and The garbage collection module GC may manage memory drive a firmware or a software loaded on the random access 25 blocks where fragmented data are stored . In the case where memory 230 . The control unit 210 may be realized in the the nonvolatile memory device 100 is configured by a flash form of a hardware or in the combined form of a hardware memory device , as described above , it is not possible for the and a software . nonvolatile memory device 100 to perform an overwrite The random access memory 230 may store a firmware or operation , and a unit of erase may be larger than a unit of a software to be driven by the control unit 210 . Also , the 30 program . For this reason , the nonvolatile memory device random access memory 230 may store data necessary for the 100 may need an operation of collecting valid data dispersed driving of the firmware or the software, for example ,meta - at physically different positions to one place , when a storage data . That is to say , the random access memory 230 may space reaches a limit . The garbage collection module GC operate as a working memory of the control unit 210 . The may perform an operation of collecting valid data frag random access memory 230 may temporarily store data to be 35 mented due to performance of a plurality of write operations transmitted from the host device to the nonvolatile memory and a plurality of erase operations , to a collection area . device 100 or from the nonvolatile memory device 100 to The bad block management module BB may manage a the host device . In other words , the random access memory memory block in which a fail has occurred , among the 230 may operate as a data buffer memory or a data cache memory blocks of the nonvolatile memory device 100 . As memory . 40 described above , a fail ( for example , a physical defect )may FIG . 10 is a diagram illustrating a firmware or a software occur in a worn - out memory cell. Data stored in a failed to be driven in the random access memory 230 shown in memory cell may not be normally read out. Moreover, data FIG . 9 . may not be normally stored in a failed memory cell . The bad In the case where the nonvolatile memory device 100 is block management module BB may manage a memory configured by a flash memory device , the control unit 210 45 block including a failed memory cell , in such a way as to be may control an erase operation in a unit of a memory block , not used . and may control a read or program operation in a unit of a The erase operation control module EC may select an page . Further , in the case where the nonvolatile memory erase operation of the nonvolatile memory device 100 device 100 is configured by a flash memory device , the according to an operation mode of the data storage device control unit 210 may perform in advance an erase operation 50 300 , and may provide an erase command corresponding to in order to store new data in memory cells which are stored the selected erase operation , to the nonvolatile memory with data . device 100 . The control unit 210 of the data storage device 300 , which For instance, when the data storage device 300 operates in uses a flash memory device as a data storage medium , may a background mode , the erase operation control module EC drive a firmware or a software referred to as a flash trans - 55 may provide a fine erase command so that memory cells of lation layer FTL , to control an operation peculiar to the flash the nonvolatile memory device 100 are erased by a fine erase memory device and provide device compatibility to the host operation . The background mode may mean a mode that is device. Through driving of such a flash translation layer performed to manage the nonvolatile memory device 100 FTL , the data storage device 300 may be recognized as a when there is no access request from the host device . During general data storage device such as a hard disk , by the host 60 the background mode , the address mapping table may be device . managed , the wear - leveling operation may be performed , The flash translation layer FTL loaded on the random the garbage collection operation may be performed , or the access memory 230 may be configured by modules for bad block management operation may be performed . performing various functions and metadata necessary for For another instance , when the data storage device 300 driving of themodules . For example , when referring to FIG . 65 operates in a normal mode , the erase operation control 10 , the flash translation layer FTL may include an address module EC may provide a normal erase command so that mapping table MAP , a wear - leveling module WL , a garbage memory cells of the nonvolatile memory device 100 are US 9 ,773 ,561 B1 11 12 erased by a normal erase operation . Also , when the data NVM _ k may perform the normal erase operation and the storage device 300 operates in the normal mode , the erase fine erase operation described above with reference to FIGS . operation control module EC may provide a fine erase 1 to 8 . command so that memory cells of the nonvolatile memory The controller 1210 and the nonvolatile memory device device 100 are erased by a fine erase operation . That is to 5 1220 may be manufactured as any one of various data say , when the data storage device 300 operates in the normal storage devices . For example , the controller 1210 and the mode, the erase operation control module EC may provide nonvolatile memory device 1220 may be integrated into one any one of a normal erase command and a fine erase semiconductor device and may be manufactured as any one command to the nonvolatile memory device 100 as the of a multimedia card in the form of an MMC , an eMMC , an occasion demands. 10 RS -MMC and a micro -MMC , a secure digital card in the FIG . 11 is a block diagram of a data processing system form of an SD , a mini -SD and an micro - SD , a universal including a data storage device , according to an embodiment serial bus (USB ) storage device , a universal flash storage of the invention . (UFS ) device , a Personal Computer Memory Card Interna Referring to FIG . 11, a data processing system 1000 may 15 tional Association (PCMCIA ) card , a compact flash ( CF ) include a host device 1100 and a data storage device 1200 card , a smart media card , a memory stick , and the like . coupled to the host device . The data storage device 1200 FIG . 12 is a block diagram of a data processing system may include a controller 1210 and a nonvolatile memory including a solid state drive (SSD ), according to an embodi device 1220 . The host device 1100 may be or comprise a ment of the invention . mobile phone, an MP3 player, a laptop computer , a desktop 20 Referring to FIG . 12 , a data processing system 2000 may computer , a game player, a TV , an in - vehicle infotainment include a host device 2100 and a solid state drive ( SSD ) system , and the like . 2200 coupled to the host device 2100 . The controller 1210 may include a host interface unit The SSD 2200 may include an SSD controller 2210 , a 1211 , a control unit 1212 , a memory interface unit 1213 , a buffer memory device 2220 , nonvolatile memory devices random access memory 1214 , and an error correction code 25 2231 to 223n , a power supply 2240 , a signal connector 2250 , ( ECC ) unit 1215 . The controller 1210 may perform the and a power connector 2260 . operation of the erase operation control module EC The SSD controller 2210 may access the nonvolatile memory devices 2231 to 223n in response to a request from described above with reference to FIG . 10 . the host device 2100 . The SSD controller 2210 may , for The control unit 1212 may control general operationsthe host of 30 example , perform the erase operation of the control module the controller 1210 in response to a request from the host 30 EC described above with reference to FIG . 10 . device 1100 . The control unit 1212 may drive a firmware or The buffer memory device 2220 may temporarily store a software for controlling the nonvolatile memory device data which are to be stored in the nonvolatile memory 1220 . devices 2231 to 223n . Further, the buffer memory device The random access memory 1214 may be used as a ,35 2220 may temporarily store data which are read from the working memory of the control unit 1212 . The random nonvolatile memory devices 2231 to 223n . The data stored access memory 1214 may be used as a buffer memory which temporarily in the buffer memory device 2220 may be temporarily stores the data read from the nonvolatile transmitted to the host device 2100 or the nonvolatile memory device 1220 or the data provided from the host memory devices 2231 to 223n under the control of the SSD device 1100 . 40 controller 2210 . The host interface unit 1211 may interface the host device The nonvolatile memory devices 2231 to 223n may be 1100 and the controller 1210 . For example , the host interface used as storage media of the SSD 2200 . Each of the unit 1211 may communicate with the host device 1100 nonvolatile memory devices 2231 to 223n may perform the through one of various interface protocols such as a univer- normal and fine erase operations described above with sal serial bus (USB ) protocol , a universal flash storage 45 reference to FIGS . 1 to 8 . (UFS ) protocol, a multimedia card (MMC ) protocol, a The nonvolatile memory devices 2231 to 223n may be peripheral component interconnection (PCI ) protocol , a PCI coupled with the SSD controller 2210 through a plurality of express ( PCI- E ) protocol, a parallel advanced technology channels CH1 to CHn, respectively . One ormore nonvolatile attachment (PATA ) protocol, a serial advanced technology memory devices may be coupled to one channel. The one or attachment (SATA ) protocol, a small computer system inter - 50 more nonvolatile memory devices coupled to one channel face ( SCSI) protocol, a serial attached SCSI (SAS ) protocol may be coupled to the same signal and data bus . and the like . The power supply 2240 may provide power PWR input The memory interface unit 1213 may interface the con - ted through the power connector 2260 , to the inside of the troller 1210 and the nonvolatile memory device 1220 . The SSD 2200 . The power supply 2240 may include an auxiliary memory interface unit 1213 may provide commands and 55 power supply 2241 . The auxiliary power supply 2241 may addresses to the nonvolatile memory device 1220 . Further supply power to allow the SSD 2200 to be normally termi more , the memory interface unit 1213 may exchange data nated when a sudden power- off occurs . The auxiliary power with the nonvolatile memory device 1220 . supply 2241 may include super capacitors capable of being The ECC unit 1215 may detect an error of the data read charged with power PWR . from the nonvolatile memory device 1220 . Also , the ECC 60 The SSD controller 2210 may exchange a signal SGL unit 1215 may be configured to correct the detected error with the host device 2100 through the signal connector 2250 . when the detected error is within a correctable range. The signal SGL may include a command , an address, data , The nonvolatile memory device 1220 may be used as a and so forth . The signal connector 2250 may be configured storage medium of the data storage device 1200 . The non - by a connector , such as of parallel advanced technology volatile memory device 1220 may include a plurality of 65 attachment ( PATA ), serial advanced technology attachment nonvolatile memory chips ( or dies ) NVM _ 1 to NVM _ k . (SATA ) , small computer system interface (SCSI ) , serial Each of the nonvolatile memory chips (or dies ) NVM _ 1 to attached SCSI (SAS ), peripheral component interconnection US 9 , 773 ,561 B1 13 14 (PCI ) and PCI express (PCI - E ) protocols , according to the application program , various program modules , program interface scheme between the host device 2100 and the SSD data and user data may be stored in the data storage device 2200 . 3300 . FIG . 13 is a block diagram of an example of the SSD The RAM 3400 may be used as a working memory of the controller 2210 shown in FIG . 12 . computer system 3000 . Upon booting, the operating system , the application program , the various program modules and Referring to FIG . 13 , the SSD controller 2210 may the program data necessary for driving programs may be include a memory interface unit 2211 , a host interface unit read from the data storage device 3300 and loaded on the 2212 , an error correction code (ECC ) unit 2213 , a control RAM 3400 . A basic input/ output system ( BIOS ) may be unit 2214 , and a random access memory 2215 . 110 activated before the operating system is driven and stored in The memory interface unit 2211 may provide a control the ROM 3500 . Information exchange between the com signal, such as a command and an address to the nonvolatile puter system 3000 and a user may be enabled through the memory devices 2231 to 223n . Moreover, the memory user interface 3600 . interface unit 2211 may exchange data with the nonvolatile While various embodiments have been described above , memory devices 2231 to 223n . The memory interface unit 15 it will be understood by those skilled in the relevant art that 2211 may scatter the data transmitted from the buffer the described embodiments are examples only of the inven memory device 2220 to the respective channels CH1 to tion . Accordingly , the nonvolatile memory device and the CHn, under the control of the control unit 2214 . Further data storage device including the same described herein more , the memory interface unit 2211 may transmit the data should not be limited based on the described embodiments read from the nonvolatile memory devices 2231 to 223n to 20 and many other embodiments and or variations of the the buffer memory device 2220 , under the control of the invention may be envisaged by those skilled in the relevant control unit 2214 . art without departing from the spirit and or scope of the The host interface unit 2212 may provide an interface invention as defined in the appended claims. with the SSD 2200 in correspondence to the protocol of the host device 2100 . For example , the host interface unit 2212 25 What is claimed is : may communicate with the host device 2100 through one of 1 . A data storage device comprising : parallel advanced technology attachment (PATA ), serial a nonvolatile memory device ; and advanced technology attachment (SATA ) , small computer a controller suitable for providing a normal erase com system interface ( SCSI) , serial attached SCSI (SAS ) , periph mand or a fine erase command to the nonvolatile eral component interconnection ( PCI) , PCI express (PCI - E ) 30 memory device ; protocols and the like . In addition , the host interface unit wherein the nonvolatile memory device is suitable for 2212 may perform a disk emulating function of supporting performing a first normal erase loop according to the the host device 2100 to recognize the SSD 2200 as a hard normal erase command , wherein the first normal erase disk drive (HDD ) . loop comprises applying a first normal erase voltage The ECC unit 2213 may generate parity bits based on the 35 and an erase verify voltage to a first erase target data transmitted to the nonvolatile memory devices 2231 to memory cell, 223n . The generated parity data may be stored along with wherein , when it is determined that the first erase target data in the nonvolatile memory devices 2231 to 223n . The memory cell is not erased by the first normal erase loop , ECC unit 2213 may detect an error of the data read from the the nonvolatile memory device performs a second nonvolatile memory devices 2231 to 223n . When the 40 normal erase loop in which a second normal erase detected error is within a correctable range , the ECC unit voltage increased by a first increment from the first 2213 may correct the detected error. normal erase voltage and the erase verify voltage are The control unit 2214 may analyze and process the signal applied to the first erase target memory cell , SGL inputted from the host device 2100 . The control unit wherein the nonvolatile memory device is suitable for 2214 may control the operations of the buffer memory 45 performing a first fine erase loop according to the fine device 2220 and the nonvolatile memory devices 2231 to erase command , wherein the first fine erase loop com 223n according to a firmware or a software for driving the prises applying a fine normal erase voltage and the SSD 2200 . erase verify voltage to a second erase target memory The random access memory 2215 may be used as a cell , working memory for driving the firmware or the software . 50 wherein , when it is determined that the second target FIG . 14 is a block diagram of a computer system includ memory cell is not erased by the first fine erase loop , ing a data storage device , according to an embodiment of the the nonvolatile memory device performs a second fine invention . Referring to FIG . 14 , a computer system 3000 erase loop in which a second fine erase voltage may include a network adaptor 3100, a central processing increased by a second increment from the first fine unit (CPU ) 3200 , a data storage device 3300 , a RAM 3400 , 55 erase voltage and the erase verify voltage to the second a ROM 3500 and a user interface 3600 , all of which may be erase target memory cell, and coupled to a system bus 3700 . The data storage device 3300 wherein a magnitude of the first increment between the may be or comprise , for example , the data storage devices normal erase loops is larger than a magnitude of the 300 and 1200 of FIGS . 9 and 11 or the SSD 2200 of FIG . 12 . second increment between the fine erase loops . The network adaptor 3100 may provide interfacing 60 2 . The data storage device according to claim 1 , wherein between the computer system 3000 and external networks . a level of the first normal erase voltage is higher than a level The CPU 3200 performs general operations for driving an of the first fine erase voltage . operating system residing at the RAM 3400 or an applica - 3 . The data storage device according to claim 1 , wherein tion program . the controller provides the fine erase command to the The data storage device 3300 may store general data 65 nonvolatile memory device, while operating in a back necessary in the computer system 3000 . For example , an ground mode in which there is no access request from an operating system for driving the computer system 3000, an external device . US 9 ,773 , 561 B1 15 16 4 . The data storage device according to claim 1 , wherein loop , the control logic performs a second normal erase the controller provides the normal erase command or the fine loop in which the voltage generator is controlled so that erase command to the nonvolatile memory device, while a second normal erase voltage increased by a first operating in a normal mode in which there is an access increment from the first normal erase voltage and the request from an external device . erase verify voltage are applied to the erase target 5 . A nonvolatile memory device comprising : memory cells, memory cells ; a voltage generator suitable for generating voltages to be wherein , when it is determined that the erase target provided to the memory cells ; and memory cells are not erased by the first fine erase loop , a control logic suitable for performing a first normal erase 10 the control logic performs a second fine erase loop in loop in which the voltage generator is controlled so that which the voltage generator is controlled so that a a first normal erase voltage and an erase verify voltage second fine erase voltage increased by a second incre are applied to erase target memory cells among the ment from the first fine erase voltage and the erase memory cells, according to a normal erase command verify voltage are applied to the erase target memory provided from an external device, and performing a 15 cells , and first fine erase loop in which the voltage generator is wherein a magnitude of the first increment between the controlled so that a first fine erase voltage and the erase normal erase loops is larger than a magnitude of the verify voltage are applied to the erase target memory second increment between the fine erase loops. cells , according to a fine erase command provided from 6 . The nonvolatile memory device according to claim 5 , an external device, 20 wherein a level of the first normal erase voltage is higher wherein , when it is determined that the erase target zu than a level of the first fine erase voltage . memory cells are not erased by the first normal erase * * * * *