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7th Generation Intel® Processor Family I/O for U/Y Platforms, 8th Generation Intel® Processor Family I/O for U/YPlatforms, and 10th Generation Intel® Processor Family I/O for Y Platforms Datasheet – Volume 1 of 2 Supporting 7th Generation Intel® Processor Families for U/Y Platforms 8th Generation Intel® Processor Family for UPlatforms formerly known as Kaby Lake and Kaby Lake Refresh, 8th Generation Intel® Processor Family for Y Platforms, and 10th Generation Intel® Processor Family for Y Platforms formerly known as Amber Lake 4-Core December 2019 Revision 006 Document Number: 334658-006 You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel technologies' features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at Intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Intel technologies' features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at intel.com, or from the OEM or retailer. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548- 4725 or visit www.intel.com/design/literature.htm. Intel, the Intel logo, Intel® OptaneTM are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 2016-2019, Intel Corporation. All rights reserved. 2 Datasheet, Volume 1 of 2 Contents 1 Introduction ............................................................................................................19 1.1 About this Manual.............................................................................................. 19 1.2 References ....................................................................................................... 19 1.3 Overview.......................................................................................................... 19 1.4 PCH SKUs......................................................................................................... 21 2 PCH Controller Device IDs .......................................................................................22 2.1 Device and Revision ID Table .............................................................................. 22 3 Flexible I/O.............................................................................................................24 3.1 Overview.......................................................................................................... 24 3.2 Flexible I/O Implementation ............................................................................... 24 3.2.1 PCH-U .................................................................................................. 24 3.2.2 PCH-Y................................................................................................... 26 3.3 HSIO Port Selection ........................................................................................... 27 3.3.1 PCIe*/SATA Port Selection....................................................................... 27 4 Memory Mapping .....................................................................................................28 4.1 Overview.......................................................................................................... 28 4.2 Functional Description........................................................................................ 28 4.2.1 PCI Devices and Functions ....................................................................... 28 4.2.2 Fixed I/O Address Ranges........................................................................ 29 4.2.3 Variable I/O Decode Ranges .................................................................... 31 4.3 Memory Map..................................................................................................... 32 4.3.1 Boot Block Update Scheme ...................................................................... 34 5 System Management ...............................................................................................36 5.1 Acronyms......................................................................................................... 36 5.2 References ....................................................................................................... 36 5.3 Overview.......................................................................................................... 36 5.4 Features .......................................................................................................... 36 5.4.1 Theory of Operation................................................................................ 37 5.4.1.1 Detecting a System Lockup ........................................................ 37 5.4.1.2 Handling an Intruder ................................................................. 37 5.4.1.3 Detecting Improper Flash Programming ....................................... 37 5.4.2 TCO Modes ............................................................................................ 38 5.4.2.1 TCO Compatible Mode ............................................................... 38 5.4.2.2 Advanced TCO Mode.................................................................. 39 6 High Precision Event Timer (HPET)..........................................................................40 6.1 References ....................................................................................................... 40 6.2 Overview.......................................................................................................... 40 6.2.1 Timer Accuracy ...................................................................................... 40 6.2.2 Timer Off-load ....................................................................................... 40 6.2.3 Off-loadable Timer.................................................................................. 41 6.2.4 Interrupt Mapping .................................................................................. 42 6.2.4.1 Mapping Option #1 (Legacy Replacement Option) ......................... 42 6.2.4.2 Mapping Option #2 (Standard Option) ......................................... 42 6.2.4.3 Mapping Option #3 (Processor Message Option)............................ 42 6.2.5 Periodic Versus Non-Periodic Modes .......................................................... 43 6.2.5.1 Non-Periodic Mode .................................................................... 43 6.2.5.2 Periodic Mode ........................................................................... 43 6.2.6 Enabling Timers ..................................................................................... 43 Datasheet, Volume 1 of 2 3 6.2.7 Interrupt Levels..................................................................................... 44 6.2.8 Handling Interrupts................................................................................ 44 6.2.9 Issues Related to 64-Bit Timers with 32-Bit Processors ............................... 44 7 Thermal Management ............................................................................................. 45 7.1 PCH Thermal Sensor ......................................................................................... 45 7.1.1 Modes of Operation ................................................................................ 45 7.1.2 Temperature Trip Point ........................................................................... 45 7.1.3 Thermal Sensor Accuracy (Taccuracy) ...................................................... 45 7.1.4 Thermal Reporting to an EC .................................................................... 45 7.1.5 Thermal Trip Signal (PCHHOT#)............................................................... 46 8 Power and Ground Signals ...................................................................................... 47 9 Pin Straps ............................................................................................................... 49 10 Electrical Characteristics......................................................................................... 52 10.1 Absolute Maximum Ratings ................................................................................ 52 10.2 PCH Power Supply Range..................................................................................
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