Moorestown Platform: Based on Lincroft Soc Designed for Next Generation Smartphones

Moorestown Platform: Based on Lincroft SoC Designed for Next Generation Smartphones

HOT CHI PS 2009

August 24 2009

Rajesh Patel Lead Architect, Lincroft SoC I ntel Corporation Legal Disclaimer

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2 Agenda

• Moorestown Platform Overview

• Moorestown Platform Re-Partitioning

• Lincroft SoC: Designed for

• High Performance

• Low Power • Summary

3 Major Reductions in Power and Form Factor

2008 2009/2010 2011

Moorestown Medfield

Menlow Moorestown Medfield Board Size 8,500 sq mm Board Size – Reduced 2x Board Size - Reduced Standby Power 1.6W Standby Power Up to 50x* Standby Power - Lower

Forecast Forecast

Power and Form Factor Reductions On Track Moorestown Idle Is Similar To Phone Level Power

•Moorestown Platform Idle power reduction (based on current platform features) compared to Menlow Platform •Drawings are not to scale 4 Moorestown Platform Overview LI NCROFT (45nm)

2D / 3D ATOM uLP Today’s Focus Graphics CPU core

Hardware Video Acceleration

Display Memory Controller Controller

LANGWELL (65nm) EVANS PEAK WiFi SDIO Ports MIPI CSI a/ b/ g/ n BRIERTOWN Interface WiMAX

NAND BT Integrated Audio Codec Controller GPS PMI C USB . . . Controller . . . 3G

5 Moorestown Platform Re-Partitioning

ATOM uLP CPU Core ATOM uLP CPU Core • 45 nm HighK SoC ATOM CPU Process Scalable Bus Interface • Intel Hyper Threading 45nm support and Coherency engine Ported Memory Internal Graphics to Display Controller • OpenGL ES2.0 45nm • OpenVG 1.0 Bus Interface and SoC Graphics Memory Support Coherency engine Video process Decode • LPDDR1 & DDR2 Memory + New Link to • Single Channel Display Video Controller Low Langwell • x32 bit interface Power Encode Video Internal Display Graphics Features Decode Lincroft • LVDS South Bridge IOs • MIPI-DSI Video Decode and Encode

Langwell Menlow (CPU+ IOH)

Moorestown (CPU+ IOH)

Re-Partitioning using 45nm SoC process  Higher Performance and Ultra Low Power 66 Lincroft I nnovation Vectors

High Performance for amazing Internet Experience

LINCROFT INNOVATION

Dramatically Lower Power Small Size Upto 50x platform idle power* For Smartphone Form Factor

Significant Advancement on all Key Vectors * Moorestown Platform Idle power reduction (based on current platform features) compared to Menlow Platform 7 Lincroft High Performance I nnovation

. Wide range of scalable frequencies for multimedia blocks . Intel Hyper threading technology . Bus Turbo Technology

. Burst Mode technology

8 Large Range of Scalable Frequencies for Multimedia Engines

Core_clk div Core_clk_selector Bus_Freq_ratio Pre_Bus_clock Bus_clock Bypass_ clk_div Bypass_ selector Bypass enable Bypass _clocks

DDR_clk0_div DDR_clk0_selector DDR_clock0 DDR_Freq_ratio Pre_DDR_clock

DDR_clk1_div DDR_clk1_selector DDR_Freq_ratio Pre_DDR_clock1 DDR_clock1

Gfx_clk_div Gfx_clk_selector GFX_Freq_ratio Pre_GFX_clock Gfx_clock

VideoD_div VideoD_clk_selector VideoD_Freq_ratio Pre_VideoD_clock VideoD_clock

VideoE_div VideoE_clk_selector VideoE_Freq_ratio Pre_VideoE_clock VideoE_clock

Display_div Display_clk_selector Display_Freq_ratio Pre_Display_clock Display_clock

Scalability enables Lincroft SoC into wide spectrum of FFs 9 I ntel Hyper-threading Technology

Hyperthreading Performance Increase in an In-order Machine

1.5 MT-EEMBC SPECint2KRate 1.39 1.4 1.36

1.3

1.19 1.2 1.17

1.1

1 performance power

Hyper-threading technology provides excellent Performance/Power efficiency

Source* : Intel Testing. Specint2k and EEMBC run in Single Threaded / Hyper Threaded Mode on Linux. For Performance the score for each binary is calculated based on the runtimes; For Power, the effective capacitance or C-dyn is measured per binary on each of the benchmark while running in ST and HT modes. The difference in C-dyn and thus total power difference is calculated for ST and HT modes. Performance tests and ratings are m easured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, visit Intel Performance Benchmark Limitations 10 “Bus Turbo Mode” -- Further Performance Boost . Motivation . To reduce memory latency and increase bus BW when CPU bursting at higher frequencies PRE-DEFINED THRESOLD TO ENABLE BUS TURBO

. Implementation Bus Turbo . HW dynamically increases Freq Bus LFM BUS frequency at pre-set CPU frequency . No need to re-lock PLL CPU FREQUENCY that provides clock to bus . Uses clock divider

“Bus Turbo Mode” substantially reduces memory

latency and provides higher bus BW 11 Burst Mode -- Addl Performance Headroom

. Taking advantage of Thermal headroom on Tj and Tskin by Burst if Temparature < Tj or Tskin Tjmax

increasing CPU frequency for Tskin POWER short duration limit TDP FREQ . When Tj and Tskin limits are No-Burst

violated, System throttles to BURST MODE Idle Idle Recovery points Time (t1) in C0-state Time (t2) in C0-state . Optimizes consumed energy TIME

. Energy(WHr)= Power x OPPORTUNI STI C time RESI DENCY SUSTAINED

. Race to idle POWER THERMAL BURST MODE LIMIT . Saves energy if TDP HFM . t2/t1 < p1/p2 LFM ULFM RECOVERY POINTS FREQUENCY Burst mode provides on-demand performance without impacting thermal design 12 Lincroft Low Power I nnovations

. Low power architecture features . MIPI-DSI . LP-DDR1 . HW accelerators for Video Decode/Encode . Enhanced Geyserville to support ULFM . Lincroft CPU Power C-states . Lincroft Distributed Power Gating

13 Enhanced Geyserville (eGVL) . Motivation . To provide lowest possible CPU frequency . To enable “As many P-states as possible” below LFM at Vmin . Linear savings of average Enhanced power when CPU is not Geyserville doing anything useful LFM while in C0 state (cV2F) Bus Freq Bus ULFM . Implementation . Added P-states below LFM at PRE-DEFINED THRESOLD Vmin TRIGGERS eGVL . OS can now request CPU to transition to these new CPU FREQUENCY P-states

eGVL mode provides additional range of low power

operating point 14 Lincroft CPU Power C-states

C0 HFM C0 LFM C0 ULFM C1/ C2 C4 C6

Core voltage

Core clock OFF OFF OFF

PLL OFF OFF

L1 caches flushed flushed off

L2 caches Partial flush off

Wakeup time active active active

Power

1515 Lincroft SoC: I REM image of Full ON vs. Power Gated

. Multiple Physical power Islands

. Distributed power gating to enable fine grain power management

. SW interface for Active Island power management

. HW manages sequencing of power ON and OFF

Aggressive Distributed Power Gating enables up-to 50x reduction in idle power* 16 * Moorestown Platform Idle power reduction (based on current platform features) compared to Menlow Platform Summary

. Moorestown: Based on Lincroft SoC, Designed for . High Performance for amazing Internet Experience . Dramatically Lower Power – Upto 50x lower idle power . Small Size for Next Generation Smartphones

. Lincroft High Performance Innovation . Wide range of scalable frequencies for multimedia blocks . Intel Hyper threading technology . Bus Turbo Technology . Burst Mode technology . Intel 45nm SoC High-K process technology

. Lincroft Low Power Innovation . Low power architecture features . Enhanced Geyserville to support ULFM . CPU C-states . Lincroft Distributed Power Gating

17 Thank you Lincroft SoC, Langwell and Moorestown platform team