14 Nm Technology Leadership Dr

Leading at the edge TECHNOLOGY AND MANUFACTURING DAY 14 nm technology leadership Dr. Ruth Brain Intel Fellow, Technology and Manufacturing Group Director, Interconnect Technology and Integration

TECHNOLOGY AND MANUFACTURING DAY Disclosures

Intel Technology and Manufacturing Day 2017 occurs during Intel’s “Quiet Period,” before Intel announces its 2017 first quarter financial and operating results. Therefore, presenters will not be addressing first quarter information during this year’s program.

Statements in this presentation that refer to forecasts, future plans and expectations are forward-looking statements that involve a number of risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “goals,” “plans,” “believes,” “seeks,” “estimates,” “continues,” “may,” “will,” “would,” “should,” “could,” and variations of such words and similar expressions are intended to identify such forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. Such statements are based on management’s expectations as of March 28, 2017, and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in these forward-looking statements. Important factors that could cause actual results to differ materially from the company’s expectations are set forth in Intel’s earnings release dated January 26, 2017, which is included as an exhibit to Intel’s Form 8-K furnished to the SEC on such date. Additional information regarding these and other factors that could affect Intel’s results is included in Intel’s SEC filings, including the company’s most recent reports on Forms 10-K, 10-Q and 8-K reports may be obtained by visiting our Investor Relations website at www.intc.com or the SEC’s website at www.sec.gov.

TECHNOLOGY AND MANUFACTURING DAY Key messages . Intel’s 14 nm technology is ~1.3x denser than others’ available “20 nm” and “16/14 nm” technologies.

. Intel’s 14 nm technology is expected to be similar density to others’ “10 nm” technology but ~3 years ahead.

. Intel’s 14 nm transistors have >20% performance leadership compared to others’ available technology.

. At the 14 nm technology node, Intel has developed all of the key enablers to hyper scale features and deliver significant CPT benefits.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. Key messages . Intel’s 14 nm technology is ~1.3x denser than others’ available “20 nm” and “16/14 nm” technologies.

. Intel’s 14 nm technology is expected to be similar density to others’ “10 nm” technology but ~3 years ahead.

. Intel’s 14 nm transistors have >20% performance leadership compared to others’ available technology.

. At the 14 nm technology node, Intel has developed all of the key enablers to hyper scale features and deliver significant CPT benefits.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. 14 nm hyper Scaling features

Fin Pitch Interconnect Pitch Cell Height Gate Pitch 60 nm 42 nm 80 nm 52 nm 840 nm 399 nm 90 nm 70 nm .70x .65x .48x .78x

22 nm 14 nm 22 nm 14 nm 22 nm 14 nm 22 nm 14 nm

14 nm uses aggressive feature scaling to deliver unprecedented 0.37x logic cell area scaling.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. Logic area scaling

1 45nm .49x

32nm .45x

22nm Logic .37x Area 0.1 (relative) 14nm

0.01 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 HVM Wafer Start Date Hyper scaling of 14 nm features provides better-than-normal 0.37x logic area scaling.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. Logic Transistor density

100

14nm Intel 37.5 MTr / mm2

2.5x (0.40x area) Transistor 22nm Density MTr / mm2 10 32nm 2.1x

2.3x 45nm

1 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 HVM Wafer Start Date Using NAND+SFF metric, 14 nm provides better-than-normal logic transistor density improvement.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. Logic Transistor density

100

14nm Intel ~1.3x 14/16nm Transistor 22nm 20nm Density 2 32nm 28nm MTr / mm 10 28/32nm Others (measured)

45nm 45/40nm

1 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 HVM Wafer Start Date Intel’s 14 nm technology is ~1.3x denser than others’ “14/16/20 nm” technologies.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. 14nm technology Features

Intel 14 nm Other “20 nm” Gate Pitch 70 nm 90 nm (1.3x) Logic cell height 399 nm 576 nm (1.4x) Fin Pitch 42 nm Planar Min Metal Pitch 52 nm 64 nm Transistor density 37.5 28.0 (MTr/mm2) (1.34x) (1x)

Introduced at similar time.

Intel 14 nm is ahead of others’ “20 nm” technology on every density metric.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. 14nm technology Features

Intel 14 nm Other “20 nm” Other “16 nm” Other “14 nm” Gate Pitch 70 nm 90 nm (1.3x) 90 nm (1.3x) 78 nm (1.1x) Logic cell height 399 nm 576 nm (1.4x) 480 nm (1.2x) 576 nm (1.4x) Fin Pitch 42 nm Planar 48 nm (1.1x) 48 nm (1.1x) Min Metal Pitch 52 nm 64 nm 64 nm 64 nm Transistor density 37.5 28.0 29.0 30.5 (MTr/mm2) (1.34x) (1x) (1.04x) (1.09x)

Others introduced ~1 year later.

Intel 14 nm is ahead of others’ “14/16 nm” technology on every density metric.

. Intel’s 14 nm technology is expected to be similar density to others’ “10 nm” technology but ~3 years ahead.

. Intel’s 14 nm transistors have >20% performance leadership compared to others’ available technology.

. At the 14 nm technology node, Intel has developed all of the key enablers to hyper scale features and deliver significant CPT benefits.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. Logic Transistor density

100

14nm ~3 years Intel 10nm (est.) 14/16nm Transistor 22nm 20nm Density 2 32nm 28nm MTr / mm 10 28/32nm Others (measured)

45nm 45/40nm

1 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 HVM Wafer Start Date Others’ “10 nm” technologies expected to have similar density to Intel 14 nm, but ~3 years later.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis. 2017-2020 are estimates based upon current expectations and available information. Key messages . Intel’s 14 nm technology is ~1.3x denser than others’ available “20 nm” and “16/14 nm” technologies.

. Intel’s 14 nm technology is expected to be similar density to others’ “10 nm” technology but ~3 years ahead.

. Intel’s 14 nm transistors have >20% performance leadership compared to others’ available technology.

. At the 14 nm technology node, Intel has developed all of the key enablers to hyper scale features and deliver significant CPT benefits.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. Technology enhancements

45nm

32nm 14 nm Enhancements 22nm 14+ 14++ 14 nm 14++ Enhancements 14nm Higher 14+ Lower Performance Performance 10nm Power (logscale) (logscale) 10nm 14nm Transistor Dynamic CapacitanceDynamic 22nm

32nm 45nm

2007 2009 2011 2013 2015 2017 2019 2021 2007 2009 2011 2013 2015 2017 2019 2021 Process Readiness Date Process Readiness Date 14+ and 14++ enhancements improve performance without increasing capacitance (active power).

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis. 2017-2021 are estimates based upon current expectations and available information. Intel Innovation Leadership FinFets

FinFET 1st Generation 2nd Generation Transistor st nd 22 nm Process 14 nm Process 1 Generation 2 Generation 22 nm Process 14 nm Process Metal Gate Metal Gate

Si Substrate Si Substrate

FinFET transistors were first introduced at 22 nm and enhanced at 14 nm. Fin pitch and height are optimized for density and performance. TECHNOLOGY AND MANUFACTURING DAY World’s highest performance transistors

14 nm Benchmark - NMOS 14 nm Benchmark - PMOS

1000 1000 Intel 14nm @ 70pp

Intel 14nm @ 70pp 100

100

10 Leakage Current

Leakage Current 10 1 better better

0.1 1 1.5 1.7 1.9 2.1 2.3 2.5 1.4 1.8 2.2 2.6 Drive Current Drive Current

Intel demonstrated leading 14 nm performance in 2015.

TECHNOLOGY AND MANUFACTURING DAY Source: Intel. World’s highest performance transistors

14 nm Benchmark - NMOS 14 nm Benchmark - PMOS

1000 1000 Intel 14nm @ 70pp Intel 14+ @ 70pp

Intel 14+ @ 70pp Intel 14nm @ 70pp 100

100

10 Leakage Current

Leakage Current +12% 10 +12% 1 better better

0.1 1 1.5 1.7 1.9 2.1 2.3 2.5 1.4 1.8 2.2 2.6 Drive Current Drive Current

Intel’s 14+ enhancement enables +12% drive current in 2016.

TECHNOLOGY AND MANUFACTURING DAY Source: Intel. World’s highest performance transistors

14 nm Benchmark - NMOS 14 nm Benchmark - PMOS

1000 1000 Intel 14nm @ 70pp Intel 14+ @ 70pp

Intel 14+ @ 70pp Intel 14nm @ 70pp 100

100

10 Intel 14++ @ 84pp Intel 14++ @ 84pp Leakage Current

Leakage Current +23% 10 +24% 1 better better

0.1 1 1.5 1.7 1.9 2.1 2.3 2.5 1.4 1.8 2.2 2.6 Drive Current Drive Current

Intel’s 14++ enhancement enables +23-24% higher drive current in 2017.

TECHNOLOGY AND MANUFACTURING DAY Source: Intel. World’s highest performance transistors

14 nm Benchmark - NMOS 14 nm Benchmark - PMOS

1000 1000 Intel 14nm @ 70pp Intel 14+ @ 70pp

Intel 14+ @ 70pp Intel 14nm @ 70pp 100

100 Others 14/16nm 78-90pp 10 Intel 14++ @ 84pp Others 14/16nm Intel 14++ @ 84pp 78-90pp Leakage Current

Leakage Current +20% 10 +23% 1 better better

0.1 1 1.5 1.7 1.9 2.1 2.3 2.5 1.4 1.8 2.2 2.6 Drive Current Drive Current

Intel’s 14++ performance is >20% better than others’ best “14/16 nm”.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. World’s highest performance transistors

1.4 14+ 1.2 14 nm 2016 2015 1.0 +26% performance 14++ 0.8 2017

0.6

0.4 -52% power Active (IV) Power (Norm/fin) 0.2

0.0 0.4 0.6 0.8 1.0 1.2 1.4 Performance (Norm) Matched leakage/fin @ 0.7V Highest performance device

Transistor performance enhanced on an annual cadence.

TECHNOLOGY AND MANUFACTURING DAY Source: Intel. Intel 14nm offers full range of capabilities

High Q Inductor

High Density Decap

Low lkg and Long L Core Device Even legs RF Transistor: Precision Resistor with Z =0.8 Transistor Templates/Modeling

Triple Well/Deep Nwell High Resistance Substrate Intel’s 14 nm technology offers a full suite of capabilities for product design needs.

TECHNOLOGY AND MANUFACTURING DAY 14nm technology offers full range of interconnects High Performance Client

High Density SoC

Airgap for performance

TECHNOLOGY AND MANUFACTURING DAY Key messages . Intel’s 14 nm technology is ~1.3x denser than others’ available “20 nm” and “16/14 nm” technologies.

. Intel’s 14 nm technology is expected to be similar density to others’ “10 nm” technology but ~3 years ahead.

. Intel’s 14 nm transistors have >20% performance leadership compared to others’ available technology.

. At the 14 nm technology node, Intel has developed all of the key enablers to hyper scale features and deliver significant CPT benefits.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. Intel innovation leadership

High-k Self FinFET Hyper Metal Gate Align Via Transistor Scaling 45nm 32nm 22nm 14nm

Traditional scaling Hyper scaling enablers enabler

Innovations are the key to scaling. Intel drives the development of key breakthroughs. At 14 nm, we have several generations of learning on traditional enablers.

TECHNOLOGY AND MANUFACTURING DAY Intel Innovation Leadership by hyper-scaling

Interconnects 14 nm Technology Hyper Scaling 52 nm Pitch 14nm

Hyper scaling enabler Self-Aligned Double Patterning

Self-Aligned Double Pattern interconnects first introduced into logic manufacturing by Intel. Key advantage for density and yield. TECHNOLOGY AND MANUFACTURING DAY Interconnect Patterning options

Intel 193nm immersion single pass

SA Double Pattern

SA Quad Pattern

120 110 100 90 80 70 60 50 40 30 20 10 Interconnect Pitch (nm) Self-Aligned patterning allows Intel to use the full range of interconnect pitches.

TECHNOLOGY AND MANUFACTURING DAY Interconnect Patterning options

Intel 193nm immersion single pass

SA Double Pattern

SA Quad Pattern Others 193nm immersion single pass

LELE

LELELE

120 110 100 90 80 70 60 50 40 30 20 10 Interconnect Pitch (nm) Other’s patterning choices limit interconnect pitch options.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. Interconnect Patterning options

Intel 193nm immersion single pass

SA Double Pattern

SA Quad Pattern Similar Others cost Similar 193nm immersion single pass cost

LELE

LELELE

120 110 100 90 80 70 60 50 40 30 20 10 Interconnect Pitch (nm) Self-Aligned Patterning allows Intel to have dense interconnects at lower cost.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. Double-patterning leads to Manufacturing benefits

Desired Pattern Double Patterning Litho / Etch

Double Patterning leads to clear benefits in process control.

TECHNOLOGY AND MANUFACTURING DAY Self-Aligned Patterning leads to process control Self-Aligned Double Patterning

Litho

Spacer deposition Thickness control ~1 nm

Etch spacer

Clean and Etch

Pitch Division

Self-Aligned Patterning has placement control required for high yield. TECHNOLOGY AND MANUFACTURING DAY Self-Aligned Patterning leads to process control Self-Aligned Double Patterning Litho-Etch-Litho-Etch

Litho Litho #1

Spacer deposition Etch #1 Thickness control ~1 nm

Litho #2 Etch spacer Good placement

Clean and Etch Etch #2

Pitch Division Pitch division

Litho-Etch-Litho-Etch can yield same pattern. TECHNOLOGY AND MANUFACTURING DAY Self-Aligned Patterning leads to process control Self-Aligned Double Patterning Litho-Etch-Litho-Etch

Litho Litho #1

Spacer deposition Etch #1 Thickness control ~1 nm

Litho #2 Or Litho #2 Etch spacer Good placement ~10 nm error

Clean and Etch Etch #2 Etch #2

Pitch Division Pitch division Pitch division

LELE process has yield and performance risk with mis-alignment between patterns. TECHNOLOGY AND MANUFACTURING DAY Self-Aligned Patterning leads to process control Self-Aligned Double Patterning Litho-Etch-Litho-Etch

B B Single mask to single mask. Single mask to multiple masks. Alignment can be tightly controlled. Difficult to control. A A1 A2

TECHNOLOGY AND MANUFACTURING DAY 14 nm technology delivers significant die scaling

0.62x Area 0.62x 100 mm2 0.46x Circuit Scale Weight Area 62 mm2 Logic .39x .60 .234x 38.4 mm2 SRAM .54x .25 .162x IO Logic 17.7 mm2 IO Logic IO .60x .15 .060x IO Logic Total .459x IO Logic

SRAM 2 2 100SRAM mm 100SRAM mm 100SRAM mm2

45 nm 32 nm 22 nm 14 nm

Hyper scaling delivers <0.50x die area scaling on 14 nm.

TECHNOLOGY AND MANUFACTURING DAY Source: Intel benefits of Intel’s 14 nm technology

14 nm hyper scaling ⇒ ~1.4x more units per $ than traditional scaling 450 mm wafer size conversion ⇒ ~1.4x more units per $ than traditional scaling

300 mm 450mm

14 nm hyper scaling delivers the equivalent economic benefit as a wafer size transition.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. summary . Intel’s 14 nm technology is ~1.3x denser than others’ available “20 nm” and “16/14 nm” technologies.

. Intel’s 14 nm technology is expected to be similar density to others’ “10 nm” technology but ~3 years ahead.

. Intel’s 14 nm transistors have >20% performance leadership compared to others’ available technology.

. At the 14 nm technology node, Intel has developed all of the key enablers to hyper scale features and deliver significant CPT benefits.

TECHNOLOGY AND MANUFACTURING DAY Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information. Leading at the edge TECHNOLOGY AND MANUFACTURING DAY