2009 INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS
Conference: October 7-9, 2009 Short Course / Workshop: October 6, 2009
The 2009 International Conference on Solid State Devices and Materials (SSDM2009) will be held from October 7 to 9, 2009 at Sendai Kokusai Hotel (Sendai, Miyagi, Japan). Since 1969, the conference has provided an excellent opportunity to discuss key aspects of solid-state devices and materials. For the 2009 conference, 14 program subcommittees have been organized covering circuits and systems, as well as devices and materials. In SSDM 2009, a one-day short course and workshop are also scheduled prior to the conference. The short course offers tutorial lectures on important aspects of the technology. The workshop offers advanced discussion on topical device technologies, “green technology” in SSDM 2009.
Original, unpublished papers will be accepted after review by the Program Committee. Several invited speakers will cover topics of current interest. An Advance Program will appear in August. More information about SSDM2009 is available online at: http://www. ssdm.jp
- 1 - SSDM 2009 Advance Program General Information DATE Conference: October 7-9, 2009 (Official language is English) Short Course/Workshop: October 6 (in English)
LOCATION Sendai Kokusai Hotel 4-6-1 Chuo, Aoba-ku, Sendai, Miyagi 980-0021, Japan Phone: +81-22-268-1111 Fax: +81-22-268-1113 Sendai Kokusai Hotel is one of the biggest major hotels in Sendai, Japan. The hotel has been greatly contributed with many kinds of international conferences in Sendai. Sendai Kokusai Hotel is located in just 5 minutes walk from Sendai Station and 40 minutes by taxi from Sendai Airport where the center of Sendai City and its attractions. http://www.tobu-skh.co.jp/ Institute of Fluid Science, Tohoku University 2-1-1 Katahira, Aoba-ku, Sendai, Miyagi, 980-8577, Japan Phone: +81-22-217-5310 Fax: +81-22-217-5311 [Short Course] Lecture room, 2nd building, 5F [Workshop] Seminar room, COE building, 3F Institute of Fluid Science is located in 15 minutes walk from Sendai Station and 40 minutes by taxi from Sendai Airport. http://www.ifs.tohoku.ac.jp/
REGISTRATION The registration desk will be open from October 7 to 9 on 2nd floor. Open hours are as follows: October 7 8:30-17:00 8 8:30-17:00 9 8:30-15:30 Early registration will be accepted only through the conference website until August 16, 2009, 24:00 Japan time. (http://www.ssdm.jp)
- 2 - Online registration will be closed on September 18, 2009, 24:00 Japan time. After the date, registration will be possible at the conference venue as on-site registration. Conference Registration Fee Before After Banquet 24:00, Aug 16 0:00, Aug 17 (Japan time) (Japan time) Regular ¥50,000 ¥55,000 ¥7,000 Student ¥20,000 ¥4,000 Accompanied person ¥4,000 Short Course / Workshop Short Course Workshop Short Course & (in English) (in English) Workshop Regular ¥15,000 ¥15,000 ¥20,000 Student ¥3,000 ¥3,000 ¥5,000 *Fees include tax.
(1) This year, we disuse a paper extended abstracts book. Extended abstracts are provided by USB thumb. The registration fee includes an extended abstract USB thumb. Banquet fee is not included. (The conference banquet will be held on the evening of Wednesday, October 7.) (2) Those who register as students are required to fax a copy of their current student ID to KNT (Fax:+81-3-5256-1588) after they complete on-line registration, and to present their student ID at the registration desk in order to be eligible for the student registration fee. When sending the fax, please write down your registration ID, which will be given at the completion of online registration of individual information. (3) Registration will be completed only with full payment.
- 3 - Payment Procedure Payment can be made by: ・One of the following credit cards: 1. VISA 2. MasterCard 3. Diners Club 4. AMEX 5. JCB ・A bank transfer to KNT Co., Ltd. (Message: SSDM) Account at Sumitomo Mitsui Banking Corp., Suzuran Branch, 1-3-12 Nishishimbashi, Minato-ku, Tokyo 105-0003, Japan (SWIFT Code: SMBCJPJT, Ordinary Account: 6103515, Account Name: Kinki Nippon Tourist Co., Ltd.) * Personal checks are not acceptable.
Confirmation of Pre-Registration Upon receipt of your online registration, a written confirmation will be e-mailed to you after your payment is confirmed. Please bring this confirmation slip with you and present it to the registration desk.
Registration Cancellation Conference: Cancellation fee of JPY3,000 will be deducted from the refund. Cancellation should be made in writing to KNT Co., Ltd. No cancellation will be accepted on or after August 16, 2009. Extended Abstracts will be sent to absent registrants after the conference. Short Course / Workshop: Cancellation fee of JPY2,000 will be deducted from the refund. Cancellations should be made in writing to KNT Co., Ltd. No cancellation will be accepted on or after August 16, 2009. Short-course and workshop textbooks will be sent to the absent registrants after the conference. Banquet: Cancellation fee of JPY1,000 will be deducted from the refund, Cancellations should be made in writing to KNT Co., Ltd. No cancellation will be accepted on or after August 16, 2009.
Inquiries for Registration Kinki Nippon Tourist Co., Ltd. (KNT) Global Business Management Branch Tokyo Kintetsu Bldg. 6F 19-2 Kanda-Matsunaga-cho Chiyoda-ku, Tokyo 101-8641, JAPAN
- 4 - Tel: +81-3-5256-1581 Fax: +81-3-5256-1588 E-mail: [email protected] Open hours: 9:30-17:30 (weekdays only)
On-site Registration Conference: Registration fees should be paid in cash (JPY) or credit cards. VISA, MasterCard, Diners Club, AMEX and JCB are acceptable. Personal checks are not acceptable. Short Course / Workshop: Registration fees should be paid in cash (JPY) only.
BANQUET The conference banquet will be held on the evening of Wednesday, October 7 19:30-21:30. The banquet fee (Regular: JPY7,000, Student/Accompanied person: JPY4,000) is NOT included in the Registration fee. Participants who wish to attend the banquet are requested to order the banquet ticket through the on-line registration. Banquet tickets may also be purchased at the on-site registration desk.
LATE NEWS PAPERS Submission of Late News Papers has been already closed on 24:00, July 27, 2009 (Japan time). The accepted papers will be on “Advance Program Part II” which will be available at the conference venue.
SPECIAL Issue of JJAP Authors of SSDM2009 papers are encouraged to submit their original papers to the Special Issue of Japanese Journal of Applied Physics which will be published in April 2010.
- 5 - RUMP SESSIONS - October 8 (Thursday) 19:00-21:30
Session A (4F Hirose-Higashi)
“Novel Lithography for more Moore/beyond CMOS and More than Moore”
Based on the discussion of orthodox lithography technology for ultimate CMOS, future of beyond CMOS technology is discussed then the novel lithography technology is foreseen with glances of beyond CMOS devices. Furthermore, lithography for toward more than Moore, such as 3D integration, MEMS integration, etc. are discussed.
Organizer: K. Masu (Tokyo Tech, Japan) Moderator: H. Wakabayashi (Sony Corp., Japan) M. Hane (NEC Corp., Japan)
Session B (4F Hirose-Nishi)
“Solar Cells for Electronics: from In-Vehicle to Ubiquitous”
Mass production of solar cells has boosted their market growth from several MW to more than 1 GW in the past quarter century. These cells present great promise as a clean, inexpensive electric power source for portable electronics applications. Future inexpensive lightweight photo voltaic devices are expected to change the electronic systems more ubiquitous ones by eliminating unnecessary electric wires. In this rump session, we will invite presenters representing application and technology sides from all the areas of the 41th SSDM to provide a vision of “How new photovoltaic systems change the electronics and human societies”.
Organizer: K. Ohashi (NEC Corp., Japan) Moderator: M. Ishiko (Toyota Central R&D Labs., Inc, Japan) N. Usami (Tohoku Univ., Japan)
- 6 - SHORT COURSE “From Basic Theory to Newest Application in MOS Devices” Date: October 6th (Tue), 2009 Location: Lecture room, 2nd build, 5F, Inst of Fluid Sci, Tohoku Univ. Organizers:Yukiharu Uraoka (NAIST) / Noriaki Matsunaga (Toshiba) ※ All lectures are given in English. Over sixty years has past after the invention of transistor by Shockley. This invention has brought about highly advanced information society which has never been expected. Miniaturization of the semiconductor device has progressed steadily until now, however, many researchers points out their limit recently. MOS (Metal-Oxide- Semiconductor) transistors have played important role in various devices such as logic or memory and their high performance have been pursued extensively. In recent years, new materials such as high-k film or strain silicon have been introduced, however, their important role will not be replaced. In this short course, MOS transistors are lectured in various view points from basic theory to newest application for beginners such as students or younger researchers. 11:00-12:00 Advanced LSI Technology - Operation Principles of Scaled MOS Transistors- T. Hiramoto, Univ. of Tokyo 13:00-14:00 Gate Stack Technology -From thin gate oxide to High-k gate dielectric- M. Niwa, Panasonic Corp. 14:00-15:00 Interconnect Technology K. Ueno, Shibaura Inst. of Tech. 15:20-16:20 Analysis Technique of LSI device S. Miyazaki, Hiroshima Univ. 16:20-17:20 Nano Device Design by Theoretical Approach K. Shiraishi, Univ. of Tsukuba
- 7 - WORKSHOP “Green Technology -Nanodevices Toward Environmental- Friendly Society-” Date: October 6th (Tue), 2009 Location: Seminar room, COE Build, 3F, Inst of Fluid Sci, Tohoku Univ. Organizers:Tetsuo Endoh(Tohoku Univ.) / Takahiro Shinada (Waseda Univ.) ※ All lectures are given in English. The earth is currently going to face environmental issues due to global warming caused by greenhouse gases. There is a growing interest in “green technologies” for building a sustainable society by reducing environmental burdens. Technological innovation in various leading- edge technology fields will drive the environmental- friendly society. This workshop is focused on device technologies: photovoltaic cell for the application of solar energy; light-emitting diode (LED) illumination and low power integrated-circuit (IC) for low power operation; power devices for power management; and micro-system technology for energy saving, so as to contribute to green technology. These technologies will be presented by experts in the fields. 12:30-13:15 Latest Technology on Solar Photovoltaics and Future Outlook M. Kondo, AIST 13:15-14:00 Low Power Organic Light Emitting Devices C. Adachi, Kyushu Univ. 14:10-14:55 Low-Power 3D CMOS Integration T. Kuroda, Keio Univ. 14:55-15:40 Ultra-Low Power IC Technology Integrated with Innovative Materials T. Hanyu, Tohoku Univ. 15:40-16:25 Leading-Edge Power Devices and Future Prospective H. Ohashi, AIST 16:35-17:20 Micro-System Technologies for Energy Saving M. Esashi, Tohoku Univ.
- 8 - AGREEMENT NOT TO PRE-PUBLISH ABSTRACTS By submitting an abstract to the committee for review, the author(s) agrees that the work will not be published prior to presentation at the conference. Papers found to be in breach of this agreement will be withdrawn by the conference committee.
AWARDS “SSDM Awards” will be given to outstanding papers presented at previous conferences. SSDM Award Given for an outstanding contribution to the field of solid state devices and materials, among papers presented in or before 2003. SSDM Paper Award Given for the best paper presented at the conference last year. SSDM Young Researcher Award Given for outstanding papers authored by young researchers and presented at the conference last year.
FINANCIAL SUPPORT Limited financial support is available for presentations by full-time students. Student presenters who are interested in support should contact the SSDM Secretariat directly (e-mail: ssdm_secretariat@intergroup. co.jp) prior to the end of August after receiving their acceptance letter. A copy of their student ID should be submitted at application.
VISA REQUIREMENT All overseas participants must have valid passports. Overseas participants who require a visa should consult the nearest Japanese Embassy or Consulate as soon as possible. If your paper is accepted for presentation at SSDM 2009 and your visa application requires an invitation to attend the conference, please contact the SSDM Secretariat.
- 9 - OFFICIAL TRAVEL AGENT Kinki Nippon Tourist Co., Ltd. (KNT) Global Business Management Branch Tokyo Kintetsu Bldg. 6F 19-2 Kanda-Matsunaga-cho, Chiyoda-ku Tokyo 101-8641, Japan Phone: +81-3-5256-1581 Fax: +81-3-5256-1588 E-mail: [email protected]
Hotel Accommodations KNT has blocked rooms at following hotels in Sendai for the conference period. Reservations can be made through the conference website beginning in June. If the hotel of your first choice is fully booked, your second choice or a hotel in the same grade will be reserved.
Hotel Name Sendai Kokusai Hotel Room Rates Single: ¥10,000 Twin ¥8,500 (per person, per night) Hotel Deposit ¥15,000 Check-in/out Check-in: 13:00 / Check-out: 12:00 Address 4-6-1, Chuo, Aoba-ku, Sendai City, Miyagi Pref., 980-0021, Japan Phone +81-22-268-1111 Access to Hotel 5 min. walk from JR Sendai Sta. To Conference site 0 min.
Hotel Name Chisun Hotel Sendai Room Rates Single: ¥6,900 (per person, per night) Hotel Deposit ¥10,000 Check-in/out Check-in: 15:00 / Check-out: 10:00 Address 4-8-7, Chuo, Aoba-ku, Sendai City, Miyagi Pref., 980-0021, Japan Phone +81-22-262-3211 Access to Hotel 5 min. walk from Sendai Sta. To Conference site 2 min. walk.
- 10 - Hotel Name Hotel Richfield Aoba Do-ri Room Rates Single: ¥7,980 (per person, per night) Hotel Deposit ¥10,000 Check-in/out Check-in: 13:00 / Check-out: 11:00 Address 2-3-18 Chuo, Aoba-ku, Sendai City, Miyagi Pref., 980-0021, Japan Phone +81-22-262-1355 Access to Hotel 7 min. walk from Sendai Sta. To Conference site 5 min. walk
Hotel Name Hotel Sunroute Sendai Room Rates Single: ¥8,000 (per person, per night) Hotel Deposit ¥10,000 Check-in/out Check-in: 14:00 / Check-out: 10:00 Address 4-10-8, Chuo, Aoba-ku, Sendai City, Miyagi Pref. 980-0021, Japan Phone +81-22-262-2323 Access to Hotel 5min. walk from Sendai Sta., west exit To Conference site 3 min. walk
Hotel Name Hotel Monterey Sendai Room Rates Single: ¥12,600 (per person, per night) Hotel Deposit ¥15,000 Check-in/out Check-in: 14:00 / Check-out: 11:00 Address 4-1-8 Chuo Aoba-ku Sendai City, Miyagi Pref., 980-0021, Japan Phone +81-22-265-7110 Access to Hotel 3 min. walk from Sendai Sta. To Conference site 5 min. walk
Hotel Name Hotel Metropolitan Sendai Room Rates Single: ¥13,900 (per person, per night) Hotel Deposit ¥15,000 Check-in/out Check-in: 14:00 / Check-out: 12:00 Address 1-1-1, Chuo, Aoba-ku, Sendai City, Miyagi Pref., 980-8477, Japan Phone +81-22-268-2525 Access to Hotel 1min. walk from Sendai Sta. To Conference site 5 min. walk
Hotel Name R&B Hotel Sendai Hirosedori Ekimae Room Rates Single: ¥5,460 (per person, per night) Hotel Deposit ¥10,000 Check-in/out Check-in: 15:00 / Check-out: 10:00 Address 2-6-37 Honcho, Aoba-ku, Sendai City, Miyagi Pref., 980-0014, Japan Phone +81-22-726-1919 Access to Hotel 8 min. walk from JR Sendai Sta. To Conference site 15 min. walk
- 11 - Notes: All room rates are per person per night including breakfast, 10% service charge, and consumption tax.
Application and Payment Participants wishing to reserve hotel accommodations should access the Registration and Accommodation pages of the conference website. The page will be opened in early June and reservations should be made by no later than September 18, 2009 (Japan time). *Confirmation sheet will be sent by KNT after the application deadline. Application should be accompanied by the payment of room deposit and communication fee of 500 JPY. No reservation will be confirmed in the absence of this payment. All payment must be paid only in Japanese yen by one of the following method.
1) Credit Card by Online (VISA, MasterCard, AMEX, Diners Club or JCB only.). *Please fill in the necessary items in the credit card section of the application form.
2) Bank Transfer: Sumitomo Mitsui Banking Corp. Suzuran Branch SWIFT Code: SMBCJPJT Account Number: 6103515 Account Name: Kinki Nippon Tourist Co., Ltd.
Cancellation In case of cancellation, a written notification should be sent to KNT to avoid any troubles. The cancellation charge are: Up to 14 days before the arrival date------No Charge 13 - 7 days before------10 % of daily room charge 6 - 2 days before------40 % of daily room charge Less than 2 days, or no notice given -----100 % of daily room charge
- 12 - INSURANCE The organizer cannot accept responsibility for accidents that may occur during a delegate’s stay. Delegates are therefore encouraged to obtain travel insurance (medical, personal accident and luggage) in their home countries prior to departure.
CLIMATE Sendai shares the same latitude as Washington D.C., the capital of the United States, and Athens, Greece. Sendai enjoys a very comfortable and temperate climate compared to other cities in Japan. Its average temperature is 12.1ºC and its annual precipitation is 1,241.8 mm. The hottest month is August with an average temperature of 24.1°C; the coldest month is January with an average temperature of 1.5°C.
ELECTRICAL APPLIANCES Japan operates on 100 volts for electrical appliances. The frequency is 50 Hz in Eastern Japan including Sendai (conference site) and Tokyo, and 60 Hz in Western Japan including Kyoto and Osaka.
- 13 - SSDM 2008 INSTRUCTION for SPEAKERS Oral Presentation Time Schedule Total session Presentation Discussion time time time Plenary 45 min. 40 min. 5 min. Invited 30 min. 25 min. 5 min. Regular-1 20 min. 15 min. 5 min. Regular-2 15 min. 10 min. 5 min. BELL: First: Warning, Second: End of speech, Third: End of the discussion.
Oral Presentation
Audio-Visual Equipment The following equipments are ready at each conference meeting room during SSDM 2009: ・LCD projector ・PC (laptop computer), Windows XP , PowerPoint 2003 (No PowerPoint 2007) or PDF The use of personal PCs for presentations is prohibited. ・Microphone ・Projection laser pointer
Preparing your Presentation Please note that the presentation file format should be PowerPoint 2003 but Acrobat pdf (Windows XP) is acceptable. Use of special fonts such as Asian fonts is prohibited. If you have to use those, embedding all fonts in PDF is only acceptable.
Uploading your Presentation The single most important action of the authors is to upload your presentation file to the SSDM PC in the Speaker’s Room (Yuki room 4F) one day in advance of your expected presentation date, or as soon as possible upon your arrival. The Speaker’s Room Hours are following. Please make sure to bring the electronic copy of your presentation files with you to the SSDM using your USB thumb drive. Speakers are requested to check the compatibility of the presentation files with the format ready in the SSDM PC.
- 14 - Speaker’s Room (Yuki room 4F) Oct. 7 Wednesday: 9:00-12:30 Oct. 8 Thursday: 10:30-12:30, 18:40-20:30 Just in case you miss the Speaker’s Room Hours, bring your presentation file directly to the Meeting Room.
Confidentiality At the end of meeting, all electronic files will be destroyed and the SSDM PC hard drives will be reformatted.
Poster Presentation Posting board and poster board Poster sessions are scheduled for Thursday, October 8, from 10:30 to 12:00 at Heisei
Short Oral Presentation for Poster Presenters All poster presenters are required to make 3 minutes short oral presentation on October 8. The presentation time should be kept strictly to 3 minutes per poster presentation, including the time needed to move on to the next speaker. To ensure the session progresses smoothly, it is essential that these short presentations be held in a quick, successive sequence. While one speaker is giving his/her presentation, the next speakers should wait nearby in line for their turn in order to move on to the next presentation. Please note that any absent speakers will be skipped and each presentation will be automatically stopped after 3 minutes have elapsed. Only a PC projector will be made available. You should send your short presentation file to the secretariat ([email protected]) by
- 15 - e-mail by before September 6, 2009. Please indicate your paper number and name in the title of your e-mail. The file must be in 3-page landscape PDF format, and the 1st page must indicate your paper title, name of authors and their affiliations only. Because of the limited presentation time, please describe clearly and tersely your research objective and results. Short oral presentations will be held as follows: 2F Heisei
- 16 - Wednesday, October 7
Opening Session (10:00-12:00) Chair: S. Samukawa, Tohoku Univ. K.Wada, Univ. of Tokyo
10:00 PL-1-0 Welcome Address and SSDM Award Presentaion M. Koyanagi, Tohoku Univ.
10:30 PL-1-1 Moore's Law Past 32nm: the Challenges in Physics and Technology Scaling K. J. Kuhn, Intel Corp., USA
11:15 PL-1-2 The Third Generation of Solar Photovoltaic Electricity T. Tomita, Univ. of Tokyo, Japan
12:00-13:30 Lunch
Area 1: Advanced Gate Stack / Si Processing & Material Science B-1: Characterization 13:30-15:40 2F Heisei
13:30 B-1-1 (Invited) Microscopic Characterization of Devices by Scanning Transmission Electron Microscopy: From Single Atom Imaging to Macroscopic Properties S. J. Pennycook, K. van Benthem, A. G. Marinopoulos and S. T. Pantelides, Oak Ridge National Lab. (USA)
14:00 B-1-2 Three-Dimensional Visualization Technique for Crystal Defects in High Performance CMOS Devices with Embedded SiGe-Source/Drain S. Kudo, N. Nakanishi, Y. Hirose, K. Sato, T. Yamashita, H. Oda, K. Kashihara, N. Murata, T. Katayama, K. Asayama, J. Komori and E. Murakami, Renesas Tech.
- 17 - Wednesday, October 7
Corp. (Japan)
14:20 B-1-3 X-ray photoelectron spectroscopy study of dipole effects at HfO2/SiO2/Si stacks L. Q. Zhu, K. Kita, T. Nishimura, K. Nagashio, S. K. Wang and A. Toriumi, Univ. of Tokyo (Japan)
14:40 B-1-4 Impact of Si Oxidation States on Dipole Layer at HfO2/Si Interface N. Miyata1,2, Y. Abe2 and T. Yasuda1, 1AIST and 2Musashi Inst. of Tech. (Japan)
15:00 B-1-5 Evaluation of Effective Work Function of Pt on Bi-layer High-k/SiO2 Stack Structure using by Backside X-ray Photoelectron Spectroscopy T. Mori, A. Ohta, H. Murakami, S. Higashi and S. Miyazaki, Hiroshima Univ. (Japan)
15:20 B-1-6 Molecular Dynamics Study of Oxidation Process with SiO emission and incorporation into the Si/SiO2 System N. Takahashi, T. Yamasaki and C. Kaneta, Fujitsu Labs. Ltd. (Japan) 15:40-16:00 Break
Area 1: Advanced Gate Stack / Si Processing & Material Science B-2: Characterization and Process Technology 16:00-18:15 2F Heisei
16:00 B-2-1 Thermally stable Ni-silicide gate electrode with TiN barrier metal for NAND flash memory application with 24 nm technology and beyond S. J. Whang, M. S. Joo, B. M. Seo, K. E. Chang,
- 18 - Wednesday, October 7
W. K. Kim, T. W. Jung, G. H. Kim, J. Y. Lim, K. Y. Kim, K. Hong and S. K. Park, Hynix Semiconductor Inc. (Korea)
16:20 B-2-2 Lanthanoid Metal Oxide MIM Capacitors for Precision Analog Circuits: Material Screening, Process Development, and Characterization J. D. Chen1, J. J. Yang1, R. Wise2, P. Steinmann2, C. Zhu1 and Y. C. Yeo1, 1National Univ. of Singapore and 2Texas Instruments Inc. (Singapore)
16:40 B-2-3 Oxygen-Terminated Si Surface for Atomic Layer Deposition and its Impact on Interfacial Electrical Quality of sub-nm-EOT high-k Gate Stacks Y. Morita, S. Migita, N. Taoka, W. Mizubayashi and H. Ota, MIRAI-AIST (Japan)
17:00 B-2-4 New Criteria for Suppressing Extrinsic Defect Generation in Ultra Thin SiON Gate Insulator (EOT<1.4nm) for Advanced CMOSFETs S. Shimamoto1, H. Kawashima2, T. Kikuchi1, Y. Yamaguchi2 and A. Hiraiwa2, 1Hitachi, Ltd. and 2Renesas Tech. Corp. (Japan)
Area 2: Characterization and Materials Engineering for Interconnect Integration D-1: 3D Integration 13:30-15:40 3F Sakura Chair: J. Kodate (NTT) J. Gambino (IBM Microelectronics)
13:30 D-1-1 (Invited) Through-Si-Via Technology Solutions for 3D System Integration E. Beyne, B. Swinnen, J. V. Olmen, D. S. Tezcan, A. Jourdain and P. Limaye, IMEC (Belgium)
- 19 - Wednesday, October 7
14:00 D-1-2 Development of EEB (Electroplated-Evaporation Bumping) Technology for Fine Pitch and Low Resistance Cu/Sn Micro-Bumps Y. Ohara, A. Noriki, E. Iwata, T. Hiraki, K. W. Lee, M. Murugesan, J. C. Bea, T. Fukushima, T. Tanaka and M. Koyanagi, Tohoku Univ. (Japan)
14:20 D-1-3 High-Aspect-Ratio Fine Cu Sidewall Interconnection over Chip Edge with Tapered Polymer for MEMS-LSI Multi- Chip Module A. Noriki, Y. Kaiho, E. Iwata, Y. Ohara, M. Murugesan, K. W. Lee, J. C. Bea, T. Fukushima, T. Tanaka and M. Koyanagi, Tohoku Univ. (Japan)
14:40 D-1-4 Back-Side Illuminated CMOS Image Sensor Fabricated using Compliant Bump N. Watanabe1, I. Tsunoda2, T. Takao1, K. Tanaka3 and T. Asano1, 1Kyushu Univ., 2Kyushu Inst. of Tech. and 3Kyushu Sangyo Univ. (Japan)
15:00 D-1-5 Tantalum lightshield for CMOS image sensor with global shutter J. Gambino, R. J. Rassel, A. Watts, C. Musante, R. Krishnasamy, B. Leidy, N. Lai, T. C. Lee, P. Razina, C. Walsh, B. Czabaj, R. Preston, D. Demuynck, J. Adkisson, J. Ellis-Monaghan and M. Jaffe, IBM (USA)
15:20 D-1-6 Nondestructive Warpage Measurements of LSI Chips in a Stacked SiP by using High-Energy X-ray Diffraction A. Toda and N. Ikarashi, NEC Corp. (Japan) 15:40-16:00 Break
Area 2: Characterization and Materials Engineering for Interconnect Integration D-2: RF Device/Process Technology 16:00-18:10 3F Sakura
- 20 - Wednesday, October 7
Chair: Y. Hayashi (NEC Electronics Corp.) N. Nakano (Keio Univ.)
16:00 D-2-1 (Invited) Wireless Interconnection by Electromagnetic Coupling of Open-Ring Resonators and Its Application to System Integration Y. Ohno1 and I. Awai2, 1Univ. of Tokushima and 2Ryukoku Univ. (Japan)
16:30 D-2-2 Transmission Characteristics of Silicon On-chip Integrated Antennas as Millimeter-Wave Wireless Interconnects W. Moriyama, K. Kimoto, S. Kubota, N. Sasaki and T. Kikkawa, Hiroshima Univ. (Japan)
16:50 D-2-3 High Gain and High Directivity UWB Bow-tie Antenna with High Impedance Metamaterial Surface S. Kubota, N. Sasaki, Y. Kayaba, W. Moriyama, T. Kozaki and T. Kikkawa, Hiroshima Univ. (Japan)
17:10 D-2-4 A Novel Multi-Layered Hetero-Structure of Ni-Zn Ferrite/ TaN Buffer for Effective Magnetic Core in On-Chip Inductors K. Kaneko, N. Inoue, N. Furutake and Y. Hayashi, NEC Electronics Corp. (Japan)
17:30 D-2-5 System-on-Package Platform with Decoupling Capacitor Integration and Thermal Performance Improvement N. Jeon, J. Noh, J. Maeng and K. S. Seo, Seoul National Univ. (Korea)
17:50 D-2-6 Stabilities of La2O3 Metal-Insulator-Metal Capacitors under Constant Voltage Stress S. H. Wu, C. K. Deng and B. S. Chiou, National Chiao Tung Univ. (Taiwan)
- 21 - Wednesday, October 7
Area 3: CMOS Devices /Device Physics A-1: SOI/GOI and Channel Engineering 13:30-16:00 2F Heisei
13:30 A-1-1 (Invited) Ultrathin Body and BOX SOI and SSOI for Low Power Application at the 22nm technology node and below F. Andrieu1, C. Fenouillet-Béranger2, O. Weber1, S. Baudot1, C. Buj1, J. P. Noel1, O. Thomas1, O. Rozeau1, P. Perreau2, L. Tosti1, L. Brévard1 and O. Faynot1, 1CEA- LETI/MINATEC and 2Also with STMicro electoronics (France)
14:00 A-1-2 Vth Dependence of Vth Variability in Intrinsic Channel SOI MOSFETs with Ultra-Thin BOX C. Lee1, A. T. Putra1, K. Shimizu1 and T. Hiramoto1,2, 1Univ. of Tokyo and 2MIRAI-Selete (Japan)
14:20 A-1-3 Counter-doping as a solution for multi threshold voltage on FDSOI MOSFETs with a single TiN/HfO2 gate stack C. Buj-Dufournet, F. Andrieu, O. Faynot, O. Weber, F. Allain, L. Tosti, C. Fenouillet-Béranger, D. Lafond and S. Deleonibus, CEA-LETI/MINATEC (France)
14:40 A-1-4 High Performance (110)-oriented GOI pMOSFETs Fabricated by Ge Condensation Technique S. Dissanayake1, S. Sugahara2, M. Takenaka1 and S. Takagi1, 1Univ. of Tokyo and 2Tokyo Tech (Japan)
15:00 A-1-5 The Impact of Uni-axial Strain and Dynamic Body Biases on Low Frequency Noise in Nanoscale pMOSFETs K. L. Yeh, C. Y. Ku, W. L. Hong and J. C. Guo, National Chiao Tung Univ. (Taiwan)
- 22 - Wednesday, October 7
15:40 A-1-7 (Invited) The Tunnel Source n-MOSFET: A Novel Asymmetric Device for Low Power Applications N. Venkatagirish, A. Tura, R. Jhaveri, H. Y. Chang and J. Woo, UCLA (USA)
Area 3: CMOS Devices /Device Physics A-2: Variability and RTS 16:00-18:20 2F Heisei
16:00 A-2-1 A new definition of threshold voltage by constant slope for analysis of statistical variations of MOSFETs T. Tanaka, H. Suzuki and O. Yamasaki, Fujitsu Microelectronics Ltd. (Japan)
16:20 A-2-2 Temperature Coefficient of Threshold Voltage in Metal/ High-k Gate Transistors with Various Thickness of TiN and Capping Layers Y. Nishida1,2, K. Eikyu1, A. Shimizu1, T. Yamashita1, H. Oda1, Y. Inoue1 and K. Shibahara2, 1Renesas Tech. Corp. and 2Hiroshima Univ. (Japan)
16:40 A-2-3 Impact of interface roughness on threshold-voltage variation in ultra-small three-dimensional MOSFETs N. Mori and H. Minari, Osaka Univ. (Japan)
17:00 A-2-4 Statistical Analysis of Time Constant Ratio of Random Telegraph Signal with Very Large-Scale Array TEG T. Fujisawa, K. Abe, S. Watabe, N. Miyamoto, A. Teramoto, S. Sugawa and T. Ohmi, Tohoku Univ. (Japan)
17:20 A-2-5 Impact of Channel Doping Concentration on Random
- 23 - Wednesday, October 7
Telegraph Signal Noise K. Abe1, A. Teramoto1, S. Watabe1, T. Fujisawa1, S. Sugawa1, Y. Kamata2, K. Shibusawa2 and T. Ohmi1, 1Tohoku Univ. and 2OKI Semiconductor Miyagi Co., Ltd. (Japan)
17:40 A-2-6 Experimental Study on Ig RTS Noise of SiON/HfO2/TaN PMOSFETs L. Zhang1, R. Wang1, J. Zhuge1, R. Huang1, T. Yu1, P. Kirsch2, H. H. Tseng2 and Y. Wang1, 1Peking Univ. and 2SEMATECH (China)
18:00 A-2-7 Leakage and Matching Optimization of SRAM-cells for Wireless Applications N. Planes1, O. Menut1, C. Laviron2, J. Bonnouvrier1, F. Wacquant1, R. Ranica1, C. Boccaccio1, O. Callen1, S. Del Medico1, D. Noblet1, M. Haond1 and F. Boeuf1, 1STMicroelectronics and 2CEA-LETI (France)
Area 4: Advanced Memory Technology G-1: DRAM 13:30-15:20 4F Hirose
13:30 G-1-1 (Invited) Overview and Future Challenges of Capacitor-less DRAM Technologies for High Density Memory Applications P. Fazan, Innovative Silicon S.A. (Switzerland)
14:00 G-1-2 A Highly Scalable 4F2 DRAM Cell Utilizing a Doubly Gated Vertical Channel W. Kwon and T. J. King. Liu, Univ. of California Berkeley (USA)
14:20 G-1-3 Highly Scalable Capacitorless DRAM Cell on Thin-Body
- 24 - Wednesday, October 7 with Band-gap Engineered Source and Drain P. Tang, D. Wu, L. Zhang and R. Huang, Peking Univ. (China)
14:40 G-1-4 Performance Improvement of the Capacitorless DRAM Cell with Quasi-SOI Structure Based on Bulk Substrate D. Wu, R. Huang, P. Tang,Y. Zhang and Y. Wang, Peking Univ. (China)
15:00 G-1-5 Seed layer and multistack approaches to reduce leakage in SrTiO3-based MIM capacitors using TiN bottom electrode N. Menou1, M. Popovici1, K. Opsomer1,2, B. Kaczer1, M. A. Pawlak1, A. Franquet1, C. Detavernier2, S. Van Elshocht1, D. J. Wouters1, S. Biesemans1 and J. A. Kittl1, 1IMEC and 2Ghent Univ. (Belgium) 15:20-16:00 Break
Area 4: Advanced Memory Technology G-2: Flash Memory I 16:00-17:50 4F Hirose
16:00 G-2-1 (Invited) Electrical Defects in Dielectrics for Flash Memories Studied by Trap Spectroscopy by Charge Injection and Sensing (TSCIS) R. Degraeve, M. Cho, B. Govoreanu, B. Kaczer, M. B. Zahid, G. Van den bosch, J. Van Houdt, M. Jurczak and G. Groeseneken, IMEC (Belgium)
16:30 G-2-2 Charge Localization During Program and Retention in NROM-like Nonvolatile Memory Devices E. Nowak1, E. Vianello1,2, L. Perniola1, M. Bocquet1, G. Molas1, R. Kies1, M. Gely1, G. Ghibaudo3, B. D. Salvo1, G. Reimbold1 and F. Boulanger1, 1CEA-LETI/MINATEC, 2Univ. of Udine and 3IMEP/INPG (France)
- 25 - Wednesday, October 7
16:50 G-2-3 Study of Transient Tunneling Current and Charge- Trapping Behaviors of SONOS-type Devices using Pulse- IV Technique P. Y. Du1,2, H. T. Lue1, S. Y. Wang1, T. Y. Huang2, K. Y. Hsieh1, R. Liu1 and C. Y. Lu1, 1Macronix Iint'l Co., Ltd. and 2National Chiao Tung Univ. (Taiwan)
17:10 G-2-4 Roles of Traps Generated in Al2O3 Film with respect to Memory Characteristics in MANOS K. Akiyama, T. Ozaki, H. Higashijima, Y. Tanaka, T. Shibata, Y. Akasaka and T. Kaitsuka, Tokyo Electron Ltd. (Japan)
17:30 G-2-5 A New Method to Extract the Charge Centroid in the Program Operation of MONOS memories S. Fujii, N. Yasuda, J. Fujiki and K. Muraoka, Toshiba Corp. (Japan)
Area 5: Advanced Circuits and Systems C-1: Interconnect-related Circuits Technology 13:30-15:40 2F Heisei
13:30 C-1-1 (Invited) Wireless CMOS TSV T. Kuroda, Keio Univ. (Japan)
14:00 C-1-2 Electromagnetic Interference and Susceptibility in Inductive-Coupling Link K. Kasuga, N. Miura, Y. Yuan, H. Ishikuro and T. Kuroda, Keio Univ. (Japan)
14:20 C-1-3 Design of On-Chip High Speed Interconnect on CMOS 180nm Technology T. Oshita, S. Amakawa, N. Ishihara and K. Masu, Tokyo
- 26 - Wednesday, October 7
Tech (Japan)
14:40 C-1-4 A Novel CMOS 800 Mb/s BPSK Detector for IR-UWB Communication M. Hafiz, N. Sasaki and T. Kikkawa, Hiroshima Univ. (Japan)
15:00 C-1-5 A 3.5-4.5 GHz CMOS UWB Receiver Frontend LNA with On-chip Integrated Antenna for Inter-chip Communication A. Azhari, K. Kimoto, N. Sasaki and T. Kikkawa, Hiroshima Univ. (Japan)
15:20 C-1-6 Bitline-Capacitance-Insensitive Readout Circuit using Capacitive-Feedback Charge-Integration Scheme for Low- Voltage FeRAM K. Kotani, Y. Koshimoto and T. Ito, Tohoku Univ. (Japan) 15:40-16:00 Break
Area 5: Advanced Circuits and Systems C-2: Power Management and Advanced Mixed-Signal Technology 16:00-18:00 2F Heisei
16:00 C-2-1 (Invited) Recent Topics in Power Management Circuits H. Kobayashi, Gunma Univ. (Japan)
16:30 C-2-2 An Enhanced PMOS Charge Pump for Low Supply Voltage Applications C. P. Hsu, H. M. Wu and H. Lin, National Chung Hsing Univ. (Taiwan)
16:50 C-2-3 (Invited) CMOS Circuit Design Techniques for Millimeter-Wave
- 27 - Wednesday, October 7
Applications R. Fujimoto, T. Mitomo, H. Hoshino and Y. Yoshihara, Toshiba Corp. (Japan)
17:20 C-2-4 A 10-bit, 290 fJ/conv. Steps, 0.13mm2, Zero-Static Power, Self-Timed Capacitance to Digital Converter T. M. Vo, Y. Kuramochi, M. Miyahara, T. Karashina and A. Matsuzawa, Tokyo Tech (Japan)
17:40 C-2-5 Qpix, a Pixel Readout LSI with a Built-in ADC for Particle Detector Applications M. K. Vu, F. Li, M. Miyahara, T. Kurashina and A. Matsuzawa, Tokyo Tech (Japan)
Area 6: Compound Semiconductor Circuits, Electron Devices and Device Physics J-1: GaN FETs and RF Devices 13:30-15:45 6F Hagi Chair: M. Kuzuhara (Univ. of Fukui) K. J. Chen (Hong Kong Univ.of Sci. and Tech.)
13:30 J-1-1 (Invited) Materials and Strain Issues in AlGaN/GaN HEMT Degradation E. Muñoz1, C. Rivera1, F. Gonzalez-Posada1, A. Redondo1,2, F. Romero1, R. Cuerdo1, F. Calle1, R. Gago3, A. Jimenez4 and C. Palacio2, 1Univ. Politécnica de Madrid, 2Univ. Autónoma de Madrid, 3CSIC and 4Univ. Alcalá de Henares (Spain)
14:00 J-1-2 Compressively Strained-InxAl1-xN/Al0.22Ga0.78N/GaN (x = 0.245 - 0.325) Heterostrucures FETs with a Regrown AlGaN Contact Layer M. Hiroki, N. Maeda and N. Shigekawa, NTT Corp. (Japan)
- 28 - Wednesday, October 7
14:15 J-1-3 AlGaN/GaN HFET using AlN/GaN Superlattice Barrier Layer S. Yagi, Y. Kawakami, X. Q. Shen, A. Nakajima, T. Ide and M. Shimizu, AIST (Japan)
14:30 J-1-4 Effect of GaN Growth Pressure on the Device Characteristics of AlGaN/ GaN HEMTs on Silicon J. Selvaraj, S. Lawrence Selvaraj and T. Egawa, Nagoya Inst. of Tech. (Japan)
14:45 J-1-5 Evaluation of GaN MOSFET with TEOS SiO2 Gate Insulator K. Nakatani1, J. P. Ao1, K. Ohmuro1, M. Sugimoto2, C. Y. Hu1, Y. Sogawa1 and Y. Ohno1, 1Univ. of Tokushima and 2Toyota Motor Corp. (Japan)
15:00 J-1-6 Quasi-Normally-Off AlN/AlGaN/GaN MIS HEMTs Grown on 4 in. Silicon Substrate S. Tan, S. Lawrence. Selvaraj and T. Egawa, Nagoya Inst. of Tech. (Japan)
15:15 J-1-7 Effective Heat Spreading with Separate Ohmic in AlGaN/ GaN HEMTs K. I. Lee1, J. H. Park1, H. J. Cho1, J. C. Her1, C. S. Yoo1,3, H. Y. Cha2 and K. S. Seo1, 1Seoul National Univ., 2Hongik Univ. and 3Korea Electronic Tech. Inst. (Korea)
15:30 J-1-8 GaN Zero-Bias RF Mixer using a Lateral Field-Effect Rectifier K. Y. Wong, W. J. Chen and K. J. Chen, Hong Kong Univ. of Sci. and Tech. (China) 15:45-16:00 Break
- 29 - Wednesday, October 7
Area 6: Compound Semiconductor Circuits, Electron Devices and Device Physics J-2: III-V High-mobility Channel Devices 16:00-18:15 6F Hagi Chair: S. Tanaka (Shibaura Inst. of Tech.) Y. Miyamoto (Tokyo Tech)
16:00 J-2-1 (Invited) High-Performance Inversion-Mode III-V MOSFETs Enabled by Atomic-Layer-Deposited Migh-k Dielectrics P. D. Ye, Purdue Univ. (USA)
16:30 J-2-2 Fabrication of InP/InGaAs Undoped Channel MOSFET with Selectively Regrown N+-InGaAs Source Region T. Kanazawa, H. Saito, K. Wakabayashi, T. Tajima, R. Terao, Y. Miyamoto and K. Furuya, Tokyo Tech (Japan)
16:45 J-2-3 Heteroepitaxy of SixGe1-x (x < 5%) Source/Drain on GaAs Substrates for the Application of III-V MOSFETs Z. Y. Han1, G. L. Luo2, S. C. Huang2, C. H. Ko3, C. H. Wann3, H. Y. Lin3, C. T. Chung1, C. C. Cheng1, C. Y. Chang1 and C. H. Chien1,2, 1National Chiao Tung Univ., 2National Nano Device Lab. and 3Taiwan Semiconductor Manufac. Co., Ltd. (Taiwan)
17:00 J-2-4 (Invited) Performance Projection of III-V and Ge Channel MOSFETs H. Tsuchiya, A. Maenaka, T. Mori and Y. Azuma, Kobe Univ. (Japan)
17:30 J-2-5 Metalorganic Vapor Phase Epitaxy of GaAs with AlP Surface Passivation Layer for Improved MOS Characteristics Y. Terada, M. Deura, Y. Shimogaki, Y. Nakano and M. Sugiyama, Univ. of Tokyo (Japan)
- 30 - Wednesday, October 7
17:45 J-2-6 Investigation of Strained-Sb Hetrostructures with High Hole Mobility A. Nainani1, M. Kobayashi1, D. Witte1, T. Irisawa1, T. Krishnamohan1, K. Saraswat1, B. R. Bennett2, M. G. Ancona2 and J. B. Boos2, 1Stanford Univ. and 2Naval Res. Lab. (USA)
Area 7: Photonic Devices and Device Physics I-1: Si Photonics and Photonic Crystals 13:30-15:45 6F Kaede Chair: H. Yamada (Tohoku Univ.) Y. Lee (Hitachi, Ltd.)
13:30 I-1-1 (Invited) Active Ge based Devices for Silicon Photonics J. Michel, J. Liu, X. Sun, M. Beals, L. C. Kimerling, MIT (USA)
14:00 I-1-2 Compact and Polarization-Independent Variable Optical Attenuator Based on a Silicon Photonic Wire Waveguide with Carrier Injection Structure H. Nishi, T. Tsuchizawa, K. Yamada, T. Watanabe, H. Shinojima and S. Itabashi, NTT Corp. (Japan)
14:15 I-1-3 Si Wire Waveguide Polarization Independent Optical Wavelength Filters H. Okayama, K. Kotani, Y. Maeno, D. Shimura, H. Yaegashi and Y. Ogawa, OKI Electric Industry Co., Ltd. (Japan)
14:30 I-1-4 Reducing Operation Voltage of Silicon-Ring Optical Modulator using High-k Cladding Layer Y. Amemiya, M. Nishida, H. Ding, M. Fukuyama and S. Yokoyama, Hiroshima Univ. (Japan)
- 31 - Wednesday, October 7
14:45 I-1-5 The Approach to Dislocation-free Ge Mesa on Si Fabricated by Dry Etching Y. Takada, J. Osaka, Y. Ishikawa and K. Wada, Univ. of Tokyo (Japan)
15:00 I-1-6 A Photonic Modulator based on a Semiconductor Soliton Device M. C. Shih, W. C. Su, I. T. Shu and W. S. Shei, National Univ. of Kaohsiung (Taiwan)
15:15 I-1-7 Demonstration of Quality Factor over 10,000 in Three- Dimensional Photonic Crys-tal Nanocavity by Cavity Size Control A. Tandaechanurat, S. Ishida, K. Aoki, D. Guimard, D. Bordel, M. Nomura, S. Iwamoto and Y. Arakawa, Univ. of Tokyo (Japan)
15:30 I-1-8 Analysis of Two-Dimensional Photonic Crystal Cavities with Low Refractive Index Material Cladding T. Yamada1,2, M. Okano2, J. Sugisaka1,2, N. Yamamoto2, M. Itoh1, T. Sugaya2, K. Komori2 and M. Mori2, 1Univ. of Tsukuba and 2AIST (Japan) 15:45-16:00 Break
Area 7: Photonic Devices and Device Physics I-2: Si Lightemitter and THz Laser 16:00-18:15 6F Kaede Chair: H. Isshiki (Univ. of Electro-Communications) M. Gotoda (Mitsubishi Electric Corp.)
16:00 I-2-1 (Invited) Optical Gain in Ultra-Thin Silicon Resonant Cavity Light- Emitting Diode S. Saito1,2, Y. Suwa1, N. Sakuma1, H. Arimoto1, D. Hisamoto1,2, H. Uchiyama1,2, J. Yamamoto1, T. Sakamizu1, T. Mine1, S. Kimura1, T. Sugawara1 and M.
- 32 - Wednesday, October 7
Aoki1,2, 1Hitachi Ltd. and 2SORST-JST (Japan)
16:30 I-2-2 PL Enhancement of Si Ring Resonators by Hydrogen Plasma Treatment Y. Wang1, J. Cai1, S. Lin1, Y. Ishikawa1, Y. Yamashita2, Y. Kamiura2 and K. Wada1, 1Univ. of Tokyo and 2Okayama Univ. (Japan)
16:45 I-2-3 Enhanced Room-Temperature 1.6 μm Electroluminescence from Si-Based Double Heterostructures Light-Emitting Diodes using Iron Disilicide M. Suzuno, T. Koizumi, H. Kawakami and T. Suemasu, Univ. of Tsukuba (Japan)
17:00 I-2-4 Fabrication and Optical Characterization of Self-standing Wide-gap Nanocrystalline Silicon Layers R. Mentek, B. Gelloz and N. Koshida, Tokyo Univ. of Agri. and Tech. (Japan)
17:15 I-2-5 Monolithic Integration of Si-Dot Light Emitting Diodes, Si Photodiodes, and Spin-Coated Optical Waveguides on Si LSI T. Tabei1, K. Maeda2, S. Yokoyama1 and H. Sunami1, 1Hiroshima Univ. and 2Central Glass Co., Ltd. (Japan)
17:30 I-2-6 Low Reflection Optical Coupling for Hybrid Integrated Wavelength Tunable Laser with Silicon Waveguide Ring Resonators N. Fujioka1,2, T. Chu1,2, S. Nakamura1 and M. Ishizaka1,2, 1NEC Corp. and 2OITDA (Japan)
17:45 I-2-7 Performance Comparison of Terahertz Quantum Cascade Lasers Predicted by Non-equilibrium Green's Function Method H. Yasuda1,2, T. Kubis3, P. Vogl3, N. Sekine2, I. Hosako2 and
- 33 - Wednesday, October 7
K. Hirakawa1, 1Univ. of Tokyo, 2NICT and 3Tech. Univ. of Munich (Japan)
18:00 I-2-8 Terahertz Laser on Optically Pumped Graphene: Concept and its Substantiation A. Dubinov1,2, V. Aleshkin2, M. Ryzhii1,4, T. Otsuji3,4 and V. Ryzhii1,4, 1Univ. of Aizu, 2Inst. For Physics of Microstructures RAS, 3Tohoku Univ. and 4CREST-JST (Japan)
Area 8: Advanced Material Synthesis and Crystal Growth Technology H-1: SiGe Related Technologies and III-V Nano Structures 13:30-15:45 6F Kiri Chair: A. Yamada (Tokyo Tech) H.H.Tan (The Australian National Univ.)
13:30 H-1-1 Epitaxial growth and defect generation in in-situ doped high percentage SiGe A. Reznicek, T. N. Adam, Z. Zhu, K. E. Fogel, J. Li, L. Tai, P. Kulkami, J. Kim, S. W. Bedell and D. K. Sadana, IBM (USA)
13:45 H-1-2 Study on SiGe Film Properties Fabricated using a Reactive Thermal CVD Method M. Wakagi1, I. Suzumura1, H. Asanuma1, E. Nishimura1, M. Matsumura1, A. Kagatsume1 and J. Hanna2, 1Hitachi, Ltd. and 2Tokyo Tech (Japan)
14:00 H-1-3 Compressively strained Ge channel heterostructures grown by RP-CVD for the next generation CMOS Devices M. Myronov, V. A. Shah, A. Dobbie, X. C. Liu, V. H. Nguyen and D. R. Leadley, Univ, of Warwick (UK)
- 34 - Wednesday, October 7
14:15 H-1-4 Formation of High Ge Concentration Virtual Substrate by Laser Annealing C. Y. Ong1, K. L. Pey1, J. P. Liu2, Q. Wang2, C. P. Wong1, Z. X. Shen1, X. C. Wang3, H. Zheng3, C. M. Ng2 and L. Chan2, 1Nanyang Technological Univ., 2Chartered Semiconductor Manufacturing Ltd. and 3Singapore Inst. Of Manufacturing Tech. (Singapore)
14:30 H-1-5 Low Temperature (375℃ ) Metal Induced Lateral Crystallization (MILC) of Si1-xGex (0≤x≤1) using Silicide/ Germanide Forming Metals (Ni, Pd and Co) T. H. Phung1, R. Xie1,2, S. Tripathy3, M. Yu2 and C. Zhu1, 1National Univ. of Singapore, 2Inst. of Microelectronics and 3Inst. of Materials Res. and Eng. (Singapore)
14:45 H-1-6 Low-dislocation-density 50nm Ge Fin Fabrication on Si substrate C. T. Chung1, S. C. Huang2, G. L. Luo2, C. H. Ko3, C. H. Wann3, H. Y. Lin3, Z. Y. Han1, C. C. Cheng1 and C. H. Chien1,2, 1National Chiao Tung Univ., 2National Nano Device Lab. and 3TSMC (Taiwan)
15:00 H-1-7 Positioning and numbering Ge quantum dots for effective quantum electrodynamic devices K. H. Chen, C. Y. Chien, W. T. Lai and P. W. Li, National Central Univ. (Taiwan)
15:15 H-1-8 Grazing Incidence X-ray Diffraction Measurements of Columnar InAs/GaAs Quantum-Dot Structures K. Watanabe, Y. Kimura and K. Mukai, Yokohama National Univ. (Japan)
15:30 H-1-9 Growth and Characterization of InGaAs Nanowires formed on GaAs(111)B by Selective-Area Metal Organic Vapor Phase Epitaxy
- 35 - Wednesday, October 7
M. Yoshimura, K. Tomioka, K. Hiruma, S. Hara, J. Motohisa and T. Fukui, Hokkaido Univ. (Japan) 15:45-16:00 Break
Area 8: Advanced Material Synthesis and Crystal Growth Technology H-2: Graphen and Nanowires 16:00-18:15 6F Kiri Chair: H. Hibino (NTT Basic Res. Labs.) K.Horn (Fritz Haber Inst.)
16:00 H-2-1 (Invited) III-V Nanowires Grown by MOCVD for Optoelectronics Applications H. H. Tan, Q. Gao, H. J. Joyce, J. H. Kang, S. Paiman, J. Wong-Leung, J. Zou, M. Paladuqu, Y. Guo, H. Wang, X. Zhang and C. Jagadish, Australian National Univ. (Australia)
16:30 H-2-2 (Invited) Growth and Electronic Structure of Epitaxial Graphene on Silicon Carbide A. Bostwick1, E. Rotenberg1, J. McChesney1,2, T. Ohta1,2, T. Seyller3 and K. Horn2, 1ALS. Lawrence Berkeley Lab., 2Fritz Haber Inst. and 3Univ. Erlangen (USA)
17:00 H-2-3 Thin Graphitic Structure Formation on Various Substrates by Gas-Source Molecular Beam Epitaxy using Cracked- Ethanol F. Maeda and H. Hibino, NTT Basic Res. Labs. (Japan)
17:15 H-2-4 Effect of Carrier Gas (Ar and He) on the Crystallographic Quality of Multi-layer Graphene Grown on Si by Photoemission-assisted Plasma CVD H. Sumi1, S. Ogawa1,2, A. Saikubo2,3, E. Ikenaga2,3, M. Nihei2,4 and Y. Takakuwa1,2, 1Tohoku Univ., 2CREST-JST, 3JASRI/SPring-8 and 4Fujitsu Ltd. (Japan)
- 36 - Wednesday, October 7
17:30 H-2-5 Electronic Structure of Carbon Nanowalls using Resonant Soft-X-Ray Emission Spectroscopy W. Takeuchi1, M. Hiramatsu2, Y. Tokuda3, H. Kano4, T. Kinoshita5, Y. Kato5, T. Muro5, S. Kimura5 and M. Hori1, 1Nagoya Univ., 2Aichi Inst. of Tech., 3Meijo Univ., 4NU Eco-Engi. Co. ,Ltd. and 5JASRI/Spring-8 (Japan)
Area 9: Physics and Applications of Novel Functional Materials and Devices K-1: Single Electron and Quantum Transport 13:30-15:45 6F Aoi Chair: M. Tabe (Shizuoka Univ.) Martin Brandt S. (Walter Schottky Institut, Technische Universitat Munchen)
13:30 K-1-1 (Invited) From Single-atom Spectroscopy to Lifetime Enhanced Triplet Transport in MOSFETs J. Verduijn1, G. P. Lansbergen1, G. C. Tettamanzi1, R. Rahman2, S. Biesemans2, N. Colleart3, G. Klimeck2, L. C. L. Hollenberg4 and S. Rogge1, 1Delft Univ. of Tech., 2Purdue Univ., 3IMEC and 4Univ. of Melbourne (Netherlands)
14:00 K-1-2 Single-Electron Transport through Discrete Dopants D. Moraru1, M. Anwar1, M. Ligowski1,2, S. Miki1, R. Nakamura1, T. Mizuno1, R. Jablonski2 and M. Tabe1, 1Shizuoka Univ. and 2Warsaw Univ. of Tech. (Japan)
14:15 K-1-3 Tunnel Spectroscopy of Electron Subbands in Thin SOI MOSFETs J. Noborisaka, K. Nishiguchi, H. Kageshima, Y. Ono and A. Fujiwara, NTT Corp. (Japan)
14:30 K-1-4 Si SET-based Flexible Multi-valued Half Adder Logic Cell S. J. Kim1, E. S. Park1, S. J. Shin1, J. B. Choi1 and
- 37 - Wednesday, October 7
Y. S. Yu2, 1Chungbuk National Univ. and 2Hankyong National Univ (Korea)
14:45 K-1-5 Dual-Gate Single-Electron Transistors (DG-SETs) with Silicon Nano-Wire Channel and Surrounding Side Gates D. S. Lee, K. C. Kang, J. E. Lee, H. S. Yang, J. H. Lee and B. G. Park, Seoul National Univ. (Korea)
15:00 K-1-6 Dislocation-Based Si-Nanodevices M. Reiche1, M. Kittler2, D. Buca3, A. Hähnel1, Q. T. Zhao3, S. Mantl3 and U. Gösele1, 1Max-Planck- Institut für Mikrostrukturphysik, 2IHP Frankfurt and 3Forschungszentrum Jülich (Germany)
15:15 K-1-7 Slow and Fast Electron Channels in a Coherent Quantum Dot Mixer D. G. Austing1,2, C. Payette1,2, G. Yu1, J. Gupta1, G. Aers1, S. Nair3, S. Amaha4 and S. Tarucha4,5, 1National Res. Council, 2McGill Univ., 3Univ. of Toronto, 4JST and 5Univ. of Tokyo (Canada)
15:30 K-1-8 Series Coupled Vertical Triple Quantum Dot Structures S. Amaha1, T. Hatano1, K. Ono2, Y. Tokura1,3, S. Tarucha1,4, J. Gupta5 and D. G. Austing5, 1ICORP-JST, 2RIKEN, 3NTT Corp., 4Univ. of Tokyo and 5National Res. Council of Canada (Japan) 15:45-16:00 Break
Area 9: Physics and Applications of Novel Functional Materials and Devices K-2: Thinfilm Transistor and Memory 16:00-17:45 6F Aoi Chair: Y. Uraoka (NAIST) P. W. Li (National Central Univ.)
16:00 K-2-1 New Tunneling Model with Dependency of Temperature
- 38 - Wednesday, October 7
Measured in Si Nano-Dot Floating Gate MOS Capacitor M. Muraguchi1, Y. Sakurai2, Y. Takada2, Y. Shigeta4, M. Ikeda3, K. Makihara3, S. Miyazaki3, S. Nomura2, K. Shiraishi2 and T. Endoh1, 1Tohoku Univ., 2Univ. of Tsukuba, 3Hiroshima Univ. and 4Univ. of Hyogo (Japan)
16:15 K-2-2 Light Induced Carrier Transfer in NiSi-Nanodots/Si- Quantum-Dots Hybrid FG in MOS Structures N. Morisawa, M. Ikeda, S. Nakanishi, A. Kawanami, K. Makihara and S. Miyazaki, Hiroshima Univ. (Japan)
16:30 K-2-3 TFT-type Flash Memory with Biomineralized Nanodots on SOI Substrate K. Ohara1, I. Yamashita1 and Y. Uraoka1, 2, 1NAIST and 2CREST (Japan)
16:45 K-2-4 Device Design Schemes and Electrical Characterization of Nonvolatile Memory Thin-Film Transistors with the Gate Structure of Al/P(VDF-TrFE)/Al2O3/ZnO S. M. Yoon, S. H. Yang, S. H. Ko Park, S. W. Jung, C. W. Byun, D. H. Cho, S. Y. Kang, C. S. Hwang and B. G. Yu, ETRI (Korea)
17:00 K-2-5 I-V Measurement of Pr0.7Ca0.3MnO3 during TEM Observation T. Fujii, H. Kaji, H. Kondou, K. Hamada, M. Arita and Y. Takahashi, Hokkaido Univ. (Japan)
17:15 K-2-6 Resistance switching memory using Si/CaF2/CdF2 quantum-well structures M. Watanabe, R. Hirasawa and Y. Nakashouji, Tokyo Tech (Japan)
17:30 K-2-7 Self-aligned Metal Double-gate P-channel Low- temperature Poly-Si TFTs Fabricated by DPSS CW Green
- 39 - Wednesday, October 7
Laser Lateral Crystallization T. Sato1, K. Hirose2, K. Kitahara2 and A. Hara1, 1Tohoku Gakuin Univ. and 2Shimane Univ. (Japan)
Area 10: Organic Materials Science, Device Physics, and Applications F-1: Organic Photonic Photovoltaic Device & Memory 13:30-15:45 4F Hirose
13:30 F-1-1 (Invited) Efficient Organic p-i-n Solar Cells Having Very Thick Codeposited i-layer using Seven-nine Purified Fullerene M. Hiramoto, IMS (Japan)
14:00 F-1-2 Efficiency Improvement of Organic Solar Cells by Hot- Pressing C. F. Shih, K. T. Hung, J. W. Wu, C. Y. Hsiao and W. M. Li, National Cheng Kung Univ. (Taiwan)
14:15 F-1-3 Fabrication and Photocurrent Generation of Composite Film of C60 Fullerene-Ethylenediamine Adduct and a Polythiophene T. Akiyama, S. Matsumura, H. Seo, K. Matsuoka and S. Yamada, Kyushu Univ. (Japan)
14:30 F-1-4 Accurate Derivation of All Parameters of the Single Diode Model from a Single Current-voltage Characteristic of a Solar Cell using an Extensively Valid and Stable Iterative Calculation Method M. M. Rahman, R. Kojima, K. Ishibashi, Y. Kimura and M. Niwano, Tohoku Univ. (Japan)
14:45 F-1-5 Single Donor-Acceptor Heterojunction Organic
- 40 - Wednesday, October 7
Photovoltaic Cell with an AgO-Based Anode C. S. Ho1, W. C. Hsu1, C. S. Lee2, K. H. Hsiao1 and W. H. Lai1, 1National Cheng Kung Univ. and 2Feng Chia Univ. (Taiwan)
15:00 F-1-6 Development of FET Type Photorewritable Memory using Photochromic Interface Layer M. Yoshida, K. Suemori, S. Uemura, S. Hoshino, N. Takada, T. Kodzasa and T. Kamata, AIST (Japan)
15:15 F-1-7 The Effects of an Electric-field Application on Properties of P(VDF-TeFE) Thin Film J. H. Jeong, H. Aoki, C. Kimura and T. Sugino, Osaka Univ.(Japan)
15:30 F-1-8 Influence of Substitution Group of the Side Chain of Polypeptide on the Morphology and its Hysteresis Property as a Ferroelectric Memory Device T. Inomata1, N. Kobayashi1, S. Uemura2 and T. Kamata2, 1Chiba Univ. and 2AIST (Japan) 15:45-16:00 Break
Area 10: Organic Materials Science, Device Physics, and Applications F-2: Organic Transistor 16:00-18:00 4F Hirose
16:00 F-2-1 (Invited) Electrical and environmental stability of organic transistors A. Benor1, J. E. Northrup2, A. Hoppe1, V. Wagner1 and D. Knipp1, 1Jacobs Univ. and 2Electronic Materials and Devices Lab. (USA)
16:30 F-2-2 Effect of Carrier Trap on the Electron Transport
- 41 - Wednesday, October 7 in Pentacene FET Observed by the Time-resolved Microscopic SHG Measurement T. Manaka, F. Liu, M. Nakao, W. Martin and M. Iwamoto, Tokyo Tech (Japan)
16:45 F-2-3 Field-Induced Electron Spin Resonance Spectroscopy for Density of Trap States in Organic Transistors H. Matsui1,2, A. S. Mishchenko3,4 and T. Hasegawa1, 1AIST, 2Univ. of Tokyo, 3RIKEN and 4RRC Kurchatov Inst. (Japan)
17:00 F-2-4 Observation of Electric Field in Tetracene Field-Effect Transistor using Optical Second Harmonic Generation Y. Ohshima, H. Satou, H. Kohn, T. Manaka and M. Iwamoto, Tokyo Tech (Japan)
17:15 F-2-5 Enhancing Mobility in Pentacene TFTs using the Film deposition in H2 on Octadecyltrichlorosilane (OTS) Treated SiO2 T. Yokoyama, C. B. Park, K. Nagashio, K. Kita and A. Toriumi, Univ. of Tokyo (Japan)
17:30 F-2-6 Organic Thin Film Transistors with Tailored Liquid Sources of HfO2 as High-κ Insulator R. Nishizawa1, S. Naka1, H. Okada1, K. Suzaki2 and K. Kato2, 1Univ. of Toyama and 2AIST (Japan)
17:45 F-2-7 Interface Charging Propagation Model for Carrier Migration in OFET M. Weis, D. Taguchi, J. Lin, T. Manaka and M. Iwamoto, Tokyo Tech (Japan)
Banquet/Paper Award and Young Researcher Award 19:30-21:30 2F Heisei
- 42 - Thursday, October 8
Short Presentation Area 1: P-1 8:45-10:09 Hirose
Area 2: P-2 8:45-9:30 Kaede Chair: Y. Hayashi (NEC Electronics Corp.) K. Ito (Kyoto Univ.)
Area 3: P-3 8:45-9:54 Heisei
Area 4: P-4 8:45-9:27 Sakura Chair: M. Moniwa (Renesas Tech. Corp.) T. Eshita (Fujitsu Microelectronics Ltd.)
Area 5: P-5 9:35-10:11 Sakura Chair: T. Komuro (Kanagawa Inst. of Tech.) S. Ishizuka (Toshiba Corp.)
Area 6: P-6 8:45-9:39 Hagi Chair: T. Hashizume (Hokkaido Univ.) M. Kuzuhara (Univ. of Fukui)
Area 7: P-7 8:45-9:48 Kiri Chair: M. Sugawara (Fujitsu Labs. Ltd.) J. Fujikata (NEC Corp.)
- 43 - Thursday, October 8
Area 8: P-8 9:40-10:22 Kaede Chair: A. Yamada (Tokyo Tech) H. Hibino (NTT Basic Res. Labs.)
Area 9: P-9 8:45-9:39 Aoi Chair: T. Fujisawa (Tokyo Tech) K. Ono (RIKEN)
Area 10: P-10 8:45-10:00 Hirose
Area 11: P-11 9:45-10:21 Aoi Chair: K. Ajito (NTT Corp.) I. Yamashita (NAIST)
Area 12: P-12 10:00-10:24 Heisei
Area 13: P-13 9:45-10:27 Hagi Chair: J. Motohisa (Hokkaido Univ.) S. Sato (Fujitsu Labs. Ltd.)
Area 14: P-14 9:55-10:28 Kiri Chair: M. Ishiko (Toyota Central R&D Labs., Inc.) T. Ujihara (Nagoya Univ.)
- 44 - Thursday, October 8
POSTER SESSION (10:30-12:00, 2F Heisei
P1 Advanced Gate Stack/Si Processing Science (27 Papers)
P-1-1 Formation of Pr Oxide Films by Atomic Layer Deposition using Pr(EtCp)3 Precursor H. Kondo, H. Matsui, K. Furuta, M. Sakashita and S. Zaima, Nagoya Univ. (Japan)
P-1-2 Advanced High-k Materials and Electrical Analysis for Memories: the Role of SiO2-high-k Dielectric Intermixing L. Morassi1, L. Larcher1, L. Pantisano2, A. Padovani1, R. Degreave2, M. B. Zahid2 and B. J. O'Sullivan2, 1Univ. di Modena e Reggio Emilia and 2IMEC (Italy)
P-1-3 Crystalline Structures and Electrical Properties of High Nitrogen-content Hf-Si-N Films K. Miyamoto, H. Kondo and S. Zaima, Nagoya Univ. (Japan)
P-1-4 Study of La-doped GeO2 Films from Defect Annihilation Viewpoint T. Tabata1,2, K. Kita1,2 and A. Toriumi1,2, 1Univ. of Tokyo and 2CREST-JST (Japan)
P-1-5 Characterization and Improvement of Charge Trapping in Gadolinium Incorporated Hf-based high-k/Metal gated n-MOSFETs C. W. Chen1, H. C. Lai1, Y. L. Yeh1, W. K. Yeh2, S. H. Shu3, C. T. Lin3, C. H. Hsu3, L. W. Cheng3 and M. Ma3, 1Ming Hsin Univ. of Sci and Tech.,2National Univ. of Kaohsiung and 3UMC (Taiwan)
- 45 - Thursday, October 8
P-1-7 Electronic Band Structures of Zirconium and Hafnium Oxides T. Hamada1,3 and T. Ohno2, 3, 1Hitachi, Ltd., 2Inst. of Materials Res. and 3Univ. of Tokyo (Japan)
P-1-8 Threshold Voltage (Vth) Tunability of pMOSFETs with Ternary HfxMoyNz Metal Gate and Gd2O3 High-k Gate Dielectric H. K. Peng, C. S. Lai and J. C. Wang, Chang Gung Univ. (Taiwan)
P-1-9 High Performance ZnO Thin-Film Transistors using High-κ TiHfO Gate Dielectrics N. C. Su1, C. C. Huang1, Y. H. Chen1, C. K. Chiang1, H. Y. Huang1, C. H. Wu2, A. Chin3 and S. J. Wang1, 1National Cheng Kung Univ., 2National Chung Hua Univ. and 3National Chiao Tung Univ. (Taiwan)
P-1-10 Superiority of ALD TiN with TDMAT Precursor for Metal-Gate MOSFET T. Hayashida1, K. Endo2, Y. X. Liu2, T. Matsukawa2, S. Ouchi2, K. Sakamoto2, J. Tsukada2, Y. Ishikawa2, H. Yamauchi2, A. Ogura1 and M. Masahara1,2, 1Meiji Univ. and 2AIST (Japan)
P-1-11 Hole Tunnel Currents in TiN/HfSiOxN/SiO2/p-Si(100) MOS Capacitors Khairurrijal1, F. A. Noor1, M. Abdullah1, Sukirno1, A. Ohta2 and S. Miyazaki2, 1Institut Teknologi Bandung and 2Hiroshima Univ. (Indonesia)
P-1-12 Nanoscale Characterization of HfO2/SiOx Gate Stack Degradation by Scanning Tunneling Microscopy K. S. Yew1, Y. C. Ong1, D. S. Ang1, K. L. Pey1, G. Bersuker2, P. S. Lysaght2 and D. Heh2, 1Nanyang Tech.
- 46 - Thursday, October 8
Univ. and 2SEMATECH (Singapore)
P-1-13 Voltage Coefficient of Capacitance Modulation for Sm2O3/ SiO2 MIM Capacitors J. J. Yang1, J. D. Chen1, R. Wise2, P. Steinmann2, M. B. Yu3, Y. C. Yeo1 and C. Zhu1, 1National Univ. of Singapore, 2Texas Instruments Inc. and 3Inst. of Microelectronics (Singapore)
P-1-14 Properties of LaAlO Film after Waterless Process using Organic Solvent containing Anhydrous HF M. Honjo, N. Komatsu, T. Masuzumi, H. Aoki, D. Watanabe, C. Kimura and T. Sugino, Osaka Univ. (Japan)
P-1-15 Atomistic Modeling of GeO2/Ge and SiO2/Si Interface Structures T. Onda, H. Yamamoto, R. Tosaka, I. Ohdomari and T. Watanabe, Waseda Univ. (Japan)
P-1-16 Highly Reliable Silicon Dioxide Formation Technique with Plasma and Thermal oxidation Y. Kabe1, J. Kitagawa1, Y. Hirota1, S. Sato2, Z. Lu2, M. Sometani2, R. Hasunuma2 and K. Yamabe2, 1Tokyo Electron AT Ltd. and 2Univ. of Tsukuba (Japan)
P-1-17 Enhancement of Carbon Diffusion Caused by Thermal Oxidation on Si1-xCx Alloy Layer / Si(001) Surafces H. Hozumi1, S. Ogawa1, A. Yoshigoe2, S. Ishidzuka3, J. Harries2, Y. Teraoka2 and Y. Takakuwa1, 1Tohoku Univ., 2Japan Atomic Energy Agency and 3Akita National College of Tech. (Japan)
P-1-18 Infrared Semiconductor Laser Annealing Used for Activation of Silicon Implanted with Boron and
- 47 - Thursday, October 8
Phosphorus Atoms N. Sano1, K. Ukawa2, T. Sameshima2, M. Naito3 and N. Hamamoto3, 1Hightec Systems Corp., 2Tokyo Univ. of Agri. And Tech. and 3Nissin Ion Equipment Co., Ltd. (Japan)
P-1-19 Impact of Carbon Ion Implantation on the Thermal Stability of Nickel Silicide and Shallow Junction C. M. Lee and B. Y. Tsui, National Chiao Tung Univ. (Taiwan)
P-1-20 Ion-Implanted Boron Activation in a Preamorphized Si Layer by Microwave Annealing K. Hara, Y. Tanushi, S. Kuroki, K. Kotani and T. Ito, Tohoku Univ. (Japan)
P-1-21 Low Contact Resistance with Low Silicide/p+-Silicon Schottky Barrier for High Performance p-channel MOSFETs H. Tanaka, T. Isogai, T. Goto, A. Teramoto, S. Sugawa and T. Ohmi, Tohoku Univ. (Japan)
P-1-22 Mobility Behavior in Ge1-xSnx Layers Grown on SOI Substrates N. Tsutsui1, Y. Shimura1, O. Nakatsuka1, A. Sakai2 and S. Zaima1, 1Nagoya Univ. and 2Osaka Univ. (Japan)
P-1-23 Evaluation of anisotropic biaxial stress using an immersion lens by Raman analysis based on the polarization rules D. Kosemura1,3, M. Takei1, K. Nagata1, H. Akamatsu1, R. Shimidzu2 and A. Ogura1, 1Meiji Univ., 2PHOTON Design Corp. and 3JSPS (Japan)
P-1-24 Comprehensive Modeling of Threshold Voltage Variability Induced by Plasma Damage in Advanced MOSFETs
- 48 - Thursday, October 8
K. Eriguchi, Y. Nakakubo, A. Matsuda, M. Kamei, Y. Takao and K. Ono, Kyoto Univ. (Japan)
P-1-25 Mechanism for Generation of Molecular-Level Line-Edge Roughness of ArF photoresist during Plasma Etching Processes K. Koyama1, B. Jinnai1, S. Maeda2, K. Kato2, A. Yasuda2, H. Momose2 and S. Samukawa1, 1Tohoku Univ. and 2Mitsubishi Rayon Co., Ltd. (Japan)
P-1-26 Mechanism of Mask Distortion during Resist Trimming N. Kofuji1 and H. Miura2, 1Hitachi, Ltd. and 2Tohoku Univ. (Japan)
P-1-27 Effect of UV irradiation in plasma on Pohotoresist LER A. Yabata, M. Takahashi and N. Kuriyama, OKI Semiconductor Miyagi Co., Ltd. (Japan)
P-1-28 Assessment of Ion-Bombardment Damage in Plasma- Exposed Si by Interface Layer Thickness and Charge- Trapping Defects A. Matsuda, Y. Nakakubo, M. Kamei, Y. Takao, K. Eriguchi and K. Ono, Kyoto Univ. (Japan)
P2 Characterization and Materials Engineering for Interconnect Integration (13 Papers)
P-2-1 Self-Formation of Ti-Based Barrier Layers in Cu(Ti)/ Porous-Low-k Samples K. Ito1, K. Kohama1, T. Tanaka1, K. Mori2, K. Maekawa2, Y. Shirai1 and M. Murakami3, 1Kyoto Univ., 2Renesas Tech. Corp. and 3The Ritsumeikan Trust (Japan)
- 49 - Thursday, October 8
P-2-2 Improvement of Cu seedless Ru barrier by insertion of an amorphous WCoCN interlayer J. B. Yeh, D. C. Perng and K. C. Hsu, National Cheng Kung Univ. (Taiwan)
P-2-3 Suppression of Fluorine Diffusion into Low-k Material (Methyl-BCN) using Low Temperature Etching M. Hara, T. Masuzumi, L. Zhiming, C. Kimura, H. Aoki and T. Sugino, Osaka Univ. (Japan)
P-2-4 Novel Particle Reduction System in Chemical-Vapor- Deposition Process of Interlayer Dielectrics M. Sato, H. Ohtake and S. Samukawa, Tohoku Univ. (Japan)
P-2-5 Prediction of UV/VUV Irradiation Damage of Interlayer Dielectrics in Plasma Etching using on-wafer Monitoring Technique B. Jinnai1, S. Fukuda1, H. Ohtake1, S. Yasuhara2, E. A. Hudson3 and S. Samukawa1, 1Tohoku Univ., 2Japan Advanced Chemicals and 3Lam Res. Corp. (Japan)
P-2-6 Low-Temperature Silicon Oxide Offset Spacer using Plasma Enhanced Atomic Layer Deposition for High-k/ Metal Gate Transistor T. Murata, Y. Miyagawa, Y. Nishida, Y. Yamamoto, T. Yamashita, M. Matsuura and K. Asai, Renesas Tech. Corp. (Japan)
P-2-7 Impact of film structures on damage to low-k SiOCH film during plasma exposure S. Yasuhara1, T. Sasaki1, K. Tajima2, H. Yano2, S. Kadomura2, M. Yoshimaru2, N. Matsunaga2 and S. Samukawa1, 1Tohoku Univ. and 2STARC (Japan)
- 50 - Thursday, October 8
P-2-8 Raman Spectroscopic Metrology for Stress measurement in Semiconductor Device Development and Process N. Naka1, S. Kashiwagi1, K. Ohtsuki1, J. H. Kim2, C. H. Lee2, S. T. Ahn2, K. H. Bae2, H. W. Yoo2 and C. H. Kim2, 1HORIBA, Ltd. and 2Hynix Semiconductor Inc. (Japan)
P-2-9 Uniaxial Tensile Testing System for Quantitative Stress Analysis in Silicon Oxide Thin Films by Cathodoluminescence Spectroscopy N. Goami1, N. Yamashita1, N. Araki1, S. Kakinuma2, K. Nishikata2, N. Naka2, K. Matsumoto2, T. Namazu1 and S. Inoue1, 1Univ. of Hyogo and 2HORIBA Ltd. (Japan)
P-2-10 Liquid Phase Bonding using Au Compliant Bumps for Fine-Pitch Solder Bump Interconnection L. J. Qiu, N. Watanabe and T. Asano, Kyushu Univ. (Japan)
P-2-11 Room-Temperature Large-Number Inter-Chip Connections using Mechanical Caulking Effect of Compliant Bump N. Watanabe and T. Asano, Kyushu Univ. (Japan)
P-2-12 Evaluation of Thin LSI Wafers by Capacitance-Time (C-t) Measurement for the Process Characterization of Three- Dimensional (3D) Integration J.C. Bea, M. Murugesan, Y. Ohara, A. Noriki, H. Kino, K. W. Lee, T. Fukushima, T. Tanaka and M. Koyanagi, Tohoku Univ. (Japan)
P-2-15 Influence of Magnetic Fieled on Permeability of Electroplating Permalloy for Micro Energy Harvesting Device E. Kubo, N. Ooi, H. Aoki, D. Watanabe, J. H. Jeong, C. Kimura and T. Sugino, Osaka Univ. (Japan)
- 51 - Thursday, October 8
P3 CMOS Devices /Device Physics (21 Papers)
P-3-1 Suppression of Vth Variability for n-MOSFET in Dual Oxide Formation Process Y. Kamata1, K. Shibusawa1, K. Abe2, S. Sugawa2, A. Teramoto2 and T. Ohmi2, 1OKI Semiconductor Miyagi Co., Ltd. and 2Tohoku Univ. (Japan)
P-3-2 Rigorous Design of 20 nm Level SOI 4-T FinFETs for Low Standby Power by Extracting Parameters from the Pre-stage 50 nm Technology Node Devices S. Cho1, S. W. Kim1, K. Endo2, S. O'uchi2, T. Matsukawa2, Y. Son1, J. P. Kim1, K. Sakamoto2, Y. Liu2, B. G. Park1 and M. Masahara2, 1Seoul National Univ. and 2AIST (Korea)
P-3-3 Quantitative Analysis of Hump Effects of Multi-Gate MOSFETs for Low-Power Electronics W. Lee and W. Y. Choi, Sogang Univ. (Korea)
P-3-4 Investigation of Novel Si/SiGe Hetero Structures and Gate Induced Source Tunneling for Improvement of P-channel Tunnel FETs H. G. Virani, R. B. Rao and A. Kottantharayil, Indian Inst. of Tech. Bombay (India)
P-3-5 Mechanical stress evaluation of Si MOSFET structure using UV Raman spectroscopy measurements and calibrated TCAD simulation A. Satoh1, T. Tada2, V. Poborchii2, T. Kanayama2 and H. Arimoto1, 1Fujitsu Microelectronics Ltd. and 2AIST (Japan)
- 52 - Thursday, October 8
P-3-6 Recovery of CHC- and NBTI-induced Degradation on MOSFETs by using Different Annealing Treatments C. H. Tu1, S. Y. Chen1, S. H. Chien1, H. S. Huang1, Z. W. Jhou2, S. Chou2 and J. Ko2, 1National Taipei Univ. of Tech. and 2UMC (Taiwan)
P-3-7 Ultra thin Ni-silicides with low contact resistance on SOI and strained-SOI L. Knoll1, Q. T. Zhao1, S. Habicht1, C. Urban1, B. Ghyselen2 and S. Mantl1, 1Forschungszentrum Juelich and 2SOITEC (Germany)
P-3-9 Experimental Analysis of Anisotropic Impact Ionization in (110) Surface pMOSFETs T. K. Kang1, C. M. Kuo1, C. L. Huang1, H. L. Liu1, C. Y. Wu1, S. L. Wu1, Y. T. Huang2 and S. J. Chang2, 1Cheng Shiu Univ. and 2National Cheng Kung Univ (Taiwan)
P-3-10 Defect-Induced Deep Levels in SiGe-on-Insulator Substrate Fabricated using Ge Condensation Technique H. Yang, D. Wang and H. Nakashima, Kyushu Univ. (Japan)
P-3-11 New Observations of FN Stress Induced Performance Degradation of RF MOSFETs B. Xiao, L. Zhang, R. Huang, D. Wu, L. Zhang, F. Song and Y. Y. Wang, Peking Univ. (China)
P-3-12 Effects of Negative Bias Temperature Stress-induced Degradation and Mismatch on pMOSFETs in 90 nm Technology C. H. Tu1, S. Y. Chen1, A. E. Chuang1, H. S. Huang1, Z. W. Jhou2, S. Chou2 and J. Ko2, 1National Taipei Univ. of Tech. and 2UMC. (Taiwan)
- 53 - Thursday, October 8
P-3-13 Subcircuit Compact Model for Dopant-Segregated Schottky Silicon-Nanowire MOSFETs G. Zhu1, X. Zhou1, Y. K. Chin1, K. L. Pey1, G. H. See2, S. Lin1, J. Zhang1 and Z. Chen1, 1Nanyang Technological Univ. and 2Chartered Semiconductor Manufacturing Ltd. (Singapore)
P-3-14 Intrinsic-Parameter-Fluctuated Power-Delay Characteristics in 16-nm-Metal-Gate CMOS Devices and Circuits M. H. Han1, C. H. Hwang1 and Y. Li1,2, 1National Chiao Tung Univ. and 2National Nano Device Labs. (Taiwan)
P-3-16 High-Temperature Dependent Data Extraction and Modeling of Effective Channel Mobility in MOSFETs using Measured S-Parameters B. Ko, D. Jung and S. Lee, Hankuk Univ. of Foreign Studies (Korea)
P-3-17 The Structure and Power-level Dependences of CMOS RF Power Cell Degradation by Hot-carrier Stress with Load Pull System C. H. Liu1, Y. K. Su1, R. L. Wang2, C. H. Tu3 and Y. Z. Juang3, 1National Cheng Kung Univ. ,2National Kaohsiung Normal Univ. and 3CIC (Taiwan)
P-3-18 Anomalous Hot-Carrier-Induced Saturation Drain Current Degradation in DEMOS Transistors J. F. Chen1, K. W. Lin1, S. Y. Chen1, K. M. Wu2, J. R. Shih2 and K. Wu2, 1National Cheng Kung Univ. and 2TSMC (Taiwan)
P-3-19 Subthreshold SRAM with Enhanced Stability using Ultra- Thin-Body and BOX SOI V. P. H. Hu, M. L. Fan, P. Su and C. T. Chuang, National
- 54 - Thursday, October 8
Chiao Tung Univ. (Taiwan)
P-3-20 Novel Dynamic Threshold Voltage Contact Etching Stop Layer (DT-CESL) Strained HfO2 nMOSFET for Very Low Voltage Operation (0.7V) W. C. Wu1, T. S. Chao1, K. T. Wang1, S. C. Lee1, T. H. Chiu1, T. Y. Lu1, C. S. Lai2, J. C. Wang2, M. W. Ma1, K. H. Kao1 and W. C. Lo1, 1National Chiao Tung Univ. and 2Chang Gung Univ. (Taiwan)
P-3-21 Low Frequency Noise (1/f ) Improvements on CMOS Transistors with a Single n+ Doped Poly Si-SiGe Gate Stack H. G. Jiménez1, L. T. Manera1,2, R. Wada2, J. A. Diniz1,2, I. Doi1,2, P. J. Tatsch1,2, H. E. Figueroa1,2 and J. W. Swart1,2, 1CCS-UNICAMP and 2Univ. of Campinas (Brazil)
P-3-22 Bi-Directional SCR Device with Dual-Triggered Mechanism for ESD Protection in Extended-Voltage- Swing I/O Application Z. W. Jiang1, S. H. Chen1 and M. D. Ker2, 1Indus. Tech. Res. Inst. and 2National Chiao Tung Univ. (Taiwan)
P-3-23 Trap Profile and Bias Temperature Instability of ALD- HfSiON Gate Stacks in Advanced MOSFETs C. K. Chiang1, Y. H. Chen1, N. C. Su1, S. J. Wang1, C. C. Huang1, H. Y. Huang1 and C. H. Wu2, 1National Cheng Kung Univ. and 2Chung Hua Univ. (Taiwan)
P4 Advanced Memory Technology (12 Papers)
P-4-1 HAX-PES Study of SiN Film for Charge Storage Layer in High Performance SONOS Type Flash Memory Cell
- 55 - Thursday, October 8
D. Kosemura1,4, M. Takei1, K. Nagata1, H. Akamatsu1, M. Hattori1, D. Katayama1, T. Nishita2, T. Nakanishi2, Y. Hirota2, M. Machida3, J. Y. Son3, T. Koganezawa3, I. Hirosawa3 and A. Ogura1, 1Meiji Univ., 2Tokyo Electron td., 3JASRI and 4JSPS (Japan)
P-4-2 Electrical Characteristics of Engineered ZrO2/SiO2 Tunnel Barrier with a High-k HfO2 Trapping Layer for Non- Volatile Memory H. W. You1, G. H. Park1, J. W. Jung2 and W. J. Cho1, 1Kwangwoon Univ. and 2Sejong Univ. (Korea)
P-4-3 Explanation of anomalous erase behaviour and the associated device instability in TANOS Flash using a new trap characterization technique R. Degraeve1, M. Zahid1, G. Van den bosch1, P. Blomme1, L. Breuil1, B. Kaczer1, M. Mercuri1, A. Rothschild1, A. Cacciato1, M. Jurczak1, G. Groeseneken2 and J. Van Houdt1, 1IMEC and 2Catholic Univ. Leuven (Belgium)
P-4-4 Precision Programming Power Control in Embedded P-channel SONOS Flash using Transient-IV Method Y. J. Chen, Y. J. Ting, C. J. Liu, W. T. Sun and R. Shen, eMemory Tech. Inc. (Taiwan)
P-4-6 Source-Side Injection Programmed P-channel Self- Aligned-Nitride OTP Cell for 90nm Logic Nonvolatile Memory Applications H. OuYang, Y. J. Chen, C. E. Huang and C. J. Lin, National Tsing Hua Univ. (Taiwan)
P-4-7 Optimized Silicon Nitride MONOS Memory for Superior Endurance of 10M Cycles K. Yamabe, S. Yoshida, Y. Taniguchi and S. Kamohara, Renesas Tech. Corp. (Japan)
- 56 - Thursday, October 8
P-4-8 Programming Current Enhancement by Ge Incorporation into Tunnel Oxide Film T. Ito, Y. Mitani, Y. Nakasaki, M. Koike, T. Konno, H. Matsuba, W. Kaneko, T. Kai and Y. Ozawa, Toshiba Corp. (Japan)
P-4-9 Improved Switching Uniformity of a Carbon-based ReRAM device by Controlling Size of Conducting Filament J. Park, H. Choi, M. Jo, J. Lee, T. W. Kim, J. Yoon, D. J. Seong, W. Lee, M. Chang, J. Shin, T. Lee and H. Hwang, Gwangju Inst. of Sci. and Tech. (Korea)
P-4-10 Formation free resistive switching memory device using Ge0.4Se0.6 solid electrolyte S. Z. Rahaman1, S. Maikap1, C. H. Lin2, T. Y. Wu2, Y. S. Chen2, P. J. Tzeng2, F. Chen2, M. J. Kao2 and M. J. Tsai2, 1Chang Gung Univ. and 2Industrial Tech. Res. Inst. (Taiwan)
P-4-11 Improved resistive switching of HfOX/TiN stack with a reactive metal layer and annealing P. S. Chen1, H. Y. Lee2,3, Y. S. Chen2, F. Chen2 and M. J. Tsai2, 1MingShin Univ. of Sci. and Tech., 2Industrial Tech. Res. Inst. and 3National Tsing Hua Univ. (Taiwan)
P-4-12 A Novel Capacitor-less 1T-DRAM on Partially Depleted SOI pMOSFET based on Direct-tunneling Current in the Partial n+ Poly Gate G. Guegan1, P. Touret1, G. Molas1, C. Raynaud1 and J. Pretet2, 1CEA - LETI/MINATEC and 2STMicroelectronics (France)
P-4-14 Ferroelectric P(VDF-TeFE) Gate FET Memory T. Watanabe, H. Miyashita, T. Kanashima and
- 57 - Thursday, October 8
M. Okuyama, Osaka Univ. (Japan)
P5 Advanced Circuits and Systems (12 Papers)
P-5-1 Highly-Accurate Ladder Model of Inductors on a Glass Substrate K. Haruyama, K. Kotani and T. Ito, Tohoku Univ. (Japan)
P-5-2 A Study of Packaging-induced Stress Distribution for Small-scale Silicon Chips N. Ueda, E. Nishiyama and H. Watanabe, Ricoh Corp. (Japan)
P-5-3 A Binary-Tree Hierarchical Multiple-Chip Architecture for Real-Time Large-Scale Learning Processor Systems Y. Ma and T. Shibata, Univ. of Tokyo (Japan)
P-5-4 31.25 ps Differential Equivalent Time Sampling Circuit using 65nm CMOS Technology A. Toya, N. Sasaki, S. Kubota and T. Kikkawa, Hiroshima Univ. (Japan)
P-5-5 4 ch × 10 Gb/s Parallel Phase-synchronization Architecture and a Phase-adjuster Circuit using a Common Clock Signal H. Katsurai, J. Terada and Y. Ohtomo, NTT Microsystem Integration Labs. (Japan)
P-5-6 An Optimal Design Method for CMOS Even-Stage Ring Oscillators Containing Plural Latches Y. Kohara1, Y. Kawakami1, Y. Uchida1, H. Koike2 and K. Nakamura1, 1Kyushu Inst. of Tech. and 2Fukuoka
- 58 - Thursday, October 8
Industry, Sci. and Tech. Foundation (Japan)
P-5-7 Design of an 8-nsec-search 72-bit-word Content- Addressable Memory using Phase-Change Devices, S. Hanzawa and T. Hanyu, Tohoku Univ. (Japan)
P-5-8 High-Speed Face Detection in Images with Massive- Parallel Bit-Serial SIMD Processor using Haar-Like Features Y. Imai, T. Kumaki, T. Koide and H. J. Mattausch, Hiroshima Univ. (Japan)
P-5-9 RF Signal Generator based on Time-to-Analog Converter in 0.18μm CMOS K. Nakano, S. Amakawa, N. Ishihara and K, Masu, Tokyo Tech (Japan)
P-5-10 Symmetrical Planar IPD Balun for WLAN and Wimax Application S. M. Wu, W. Y. Lin, S. W. Guan and Y. H. Chen, National Univ. of Kaohsiung (Taiwan)
P-5-11 A 3-D Binocular Range Sensor LSI with an Enhanced Correlation Signal M. Kawano1, N. Kawaguchi2, T. Yoshida2 and Y. Arima2, 1Fukuoka Industry, Sci. and Tech. Foundation and 2Kyushu Inst. of Tech. (Japan)
P-5-12 3-D Binocular Range Sensor LSI with A High-Speed Data Output Method N. Kawaguchi1, M. Kawano2 and Y. Arima1, 1Kyushu Inst. of Tech. and 2Fukuoka Industry, Sci. and Tech. Foundation (Japan)
- 59 - Thursday, October 8
P6 Compound Semiconductor Circuits, Electron Devices and Device Physics (17 Papers)
P-6-1 A Micromachined Air-Cavity Oscillator for 94 GHz Applications Y. Koh, U. Son, S. Song and K. S. Seo, Seoul National Univ. (Korea)
P-6-2 Fabrication Low-voltage Amorphous Indium Zinc Oxide(a-IZO) Thin Film Transistors using High Dielectric HfO2 as Gate Insulator at Room Tempature W. K. Lin1, C. S. Li2, K. C. Liu2 and S. T. Chang1, 1National Chung Hsing Univ. and 2Chang Gung Univ. (Taiwan)
P-6-3 Self-cleaning Effects on Atomic Layer Deposition (ALD) of Al2O3 on InGaAs with Several Surface Treatments H. D. Trinh1,2, E. Y. Chang1, Y. Y. Wong1, C. Y. Chang1 and C. C. Yu3, 1National Chiao Tung Univ., 2Hanoi National Univ. of Edu. and 3National Applied Res. Labs. (Taiwan)
P-6-4 Enhanced Photovoltaic Effects of InGaN-based Materials for Future Full-Solar-Spectrum Solar Cells C. C. Yang1, J. K. Sheu1, S. J. Tu1, C. K. Tseng1, M. S. Huang1, K. H. Chang1, T. H. Hsueh1, M. L. Lee2, L. C. Peng1 and W. C. Lai1, 1National Cheng Kung Univ. and 2Southern Taiwan Univ. (Taiwan)
P-6-5 Low Leakage AlGaN/GaN HEMTs with a High On/Off Current Ratio Y. S. Lin1, Y. W. Lian1, S. S. H. Hsu1 and T. C. Lee2, 1National Tsing Hua Univ. and 2National Chiao Tung Univ. (Taiwan)
- 60 - Thursday, October 8
P-6-6 High Breakdown GaN Schottky Diodes with Buried P-layer Structure Y. W. Lian, Y. S. Lin and S. S. H. Hsu, National Tsing Hua Univ. (Taiwan)
P-6-7 High Mobility In-Ga-Zn-oxide Thin-film Transistor with Sb2TeOx Gate Insulator Fabricated by Reactive Sputtering W. S. Cheong, S. M. Yoon, S. Yang and C. S. Hwang, ETRI (Korea)
P-6-9 Temperature Dependence of the Resistance of AlGaN/GaN Heterostructures and their Applications as Temperature Sensors A. H. Zahmani1, A. Nishijima1, Y. Morimoto1, H. Wang1,2, J. F. Li2 and A. Sandhu1, 1Tokyo Tech and 2Tsinghua Univ. (Japan)
P-6-10 Stress Analysis in GaN Epilayer after Chemical Mechanical Polishing (CMP) from Sapphire Substrates Y. K. Su1,2, C. C. Kao1, C. L. Lin2 and J. J. Chen1, 1National Cheng Kung Univ. and 2Kun-Shan Univ. (Taiwan)
P-6-11 Investigation of Electrostatic Integrity for Ultra-Thin- Body GeON MOSFET V. P. H. Hu, Y. S. Wu and P. Su, National Chiao Tung Univ. (Taiwan)
P-6-12 The Effect of Distribute Bragg Reflector in Device Temperature of AlGaInP Light-emitting Diode Y. K. Yang1, W. C Lien1, Y. S. Wang2, L. H. Zen1, J. F. Chen1 and N. C. Chen1, 1Chang Gung Univ. and 2National Chiao Tung Univ. (Taiwan)
P-6-13 Improved Characteristics of InAlAs/InGaAs MOS-
- 61 - Thursday, October 8
MHEMTs by using Ozone Water Oxidation Method A. Y. Kao1, C. S. Ho2, W. C. Hsu2, Y. N. Lai2 and C. S. Lee1, 1Feng Chia Univ. and 2National Cheng Kung Univ. (Taiwan)
P-6-14 Width Dependent Electrically Stress Degradation of Bottom Gate Amorphous Indium Gallium Zinc Oxide Thin Film Transistors D. H. Nam, K. I. Chai, S. S. Park, J. G. Park, H. J. Yun, W. H. Choi, H. D. Lee and G. W. Lee, Chungnam National Univ. (Korea)
P-6-15 Transparent AZO-Gated Double δ-Doped AlGaAs/InGaAs HEMTs B. Y. Chou1, C. S. Lee1, W. C. Hsu2, S. Y. Chu2, Y. N. Lai2, C. S. Ho2, Z. L. Tseng2 and M. F. Shih2, 1Feng Chia Univ. and 2National Cheng Kung Univ. (Taiwan)
P-6-16 Effect of Two-Step E-Beam SiO2 Passivation on AlGaN/ GaN HEMT Performance H. L. Yu, H. K. Lin and Y. J. Chan, National Central Univ. (Taiwan)
P-6-17 GZO/GaN Schottky Barrier Ultraviolet Band-pass Photodetector with a Low-temperature-grown GaN Cap Layer K. H. Chang1, J. K. Sheu1, M. L. Lee2, T. H. Hsueh1, C. C. Yang1, K. S. Kang1, J. F. Huang1, L. C. Peng1 and W. C. Lai1, 1National Cheng Kung Univ. and 2Southern Taiwan Univ. (Taiwan)
P-6-18 Effects of Pre-treatment on Passivation of AlGaN/GaN on Silicon HEMTs J. H. Kim1,2, H. G. Choi1, H. J. Song1, C. H. Roh1, J. H. Lee1, J. H. Park2 and C. K. Hahn1, 1Korea Electronics Tech. Inst. and 2Korea Univ. (Korea)
- 62 - Thursday, October 8
P7 Photonic Devices and Device Physics (18 Papers)
P-7-1 Silicon Lateral Avalanche Photodiodes Fabricated by Standard 0.18 μm Complementary Metal-Oxide- Semiconductor Process K. Iiyama, H. Takamatsu and T. Maruyama, Kanazawa Univ. (Japan)
P-7-3 Nitride-based MSM Photodetectors with InN/GaN Multiple Nucleation Layers C. H. Chen, H. J. Chien, K. R Wang, S. Y. Tsai and S. L. Wu, Cheng Shiu Univ. (Taiwan)
P-7-4 Investigation of AlGaN MSM Photodetectors with Low- Temperature AlN Cap and Recess Etched Layers C. H. Chen1, S. J. Chang2, M. H. Wu2, S. Y. Tsai1 and H. J. Chien1, 1Cheng Shiu Univ. and 2National Cheng Kung Univ. (Taiwan)
P-7-5 Photoresponse of Phase Separated Hafnium Silicate in Metal-Insulator-Semiconductor Structure C. F. Shih, C. Y. Hsiao, C. B. Shu, K. T. Hung and W. M. Li, National Cheng Kung Univ. (Taiwan)
P-7-6 Fabrication and Evaluation of an Er2SiO5 Waveguide with a Buried Si Guide Layer for Optical Amplifier in Si Photonics T. Nakajima, K. Honma, T. Kimura and H. Isshiki, Univ. of Electro- Communications (Japan)
P-7-7 Amorphous Polyethylene Terephthalate Optical Channel Waveguide
- 63 - Thursday, October 8
K. Iiyama, Y. Ono, T. Maruyama and T. Yamagishi, Kanazawa Univ. (Japan)
P-7-8 Separate Control of Interband and Intersubband Transition Wavelengths of In0.8Ga0.2As/AlGaAs/AlAs0.56Sb0.44 Coupled Double Quantum Wells by Only Changing Al Composition S. Gozu, T. Mozume, R. Akimoto, K. Akita, G. Cong and H. Ishikawa, AIST (Japan)
P-7-9 Influence of Heterointerface Abruptness on Electrorefractive Effect in InGaAs/InAlAs Five-Layer Asymmetric Coupled Quantum Well (FACQW) Y. Iseri1, T. Arakawa1, K. Tada2 and N. Haneji1, 1Yokohama Nationai Univ. and 2Kanazawa Inst. of Tech. (Japan)
P-7-10 Ridge-Type Semiconductor Lasers with Antiguiding Cladding Layers for Horizontal Transverse Modes H. Takada and T. Numai, Ritsumeikan Univ. (Japan)
P-7-11 Ridge-Type Semiconductor Lasers with Optical Antiguiding Layers for Horizontal Transverse Modes: Dependence on Step Positions N. Shomura and T. Numai, Ritsumeikan Univ. (Japan)
P-7-12 Electrorefractive Effect in Asymmetric Triple Coupled Quantum Well K. Ema1, W. Endo1, T. Arakawa1 and K. Tada2, 1Yokohama Nationai Univ. and 2Kanazawa Inst. of Tech. (Japan)
P-7-13 Indium-doped MgxZn1-xO films for ZnO-based Heterojunction Diodes T. Tsuboi, K. Yamamoto, A. Nakamura and J. Temmyo, Shizuoka Univ. (Japan)
- 64 - Thursday, October 8
P-7-15 Improved Light Output Power of GaN-Based Light Emitting Diodes using Double Photonic Quasi-Crystal Patterned J. K. Huang1, H. W. Huang1,2, C. H. Lin2, K. Y. Lee2, C. C. Yu2, H. C. Kuo1, T. C. Lu1 and S. C. Wang1, 1National Chiao Tung Univ. and 2Luxtaltek Corp. (Taiwan)
P-7-16 III-Nitride Light Emitting Diodes with GaN Micro-Pillars around Mesa and Patterned Substrate L. C. Peng1, W. C. Lai1, M. N. Chang1, C. Y. Yeh1, Y. Y. Yang1, S. C. Shei2, T. H. Hsueh1, K. H. Chang1, C. C. Yang1 and J. K. Sheu1, 1National Cheng Kung Univ. and 2National Univ. of Tainan (Taiwan)
P-7-18 Thermal Characteristics of InGaN/GaN MQW Blue LEDs H. K. Lee and J. S. Yu, Kyung Hee Univ. (Korea)
P-7-19 Emission Intensity and Fabry-Pérot-Type Surface Plasmons in Tri-Layer Ag/SiO2/Ag Plasmonic Thermal Emitter with Different SiO2 Thickness Y. T. Chang, H. H. Chen, J. H. Lee, Y. T. Wu, H. F. Huang and S. C. Lee, National Taiwan Univ. (Taiwan)
P-7-20 The Influence of the Hole Size on the Peak Emission Wavelength of a Plasmonic Thermal Emitter H. H. Chen, Y. W. Jiang, Y. T. Wu, Y. T. Chang, P. E. Chang, H. F. Huang and S. C. Lee, National Taiwan Univ. (Taiwan)
P-7-21 Enhanced Thermal Radiation Observed in Metal- dielectric-metal Thermal Emitter by Surface Plasmon Resonance Y. W. Jiang, D. C. Tzuang, Y. T. Wu, M. W. Tsai and S. C. Lee, National Taiwan Univ. (Taiwan)
- 65 - Thursday, October 8
P8 Advanced Material Synthesis and Crystal Growth Technology (13 Papers)
P-8-2 Fabrication of In0.15Ga0.85 As Nanohole Templates on GaAs (001) for Quantum Dot Molecules P. Boonpeng, W. Jevasuwan, S. Panyakeow and S. Ratanathammaphan, Chulalongkorn Univ. (Thailand)
P-8-3 Hydrophilic Property of titanium oxide film crystallization induced by an oxidation nickel seed Layer T. W. Lin1, B. S. Chiang1, S. Chang2 and D. S. Liu1, 1National Formosa Univ. and 2Far East Univ. (Taiwan)
P-8-4 Raman Spectroscopy, TEM and Bulk-sensitive XPS Study of Multi-layer Graphene Grown on SiO2(350 nm)/Si S. Ogawa1,2, H. Sumi1, A. Saikubo2,3, E. Ikenaga2,3, M. Sato2,4, M. Nihei2,4 and Y. Takakuwa1,2, 1Tohoku Univ., 2CREST-JST, 3JASRI/SPring-8 and 4Fujitsu Ltd. (Japan)
P-8-5 Investigation on direct-growth Of a-GaN on r-sapphire by MOCVD H. C. Hsu, Y. K. Su and S. J. Huang, National Cheng Kung Univ. (Taiwan)
P-8-6 Microwave Dielectric Properties of MgTiO3 by Sintering MgO and TiO2 Nanostructures C. F. Shih, W. M. Li, K. S. Tung, C. Y. Hsiao and K. T. Hung, National Cheng Kung Univ. (Taiwan)
P-8-7 High quality of a-plane (11-20) GaN using a high pressure buffer layer J. H. Choi1, L. W. Jang1, J. W. Ju1, S. M. Hwang2 and
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I. H. Lee1, 1Chonbuk National Univ. and 2Korea Electronics Tech. Inst. (Korea)
P-8-8 Generation Mechanism of Photoemission-assisted Plasma on SiO2(350 nm)/Si Substrate T. Kaga1, S. Ogawa1,2, H. Hozumi1, H. Sumi1, M. Sato2,3, M. Nihei2,3 and Y. Takakuwa1,2, 1Tohoku Univ., 2CREST-JST and 3Fujitsu Ltd. (Japan)
P-8-9 Annealing a Ge layer embedded between the SiO2 and patterned Si substrate into crystalline C. W. Chiu, H. J. Huang, T. W. Liao, J. H. Lin and C. H. Kuan, National Taiwan Univ. (Taiwan)
P-8-10 In situ X-ray diffraction study of lateral and vertical structures of InAs/GaAs(001) quantum dots M. Takahasi, Japan Atomic Energy Agency (Japan)
P-8-11 Advanced transparent conductive ZnO/ITO/ZnO multilayer thin films K. J. Chen, F. Y. Hung, S. J. Chang, S. J. Young and Z. S. Hu, National Cheng Kung Univ. (Taiwan)
P-8-12 Laser-Induced Backward Transfer Technique for Maskless Patterning of Poly-Si Thin Films H. Ikenoue and M. Tani, Kochi National Colledge of Tech. (Japan)
P-8-13 Development of Experiment Integrated Computational Chemistry and Its Application to Advanced Materials A. Endou, K. Nishitani, I. Yamashita, T. Onodera, M. Ise, Y. Obara, A. Suzuki, H. Tsuboi, N. Hatakeyama, H. Takaba, M. Kubo and A. Miyamoto, Tohoku Univ. (Japan)
- 67 - Thursday, October 8
P-8-14 High Quality Ultraviolet Photodetector based on Ternary ZnSe1-xTe x Nanotips Grown by MBE S. H. Chih1, C. H. Hsiao1, B. W. Lan1, S. J. Chang1, S. B. Wang1, S. P. Chang1, Y. C. Cheng2, T. C. Li2 and W. J. Lin2, 1National Cheng Kung Univ. and 2Chung Shan Inst. of Sci. and Tech. (Taiwan)
P9 Physics and Applications of Novel Functional Materials and Devices (14 Papers)
P-9-1 The Drivability Enhancement of Poly-Si TFTs by use of Nanograting Substrate S. Kuroki, X. Zhu, K. Kotani and T. Ito, Tohoku Univ. (Japan)
P-9-2 Characterization of Polycrystalline Silicon Thin-Film Transistors with Nickel-Titanium Oxide Gate Dielectric Coating by Sol-Gel Method S. C. Wu1, R. C. Yen1, C. K. Deng1, T. S. Chao1, S. H. Chuang2 and T. F. Lei1, 1National Chiao Tung Univ. and 2National Univ. of Kaohsiung (Taiwan)
P-9-3 Metal-oxide Thin Film Transistors with Co-sputtering Novel Aluminum Zinc Oxide Yttrium Channel Layer S. F. Chen, Y. L. Lee, S. Cho, K. M. Huang, Y. H. Chu and M. C. Wu, National Tsing Hua Univ. (Taiwan)
P-9-5 A Large Scale Quantum Chemistry Study for the High γMgO Protecting Layer of Plasma Display Panels K. Serizawa1, H. Onuma1, H. Kikuchi2, K. Suesada2, M. Kitagaki2, I. Yamashita1, A. Suzuki1, H. Tsuboi1, N. Hatakeyama1, A. Endou1, H. Takaba1, M. Kubo1, H. Kajiyama2 and A. Miyamoto1, 1Tohoku Univ. and
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2Hiroshima Univ. (Japan)
P-9-7 Transient Current Study on Pt/TiO2-x/Pt Capacitor N. Zhong1,2, H. Shima1,2 and H. Akinaga1,2, 1AIST and 2CREST-JST (Japan)
P-9-8 Nanoscale Fabrication of Planar-type Structures on thin Graphite Flake using Focused Ion Beam System G. Venugopal and S. J. Kim, Jeju National Univ. (Korea )
P-9-9 Capacitances in Tunneling Field-Effect Transistors Y. Yang, X. Tong, L. T. Yang, P. F. Guo, L. Fan, G. S. Samudra and Y. C. Yeo, National Univ. of Singapore (Singapore)
P-9-10 Comparative Study of Tunnel FETs and MOSFETs for Low-Power Consumption W. Y. Choi, Sogang Univ. (Korea)
P-9-11 A Non-local Algorithm for Simulation of Band-to-Band Tunneling in a Heterostructure Tunnel Field-Effect Transistor (TFET) L. Fan, L. T. Yang, Y. Yang, P. F. Guo, G. Samudra and Y. C. Yeo, National Univ. of Singapore (Singapore)
P-9-14 New Type Oxygen Sensing Device using Oxygen Intercalation of Layered Semiconductor TiS2 T. Imamura, T. Nugroho, Y. Ikawa, K. Kishiro and H. Kuriyaki, Kyushu Univ. (Japan)
P-9-15 Electrical Interface Structure of Schottky Junctions by π-conjugated Polymer/III-nitride Hetero Structure N. Matsuki1, Y. Nakano2, Y. Irokawa1 and M. Sumiya1, 1NIMS and 2Chubu Univ. (Japan)
- 69 - Thursday, October 8
P-9-16 Suppression of Critical Current in Submicron Intrinsic Josephson Junction Fabricated in a Bi2Sr2Ca2Cu3O10+δ (Bi-2223) Single Crystal Whisker S. Saini and S. J. Kim, Jeju National Univ.(Korea)
P-9-17 First-principles Study of Rectifying Properties of Pt/TiO2 Interface T. Tamura1,3, S. Ishibashi1,3, K. Terakura1,2,3 and H. Weng2,3, 1AIST, 2JAIST and 3CREST-JST (Japan)
P-9-18 Anisotropic Transport in Epitaxial Graphene Transistor on Vicinal SiC Substrate S. Odaka1,2,3, H. Miyazaki1,3, A. Kanda3,4, K. Morita5, S. Tanaka5, Y. Miyata6, H. Kataura6, K. Tsukagoshi1,3,6 and Y. Aoyagi3,7, 1NIMS, 2Tokyo Tech, 3CREST-JST, 4Univ. of Tsukuba, 5Kyushu Univ., 6AIST and 7Ritsumeikan Univ. (Japan)
P10 Organic Materials Science, Device Physics, and Applications (24 Papers)
P-10-1 Device Characteristics of Short-Channel Organic Field- Effect Transistors T. Hirose1, T. Nagase1, T. Kobayashi1, R. Ueda2, A. Otomo2 and H. Naito1, 1Osaka Prefecture Univ. and 2NICT (Japan)
P-10-2 Interface Characterization and Charge Storage Effect of a Polystrene Gate Dielectric Organic Thin-Film Transistor K. Kim1, J. Jeong2, T. Lim2 and Y. Kim2, 1Samsung Electronics Co., Ltd. and 2Hongik Univ. (Korea)
P-10-3 Instability of Amorphous-Indium Gallium Zinc Oxide
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(a-IGZO) Thin Film Transistors under DC and AC Bias Stress K. I. Choi, D. H. Nam, J. G. Park, S. S. Park and G. W. Lee, Chungnam National Univ. (Korea)
P-10-4 Phase Transition Induced by a Gate Electric Field in (BEDT-TTF)(TCNQ) Single Crystalline Field Effect Transistor M. Sakai, Y. Ito, T. Takahara, M. Nakamura and K. Kudo, Chiba Univ. (Japan)
P-10-5 Enhanced Performance of Organic Base-modulation Triodes by Nanoscale Interfacial Modification S. S. Cheng1, G. Y. Chen1, J. H. Chen1, M. C. Wu1, D. Kekuda2 and C. W. Chu2,3, 1National Tsing Hua Univ., 2Academia Sinica and 3National Chiao Tung Univ. (Taiwan)
P-10-6 Bulk Heterojunction Ambipolar Thin Film Transistors L. F. Chu1, C. F. Sung2,3, Y. Z. Lee3, F. C. Chen2, M. C. Wu1 and C. W. Chu2,4, 1National Tsing Hua Univ., 2National Chiao Tung Univ., 3Indus. Tech. Res. Inst. and 4Academia Sinica (Taiwan)
P-10-7 Molecular Orientation of Poly(3-hexylthiophene)/ Fullerene Composite Thin Films K. A. Mohamad, N. Komatsu, K. Uesugi and H. Fukuda, Muroran Inst. of Tech. (Japan)
P-10-8 Geometrical and Electrical Characteristics of Gate Electrodes for OTFT Fabricated by Screen Printing and Wet Etching M. Y. Lee and C. K. Song, Dong-A Univ. (Korea)
P-10-9 Front-Light Source using Inverted Organic Light-Emitting
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Diodes with Micro Cathode Arrays K. Urata, S. Naka and H. Okada, Univ. of Toyama (Japan)
P-10-11 Characterization of the Anomalous Temperature-dependent Carrier Transports in the Disordered ITO/PEDOT/PF/Ca/ Al Polymer Light-emitting Diodes Y. T. Chen, J. W. Teng, J. C. Wang, T. E. Nee and G. M. Wu, Chang Gung Univ. (Taiwan)
P-10-12 High Efficiency White Organic Light-Emitting Diodes with Tandem Structure C. C. Hou, C. T. Wu, L. C. Kao, S. H. Su and M. Yokoyama, I-Shou Univ. (Taiwan)
P-10-13 Luminescent Characteristics of OLED using Zn(PQ)2 as Electron Transporting Layer and Hole Blocking Layer J. W. Park1, G. C. Choi1, B. S. Kim1 T. D. Hoanh2, B. J. Lee2 and Y. S. Kwon1, 1Dong-A Univ. and 2Inje Univ. (Korea)
P-10-14 Evaluation of Seebeck Coefficients of Organic Thin Films toward Flexible Thermoelectric Power Generators A. Hoshi, M. Sakai, K. Kudo and M. Nakamura, Chiba Univ. (Japan)
P-10-15 Study on Electronic Structure of Au, Ag, and Ca-doped Bathocuproine Layers H. Kitazume1, S. Toyoshima1, T. Sakurai1, M. Aoki2, S. Masuda2 and K. Akimoto1, 1Univ. of Tsukuba and 2Univ. of Tokyo (Japan)
P-10-16 Growth and Electric Properties of C60 Nano-Crystals Directly Grown between Electrodes from Solution by Dipping Technique K. Kurihara, Y. Iio, N. Iwata and H. Yamamoto, Nihon
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Univ. (Japan)
P-10-17 Morphology Observation of Langmuir-Blodgett Thin Film based on Silsesquioxane Dendrimer G. C. Sung, J. Y. Lee, D. S. Shin, C. Kim and Y. S. Kwon, Dong-A Univ. (Korea)
P-10-18 Fine Pattern Preparation for Various Metals by using Selective Deposition based on Photochromic Surfaces Y. Sesumi1, S. Yokojima2, S. Nakamura2, K. Uchida3 and T. Tsujioka1, 1Osaka Kyoiku Univ., 2Mitsubishi Chemical Group Sci. and Tech. Res. Center Inc. and 3Ryukoku Univ. (Japan)
P-10-19 Surface Modification of Organic Thin Films by Neutral Beam Irradiation M. Hirade1,2, T. Kubota2,3, Y. Tsuru2,4, M. Yahiro1,2,6, K. Miyazaki2,4, S. Samukawa2,5 and C. Adachi1,2, 1Kyushu Univ., 2Beans Lab., 3Univ. of Tokyo, 4Kyushu Inst. of Tech., 5Tohoku Univ. and 6ISIT (Japan)
P-10-20 Gas Adsorption Properties of Fluorocarbon Polymer Thin Films Prepared by Three Different Types of r.f. Magnetron Sputtering Systems N. Hasegawa1, S. Yano1, S. Iwamori1 and K. Noda2, 1Kanazawa Univ. and 2AIST (Japan)
P-10-21 Adsorption Properties of Polymer Thin Films Prepared by r.f. Sputtering with a BPDA-PDA Polyimide Target S. Yano1, A. Uemura1,2, S. Iwamori1 and K. Noda3, 1Kanazawa Univ., 2Indus. Res. Inst. of Ishikawa and 3AIST (Japan)
P-10-22 Evaluation of 5CB Liquid Crystal Molecules on SiO2 Alignment Layer by Simultaneous Surface Plasmon
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Resonance and Optical Waveguide Spectroscopy A. Ikarashi, A. Baba, K. Shinbo, K. Kato and F. Kaneko, Niigata Univ. (Japan)
P-10-23 Enhancing the Fill Factor in Polymer Photovoltaic Cell by using a Hole Transporting Layer W. T. Chiang, S. H. Su, Y. C. Liu and M. Yokoyama, I-Shou Univ. (Taiwan )
P-10-24 Study of Opto-electronic and Physical Properties of Novel Flexible Substrate Material W. G. Sie, W. Y. Huang, C. C. Lee and W. T. Liu, National Sun Yat-sen Univ. (Taiwan)
P-10-25 Donor - Acceptor Type Conjugated Polymers Containing Carbazole and Fluorene for Organic Photovoltaic Applications W. J. Lee, J. R. Haw and D. K. Moon, Konkuk Univ. (Korea)
P11 Micro/Nano Electromechanical and Bio-Systems (Devices) (12 Papers)
P-11-1 Terahertz Spectroscopic Technology for Safety and Security T. Uno and H. Tabata, Univ. of Tokyo (Japan)
P-11-2 Discharge Current Controlled Atmospheric Microplasma Generation H. Park1, J. Kim1 and Y. Kim1, Hongik Univ. (Korea)
P-11-3 Continuous Manipulation of Micro Particles by Use of
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Asymmetric Electrodes Array M. Midorikawa, S. Kuroki, D. Obara, K. Kotani and T. Ito, Tohoku Univ. (Japan)
P-11-4 Actuation of Magnetic Beads on a CMOS Chip for Biological Applications T. Ishikawa, K. Johguchi and F. Kaneko, Hiroshima Univ. (Japan)
P-11-5 A Novel Differential LAPS with PVC and HfO2 Sensing Membranes for pH Sensors C. S. Lai1, C. M. Wu1, C. E. Lue1, T. F. Lu1, C. M. Yang2 and H. Y. Chen1, 1Chang Gung Univ. and 2Inotera memories Inc. (Taiwan)
P-11-6 Ultra-Conformal Metal Coating on High-aspect-ratio 3D Structures using Supercritical Fluid: Controlled Selectivity/Non-Selectivity T. Momose1,2, T. Uejima1, H. Yamada2, M. Sugiyama1,2 andY. Shimogaki1,2, 1Univ. of Tokyo and 2BEANS Project, METI (Japan)
P-11-7 Fabrication of Electrostatic Actuated Rotary for Micro Interferometer Y. M. Lee, M. Toda, T. Ono and M. Esashi, Tohoku Univ. (Japan)
P-11-8 Thermopile IR Detector Integrated with Wavelength Selective Filter Stable against Temperature and Incident Angle Change K. Masuno, S. Kumagai, M. Sasaki and K. Tashiro, Toyota Technological Inst. (Japan)
P-11-9 Silane-coupling Silicon Substrate that Fixes Protein without Adsorption of Protein Buffer Components for
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Device Fabrication M. Fukuta1 and I. Yamashita1,2, 1NAIST and 2Panasonic Corp. (Japan)
P-11-10 Multi-channel Bio Sensing and Stimulation LSI Chip using 0.18 μm CMOS Process M. Yamaguchi1, A. Shimada2, K. Torimitsu2 and N. Nakano1, 1Keio Univ. and 2NTT Corp. (Japan)
P-11-11 Fabrication of Smart Electrochemical Sensor with CMOS Integrated Circuits T. Yamazaki1,2, T. Ikeda1, Y. Kano1, H. Takao1.3, M. Ishida1.3 and K. Sawada1.3, 1Toyohashi Univ. of Tech., 2HIOKI E. E. Corp. and 3CREST-JST (Japan)
P-11-12 In vivo Neural Signal Recording using Double-sided Si Neural Probe S. Lee, R. Kobayashi, S. Kanno, K. Lee, T. Fukushima, K. Sakamoto, Y. Matsuzaka, N. Katayama, H. Mushiake, M. Koyanagi and T. Tanaka, Tohoku Univ. (Japan)
P12 Spintronic Materials and Devices (7 Papers)
P-12-1 Dielectric Breakdown in MgO-barrier Magnetic Tunnel Junctions with a CoFeB based Synthetic Ferrimagnetic Recording Layer M. Yamanouchi1, Y. Mori1, J. Hayakawa1, H. Yamamoto1, K. Miura1, H. Hasegawa1, K. Ito1, K. Takeda1, K. Meguro1, H. Takahashi1, H. Matsuoka1, S. Ikeda2 and H. Ohno2, 1Hitachi, Ltd. and 2Tohoku Univ. (Japan)
P-12-2 SpinFET on Epitaxial Graphene T. Shen1, Y. Q. Wu1, A. Chernyshov1, L. P. Rokhinson1,
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M. L. Bolen1, M. A. Capano1, A. R. Pirkle2, J. Kim2, R. M. Wallace2, J. J. Gu1, K. Xu1, L. W. Engel3 and P. D. Ye1, 1Purdue Univ., 2Univ. of Texas at Dallas and 3National High Magnetic Field Lab. (USA)
P-12-3 Growth and Magnetic Properties of Mn2.5Ga Films for Spintronic Devices F. Wu, S. Mizukami, D. Watanabe, H. Naganuma, M. Oogane, Y. Ando and T. Miyazaki, Tohoku Univ. (Japan)
P-12-4 Formation of Cr-rich Columnal Regions in Magnetic Semiconductor (Zn,Cr)Te Y. Nishio1, K. Ishikawa1, S. Kuroda1, M. Mitome2 and Y. Bando2, 1Univ. of Tsukuba and 2NIMS (Japan)
P-12-6 Effects of Hole Doping in the Ferromagnetic Semiconductor Mn-doped ZnO Thin Film Studied by X-ray Magnetic Circular Dichroism T. Kataoka1, Y. Sakamoto1, M. Kobayashi1, V. R. Singh1, Y. Yamazaki1, A. Fujimori1,2, F. H. Chang3, H. J. Lin3, D. J. Huang3, C. T. Chen3, Y. Takeda2, T. Ohkochi2, T. Okane2, Y. Saitoh2, H. Yamagami2,4, M. Kapilashrami5, L. Belova5 and K. V. Rao5, 1Univ. of Tokyo, 2JAEA/ SPring-8, 3NSRRC, 4Kyoto Sangyo Univ. and 5Royal Inst. of Tech. (Japan)
P-12-7 Advanced Macro-Model with Pulse-Width Dependent Switching Characteristic for Spin-Transfer-Torque based Magnetic-Tunnel-Junction Elements S. Kim, S. Lee and H. Shin, Ewha Womans Univ. (Korea)
P-12-8 Local Probing of Magnetization Reversal in a Ni-Fe Nanowire with a Notch Measured with Magnetic Field Sweeping(MFS)-Magnetic Force Microscopy(MFM) Y. Endo, Y. Mitsuzuka, M. Watanabe and M. Yamaguchi,
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Tohoku Univ. (Japan)
P13 Applications of Nanotubes and Nanowires (14 Papers)
P-13-1 High thermo-acoustic property of Carbon-nanotube speaker K. Suzuki, S. Sakakibara, S. Shimizu, M. Okada, Y. Neo, H. Mimura, Y. Suzuki, Y. Minami, A. Murakami, J. Muramatsu and Y. Inoue, Shizuoka Univ. (Japan)
P-13-2 Fabrication of Quantum Dots in Twin-Free GaAs Nanopillars on Si K. Tateno, G. Zhang, H. Gotoh and H. Nakano, NTT Basic Res. Labs. (Japan)
P-13-3 Gate induced Cross-over between Fabry Perot and Quantum Dot Behavior in a Single-Walled Carbon Nanotube Hole-Transistor with Double Gate Structure T. Kamimura1,2,3 and K. Matsumoto1,3,4, 1AIST, 2JSPS , 3CREST-JST and 4Osaka Univ. (Japan)
P-13-4 Enhanced Visible Light and Electron Field Emission of Porous Silicon Nanowires W. I. Hsu, S. J. Wang, W. C. Tsai, W. C. Hsu, F. S. Tsai and H. Y. Huang, National Cheng Kung Univ. (Taiwan)
P-13-5 First Principles Study of Metals Coating on Single Wall Carbon Nanotube Y. He, J. Zhang, Y. Wang and Z. Yu, Tsinghua Univ. (China)
P-13-6 The Preparation of SiO2 Nanotubes with Controllable
- 78 - Thursday, October 8 inner/outer Diameter and Length using Hydrothermally Grown ZnO Nanowires D. M. Kuo1, S. J. Wang1, K. M. Uang2, W. C. Tsai1, W. I. Hsu1, W. C. Lee1, P. R. Wang1 and C. R. Tseng1, 1National Cheng Kung Univ. and 2WuFeng Inst. of Tech. (Taiwan)
P-13-7 Diameter dependence of hole current in silicon and germanium nanowire FETs H. Minari and N. Mori, Osaka Univ. (Japan)
P-13-8 Shape Effects on the Performance of Si and Ge Nanowire FETs based on Size De-pendent Bandstructure C. S. Koong, G. Samudra and G. Liang, National Univ. of Singapore (Singapore)
P-13-9 Experimental Investigation of Electron-Phonon Scattering Effect in Strained Si Nanowire FETs at Low Temperature I. Tsuchida1, A. Seike1, H. Takai1, J. Masuda2, D. Kosemura2, A. Ogura2, T. Watanabe1 and I. Ohdomari1, 1Waseda Univ. and 2Meiji Univ. (Japan)
P-13-10 Simulation on the Heat Transport in a Silicon Nano- Structure Covered with Oxide Films T. Zushi1, K. Kukita2, Y. Kamakura2, K. Taniguchi2, I. Ohdomari1 and T. Watanabe1, 1Waseda Univ. and 2Osaka Univ. (Japan)
P-13-11 Interface and Passivation Effect on Subthreshold Transport of Carbon Nanotube Network Transistor by Plasma Enhanced Chemical Vapor Deposition S. G. Jung1, U. J. Kim2 and Wanjun Park1, 1Hanyang Univ. and 2Samsung Advanced Inst. of Tech. (Korea)
P-13-12 Selectivity Lateral Grown ZnO Nanowire UV
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Photodetectors on Glass Substrate W. Y. Weng1, T. J. Hsueh2, S. J. Chang1 and C. L. Hsu3, 1National Cheng Kung Univ, 2National Nano Device Laboratories and 3National Univ of Tainan (Taiwan)
P-13-13 Post-Annealing Effect on the Electrical Properties of Top- gated SWNT Network Transistors S. C. Min1,2, W. J. Park1 and U. J. Kim2, 1Hanyang Univ. and 2Samsung Advanced inst. of tech (Korea)
P-13-14 Electronic Transport Properties in Irradiated C60 FNW T. Doi1, Y. Chiba1, H. Tsuji1, M. Ueno1, S. R. Chen1,2, N. Aoki1 and Y. Ochiai1, 1Chiba Univ. and 2Southern Taiwan Univ. of Tech. (Japan)
P14 Power Electronics (11 Papers)
P-14-1 Reducing the Gate Charge of Dual Gate Power VDMOSFET by Pseudo-Gate C. N. Liao1, F. T. Chien2, C. M. Lin3, C. H. Ho1 and Y. T. Tsai1, 1National Central Univ., 2Feng Chia Univ. and 3Southern Taiwan Univ. (Taiwan)
P-14-2 The Cryogenic behaviour of High Power Si and GaAs Schottky Diodes K. Leong, A. Bryant and P. Mawby, Univ. of Warwick, (UK)
P-14-3 Cathodoluminescence Microcharacterization of Recombination Centers in Lifetime-Controlled IGBTs R. Sugie1, T. Mitani1, M. Yoshikawa1, Y. Iwata2 and R. Satoh2, 1Toray Res. Center Inc. and 2Osaka Univ. (Japan)
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P-14-4 Improvement in Quantitative Analysis of Defects and Microstructures in Si Multicrystals using X-ray Diffraction K. Kutsukake, N. Usami, K. Fujiwara and K. Nakajima, Tohoku Univ. (Japan)
P-14-5 Selection of Material for the Back Electrodes of Thin-Film Solar Cells using Polycrystalline Silicon Films Formed by Flash Lamp Annealing K. Ohdaira, T. Fujiwara, K. Shiba and H. Matsumura, JAIST (Japan)
P-14-6 Defect Passivation of Solar Cells by High Pressure H2O Vapor Treatment M. Hasumi, M. Shimokawa, K. Ukawa, T. Haba, Y. Mizutani and T. Sameshima, Tokyo Univ. of Agri. and Tech. (Japan)
P-14-7 Development of an Ultra-Accelerated Quantum Chemical Molecular Dynamics Method and its Application to Ion Transport in Li-ion Battery Y. Suzuki, T. Ogawa, H. Tsuboi, N. Hatakeyama, A. Endou, A. Suzuki, H. Takaba, M. Kubo and A. Miyamoto, Tohoku Univ. (Japan)
P-14-8 Surface Modification of SnO2 Electrodes for Highly Efficient Dye Sensitized Solar Cells F. Hirose, H. Yoshida, M. Shikaku, T. Suzuki and Y. Narita, Yamagata Univ. (Japan)
P-14-9 High Performance Transparent Conducting Ga-doped ZnO film Deposited by RF-magnetron Sputter Deposition Technique J. K. Kim1,2, J. M. Lee1,2, J. W. Lim1,2, J. H. Kim2 and S. J. Yun1,2, 1Univ. of Sci. and Tech. and 2Electronics and Telecommunications Res. Inst. (Korea)
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P-14-10 Improvement of Opt-Electrical Properties in GaAsN by Controlling Step Density During Chemical Beam Epitaxy Growth H. Suzuki, M. Inagaki, T. Honda, Y. Ohshita, N. Kojima and M. Yamaguchi, Toyota Technological Inst. (Japan)
P-14-11 First Principles Calculations on Σ 3 Grain Boundary Impurities in Polycrystalline Silicon A. Suvitha, N. S. Venkataramanan, R. Sahara, H. Mizuseki and Y. Kawazoe, Tohoku Univ. (Japan)
12:00-13:15 Lunch
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Plenary Session 15:00-15:45 2F Heisei Chair: S. Chung, National Chiao Tung Univ.
15:00 PL-2-1 Long term strategy for mitigating climate change Y. Kaya, RITE, Japan
Area 1: Advanced Gate Stack / Si Processing & Material Science A-3: Source/Drain Engineering 13:05-14:40 2F Heisei
13:05 A-3-1 Carbon Incorporation into Substitutional Silicon Site by Molecular Carbon Ion Implantation and Recrystallization Annealing for Stress Technique in nMOSFETs H. Itokawa, K. Miyano, Y. Oshima, I. Mizushima and K. Suguro, Toshiba Corp. (Japan)
13:25 A-3-2 Influence of Carbon in in-situ Carbon Doped SiGe (SiGe:C) Films on Si (001) Substrates on Epitaxial Growth Characteristics H. Oomae1, H. Itokawa2, I. Mizushima2, S. Nakamura3 and N. Uchitomi1, 1Nagaoka Univ. of Tech., 2Toshiba Corp. and 3Aoyama Gakuin Univ. (Japan)
13:45 A-3-3 Carbon Profile Engineering for Silicon-Carbon Source/ Drain Stressor Formed by Carbon Ion Implantation and Solid Phase Epitaxy Q. Zhou1, S. M. Koh1, Z. Y. Zhao2, T. Toh2, H. Maynard2, N. Variam2, T. Henry2, Y. Erokhin2 and Y. C. Yeo1, 1National Univ. of Singapore and 2Varian Semiconductor (Singapore)
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14:05 A-3-4 Contribution of Carbon to Activation and Diffusion of Boron in Silicon H. Itokawa1, Y. Agatsuma2, N. Aoki1, N. Uchitomi2 and I. Mizushima1, 1Toshiba Corp. and 2Nagaoka Univ. of Tech. (Japan) 15:00-15:45 Plenary Session
Area 1: Advanced Gate Stack / Si Processing & Material Science B-4: High-k/Metal Gate I 16:00-17:30 2F Heisei
16:00 B-4-1 (Invited) Development of high-k / Metal Gate CMOS Technology in Selete K. Ikeda, J. Yugami, T. Aoyama and Y. Ohji, Selete (Japan)
16:30 B-4-2 Gate Leakage Advantage of LaO Incorporation for Vt Tuning in High-k nMOSFETs over Metal Gate WF Control M. Kadoshima1, S. Sakashita1, T. Kawahara1, M. Inoue1, M. Mizutani1, Y. Nishida1, A. Shimizu1, Y. Takeshima1, S. Yamanari1, M. Anma1, R. Mitsuhash2, Y. Satoh2, S. Matsuyama2, A. Tsudumitani2, Y. Okuno2, H. Umeda1, J. Yugami1, H. Yoshimura1 and H. Miyatake1, 1Renesas Tech. Corp. and 2Panasonic Corp. (Japan)
16:50 B-4-3 Influence of Post Cap-layer Deposition Annealing Temperature on MgO Diffusion in High-k/IFL Stacks T. Morooka, T. Matsuki, T. Nabatame, J. Yugami, K. Ikeda and Y. Ohji, Selete (Japan)
17:10 B-4-4 Bottom-La Inserted HfSiON Gate Dielectrics with
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MOCVD HfCN Metal Gate Electrode Realizing High Mobility and Reliability Improvement S. Inumiya, A. Kaneko, K. Nagatomo, M. Goto, K. Tatsumura, I. Hirano, S. Kawanaka, A. Azuma, K. Nakajima, T. Aoyama, K. Eguchi, A. Nishiyama, Y. Toyoshima and Y. Tsunashima, Toshiba Corp.(Japan) 17:30-17:40 Break
Area 1: Advanced Gate Stack / Si Processing & Material Science B-5: High-k/Metal Gate II 17:40-19:00 2F Heisei
17:40 B-5-1 Channel Strain Analysis in High Performance Damascene- gate pMOSFETs by High Spatial Resolution Raman Spectroscopy M. Takei1, D. Kosemura1, K. Nagata1, H. Akamatsu1, S. Mayuzumi1,2, S. Yamakawa2, H. Wakabayashi2 and A. Ogura1, 1Meiji Univ. and 2Sony Corp. (Japan)
18:00 B-5-2 Effect of Post Cap-Layer Deposition Annealing Temperature and TiN Thickness on SMDH CMOS Process using TiN Hard Mask H. Shinohara, A. Katakami, T. Watanabe, M. Hayashi, S. Kamiyama, Y. Sugita, T. Matsuki, T. Eimori, J. Yugami, K. Ikeda and Y. Ohji, Selete (Japan)
18:20 B-5-3 Improvement of Interfacial Characteristics and Reliability in Poly/SiON Gate Stack by Catalytic Effect of Hafnium Incorporation Technique T. Shimizu, Y. Arayashiki, S. Inumiya, K. Nakajima, T. Aoyama and K. Eguchi, Toshiba Corp. (Japan)
18:40 B-5-4 Influence of Gate Electrode Stress on Channel Stress and
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Device Performance in Gate-First W/TiN Gate MOSFETs T. Matsuki, J. Yugami, T. Eimori, Y. Nara and K. Ikeda, Selete (Japan)
Area 2: Characterization and Materials Engineering for Interconnect Integration D-4: Scaled-down Cu Metallization 16:00-17:10 3F Sakura Chair: S. Matsumoto (Panasonic Corp.) T. Hasegawa (Sony Corp.)
16:00 D-4-1 (Invited) Patterning & Metallization Options for Advanced Contact Module Integration S. Demuynck, IMEC (Belgium)
16:30 D-4-2 Effect of Via-Profile on the Via Reliability in Scaled-down Low-k/Cu Interconnects I. Kume, N. Inoue, S. Saito, N. Furutake, J. Kawahara and Y. Hayashi, NEC Electronics Corp. (Japan)
16:50 D-4-3 On the Reliability of Cu Contacts for the 32nm Technology Node and beyond T. Kauerauf, S. Demuynck, G. Butera, J. Bogan, Zs. Tökei and G. Groeseneken, IMEC (Belgium) 17:10-17:30 Break
Area 2: Characterization and Materials Engineering for Interconnect Integration D-5: Characterization and Reliability for Metallization 17:30-18:40 3F Sakura Chair: G. Beyer (IMEC) M. Kodera (Toshiba Corp. )
17:30 D-5-1 (Invited) High-Resolution and Thermodynamic Analysis of Interconnect Metals and Diffusion Barriers R. Sinclair, Stanford Univ. (USA)
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18:00 D-5-2 Rutherford Backscattering Spectrometry Analysis of Growth of Ti-Rich Layer Formed at Cu(Ti)/Low-k Interfaces K. Kohama1, K. Ito1, K. Mori2, K. Maekawa2, Y. Shirai1 and M. Murakami3, 1Kyoto Univ., 2Renesas Tech. Corp. and 3The Ritsumeikan Trust (Japan)
18:20 D-5-3 A Comparison of Lifetime Improvements in Electromigration between Ti Barrier Metal and CVD Co Capping Y. Kakuhara and S. Yokogawa, NEC Electronics Corp. (Japan)
Area 3: CMOS Devices /Device Physics A-4: Novel Device Structure and Physics 16:30-17:10 2F Heisei
16:30 A-4-1 Multiple-Gate Tunneling Field Effect Transistors with sub- 60mV/dec Subthreshold Slope D. Leonelli1,2, A. Vandooren1, R. Rooyackers1, A. S. Verhulst1,2, S. De Gendt1,2, M. M. Heyns1,2 and G. Groeseneken1,2, 1IMEC and 2Katholieke Univ. Leuven (Belgium)
16:50 A-4-2 Novel Source Heterojunction Structures with Relaxed-/ Strained-Layers for Quasi-Ballistic CMOS Transistors using Ion Implantation Induced Relaxation Technique of Strained-Substrates T. Mizuno1,2, N. Mizoguchi1, K. Tanimoto1, T. Yamauchi1, T. Tezuka3 and T. Sameshima4, 1Kanagawa Univ., 2MIRAI- NIRC, 3MIRAI-Toshiba and 4Tokyo Univ. of Agri. and Tech. (Japan) 17:10-17:30 Break
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Area 3: CMOS Devices /Device Physics A-5: New Device Technologies 17:30-18:50 2F Heisei
17:30 A-5-1 NiSi metal S/D transistors with ultimaltely low Schottky barrier by sulfur Implantation After Silicidation Process Y. Nishi and A. Kinoshita, Toshiba Corp. (Japan)
17:50 A-5-2 A New Diamond-like Carbon (DLC) Ultra-High Stress Liner Technology for Direct Deposition on P-Channel Field-Effect Transistors B. Liu1, M. C. Yang2 and Y. C. Yeo1, 1National Univ. of Singapore and 2Data Storage Inst. (Singapore)
18:10 A-5-3 Investigation on Enhanced Impact Ionizaion in Uniaxially Strained Si MOSFET S. Adachi and T. Asano, Kyushu Univ. (Japan)
18:30 A-5-4 Influence of Carrier Transit Delay on CMOS Switching Performance D. Hori1, M. Miyake1, N. Sadachika1, H. J. Mattausch1, M. Miura-Mattausch1, T. Iizuka2, T. Hoshida2, K. Matsuzawa2, Y. Sahara2 and T. Tsukada2, 1Hiroshima Univ. and 2STARC (Japan)
Area 4: Advanced Memory Technology G-3: Flash Memory II 13:15-14:35 4F Hirose
13:15 G-3-1 Direct Measurement of Back-Tunneling Current during
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Program/Erase Operation of MONOS Memories and Its Dependence on Gate Work Function J. Fujiki, S. Fujii, N. Yasuda and K. Muraoka, Toshiba Corp. (Japan)
13:35 G-3-2 Thickness Effect on Read Window in a Two-Bit Nitrided- based Trapping Storage Cell G. D. Lee, C. H. Cheng, S. H. Ku, C. H. Liu, S. H. Kuo, C. H. Lee, S. W. Huang, N. K. Zous, M. S. Chen, W. P. Lu, K. C. Chen and C. Y. Lu, Macronix Int'l Co., Ltd. (Taiwan)
13:55 G-3-3 Engineering of Si-rich Nitride Charge-Trapping Layer for Highly Reliable MONOS Type NAND Flash Memory with MLC Operation R. Fujitsuka, K. Sekine, A. Sekihara, A. Fukumoto, J. Fujita, F. Aiso and Y. Ozawa, Toshiba Corp. (Japan)
14:15 G-3-4 Thermally Robust Nanocrystal Memory with Co Bio- nanodot Self-assembled Monolayer as a Charge Trap Medium on Ultrathin LaAlO3 Layer S. Jung1, K. Ohara2, Y. Uraoka2, T. Fuyuki2, I. Yamashita2 and H. Hwang1, 1Gwangju Inst. of Sci. and Tech. and 2NAIST (Korea) 15:00-15:45 Plenary Session
Area 4: Advanced Memory Technology G-4: Flash Memory III 16:00-17:20 4F Hirose
16:00 G-4-1 Depletion-type Cell-Transistor of 23 nm Cell Size on Partial SOI Substrate for NAND Flash Memory M. Mizukami1, K. Nishihara2, H. Ishida2, F. Aiso2, T. Iguchi2, D. Ichinose2, A. Fukumoto2, N. Aoki2,
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M. Kondo2, T. Izumida2, H. Tanimoto2, T. Enda2, T. Suzuki2, I. Mizushima2 and F. Arai2, 1Toshiba R&D Center and 2Toshiba Advanced Micro-electronics Center (Japan)
16:20 G-4-2 The Operation Scheme and Process Optimization in TLC(Triple Level Cell) NAND Flash Characteristics J. Yang, M. Park, S. Jung, S. Park, S. Cho, J. An, J. Lee, S. Cho, H. Lee, M. K. Cho, K. O. Ahn, K. Jin and Y. Koh, Hynix Semiconductor Inc. (Korea)
16:40 G-4-3 The Influence of Mechanical Stress on Data Retention in Advanced NAND Flash S. W. Seo, H. Oh, Y. Yang, S. M. Yi, S. Y. Kim, P. Kim, D. K. Lee, H. Yang, H. Lee, M. K. Cho, K. O. Ahn and Y. Koh, Hynix Semiconductor Inc. (Korea)
17:00 G-4-4 A New Differential Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell Y. H. Tsai, H. L. Yang, W. J. Lin, C. J. Lin and Y. C. King, National Tsing Hua Univ. (Taiwan) 17:20-17:30 Break
Area 4: Advanced Memory Technology G-5: PRAM 17:30-18:20 4F Hirose
17:30 G-5-1 (Invited) Current Status and Future Challenge of PRAM Y. H. Shih, Macronix Int'l Co., Ltd. (Taiwan)
18:00 G-5-2 Elevated-Confined Phase Change RAM cells H. K. Lee1, L. P. Shi1, R. Zhao1, H. X. Yang1, K. G. Lim1, J. M. Li1 and T. C. Chong1,2, 1A*STAR and 2National Univ.
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Area 6: Compound Semiconductor Circuits, Electron Devices and Device Physics J-3: SiC and Diamond Devices 13:15-14:45 6F Hagi Chair: R. Hattori (Mitsubishi Electric Corp.) T. Tanaka (Panasonic Corp.)
13:15 J-3-1 (Invited) SiC Power MOSFETs and Diodes for Next Generation J. W. Palmour, A. Agarwal, R. Callanan and J. Richmond, Cree, Inc. (USA)
13:45 J-3-2 Improvement of Interface Properties by NH3 Pretreatment for 4H-SiC(000-1) MOS Structure Y. Iwasaki, H. Yano, T. Hatayama, Y. Uraoka and T. Fuyuki, NAIST (Japan)
14:00 J-3-3 Very Smooth SiO2/SiC Interface Formed by Supercritical Water Oxidation of Low Temperature T. Futatsuki1,2, T. Oe2, H. Aoki1, N. Komatsu1, C. Kimura1 and T. Sugino1, 1Osaka Univ. and 2Organo Corp. (Japan)
14:15 J-3-4 Interface Properties of C-face 4H-SiC Metal-Oxide- Semiconductor Structures Prepared by Direct Oxidation in Nitric Oxide D. Okamoto, H. Yano, Y. Oshiro, T. Hatayama, Y. Uraoka and T. Fuyuki, NAIST (Japan)
14:30 J-3-5 High-temperature Operation of Boron-implanted Diamond FETs K. Ueda, Y. Yamauchi and M. Kasu, NTT Basic Res. Labs. (Japan) 15:00-15:45 Plenary Session
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Area 6: Compound Semiconductor Circuits, Electron Devices and Device Physics J-4: High-frequency Devices 16:00-17:15 6F Hagi Chair: S. Yamahata (NTT Corp.) K. S. Seo (Seoul National Univ.)
16:00 J-4-1 A 20-Gb/s Pulse Generator with 4.9-ps FWHM using 75- nm InP-based HEMTs Y. Nakasha1, Y. Kawano1, T. Suzuki1, T. Ohki2, T. Takahashi1, K. Makiyama1 and N. Hara1, 1Fujitsu Ltd. and 2Fujitsu Labs. Ltd. (Japan)
16:15 J-4-2 Ultra-Fast Optical Response by InAlAs/InAs/InGaAs Pseudomorphic High Electron Mobility Transistors H. Taguchi, Y. Oishi, T. Ando, K. Uchimura, M. Mochiduki, M. Enomoto, T. Iida and Y. Takanashi, Tokyo Univ. of Sci. (Japan)
16:30 J-4-3 0.25-μm-Emitter InP HBTs with a Passivation Ledge Structure N. Kashio, K. Kurishima, Y. K. Fukai, M. Ida and S. Yamahata, NTT Corp. (Japan)
16:45 J-4-4 In0.49GaP/Al0.45GaAs/In0.22GaAs/Al0.22GaAs Barrier Enhancement-mode Pseudo-morphic High Electron Mobility Transistor with an Enhanced Gate Forward Turn- on Voltage J. Sung, J. Kim, K. Jang and K. S. Seo, Seoul National Univ. (Korea)
17:00 J-4-5 RF Small Signal Characterization of Active Transmission Lines Load by InGaAs/AlAs Resonant Tunneling Diodes K. Kasahara, T. Ohe, M. Mori and K. Maezawa, Univ. of Toyama (Japan)
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17:15-17:30 Break
Area 6: Compound Semiconductor Circuits, Electron Devices and Device Physics J-5: Graphen and Oxide Devices 17:30-18:45 6F Hagi Chair: K. Maezawa (Univ. of Toyama) Y. Ohno (Univ. of Tokushima)
17:30 J-5-1 Extraction of Drain Current and Effective Mobility in Epitaxial Graphene Channel FETs on Silicon Substrates H. C. Kang1, R. Olac-vaw1, H. Karasawa1, Y. Miyamoto1, H. Handa1, T. Suemitsu1,2, H. Fukidome1,2, M. Suemitsu1,2 and T. Otsuji1,2, 1Tohoku Univ. and 2CREST-JST (Japan)
17:45 J-5-2 Enhancement-mode MOCVD Grown ZnO TFTs on Glass Substrates using N2O Plasma Treatment K. Remashan, Y. S. Choi, S. J. Park and J. H. Jang, Gwangju Inst. of Sci. and Tech. (Korea)
18:00 J-5-3 Effect of Post Thermal Annealing of ZnO-TFTs by Atomic Layer Deposition Y. Kawamura1 and Y. Uraoka1,2, 1NAIST and 2CREST-JST (Japan)
18:15 J-5-4 Low Voltage Operation of Inverted Staggered Amorphous Indium Gallium Zinc Oxide Thin Film Transistor with Al2O3 High-k Dielectric Material Y. G. Yoon and J. H. Jang, Gwangju Inst. of Sci. and Tech. (Korea)
18:30 J-5-5 Characteristics of Transparent ZnO Based Thin Film Transistors with High-k Dielectric Gd2O3 Gate Insulators Fabricated at Room Temperature J. R. Tsai, C. S. Li, J. N. Chen, C. J. Tseng, P. H. Chien, W. S. Feng and K. C. Liu, Chang Gung Univ. (Taiwan)
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Area 7: Photonic Devices and Device Physics I-3: LED I 13:15-14:45 6F Kaede Chair: M. Gotoda (Mitsubishi Electric Corp.) H. Yamada (Tohoku Univ.)
13:30 I-3-2 Divergent Far-Field Pattern from GaN-based Film- Transferred Photonic Crystal Light-Emitting Diodes C. F. Lai1, H. C. Kuo1, C. H. Chao2, H. H. Yeh1, C. E. Lee1, C. Y. Huang2 and W. Y. Yeh2, 1National Chiao Tung Univ. and 2Indus. Tech. Res. Inst. (Taiwan)
13:45 I-3-3 High Performance Angled Light-Emitting Diodes by Laser Micromachining K. N. Hui1,2, P. T. Lai2 and H. W. Choi2, 1State Univ of New Jersey and 2Univ. of Hong Kong (USA)
14:00 I-3-4 A Screen Printed Sn-based Dicing-Free Metal Substrate Technology for the Fabrication of Vertical-Structured GaN-based Light-Emitting Diodes P. R. Wang1, P. H. Wang1, H. Y. Kuo1, K. M. Uang2, T. M. Chen2, D. M. Kuo1 and S. J. Wang1, 1National Cheng Kung Univ. and 2Wufeng Inst. Of Tech. (Taiwan)
14:15 I-3-5 Fabrication of High Qualify factor of GaN-based Vertical- cavity Light Emitting Diodes with AlN/GaN and Ta2O5/ SiO2 Hybrid Mirrors S. W. Chen, C. K. Chen, T. T. Kao, C. H. Chen, M. H. Lo, Z. Y. Li, T. C. Lu, H. C. Kuo and S. C. Wang, National Chiao Tung Univ. (Taiwan)
14:30 I-3-6 Enhanced Light Output of Vertical-Structured GaN-based LEDs with Surface Roughening using KrF Laser and ZnO Nanorods W. C. Lee1, K. M. Uang2, T. M. Chen2, D. M. Kuo1,
- 94 - Thursday, October 8
P. R. Wang1, C. R. Tseng1, C. K. Wu1 and S. J. Wang1, 1National Cheng Kung Univ. and 2Wufeng Inst. Of Tech. (Taiwan) 15:00-15:45 Plenary Session
Area 8: Advanced Material Synthesis and Crystal Growth Technology H-3: Oxide Materials 13:15-14:45 6F Kiri Chair: M. Nakada (NEC Corp.) T. Fukumura (Tohoku Univ.)
13:15 H-3-1 (Invited) High throughput combinatorial materials Exploration for advanced magneto-electronics T. Fukumura1,2, 1Tohoku Univ. and 2PRESTO-JST (Japan)
13:45 H-3-2 Control of Crystal-growth of VO2 Films Fabricated by Excimer Laser Assisted Metal Organic Deposition M. Nishikawa1, T. Nakajima2, T. Kumagai2, T. Okutani1 and T. Tsuchiya2, 1Yokohama National Univ. and 2AIST (Japan)
14:00 H-3-3 Prediction of Crystallization Temperature for HfO2 Thin Film in High Temperature Annealing Process by Reaction Time Accelerating Molecular Dynamics K. Nishitani1,2, H. Yabuhara1, A. Endou2, A. Suzuki2, H. Tsuboi2, N. Hatakeyama2, H. Takaba2, M. Kubo2 and A. Miyamoto2, 1Toshiba Corp. and 2Tohoku Univ. (Japan)
14:15 H-3-4 Electrical and Physical Characteristics of the High-K Gd2O3 (Gadolinium) Dielectric Deposited on the Polycrystalline Silicon J. S. Chiu1, C. H. Kao1, H. Chen2, P. Y. Tsung1, Y. C. Liao1, W. S. Liao1, Y. T. Chung1, H. C. Fan1, P. L. Lai1, C. Y. Huang1, C. S. Lin1 and J. M. Dai1, 1Chang Gung Univ. and 2Chi Nan Univ. (Taiwan)
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14:30 H-3-5 Highly-(001)-Oriented Ferroelectric PZT Thin Films on Glass by CW Green-Laser Crystallization J. Jiang, S. Kuroki, K. Kotani and T. Ito, Tohoku Univ. (Japan) 15:00-15:45 Plenary Session
Area 8: Advanced Material Synthesis and Crystal Growth Technology H-4: Advanced Nitride Growth and Structures 16:00-17:15 6F Kiri Chair: Y. Sakuma (NIMS) T. Iwai (Fujitsu Labs. Ltd.)
16:00 H-4-1 (Invited) Recent advances in InN-based III-nitrides towards novel nanostructure photonic devices A. Yoshikawa, Y. Ishitani, S. B. Che, N. Hashimoto, A. Yuki, H. Watanabe and K. Kusakabe, Chiba Univ. (Japan)
16:30 H-4-2 Epitaxial overgrowth of GaN Nanorods on Si (111) substrates by rf-plasma-assisted molecular-beam Epitaxy J. T. Ku, T. H. Yang, J. R. Chang, Y. Y. Wong, W. C. Chou and C. Y. Chang, National Chiao Tung Univ. (Taiwan)
16:45 H-4-3 Growth of (10-1 3) semipolar GaN on Si substrate with a CrN interlayer by molecular beam epitaxy K. W. Liu, T. H. Hsueh, S. J. Young, H. Hung, S. X. Chen, Y. Z. Chen and S. J. Chang, Nation Cheng Kung Univ. (Taiwan)
17:00 H-4-4 Growth of Quaternary AlInGaN with Various TMI Molar Rates S. F. Yu, S. J. Chang and S. P. Chang, National Cheng Kung Univ. (Taiwan) 17:15-17:30 Break
- 96 - Thursday, October 8
Area 8: Advanced Material Synthesis and Crystal Growth Technology H-5: Advanced Nitride Growth and Structures 17:30-18:45 6F Kiri Chair: T. Iwai (Fujitsu Labs. Ltd.) Y. Sakuma (NIMS)
17:45 H-5-2 Growth and Characterization of High Quality a-plane InGaN/GaN Single Quantum Well Structure Grown by Multi-buffer Layer Technique H. Song1,2, J. S. Kim1, E. K. Kim1, Y. G. Seo2 and S. M. Hwang2, 1Hanyang Univ. and 2Korea Electronics Tech. Inst. (Korea)
18:00 H-5-3 Enhanced Extraction and Efficiency of Blue Light Emitting Diodes Prepared using Two-Step-Etched Patterned Sapphire Substrates Y. C. Lu1, S. F. Yu2, Y. C. S. Wu3, C. H. Chiang1, W. C. Hsu4, S. J. Chang2 and R. M. Lin1, 1Chang Gung Univ., 2National Cheng Kung Univ., 3National Chiao Tung Univ. and 4Sino-American Silicon Products Inc. (Taiwan)
18:15 H-5-4 Improvement of the blue LED using patterned sapphire substrates with low threading dislocation densities S. M. Jeong1, S. Kissinger1, Y. H. Ra1, S. H. Yun1, D. W. Kim1, S. J. Lee2, J. S. Kim1 and C. R. Lee1, 1Chonbuk National Univ. and 2Korea Photonics Tech. Inst. (Korea)
18:30 H-5-5 Hexagonal AlN (0001) heteroepitaxial growth on cubic diamond (001) K. Hirama, Y. Taniyasu and M. Kasu, NTT Corp.(Japan)
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Area 9: Physics and Applications of Novel Functional Materials and Devices K-3: Electron Spin and Quantum Information 13:15-14:45 6F Aoi Chair: H. Gotoh (NTT Basic Res. Labs.) Sven Rogge (Delft Univ. of Tech.)
13:15 K-3-1 (Invited) Spin Read-Out of Donors in Silicon M. Brandt, Munich Univ. of Tech. (Germany)
13:45 K-3-2 Single-electron Spin Resonance in a g-factor-controlled Semiconductor Quantum Dot T. Kutsuwa1, M. Kuwahara1, K. Ono2 and H. Kosaka1,3, 1CREST-JST, 2RIKEN and 3Tohoku Univ. (Japan)
14:00 K-3-3 Electron - Nuclear Spin Interaction in Vertical Double Quantum Dot with Different g-factor Layers System R. Takahashi1,2, K. Kono1,2, S. Tarucha3,4 and K. Ono1,5, 1RIKEN, 2Tokyo Tech, 3Univ. of Tokyo, 4ICORP-JST and 5CREST-JST (Japan)
14:15 K-3-4 Robustness of Charge-qubit Cluster States to Double Quantum Point Contact Measurement T. Tanamoto, Toshiba Corp. (Japan) 14:30 K-3-5 Measurement of Electron Spin States in a Semiconductor Quantum well using Tomographic Kerr Rotation T. Inagaki1, H. Kosaka1,2, Y. Rikitake2,3, H. Imamura2,4, Y. Mitsumori1,2 and K. Edamatsu1, 1Tohoku Univ., 2CREST- JST, 3Sendai National College of Tech. and 4AIST (Japan) 15:00-15:45 Plenary Session
- 98 - Thursday, October 8
Area 9: Physics and Applications of Novel Functional Materials and Devices K-4: Nanomechanical Systems 16:00-17:15 6F Aoi Chair: D. G. Austing (National Res. Council of Canada) K. Ono (RIKEN)
16:00 K-4-1 (Invited) Electromechanical Systems for Memory and Logic Devices I. Mahboob and H. Yamaguchi, NTT Corp. (Japan)
16:30 K-4-2 Noise-enhanced Sensing using Micromechanical Nonlinear Resonator Y. Yoshida and T. Ono, Tohoku Univ. (Japan)
16:45 K-4-3 Carrier-induced Dynamic Backaction in GaAs Micromechanical Resonators H. Okamoto1, D. Ito1,2, K. Onomitsu1, H. Sanada1, H. Gotoh1, T. Sogawa1 and H. Yamaguchi1,2, 1NTT Basic Res. Labs. and 2Tohoku Univ. (Japan)
17:00 K-4-4 A Novel Thin-film Transistor with Suspended Nanowire Channels and Side-gated Configuration C. H. Kuo1, H. C. Lin1,2, G. J. Li1, H. H. Hsu1, C. J. Su1 and T. Y. Huang1, 1National Chiao Tung Univ. and 2National Nano Device Labs. (Taiwan) 17:15-17:30 Break
Area 9: Physics and Applications of Novel Functional Materials and Devices K-5: Novel Devices and Matarials 17:30-18:30 6F Aoi Chair: B. G. Park (Seoul National Univ.) M. Watanabe (Tokyo Tech)
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17:30 K-5-1 High hole current density in diamond MOSFETs fabricated on H-terminated IIa-type (111) diamond substrate K. Tsuge1, Y. Jingu1, H. Umezawa2 and H. Kawarada1, 1Waseda Univ. and 2AIST (Japan)
17:45 K-5-2 Performance Comparisons of Ballistic Silicon-Nanowire and Graphene Nanoribbon MOSFETs Considering First- Principles Bandstructure Effects H. Ando, S. Sawamoto, T. Maegawa, T. Hara, H. Yao, H. Tsuchiya and M. Ogawa, Kobe Univ. (Japan)
18:00 K-5-3 Formation of Highly B-doped Source & Drain Layers with TiC Ohmic Contacts for H-terminated Diamond MOSFETs T. Tsuno1, Y. Jingu1, H. Umezawa2 and H. Kawarada1, 1Waseda Univ. and 2AIST (Japan)
18:15 K-5-4 Cross-sectional Low-temperature Scanning Tunneling Spectroscopy of a p-n Junction and an Inversion Layer in InAs K. Suzuki, K. Kanisawa, K. Onomitsu and K. Muraki, NTT Basic Res.Labs. (Japan)
Area 10: Organic Materials Science, Device Physics, and Applications F-4: Organic Transistor 16:00-17:15 4F Hirose
16:00 F-4-1 (Invited) Surface-selective deposition for organic transistor K. Tsukagoshi1,2,3,4 and T. Minari1,3,4, 1MANA-NIMS, 2AIST, 3RIKEN and 4CREST-JST (Japan)
- 100 - Thursday, October 8
16:30 F-4-2 High-Speed Operation of Step-Edge Vertical-Channel Organic Transistors K. Kudo, T. Takano, H. Yamauchi, M. Iizuka and M. Nakamura, Chiba Univ. (Japan)
16:45 F-4-3 Demonstration of a Record High Current-gain Cutoff Frequency ( >10 MHz ) in Organic Thin-film Transistors M. Kitamura and Y. Arakawa, Univ. of Tokyo (Japan)
17:00 F-4-4 Tuning of Threshold Voltage in Organic Field-effect Transistor by Dipole Monolayer W. O. Yang, X. Chen, M. Weis, T. Manaka and M. Iwamoto, Tokyo Tech (Japan) 17:15-17:30 Break
Area 10: Organic Materials Science, Device Physics, and Applications F-5: Organic Transistor 17:30-18:30 4F Hirose
17:30 F-5-1 Organic Field Effect Transistors from Oriented Pentacene Crystal Fibers N. Wachi, H. Kubo, J. Nishide, H. Sasabe and O. Karthaus, Chitose Inst. of Sci. and Tech. (Japan)
17:45 F-5-2 Temperature Dependence of Electrical Properties of Ambipolar Organic Transistors based on F16CuPc/α6T pn Heterojunction R. Ye1, M. Baba1, K. Ohta1, T. Suzuki2 and K. Mori1, 1Iwate Univ. and 2Iwate Indus. Res. Inst. (Japan)
18:00 F-5-3 Organic Inverters with Double-gate Organic Thin-film
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Transistor using Photosensitive Polymer as the Dielectric Layer C. C. Wang, W. H. Lee, C. T. Liu and S. H. Hsu, National Cheng Kung Univ. (Taiwan)
18:15 F-5-4 Displacement Current and Transfer Curve Simultaneous Measurement in Bottom-Contact Organic Thin-film Transistors S. Suzuki, T. Suzuki, A. Bhaswara and Y. Majima, Tokyo Tech (Japan)
Area 13: Applications of Nanotubes and Nanowires I-4: Compound Semiconductor Nanowires 16:00-17:15 6F Kaede Chair: K. Tateno (NTT Basic Res. Labs.) K. Ishibashi (RIKEN)
16:00 I-4-1 (Invited) Giant, Level-dependent electron g-factors and Kondo physics in few-electron InSb nanowire quantum dots H. Xu, Lund Univ. (Sweden)
16:30 I-4-2 Fabrication of InAs Nanowire Vertical Surrounding-Gate Field Effect Transistor on Si Substrates T. Tanaka, K. Tomioka, J. Motohisa, S. Hara and T. Fukui, Hokkaido Univ. (Japan)
16:45 I-4-3 Design and Fabrication of BDD-based Reconfigurable Logic Circuit on GaAs Nanowire Network Y. Shiratori1, K. Miura1 and S. Kasai1,2, 1Hokkaido Univ. and 2PRESTO-JST (Japan)
17:00 I-4-4 Preparation of NiO/ZnO Nanoheterojunction Arrays and Their Optoelectric Characteristics under UV Light Illumination W. C. Tsai1, S. J. Wang1, J. C. Lin2, C. R. Tseng1,
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F. S. Tsai1 and W. I. Hsu1, 1National Cheng Kung Univ. and 2St. John's Univ. (Taiwan)
Rump Session 19:00-21:30 Session A (4F Hirose-Higashi) "Novel Lithography for more Moore/beyond CMOS and More than Moore" Session B (4F Hirose-Nishi) "Solar Cells for Electronics : from In-Vehicleto Ubiquitous"
- 103 - Friday, October 9
Area 1&3: Joint Session C-7: FinFETs and Multi-Gate FETs 10:45-12:15 2F Heisei
10:45 C-7-1 (Invited) Characteristics and Integration Challenges of FinFET- based Devices for (Sub-)22nm Technology Nodes Circuit Applications A. Veloso1, M..J. H. Van Dal2, N. Collaert1, A. De Keersgieter1, L. Witters1, R. Rooyackers1, A. Redolfi1, S. Brus1, R. Duffy2, B. J. Pawlak2, G. Vellianitis2, B. Duriez2, T. Mérelle2, P. P. Absil1, S. Biesemans1, M. Jurczak1, T. Hoffmann1 and R. J. P. Lander2, 1IMEC and 2NXP-TSMC Res. Center (Belgium)
11:15 C-7-2 High-Performance three-terminal FinFETs by Combination of Damage-Free Neutral-Beam Etching and Neutral-Beam Oxidation Technologies K. Sano1, M. Yonemoto1, A. Wada1, K. Endo2, T. Matsukawa2, M. Masahara2 and S. Samukawa1, 1Tohoku Univ. and 2AIST (Japan)
11:35 C-7-3 Investigation of Low-Energy Tilted Ion Implantation for FinFET Extension Doping Y. X. Liu, T. Matsukawa, K. Endo, S. O'uchi, K. Sakamoto, J. Tsukada, Y. Ishikawa, H. Yamauchi and M. Masahara, AIST (Japan)
11:55 C-7-4 Impact of Attractive Ion in Undoped Channel on the Characteristics of Nanoscale Multi-Gate FETs: A 3D NEGF Study Y. Kamakura, G. Mil'nikov, N. Mori and K. Taniguchi, Osaka Univ. (Japan)
- 104 - Friday, October 9
Area 1&3: Joint Session B-9: Device Reliability 15:20-17:10 2F Heisei
15:20 B-9-1 (Invited) On the Reliability of and Self-Compensation in Strained Transistors M. A. Alam and A. E. Islam, Purdue Univ. (USA)
15:50 B-9-2 Decoupling method of BTI component from hot carrier degradation in ultra-thin HfSiON MOSFETs A. Masada, I. Hirano, S. Fukatsu and Y. Mitani, Toshiba Corp. (Japan)
16:10 B-9-3 Study of Negative Vth Shift in PBTI and Positive Shift in NBTI for Yttrium Doped HfO2 Gate Dielectrics M. Sato, S. Kamiyama, T. Matsuki, D. Ishikawa, T. Ono, T. Morooka, J. Yugami, K. Ikeda and Y. Ohji, Selete (Japan)
16:30 B-9-4 Forward Body Bias Enhanced NBTI Recovery on pMOSFETs Y. He, G. Du, Y. X. Yang and G. Zhang, Peking Univ. (China)
16:50 B-9-5 The Simulation of ESD Protection Devices Fabricated in Multiple-Gate FETs D. Hagishima and K.Matsuzawa, Toshiba Corp. (Japan)
Area 1: Advanced Gate Stack / Si Processing & Material Science B-6: Epitaxy 9:00-10:20 2F Heisei
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B. Mizuno (UJT Lab. Inc.)
9:20 B-6-2 Impact of Very Low Series Resistance due to Raised Metal S/D Structure with Very Low Contact Resistance Silicide for sub-100-nm nMOSFET R. Kuroda, T. Isogai, H. Tanaka, Y. Nakao, A. Teramoto, S. Sugawa and T. Ohmi, Tohoku Univ. (Japan)
9:40 B-6-3 First LSI Applicable Thin SOI Films Formed by Lateral Solid Phase Epitaxy H. Ishida, F. Aiso, M. Mizukami, K. Nishihara, T. Iguchi, D. Ichinose, A. Fukumoto, T. Suzuki, F. Arai and I. Mizushima, Toshiba Corp. (Japan)
10:00 B-6-4 High Hole Mobilities in Single-Crystalline Ge Thin-Films on Insulating Substrate Formed by SiGe Mixing-Triggered Directional Melting-Growth K. Toko, T. Tanaka, T. Sadoh and M. Miyao, Kyushu Univ. (Japan) 10:20-10:35 Break
Area 1: Advanced Gate Stack / Si Processing & Material Science B-7: Ge-MOS 10:35-12:15 2F Heisei
10:35 B-7-1 High Electron Mobility Ge n-Channel MOSFETs with GeO2 grown by High Pressure Oxidation C. H. Lee1, T. Nishimura1,2, T. Tabata1,2, K. Nagashio1,2, K. Kita1,2 and A. Toriumi1,2, 1Univ. of Tokyo2 and CREST- JST (Japan)
10:55 B-7-2 18 O isotope tracing Study of GeO Desorption from GeO2/
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Ge Structure S. Wang1, K. Kita1,2, T. Nishimura1,2, K. Nagashio1,2 and A. Toriumi1,2, 1Univ. of Tokyo and 2CREST-JST (Japan)
11:15 B-7-3 Diffusion control of n-type impurities in Ge using co- doping technique for ultra-shallow and highly doped n+/p junction in Ge nMOSFETs M. Koike1 and K. Tatsumura2, 1MIRAI-Toshiba and 2Toshiba Corp. (Japan)
11:35 B-7-4 Effects of MIS Interfacial Layers on Interface Trap Density near Conduction Band Edge in Ge MIS Structures N. Taoka1, W. Mizubayashi1, Y. Morita1, S. Migita1, H. Ota1 and S. Takagi1,2, 1MIRAI-AIST and 2Univ. of Tokyo (Japan)
11:55 B-7-5 Spectroscopic Ellipsometry Study on Defects Generation in GeO2/Ge stacks K. Kita1,2, M. Yoshida1, T. Nishimura1,2, K. Nagashio1,2 and A. Toriumi1,2, 1Univ. of Tokyo and 2CREST-JST (Japan) 12:15-13:15 Lunch
Area 1: Advanced Gate Stack / Si Processing & Material Science B-8: Doping Technology 13:15-15:05 2F Heisei
13:15 B-8-1 (Invited) Process Condition Dependence of Random VT Variability in NFETs and PFETs T. Tsunomura1, A. Nishida1, K. Takeuchi1, S. Inaba1, S. Kamohara1, K. Terada2, T. Hiramoto1,3 and T. Mogami1, 1MIRAI-Selete, 2Hiroshima City Univ. and 3Univ. of Tokyo (Japan)
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13:45 B-8-2 Comprehensive Design Methodology of Extension Profile to Suppress Boron TED in High Performance High-k/ Metal SiGe pMOSFETS C. Y. Kang1, Y. H. Kim2, M. S. Park3, J. W. Oh1, B. G. Min4, K. S. Lee4, S. K. Banerjee2, P. Majhi1, H. H. Tseng1 and R. Jammy1, 1SEMATECH, 2Univ. of Texas at Austin, 3POSTECH and 4Jusung Engineering (USA)
14:05 B-8-3 Leakage Reduction by Thermal Annealing of NiPtSi Silicided Junctions and Anomalous Spider-Web of In- Layer Pt Network M. Tsuchiaki and A. Nishiyama, Toshiba Corp. (JAPAN)
14:25 B-8-4 Concentration of Active Dopants at NiSi/Si Interface Segregated by "Snowplow" Effect for Schottky Barrier Height Tuning S. Migita, Y. Morita, N. Taoka, W. Mizubayashi and H. Ota, MIRAI-AIST (Japan)
14:45 B-8-5 Activation of B and As in Ultra Shallow Junction with Heating and Cooling Rates Controlled Millisecond Annealing Induced by Thermal Plasma Jet K. Matsumoto, S. Higashi, H. Furukawa, T. Okada, H. Murakami and S. Miyazaki, Hiroshima Univ. (Japan)
Area 2: Characterization and Materials Engineering for Interconnect Integration D-8: Advanced Material/Process Technology 13:15-15:05 3F Sakura Chair: M. Nihei (Fujitsu Labs. Ltd.) M. Matsuura (Renesas Tech. Corp.)
13:15 D-8-1 (Invited) Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects K. Banerjee, H. Li and C. Xu, Univ. of California-Santa
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Barbara (USA)
13:45 D-8-2 High Current Reliability of Carbon Nanotube Via Interconnects M. Sato, T. Hyakushima, A. Kawabata, T. Nozue, S. Sato, M. Nihei and Y. Awano, MIRAI-Selete (Japan)
14:05 D-8-3 Effect of UV Photons and Radicals for Low-Frequency Line-Edge Roughness (LER) of ArF Photo-resist during Fluorocarbon plasma etching B. Jinnai1, E. Soda1,2, K. Koyama1, S. Saito2 and S. Samukawa1, 1Tohoku Univ. and 2Selete (Japan)
14:25 D-8-4 Hard Mask through UV Light-induced Damage to Low-k Film During Plasma Process for Dual Damascene N. Matsunaga1,2, H. Okumura1, B. Jinnai1 and S. Samukawa1, 1Tohoku Univ. and 2Toshiba Corp. (Japan)
14:45 D-8-5 Super-Low-k SiOCH Film (k=1.9) with High Water Resistance and High Thermal Stability Formed by Neutral- Beam-Enhanced-CVD T. Sasaki1, S. Yasuhara1, T. Shimayama2, K. Tajima2, H. Yano2, S. Kadomura2, M. Yoshimaru2, N. Matsunaga2 and S. Samukawa1, 1Tohoku Univ. and 2STARC (Japan) 15:05-15:15 Break
Area 2: Characterization and Materials Engineering for Interconnect Integration D-9: Characterization and Reliability for Low-k Materials 15:15-17:05 3F Sakura Chair: S. Ogawa (Selete) K. Ito (Kyoto Univ.)
15:15 D-9-1 (Invited) The Helium Ion Microscope for Interconnect Material
- 109 - Friday, October 9
Imaging W. Thompson1, S. Ogawa2, L. Stern1, L. Scipioni1, J. Notte1, L. Farkas1 and L. Barriss1, 1Carl Zeiss SMT and 2Selete (USA)
15:45 D-9-2 Relative Density Characterization of Patterned Low-k material by VEELS Y. Otsuka1, Y. Shimizu1, N. Kawasaki1 and S. Ogawa2, 1Toray Res. Center, Inc. and 2Selete (Japan)
16:05 D-9-3 Evaluation of Dielectric Constant through Direct CMP of Porous Low-k Film M. Kodera, T. Takahashi and G. Minamihaba, Toshiba Corp. (Japan)
16:25 D-9-4 Prediction of Abnormal Etching Profile at High-Aspect- Ratio Via/ Hole Etching by using On-wafer Monitoring System H. Ohtake1, S. Fukuda1, B. Jinnai1, T. Tatsumi2 and S. Samukawa1, 1Tohoku Univ. and 2OKI Semiconductor Miyagi Co. Ltd. (Japan)
16:45 D-9-5 Integration and dielectric reliability of 30nm ½ pitch structures in Aurora ®LK HM S. Demuynck1, C. Huffman1, M. Claes1, S. Suhard1, J. Versluijs1, H. Volders1, N. Heylen1, K. Kellens1, K. Croes1, H. Struyf1, G. Vereecke1, P. Verdonck1, D. De Roest2, J. Beynet2, H. Sprey2 and G. P. Beyer1, 1IMEC and 2ASM Belgium (Belgium)
Area 3: CMOS Devices /Device Physics C-6: High-k/Metal-Gate 9:00-10:20 2F Heisei
- 110 - Friday, October 9
9:00 C-6-1 Optimization of Bulk+/SON Integration for Low Stand-by Power (LstP) Applications F. Boeuf1, G. Bidal1,2, S. Denorme1, J. L. Huguenin1,2, S. Monfray1, D. Chanemougame1, N. Loubet1 and T. Skotnicki1, 1STMicroelectronics and 2IMEP-LAHC MINATEC (France)
9:20 C-6-2 Sub-30 nm CMOSFET with Ni(Pt)-FUSI/SiON Gate Stack H. Fukutome, K. Okubo, S. Akiyama, N. Idani, H. Ohta, K. Kawamura, Y. Momiyama and S. Satoh, Fujitsu Microelectronics Ltd. (Japan)
9:40 C-6-3 Novel Single Metal Gate CMOS Integration with Effective Workfunction Modulation by a Differential Spacer: Manipulation of Oxygen Vacancy Y. H. Kim, K. Schonenberg, T. Ando, D. Neumayer, R. Mo, H. Bu, J. Sleight, E. Cartier, N. Moumen, R. Jha, W. Yan, Y. Liang, V. Narayanan, M. P. Chudzik and S. Guha, IBM (USA)
10:00 C-6-4 High Performance High-K Metal-Gate Poly-Si TFTs with Subthreshold Swing < 200 mV/dec for Monolithic 3D Integrated Circuits Applications M. H. Lee1, K. J. Chen1, S. C. Weng1, W. H. Liu1, M. J. Yang2, C. T. Shih3, L. S. Lee3 and M. J. Kao3, 1National Taiwan Normal Univ., 2National Nano Device Labs. and 3Indus. Tech. Res. Inst. (Taiwan)
Area 3: CMOS Devices /Device Physics C-8: Transport Physics 13:15-14:35 2F Heisei
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13:15 C-8-1 Impact of Coulomb Scattering on the Characteristics of Nanoscale Devices F. Boeuf1, G. Ghibaudo2 and T. Skotnicki1, 1STMicroelectronics and 2IMEP-LAHC MINATEC(France)
13:35 C-8-2 Comprehensive Study on Electron Mobility and Band Gap in Tensile Strained Ge M. Ono and T. Tezuka, MIRAI-Toshiba (Japan)
13:55 C-8-3 Inversion-Layer Mobility Limited by Coulomb Scattering on Si (100), (110) and (111) n-MOSFETs Y. Nakabayashi1, T. Ishihara1, T. Numata1, K. Uchida2 and S. Takagi3, 1Toshiba Corp., 2Tokyo Tech and 3Univ. of Tokyo (Japan)
14:15 C-8-4 Experimental Study on Hall Factor in Ultrathin-Body SOI n-MOSFETs S. Kobayashi1, M. Saitoh1, Y. Nakabayashi1, T. Ishihara1, T. Numata1 and K. Uchida2, 1Toshiba Corp. and 2Tokyo Tech (Japan)
Area 4: Advanced Memory Technology G-6: FeRAM/MRAM 9:00-10:40 4F Hirose
9:00 G-6-1 (Invited) Overview and Future Challenges of High Density FeRAM I. Kunishima, Y. Shimojo, A. Konno, J. Nishimura, T. Okada, H. Nakaki, Y. Yamada, S. Kitazaki, H. Furuhashi, Y. Minami, H. Kanaya, S. Shuto, K. Tomioka, K. Natori, K. Yamakawa, S. Shiratake, D. Takashima, T. Hamamoto, Y. Watanabe and A. Nitayama, Toshiba Corp. (Japan)
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9:30 G-6-2 A Negative Word-line Voltage Step-Down Erase Pulse 1 Scheme with ΔVTH= －6 ΔVERASE for Enterprise SSD Application Ferroelectric(Fe)-NAND Flash Memories R. Yajima1, T. Hatanaka1, M. Takahashi2, S. Sakai2 and K. Takeuchi1, 1Univ. of Tokyo and 2AIST (Japan)
9:50 G-6-3 (Invited) Advancements and Future Challenges of Spin Torque Transfer MRAM H. Yoda1, T. Kishi1, M. Yoshikawa1, T. Nagase1, K. Nishiyama1, E. Kitagawa1, T. Daibou1, M. Amano1, N. Shimomura1, S. Takahashi1, T. Kai1, M. Nakayama1, H. Aikawa1, S. Ikegawa1, M. Nagamine1, J. Ozeki1, S. Yuasa2, M. Oogane3, S. Mizukami3, Y. Ando3, Y. Suzuki4, Y. Nakatani5, T. Miyazaki3 and K. Ando2, 1Toshiba Corp., 2AIST, 3Tohoku Univ., 4Osaka Univ. and 5Univ. of Electro- comminumations (Japan)
10:20 G-6-4 Effect of Self-heating on TDDB in Ultra-thin MgO Magnetic Tunnel Junctions for Spin MRAM K. Hosotani, M. Nagamine, T. Ueda, H. Aikawa, S. Ikegami, Y. Asao, H. Yoda and A. Nitayama, Toshiba Corp. (Japan) 10:40-10:45 Break
Area 4: Advanced Memory Technology G-7: ReRAM 10:45-12:15 4F Hirose
10:45 G-7-1 (Invited) Switching Mechanism of TaOx ReRAM Z. Wei, Y. Kanzawa, K. Arita, Y. Katoh, S. Muraoka, S. Mitani, S. Fujii, K. Katayama, T. Ninomiya and T. Takagi, Panasonic Corp. (Japan)
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11:15 G-7-2 Physical model for reset state of Ta2O5/TiO2 stacked ReRAM Y. Sakotsubo, M. Terai, S. Kotsuji, T. Sakamoto and H. Hada, NEC Corp. (Japan)
11:35 G-7-3 High-Speed Multilevel Resistive RAM using RTO WOX W. C. Chien1,2, Y. C Chen1, E. K. Lai1,3, Y. Y. Lin1, K. P. Chang1, Y. D. Yao2, P. Lin2, S. F. Horng3, J. Gong3, S. C. Tsai1, C. H. Lee1, S. H. Hsieh1, C. F. Chen1, Y. H. Shih1, K. Y. Hsieh1, R. Liu1 and C. Y. Lu1, 1Macronix Int'l Co., Ltd., 2National Chiao Tung Univ. and 3National Tsing Hua Univ. (Taiwan)
11:55 G-7-4 Impact of Oxygen Vacancy on Interfacial Band Diagram Ti/Pr1-xCaxMnO3 Resistive Switching Junctions S. Asanuma1, H. Yamada1, H. Akoh1,2 and A. Sawa1, 1AIST and 2JST (Japan)
Area 5: Advanced Circuits and Systems D-6: Image Sensing Devices 9:00-10:30 3F Sakura Chair: S. Kawahito (Shizuoka Univ.) T. Hamasaki (Texas Instruments Japan Ltd.)
9:00 D-6-1 (Invited) Recent Progress in High-Resolution and High-Speed CMOS Image Sensor Technology I. Takayanagi and J. Nakamura, Aptina Japan, LLC. (Japan)
9:30 D-6-2 Pixel Scaling in CMOS Image Sensors with Lateral Overflow Integration Capacitor Y. Tashiro1, S. Sakai1, S. Kawada1, R. Kuroda1, N. Akahane2, K. Mizobuchi2 and S. Sugawa1, 1Tohoku Univ. and 2Texas Instruments Japan Ltd. (Japan)
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9:50 D-6-3 WRGB LOFIC CMOS Image Sensor with Color- Independent Exposure and Widely-Spectral High Sensitivity S. Kawada, S. Sakai, Y. Tashiro and S. Sugawa, Tohoku Univ. (Japan)
10:10 D-6-4 Current-Mode Multiple-Resolution Edge-Filtering CMOS Image Sensor Employing Self-Similitude Processing N. Takahashi and T. Shibata, Univ. of Tokyo (Japan) 10:30-10:45 Break
Area 5: Advanced Circuits and Systems D-7: Physical Subjects for Low-power Circuit/Device Design 10:45-12:05 3F Sakura Chair: T. Matsuoka (Osaka Univ.) T. Koide (Hiroshima Univ.)
10:45 D-7-1 A Reference CMOS Circuit Structure for Evaluation of Dynamic Voltage Variation in Power Delivery Networks T. Matsuno1, D. Kosaka1 and M. Nagata1,2, 1Kobe Univ. and 2CREST-JST (Japan)
11:05 D-7-2 Substrate Noise Analysis of Digital Circuits to Optimize Substrate-Contact Space S. Komatsu1, M. Yamaoka1, Y. Kanno1, Y. Yasu2, K. Ishibashi2 and K. Osada1, 1Hitachi, Ltd. and 2Renesas Tech. Corp. (Japan)
11:25 D-7-3 Within-Die/Wafer Variation Analysis of Basic CMOS Circuits based on Surface-Potential-Model HiSIM2 K. Johguchi, A. Kaya, S. Izumi, H. J. Mattausch, T. Koide and N. Sadachika, Hiroshima Univ. (Japan)
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11:45 D-7-4 Random Telegraph Signal and Flicker Noise In CMOS Image Sensor using Column Source Follower Readout Circuits T. Kohara1, W. Lee1, K. Mizobuchi2 and S. Sugawa1, 1Tohoku Univ. and 2Texas Instruments Japan Ltd. (Japan)
Area 6: Compound Semiconductor Circuits, Electron Devices and Device Physics G-8: GaN Processing and Interface Technologies 13:15-15:15 4F Hirose
13:15 G-8-1 (Invited) Advances In High Power Density GaN Transistors Y. F. Wu, Transphorm Inc. (USA)
13:45 G-8-2 Chemical and Electronic Properties of ALD-Al2O3/AlGaN Interfaces Y. Hori1, C. Mizue1, K. Ooyama1, M. Miczek2 and T. Hashizume1, 1Hokkaido Univ. and 2Silesian Univ. of Tech. (Japan)
14:00 G-8-3 Metal-Gate/High-Permittivity Dielectric Stack on Gallium Nitride formed by Silane Surface Passivation and Metal- Organic Chemical Vapor Deposition X. Liu, H. C. Chin, L. S. Tan and Y. C. Yeo, National Univ. of Singapore (Singapore)
14:15 G-8-4 Electrical Properties of Metal-Insulator-Semiconductor Capacitors on Freestanding GaN Substrate E. Kim, N. Soejima, Y. Watanabe, M. Ishiko and T. Kachi, Toyota Central R&D Labs., Inc. (Japan)
14:30 G-8-5 MIS Diode Characterization on n-GaN by C-V
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Measurement at 150 ℃ C. Y. Hu, H. Nokubo, M. Okada, J. P. Ao and Y. Ohno, Univ. of Tokushima (Japan)
14:45 G-8-6 Low Resistivity V/Al/Mo/Au Ohmic Contacts on AlGaN/ GaN Annealed at Low Temperatures N. Yafune1,3, M. Nagamori2, F. Watanabe2, K. Sakuno1 and M. Kuzuhara2, 1Sharp Corp., 2Univ. of Fukui and 3JRCM (Japan)
15:00 G-8-7 Electrochemical Oxidation of GaN for Surface Control of GaN-based Device Structures N. Harada, N. Shiozaki, E. Ogawa and T. Hashizume, Hokkaido Univ. (Japan)
Area 7: Photonic Devices and Device Physics I-6: Quantum Dot Devices 9:00-10:30 6F Kaede Chair: O. Wada (Kobe Univ.) M. Sugawara (Fujitsu Labs. Ltd.)
9:00 I-6-1 (Invited) Quantum Dot Lasers. Commercial Challeges and Opportunities A. Kovsh, Innolume GmbH (Germany)
9:30 I-6-2 Influence of Cavity Mode Emission on Single Photon Generation in Quantum-Dot-Cavity Systems T. Tawara1, H. Kamada1, S. Hughes2, H. Okamoto1, M. Notomi1 and T. Sogawa1, 1NTT Corp. and 2 Queen's Univ. (Japan)
9:45 I-6-3 Optical Mode-selection of Quantum Dot Frequency Comb Laser for 1-μm Waveband Optical Communications N. Yamamoto1, K. Akahane1, T. Kawanishi1, R. Katouf1 and H. Sotobayashi1,2, 1NICT and 2Aoyama Gakuin Univ.
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(Japan)
10:00 I-6-4 Quantum Dots in a Vertical Cavity for All-Optical Switching Devices C. Y. Jin1, O. Kojima1, T. Kita1, O. Wada1, M. Hopkinson2 and K. Akahane3, 1Kobe Univ., 2Univ. of Sheffield and 3NICT (Japan)
10:15 I-6-5 A GaAs/AlAs Multilayer Cavity with InAs Quantum Dots Embedded in Strain-relaxed Barriers for Planar-type Optical Kerr Gate Switches T. Takahashi, T. Mukai, K. Morita, T. Kitada and T. Isu, Univ. of Tokushima (Japan) 10:30-10:45 Break
Area 7: Photonic Devices and Device Physics I-7: Photo Diodes 10:45-12:15 6F Kaede Chair: R. Akimoto (AIST) M. Ezaki (Toshiba Corp.)
10:45 I-7-1 A 5 Gb/s CMOS Photodiode with High Responsivity of 2.49 A/W G. Y. Chen, F. P. Chou, W. K. Huang and Y. M. Hsin, National Central Univ. (Taiwan)
11:00 I-7-2 A High-responsivity of 4.1 A/W Si PD with BJT Amplifier in Standard CMOS Process F. P. Chou, G. Y. Chen and Y. M. Hsin, National Central Univ. (Taiwan)
11:15 I-7-3 Thermal Stability of Germanium Quantum Dots Phototransistors for Near Ultra-violet Applications I. H. Chen, S. S. Tseng and P. W. Li, National Central Univ. (Taiwan)
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11:30 I-7-4 Color Selective Design for Quantum Dot Infrared Photodetectors J. H. Lee1, Y. T. Chang1, S. Y. Lin2 and S. C. Lee1, 1National Taiwan Univ. and 2Academia Sinica (Taiwan)
11:45 I-7-5 Low-noise p-GaN/i-ZnO/n-ZnO:Al Ultraviolet Photodetectors using Vapor Cooling Condensation Technique C. H. Chen, T. H. Lee, B. J. Li and C. T. Lee, National Cheng Kung Univ. (Taiwan)
12:00 I-7-6 Accurate Prediction of Photocurrent Response for High Performance Optoelectric Circuit Simulation Y. Shintaku, S. Kusu, T. Miyoshi, M. Miyake, N. Sadachika, K. Konno, G. Suzuki and M. Miura-Mattausch, Hiroshima Univ. (Japan) 12:15-13:15 Lunch
Area 7: Photonic Devices and Device Physics I-8: LED II 13:15-15:15 6F Kaede Chair: M. Ezaki (Toshiba Corp.) H. Isshiki (The Univ. of Electro-Communications)
13:15 I-8-1 High Efficiency Blue Light Emitting Diodes with Maskless Defects Passivation layer C. H. Wang1, M. H. Lo1, P. M. Tu1, C. W. Hung1, S. C. Hsu2, Y. J. Cheng1,2, H. C. Kuo1, H. W. Zan1, S. C. Wang1, C. Y. Chang1 and C. M. Liu3, 1National Chiao Tung Univ., 2Academia Sinica and 3Sino-American Silicon Products Inc. (Taiwan)
13:30 I-8-2 Enhanced Luminescence Efficiency of InGaN/GaN Multiple Quantum Wells by A Strain Relief Layer and Proper Si Doping
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P. C. Tsai, Y. K. Su and C. Y. Huang, National Cheng Kung Univ. (Taiwan)
14:00 I-8-4 Light Extraction Enhancement of Wafer-Bonded AlGaInP- based Light-Emitting Diodes with Micro- and Nano-Scale Patterned Surface B. S. Cheng, Y. C. Lee, H. C. Kuo, T. C. Lu and S. C. Wang, National Chiao Tung Univ. (Taiwan)
14:15 I-8-5 Novel Stacked Polychromatic Light-emitting Diodes K. N. Hui1,2, X. H. Wang2, Z. L. Li2, P. T. Lai2 and H. W. Choi2, 1State Univ. of New Jersey and 2Univ of Hong Kong (USA)
14:30 I-8-6 Investigation of ZnO P-I-N Light-emitting Diodes Y. H. Lin, L. W. Lai, L. R. Lou and C. T. Lee, National Cheng Kung Univ. (Taiwan)
14:45 I-8-7 Light-emitting Diode based on ZnO by Plasma Enhanced MOCVD Employing Microwave Exited Plasma H. Asahara1,2, D. Takamizu2, A. Inokuchi1,3, M. Hirayama1, A. Teramoto1 and T. Ohmi1, 1Tohoku Univ., 2ROHM Co., Ltd. and 3Tokyo Electron Ltd. (Japan)
15:00 I-8-8 The Characteristics of Cavity Mode in Trilayer Dielectric/ Metal/Dielectric Plasmonic Thermal Emitter Y. W. Jiang, D. C. Tzuang, Y. T. Wu, M. W. Tsai and S. C. Lee, National Taiwan Univ. (Taiwan) 15:15-15:30 Break
Area 7: Photonic Devices and Device Physics I-9: Nonliner Optical Devices 15:30-16:45 6F Kaede Chair: R. Akimoto (AIST) O. Wada (Kobe Univ.)
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15:30 I-9-1 Novel Second Harmonic Generation Optical Devices by using Nano-Domain Engineering M. Minakata1, H. Awano1, M. Ohotsuka1, F. Iwata1 and T. Taniuchi2, 1Shizuoka Univ. and 2Tohoku Univ. (Japan)
15:45 I-9-2 Strong Sum Frequency Generation in a GaAs/AlAs Coupled Multilayer Cavity Grown on a (113)B-oriented GaAs Substrate F. Tanaka, T. Takahashi, K. Morita, T. Kitada and T. Isu, Univ. of Tokushima (Japan)
16:00 I-9-3 ZnO Channel Waveguides for Nonlinear Optic Applications Y. Morales, T. Kita, A. Tsukazaki, M. Kawasaki, Y. Ohtera and H. Yamada, Tohoku Univ. (Japan)
16:15 I-9-4 Evidence of Carrier Accumulation Effects on the Response Enhancement in Thin-Film Electrochromic Devices H. Yoshimura1, Y. Tsuchiya2, H. Mizuta2 and N. Koshida1, 1Tokyo Univ. of Agri. and Tech. and 2Southampton Univ. (Japan)
16:30 I-9-5 Accurate Measurement of Nonlinear Optical Coefficients of Gallium Nitride M. Abe1, H. Sato2, J. Suda3, M. Yoshimura4, Y. Kitaoka4, Y. Mori4, I. Shoji2 and T. Kondo1, 1Univ. of Tokyo, 2Chuo Univ., 3Kyoto Univ. and 4Osaka Univ. (Japan)
Area 9: Physics and Applications of Novel Functional Materials and Devices G-9: Physics and Applications of Graphene 15:30-17:15 4F Hirose
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15:30 G-9-1 (Invited) AFM Nanolithography of Grapheme L. Rokhinson, L. Weng, L. Zhang and Y. P. Chen, Purdue Univ. (USA)
16:00 G-9-2 Graphene Channel Field-Effect Transistors with Schottky Tunneling Source and Drain J. Zhu and J. C. S. Woo, UCLA (USA)
16:15 G-9-3 Computational Study of Edge Roughness Effect on the Device Performance of Graphene Nanoribbon Resonant Tunneling Diodes S. B. Khalid, K. T. Lam and G. Liang, National Univ. of Singapore (Singapore)
16:30 G-9-4 Performance Evaluation of Graphene Nanoribbon Tunneling Field Effect Transistors K. T. Lam1, S. B. Kumar1, S. K. Chin2, D. W. Seah1 and G. Liang1,2, 1National Univ. of Singapore and 2Inst. of High Performance Computing (Singapore)
16:45 G-9-5 Self-Excitation of Terahertz Plasma Oscillations in Optically Pumped Graphene V. Ryzhii1,3, M. Ryzhii1,3, A. Satou1,3, E. M. Amine2 and T. Otsuji2,3, 1Univ. of Aizu, 2Tohoku Univ. and 3CREST-JST (Japan)
Area 10: Organic Materials Science, Device Physics, and Applications F-6: Organic Transistor 9:00-10:30 4F Hirose
9:00 F-6-1 (Invited) Roll-to-Roll Printable 13.56 MHz Operated RFID Tags on
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Plastic Foils M. Jung1,2, J. Kim2, N. Lim2, J. Kim3, H. Kang2, C. Lim1,2, K. Lee,1, A. Leonard3, J. M. Tour3 and G. Cho1,2, 1Sunchon National Univ., 2Paru Co., and 3Rice Univ. (Korea)
9:30 F-6-2 Fabrication of Flexible EPD Panel using the Solution Processable OTFT M. W. Lee, M. Y. Lee, J. C. Choi, J. S. Park and C. K. Song, Dong-A Univ. (Korea)
9:45 F-6-3 Current Reduction Mechanism of Organic Thin Film Transistor Y. Ishikawa, Y. Wada, K. Tsutsui and T. Toyabe, Toyo Univ. (Japan)
10:00 F-6-4 Characteristics of Top-Gate Type Ambipolar Organic Field-Effect Transistors using Polyfluorene Derivatives H. Kajii, K. Koiwai, Y. Hirose and Y. Ohmori, Osaka Univ. (Japan)
10:15 F-6-5 Polymer Field Effect Transistors of Polyfluorene Prepared by Evaporative Spray Deposition using Ultradilute Solution K. Sagane, M. Shakutsui and K. Fujita, Kyushu Univ. (Japan) 10:30-10:45 Break
Area 10: Organic Materials Science, Device Physics, and Applications F-7: Organic Electronics & Transistor 10:45-12:00 4F Hirose
10:45 F-7-1 Coulomb Blockade Electron Shuttle with Chemisorbed Au
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Nanodot Y. Azuma1,2, N. Kobayashi1,2, M. Kanehara2,3, T. Teranishi2,3, S. Chorley4, J. Prance4, C. G. Smith4 and Y. Majima1,2, 1Tokyo Tech, 2CREST-JST, 3Univ. of Tsukuba and 4Univ. of Cambridge (Japan)
11:00 F-7-2 Molecular relaxation dynamics in molecular tunnel junctions N. Clement1, S. Pleutin1, D. Guerin1, D. Cahen2 and D. Vuillaume1, 1CNRS IEMN and 2Weizmann Inst. Of Sci. (France)
11:15 F-7-3 Study of Injected Carrier Energetics in Organic-field- effect-transistor by Charge Modulation Spectroscopy R. Miyazawa, D. Taguchi, M. Weis, T. Manaka and M. Iwamoto, Tokyo Tech (Japan)
11:30 F-7-4 Effect of SAM Modification on ITO Surface for UV- Assisted Vapor Deposition of Carbazole Thin Films Y. Umemoto1, S. H. Kim1, R. C. Advincula2, K. Tanaka1 and H. Usui1, 1Tokyo Univ. Agri. and Tech. and 2Univ. of Houston (Japan)
11:45 F-7-5 Interface Trap Reduction based on Poly(styrene-co-methyl methacrylate)/Hafnium Oxide Bilayer Dielectrics for Low Voltage OTFT T. H. Huang1, Z. Pei1, W. K. Lin1, S. T. Chang1 and K. C. Liu2, 1National Chung Hsing Univ. and 2Chang Gung Univ. (Taiwan) 12:00-13:15 Lunch
Area 10: Organic Materials Science, Device Physics, and Applications F-8: Organic Electronics & Photonics 13:15-15:15 4F Hirose
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S. Aratani (Hitachi, Ltd.)
13:15 F-8-1 Liquid Phase Crystal Growth of an Alternating Co- Oligomer Composed of Thiophene and Phenylene Rings T. Yamao1, Y. Nishimoto1, H. Akagami1, T. Katagiri1,2 and S. Hotta1, 1Kyoto Inst. of Tech. and 2Sumitomo Seika Chemicals Co., Ltd. (Japan)
13:30 F-8-2 Preparation of Electrospun Polymer Fibers using a Copper Wire Electrode in a Capillary Tube K. Shinbo, S. Onozuka, R. Hoshino, Y. Mizuno, Y. Ohdaira, A. Baba, K. Kato and F. Kaneko, Niigata Univ. (Japan)
13:45 F-8-3 Change and Field Modulation Spectroscopy on Pentacene Thin-Film Devices S. Haas1, H. Matsui1,2, T. Yamada1 and T. Hasegawa1, 1AIST and 2Univ. of Tokyo (Japan)
14:00 F-8-4 Surface Plasmon Resonance Sensor using Grating Coupling Multimode Excitations R. Yamazaki1, A. Baba1, K. Shinbo1, K. Kato1, F. Kaneko1, S. Samanta2 and J. Locklin2, 1Niigata Univ. and 2Univ. of Georgia (Japan)
14:15 F-8-5 Oriented Growth of Sexithiophene Induced by Edge of Metal Electrodes S. Ikeda1, Y. Wada2 and K. Saiki3, 1Tohoku Univ., 2Toyo Univ. and 3Univ. of Tokyo (Japan)
14:30 F-8-6 Refractive Index Control of Organic-Inorganic Hybrid Film Consisting of Ge-Ge Chain A. Watanabe, S. Tadenuma, R. Fujii and T. Miyashita, Tohoku Univ. (Japan)
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14:45 F-8-7 Development of Computational Analysis Method for Carrier Transport Pathway in Light-Emitting Polymers I. Yamashita1, K. Serizawa1, H. Onuma1, A. Suzuki1, H. Tsuboi1, N. Hatakeyama1, A. Endou1, H. Takaba1, M. Kubo1, M. C. Williams1,2 and A. Miyamoto1, 1Tohoku univ. and 2Univ. of Utah (Japan)
15:00 F-8-8 High Efficiency Top-Emission Organic Light-Emitting Diodes Y. N. Lai1, W. C. Hsu1, C. S. Lee2, C. W. Wang3, T. Y. Lu1, C. S. Ho1 and W. F. Lai1, 1National Cheng Kung Univ., 2Feng Chia Univ. and 3National Chung Cheng Univ. (Taiwan) 15:15-15:30 Break
Area 10: Organic Materials Science, Device Physics, and Applications F-9: Organic Transistor & Light Emitting Diode 15:30-16:45 4F Hirose
15:30 F-9-1 (Invited) Organic TFT-driven Flexible Displays K. Nomoto, Sony Corp. (Japan)
16:00 F-9-2 Studies on Thermally Activated Delayed Fluorescence: Novel Exciton Formation Mechanism for OLEDs A. Endo1, M. Ogasawara1, A. Takahashi2, D. Yokoyama1, Y. Kato1 and C. Adachi1, 1Kyushu Univ. and 2Sogo Pharmaceutical Co., Ltd. (Japan)
16:15 F-9-3 Dual Electroluminescence from Hybrid p-n Junction LEDs Composed of Oxide and Organic Semiconductors J. H. Na, M. Kitamura, M. Arita and Y. Arakawa, Univ. of Tokyo (Japan)
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16:30 F-9-4 Color-Tunable Polymer Light-Emitting Diodes with Conjugated Polymer Homojunctions C. Y. Huang, Y. K. Su, C. Y. Cheng, M. V. M. Rao, Y. C. Chen, T. S. Huang, T. C. Wen and T. F. Guo, National Cheng Kung Univ. (Taiwan)
Area 11: Micro/Nano Electromechanical and Bio- Systems (Devices) J-6: NEMS and MEMS 9:00-10:15 6F Hagi Chair: M. Sasaki (Toyota Technological Inst.) K. Ajito (NTT Corp.)
9:00 J-6-1 Fabricarion Technique of Einzel Lens Array with RIE Process E. Tomono, H. Miyashita, T. Ono and M. Esashi, Tohoku univ. (Japan)
9:15 J-6-2 Novel Design for Optical Scanner with Piezoelectric Film by MOCVD H. Matsuo1, Y. Kawai2 and M. Esashi2, 1The Nippon Signal Co., Ltd. and 2Tohoku Univ. (Japan)
9:30 J-6-3 Nonlinear Spring of Thin Film Torsion Bar with Tension for Micromirror M. Sasaki1, S. Kumagai1, M. Fujishima2, K. Hane2 and H. Miura2, 1Toyota Technological Inst. and 2Tohoku Univ. (Japan)
9:45 J-6-4 PZT Acoustic Energy Harvester Proposed for use in MEMS/IC Integrated Systems H. Ichioka, S. Kimura, T. Sugou and Y. Nishioka, Nihon Univ. (Japan)
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10:00 J-6-5 Design and Analysis of an In-Plane Resonant Nano- Electro-Mechanical Sensor for Sub-Attogram-Level Molecular Mass-Detection F. A. Hassani1, C. Cobianu2, S. Armini3, V. Petrescu4, P. Merken4, D. Tsamados5, A. M. Ionescu5, Y. Tsuchiya1 and H. Mizuta1, 1Univ. of Southampton, 2Honywell Romania SRL, 3IMEC, 4Stichting IMEC-NL and 5EPFL (UK) 10:15-10-45 Break
Area 11: Micro/Nano Electromechanical and Bio- Systems (Devices) J-7: Bio Seosors and Bio Chips 10:45-12:15 6F Hagi Chair: I. Yamashita (NAIST) K. Sawada (Toyohashi Univ. of Tech.)
10:45 J-7-1 (Invited) Ultrasonic standing wave manipulation of cells in microfluidic systems T. Laurell, Lund Univ. (Sweden)
11:15 J-7-2 Detection of 28nm Diameter Superparamagnetic Beads by Magnetically- Induced Self-assembly with Micrometer- sized Magnetic Beads: A New Protocol for Magnetically- labeled Biosensing Y. Morimoto, S. Sakamoto, H. Handa and A. Sandhu, Tokyo Tech (Japan)
11:30 J-7-3 Biohybird Chemical Sensor Composed of Microfluidic Device and Cell N. Misawa, H. Mitsuno, R. Kanzaki and S. Takeuchi, Univ. of Tokyo (Japan)
11:45 J-7-4 A Multimodal CMOS Sensor Device with an On-Chip Mounted LED and Electrodes for Imaging of Fluorescence
- 128 - Friday, October 9 and Electrical Potential in a Mouse Deep Brain A. Tagawa1, H. Minami1, M. Mitani1, T. Noda1,2, K. Sasagawa1,2, T. Tokuda1,2, H. Tamura1,2, Y. Hatanaka1,2, Y. Ishikawa1,2, S. Shiosaka1,2 and J. Ohta1,2, 1NAIST and 2CREST-JST (Japan)
12:00 J-7-5 Light Guide Array Structure for Spatial Resolution Improvement of Implantable Image Sensor K. Sasagawa1,2, M. Mitani1, T. Noda1,2, T. Tokuda1,2, S. Shiosaka1,2 and J. Ohta1,2, 1NAIST and 2CREST-JST (Japan) 12:15-13:15 Lunch
Area 11: Micro/Nano Electromechanical and Bio- Systems (Devices) J-8: Nanotechnology for Bio Sensing 13:15-15:15 6F Hagi Chair: J. Ohta (NAIST) M. Niwano (Tohoku Univ.)
13:15 J-8-1 (Invited) Bio-Transducers for Biomedical Applications K. Mitsubayashi, Tokyo Medical and Dental Univ. (Japan)
13:45 J-8-2 Selective Detection of Antigen-Antibody Reaction using Si Ring Optical Resonators S. Yamatogi, M. Fukuyama, H. Ding, M. Nishida, C. Kawamoto, Y. Amemiya, T. Ikeda, T. Noda, S. Kawamoto, K. Ono, A. Kuroda and S. Yokoyama, Hiroshima Univ. (Japan)
14:00 J-8-3 Proposed a Progressive Type pH and Optical Fused Image Sensor H. Nakazawa1, M. Ishida1,2 and K. Sawada1,2, 1Toyohashi Univ. of Tech. and 2CREST-JST (Japan)
- 129 - Friday, October 9
14:15 J-8-4 A Real Time Monitoring System using a Multi-Modal Sensor with EC Sensor Areas and a Temperature Sensor Area for Cows' Health Control M. Futagawa1, T. Iwasaki1, M. Ishida2, H. Takao1,3, M. Ishida1,3 and K. Sawada1,3, 1Toyohashi Univ. of Tech., 2NILGS and 3CREST-JST (Japan)
14:30 J-8-5 Integrated Bio-Photosensor Array with CMOS Cascade Source-Drain Follower H. Matsumoto1, J. Tsukada1, H. Ozawa1, S. Uno1, K. Nakazato1, N. Terasaki2, N .Yamamoto2, T. Hiraga2, M. Iwai3, M. Konno3, K. Ito3 and Y. Inoue3, 1Nagoya Univ., 2AIST and 3Tokyo Univ. of Sci. (Japan)
14:45 J-8-6 Effect of Nanogap Structure on Dynamics of Supported Lipid Bilayer Y. Kashimura, K. Furukawa and K. Torimitsu, NTT Basic Res. Labs. (Japan)
15:00 J-8-7 Simultaneous Electrophysiological and Infrared Spectroscopic Studies of Lipid Bilayer Formation A. Oshima, A. Hirano-Iwata, K. Onodera, T. Taira, Y. Kimura and M. Niwano, Tohoku Univ. (Japan) 15:15-15-30 Break
Area 11: Micro/Nano Electromechanical and Bio- Systems (Devices) J-9: Bio Nano Process 15:30-17:00 6F Hagi Chair: H. Tabata (Univ. of Tokyo) K. Ajito (NTT Corp.)
15:30 J-9-1 (Invited) Soft Bio-materials in Solid State Devices K. Shiba, Japanese Foundation for Cancer Res. (Japan)
- 130 - Friday, October 9
16:00 J-9-2 Fabrication of Nano-Scaled Structures using Genetically Engineered Tobamoviruses M. Kobayashi1, K. Onodera1, Y. Watanabe2 and I. Yamashita1,3, 1NAIST, 2Univ. of Tokyo and 3Panasonic Corp. (Japan)
16:15 J-9-3 New Functional Device Characteristics with 2-Dimensional Array of Si Nanodisks Fabricated by Combination of Bio-Template and Ultimate Top-down Etching M. Igarashi1, C. H. Huang1, M. Tomura1, M. Takeguchi2, S. Horita3, Y. Uraoka4, T. Fuyuki4, I. Yamashita4,5, T. Morie6 and S. Samukawa1, 1Tohoku Univ., 2NIMS, 3JAIST, 4NAIST, 5Panasonic Corp. and 6Kyushu Inst. of Tech. (Japan)
16:30 J-9-4 A New Structure of Nanodisk (Stacked Nanodisk) Fabricated by Bio-nano-process and Defect-free Neutral Beam Etching C. H. Huang1, M. Igarashi1, M. Tomura1, M. Takeguchi2, S. Horita3, Y. Uraoka4, T. Fuyuki4, I. Yamashita4,5 and S. Samukawa1, 1Tohoku Univ., 2NIMS, 3JAIST, 4NAIST and 5Panasonic Corp. (Japan)
16:45 J-9-5 Integration Module of Microcoil Magnetic Manipulation with High Sensitivity CMOS Photosensor Detection in Bio-Analyses C. Y. Chen, C. Y. Huang, C. J. Lin and Y. C. King, National Tsing Hua Univ. (Taiwan)
Area 12: Spintronic Materials and Devices K-6: Spintronics (I): Spintronic Materials & Devices 9:00-10:30 6F Aoi Chair: K. Ito (Hitachi, Ltd.) Y. Ohno (Tohoku Univ.)
- 131 - Friday, October 9
9:00 K-6-1 Electrical Excitation, Manipulation and Detection of Spin Waves in a Py Strip L. Bai1, M. Kohda1,2 and J. Nitta1, 1Tohoku Univ. and 2PRESTO-JST (Japan)
9:15 K-6-2 Magnetoresistance of Magnetostatically Coupled Multilayered Rings T. Miyawaki1, Y. Watanabe1, M. Kohda1,2, K. Saito1, S. Mitani1, K. Takanashi1 and J. Nitta1, 1Tohoku Univ. and 2PRESTO-JST (Japan)
9:30 K-6-3 Electrical Control of the Magnetic Properties in (Ga,Mn)As Channel in Electric Double Layer Transistor M. Endo1, D. Chiba1,2, H. Shimotani1,3, F. Matsukura1,2, Y. Iwasa1,3 and H. Ohno1,2, 1Tohoku Univ., 2ERATO-JST and 3CREST-JST (Japan)
9:45 K-6-4 Spin Orbit Interaction in an In0.53Ga0.47As / In0.7Ga0.3As Shallow Two Dimensional Electron Gas for Electrical Spin Injection and Detection M. Kohda1,2, T. Shibata1 and J. Nitta1, 1Tohoku Univ. and 2PRESTO-JST (Japan)
10:00 K-6-5 Optical Study on Fast Magnetization Dynamics in Perpendicularly Magnetized Pt/Co/Pt Trilayer Films S. Mizukami, E. P. Sajitha, D. Watanabe, F. Wu, M. Oogane, H. Naganuma, Y. Ando and T. Miyazaki, Tohoku Univ. (Japan)
10:15 K-6-6 Fine-Grain Power-Gating Scheme of a CMOS/MTJ- Hybrid Bit-Serial Ternary Content-Addressable Memory S. Matsunaga, A. Matsumoto, M. Natsui, T. Endoh, H. Ohno and T. Hanyu, Tohoku Univ. (Japan) 10:30-10:45 Break
- 132 - Friday, October 9
Area 12: Spintronic Materials and Devices K-7: Spintronics (II): Magnetic Tunnel Junction 10:45-12:15 6F Aoi Chair: H. Kano (Sony Corp.) M. Yamamoto (Hokkaido Univ.)
10:45 K-7-1 CoFeB/MgO/CoFeB Magnetic Tunnel Junctions with Low Resistance-Area Product and High Magnetoresistance H. D. Gan1, K. Mizunuma1, S. Ikeda1, H. Yamamoto1, K. Miura1,2, H. Hasegawa1, J. Hayakawa2, F. Matsukura1 and H. Ohno1, 1Tohoku Univ. and 2Hitachi, Ltd. (Japan)
11:00 K-7-2 CoFeB Inserted Perpendicular Magnetic Tunnel Junctions with CoFe/Pd Multilayers for High Tunnel Magnetoresistance Ratio K. Mizunuma1, J. H. Park1, S. Ikeda1, H. Yamamoto1,2, K. Miura1,2, H. Gan1, H. Hasegawa1, J. Hayakawa2, K. Ito2, F. Matsukura1 and H. Ohno1, 1Tohoku Univ. and 2Hitachi, Ltd. (Japan)
11:15 K-7-3 Perpendicular-MgO-MTJs with fcc(111)-oriented CoPt superlattices K. Yakushiji, H. Kubota, A. Fukushima, T. Nagahama, S. Yuasa and K. Ando, AIST (Japan)
11:30 K-7-4 Annealing Temperature Dependence of Critical Current and Thermal Stability Factor in MgO-Barrier Magnetic Tunnel Junctions with CoFeB based Synthetic Ferrimagnetic Recording Layer J. Hayakawa1, H. Yamamoto1,2, S. Ikeda2, H. Hasegawa2, M. Yamanouchi1, K. Ito1, H. Takahashi1 and H. Ohno2, 1Hitachi, Ltd. and 2Tohoku Univ. (Japan)
11:45 K-7-5 Spin-transfer Switching and Enhanced Thermal Stability of Magnetic Tunnel Junc-tions with CoFeB/Ru/CoFeB
- 133 - Friday, October 9
Ferromagnetically-coupled Free Layer H. Kubota, S. Yakata, A. Fukushima, K. Yakushiji, T. Seki, S. Yuasa and K. Ando, AIST (Japan)
12:00 K-7-6 The Performance of Magnetic Tunnel Junction Integrated on the Back-end Metal Line of CMOS Circuits T. Endoh1, F. Iga1, S. Ikeda2, K. Miura2,3, J. Hayakawa3, M. Kamiyanagi1, H. Hasegawa2, T. Hanyu4 and H. Ohno2, 1Tohoku Univ. and 2Hitachi, Ltd. (Japan) 12:15-13:15 lunch
Area 12: Spintronic Materials and Devices K-8: Spintronics (III): Special Session on Spin-related Phenomena and Future Devices 13:15-15:15 6F Aoi Chair: S. Seo (Samsung Advanced Inst. of Tech.) K. Ando (AIST)
13:15 K-8-1 (Invited) High-speed Magnetic Memory based on Spin-Torque Domain Wall Motion N. Ishiwata1, S. Fukami1, T. Suzuki1, K. Nagahara1, N. Ohshima1, Y. Ozaki2, S. Saito1, R. Nebashi1, N. Sakimura1, H. Honjo1, K. Mori1, C. Igarashi1, S. Miura1 and T. Sugibayashi1, 1NEC Corp. and 2NEC Electronics Corp. (Japan)
13:45 K-8-2 (Invited) MOS/MTJ-Hybird Circuit with Nonvolatile Logic-in- Memory Architecture M. Natsui and T. Hanyu, Tohoku Univ. (Japan)
14:15 K-8-3 (Invited) Spin transfer Oscillations in MgO based Magnetic Tunnel Junctions J. Grollier1, B. Georges.1, A. Dussaux1, A. K. Khvalkovskiy1, V. Cros1, A. Fert1, A. Fukushima2, M. Konoto2, H. Kubota2, R. Matsumoto2, K. Yakushijin2, S. Yuasa2 and K. Ando2, 1Unité Mixte de Physique CNRS/
- 134 - Friday, October 9
Thales and 2AIST (France)
14:45 K-8-4 (Invited) Spin Injection, Transport, and Control in Silicon I..Appelbaum, Univ. of Maryland (USA) 15:15-15-30 Break
Area 12: Spintronic Materials and Devices K-9: Spintronics (IV): Special Session on Spin-related Phenomena and Future Devices 15:30-16:45 6F Aoi Chair: M. Tanaka (Univ. of Tokyo) K. Ando (AIST)
15:30 K-9-1 (Invited) Silicon Spintronics R. Jansen1, Univ. of Twente (Netherlands)
16:00 K-9-2 (Invited) Graphene Spintronics M. Shiraishi1,2, 1Osaka Univ. and 2PRESTO-JST (Japan)
16:30 K-9-3 Spin-Transfer-Torque-Induced RF Oscillation for Fe/Cr/Fe Layers with an Antiferromagnetic Coupling Field T. Seki, H. Tomita, T. Yamane, M. Shiraishi, T. Shinjo and Y. Suzuki, Osaka Univ. (Japan)
Area 13: Applications of Nanotubes and Nanowires E-6: Semiconductor Nanowires (I) 9:00-10:30 3F Keyaki Chair: J. Motohisa (Hokkaido Univ.) S. Sato (Fujitsu Labs. Ltd.)
9:00 E-6-1 (Invited) Metal-free Elementary Semiconductor Nanowires: Synthesis and Device Applications D. Whang and S. Hwang, Sungkyunkwan Univ. (Korea)
- 135 - Friday, October 9
9:30 E-6-2 Theoretical Study on Thermoelectric Properties of Ge and Si Nanowires W. Huang, C. S. Koong and G. Liang, National Univ. of Singapore (Singapore)
9:45 E-6-3 Shell Strain Effects on Valence Band Structure and Transport Property in Ge/Si1-xGex Core-Shell Nanowire H. Xu, Y. Zhao, Y. He, C. Fan, G. Du, X. Liu, R. Han and J. Kang, Peking Univ. (China)
10:00 E-6-4 RF Characterization and Equivalent Circuit Modeling of Ge Nanowires J. H. Ahn1, M. G. Kang1, B. S. Kim2, J. Lee2, D. H. Hwang1, D. J. Lee1, H. T. Kim1, S. W. Hwang1, D. Whang2 and D. Ahn3, 1Korea Univ., 2Sungkyunkwan Univ. and 3Univ. of Seoul (Korea)
10:15 E-6-5 Device and Circuit Co-Design Strategy for Radio Frequency (RF) Applications based on Silicon Nanowire (SNW) MOSFETs S. Cho, H. S. John, I. H. Park, J. H. Lee, H. Shin and B. G. Park, Seoul National Univ. (Korea) 10:30-10:45 Break
Area 13: Applications of Nanotubes and Nanowires E-7: Si Nanowires 10:45-12:15 3F Keyaki Chair: K. Nishiguchi (NTT Basic Res. Labs.) S. Akita (Osaka Prefecture Univ.)
10:45 E-7-1 Performance Improvement of Poly-Si Nanowire Transistors Featuring In-Situ Doped Source/Drain W. C. Chen1, H. C. Lin1,2, Y. C. Chang1 and T. Y. Huang1, 1National Chiao Tung Univ. and 2National Nano Device Lab. (Taiwan)
- 136 - Friday, October 9
11:00 E-7-2 Series Resistance Behavior Extracted from Silicon Nanowire Transistors using the Y-function Technique R. H. Baek1, C. K. Baek2, S. W. Jung3, Y. Y. Yeoh4, D. W. Kim4, J. S. Lee1,3, D. M. Kim2 and Y. H. Jeong1,3, 1POSTECH, 2KIAS, 3NCNT and 4Samsung Electronics Corp. (Korea)
11:15 E-7-3 A Theoretical Study of Electron-Modulated-Acoustic- Phonon Interactions in Silicon Nanowire MOSFETs J. Hattori1,3, S. Uno1,3, N. Mori2 and K. Nakazato1,3, 1Nagoya Univ., 2Osaka Univ. and 3SORST-JST (Japan)
11:30 E-7-4 Impact of adequate selection of channel direction on (001) and (110) wafer orientation for strained nanowire transistors A. Seike1, H. Takai1, I. Tsuchida1, J. Masuda2, D. Kosemura2, A. Ogura2, T. Watanabe1 and I. Ohdomari1, 1Waseda Univ. and 2Meiji Univ. (Japan)
11:45 E-7-5 Systematic Study on Size Dependences of Transport Parameters for Ballistic Nanowire-FET with Effective Mass Approximation Y. Lee1, K. Kakushima1, K. Shiraishi2, K. Natori1 and H. Iwai1, 1Tokyo Tech and 2Univ. of Tsukuba (Japan)
12:00 E-7-6 Silicon Nanowire Array Solar Cell Prepared by Metal- induced Electroless Etching with a Novel Processing Technology H. D. Um1, H. S. Seo1, J. Y. Jung1,2, S. W. Jee1, S. A. Moiz1 and J. H. Lee1, 1Hanyang Univ. and 2ADP engineering Corp. (Korea) 12:15-13:15 Lunch
- 137 - Friday, October 9
Area 13: Applications of Nanotubes and Nanowires E-8: Carbon Nanotubess and Graphene 13:15-15:15 3F Keyaki Chair: N. Aoki (Chiba Univ.) Y. Ohno (Nagoya Univ.)
13:15 E-8-1 Photo-Response of Carbon Nanotube FETs with Thick Piezoelectric Gate Insulator N. Nei1, T. Ikeyama1, T. Arie1,2 and S. Akita1,2, 1Osaka Prefecture Univ. and 2CREST-JST (Japan)
13:30 E-8-2 Electric Characterization of Carbon Nanotubes Grown at Low Temperature by Remote Plasma Chemical Vapor Deposition for LSI Interconnects M. Iizuka1, D. Yokoyama1, K. Ishimaru1, I. Yuitho1, T. Takeuchi1, S. Sato2, M. Nihei2, Y. Awano2 and H. Kawarada1, 1Waseda Univ. and 2MIRAI-Selete (Japan)
13:45 E-8-3 Quantum Transport Calculations of Carbon Nanotube based Materials K. Hirose1, H. Ishii2 and N. Kobayashi3, 1NEC Corp., 2Univ. of Tokyo and 3Univ. of Tsukuba (Japan)
14:00 E-8-4 Fe/Ge Catalyzed Carbon Nanotube Growth on HfO2 for Nano-Sensor Applications T. Uchino1, G. N. Ayre1, D. C. Smith1, J. L. Hutchison2, C. H. de Groot1 and P. Ashburn1, 1Univ. of Southampton and 2Univ. of Oxford (UK)
14:15 E-8-5 Multi-walled Carbon Nanotube-Dispersed Resin Films for Remote Strain Measurement K. Ohsaki, H. Fuji, M. Ohnishi, K. Suzuki and H. Miura, Tohoku Univ. (Japan)
- 138 - Friday, October 9
14:30 E-8-6 Electrolyte-Gated Graphene Field-Effect Transistors Y. Ohno, K. Maehashi, Y. Yamashiro and K. Matsumoto, Osaka Univ. (Japan)
14:45 E-8-7 Study of Metal/Graphene Contact with Different Electrode Geometry K. Nagashio, T. Nishimura, K. Kita and A. Toriumi, Univ. of Tokyo (Japan)
15:00 E-8-8 Formation of Quantum Dots in Graphene with Constrictions Y. Yamashiro, Y. Ohno, K. Maehashi, K. Inoue and K. Matsumoto, Osaka Univ. (Japan) 15:15-15:30 Break
Area 13: Applications of Nanotubes and Nanowires E-9: Semiconductor Nanowires (II) 15:30-17:15 3F Keyaki Chair: K. Ishibashi (RIKEN) K. Maehashi (Osaka Univ.)
15:30 E-9-1 (Invited) Identification of Single Boron Acceptors in Nanowire MOSFETs Y. Ono1, M.A.H. Khalafalla1, S. Horiguchi2, K. Nishiguchi1 and A. Fujiwara1, 1NTT Basic Research Lab. and 2Akita Univ. (Japan)
16:00 E-9-2 An Analytical Compact Model of Ballistic Cylindrical Nanowire MOSFET T. Numata1, S. Uno1, K. Nakazato1, Y. Kamakura2 and N. Mori2, 1Nagoya Univ. and 2Osaka Univ. (Japan)
16:15 E-9-3 Random Telegraph Signal and Low Frequency Noise in Silicon Charge-Sensitive Electrometers
- 139 - Friday, October 9
N. Clement1, K. Nishiguchi2, A. Fujiwara2 and D. Vuillaume1, 1IEMN and 2NTT Basic Res. Labs. (France)
16:30 E-9-4 Single-electron Counting Statistics of Shot Noise in Nanowire Si MOSFETs K. Nishiguchi, Y. Ono and A. Fujiwara, NTT Basic Res. Labs. (Japan)
Area 14: Power Electronics H-6: Power Devices and Applications 9:00-10:30 6F Kiri Chair: S. Matumoto (NTT Energy and Environment Systems Labs.) M. Mori (Hitachi, Ltd.)
9:00 H-6-1 (Invited) Current Status and Technology Trends of Grid-Interactive Inverter for PV Application S. Nishi, Sharp Corp. (Japan)
9:30 H-6-2 Analysis of Hot Carrier Degradation for LDMOS under Gate Pulse Stress K. Furuya1, T. Nitta2, T. Katayama1, K. Hatasako2, T. Kuroi2 and S. Maegawa2, 1Renesas Semiconductor Eng. Corp. and 2Renesas Tech. Corp. (Japan)
9:45 H-6-3 Current Distribution Analysis of IGBT Cells H. Long, M. R. Sweet, N. Luther-King and E. M. S. Narayanan, Univ. of Sheffield (UK)
10:00 H-6-4 High-Temperature Diamond SBDs H. Umezawa and S. Shikata, AIST (Japan)
10:15 H-6-5 Lateral Back-to-back-diode for Low-Capacitance Transient Voltage Suppressor
- 140 - Friday, October 9
C. C. Chen, S. H. Dai, J. J. Peng, C. J. Lin and Y. C. King, Natioanl Tsing Hua Univ. (Taiwan) 10:30-10:45 Break
Area 14: Power Electronics H-7: Materials for Power Devices 10:45-12:15 6F Kiri Chair: M. Ishiko (Toyota Central R&D Labs., Inc.) N. Iwamuro (Fuji Electric Device Tech. Co.,Ltd.)
10:45 H-7-1 (Invited) Technology Trends of CZ-Silicon Substrates for Power Devices K. Kashima, Covalent Materials Corp. (Japan)
11:15 H-7-2 (Invited) Silicon Carbide Wafer Technologies for Power Devices S. Nishizawa, AIST (Japan)
11:45 H-7-3 Polytype-Stabilized Solution Growth of 3C-SiC T. Ujihara, K. Seki, R. Tanaka and Y. Takeda, Nagoya Univ. (Japan)
12:00 H-7-4 Large-scale Quantum Chemical Molecular Dynamics Study on the SiC/SiO2 Interface for SiC-based Devices J. P. Yacapin, A. Suzuki, H. Tsuboi, N. Hatakeyama, A. Endou, H. Takaba, M. Kubo and A. Miyamoto, Tohoku Univ. (Japan) 12:15-13:15 Lunch
Area 14: Power Electronics H-8: New Approaches to High-efficiency Solor Cells 13:15-15:00 6F Kiri Chair: A. Masuda (AIST) T. Minemoto (Ritsumeikan Univ.)
13:15 H-8-1 (Invited) Towards a Better Understanding of Silicon Heterojunction
- 141 - Friday, October 9
Solar Cells S. De Wolf, J. Damon-Lacoste, L. Fesquet, G. Choong and C. Ballif, EPFL (Switzerland)
13:45 H-8-2 A new approach to increase efficiency of thin Si solar cells with scatterer A. Yanai, R. Ichikawa, Y. Ishikawa and K. Wada, Univ. of Tokyo (Japan)
14:00 H-8-3 Epitaxial Growth and Photoresponse Properties of BaSi2 Layers toward Si-based High-Efficiency Solar Cells Y. Matsumoto1, D. Tsukada1, R. Sasaki1, M. Takeishi1, T. Saito1 and T. Suemasu1,2, 1Univ. of Tsukuba and 2JST- PRESTO (Japan)
14:15 H-8-4 Orientation Control of Large Grain Poly-Si on Glass by Interfacial Oxide Layer Controlled Al-Induced Crystallization M. Kurosawa, N. Kawabata, T. Sadoh and M. Miyao, Kyushu Univ. (Japan)
14:30 H-8-5 III-V Coupled Quantum Well Solar Cells: Predicted Performances and Growth Challenges M. Sugiyama, W. Yu, Y. Wang, R. Onitsuka, M. Deura and Y. Nakano, Univ. of Tokyo (Japan)
14:45 H-8-6 Development and Application of Multiscale Simulator for Dye-Sensitized Solar Cells M. Onodera1, K. Ogiya1, A. Suzuki1, H. Tsuboi1, N. Hatakeyama1, A. Endou1, H. Takaba1, M. Kubo1, M. C. Williams2 and A. Miyamoto1, 1Tohoku Univ. and 2Univ. of Utah (Japan) 15:00-15:30 Break
- 142 - Friday, October 9
Area 14: Power Electronics H-9: Materials Science for Solor Cells 15:30-17:00 6F Kiri Chair: N. Usami (Tohoku Univ.) Stefaan De Wolf (Ecole Polytechnique Fédérale de Lausanne)
15:30 H-9-1 (Invited) Defect Characterization of CIS-related Compound Solar Cells by Admittance Spectroscopy and DLTS P. L. Zabierowski, Warsaw Univ. of Tech. (Poland)
16:00 H-9-2 Potential Profiles around Grain Boundary Studied by Photoassisted Kelvin Probe Force Microscopy on Cu(InGa)Se2 Solar Cells M. Takihara1, T. Minemoto2, Y. Wakisaka2 and T. Takahashi1, 1Univ. of Tokyo and 2Ritsumeikan Univ. (Japan)
16:15 H-9-3 Electronic Structure and Characteristics of Chemical Bonds in CuInSe2, CuGaSe2 and CuAlSe2 T. Maeda and T. Wada, Ryukoku Univ. (Japan)
16:30 H-9-4 Lift-off Process for Flexible Cu(In,Ga)Se2 Solar Cells T. Minemoto, T. Anegawa, S. Osada and H. Takakura, Ritsumeikan Univ. (Japan)
16:45 H-9-5 A Computational Investigation of Relationship Between Shear Stress and Multicrystal Structure in Si I. Takahashi, N. Usami, K. Kutsukake, K. Morishita and K. Nakajima, Tohoku Univ. (Japan)
- 143 - ORGANIZING COMMITTEE Chair: M. Koyanagi (Tohoku Univ.) Vice-chair: Y. Arakawa (Univ. of Tokyo) Member: Y. Aoyagi (Ritsumeikan Univ.) T. Asano (Kyushu Univ.) H. Hasegawa (Hokkaido Univ.) K. Hashimoto (Sony Corp.) S. Hiraki (Toshiba Corp.) Y. Horiike (NIMS) A. Ibaraki (SANYO Electric Co., Ltd.) Y. Inoue (Renesas Tech. Corp.) H. Ishiwara (Tokyo Tech) H. Ito (Tokyo Electron Ltd.) A. Kamisawa (ROHM Co., Ltd.) T. Kamiya (NICT) T.Kanayama (AIST) T. Kihara (Hitachi ULSI Systems Co., Ltd.) T. Masuhara (ASET) K. Natori (Tokyo Tech) T. Ohmi (Tohoku Univ.) T. Oomori (Mitsubishi Electric Corp.) N. Saito (NHK) H. Sakaki (Toyota Technological Inst.) T. Shibata (Univ. of Tokyo) Y. Shiraki (Tokyo City Univ.) J. Sone (NEC Corp.) T. Suga (Univ. of Tokyo) K. Tada (Kanazawa Inst. of Tech.) A. Takahashi (Sharp Corp.) K. Taniguchi (Osaka Univ.) K. Tsubouchi (Tohoku Univ.) H. Uchida (Panasonic Corp.) J. Ueda (SILIJ) H. Watanabe (Selete) Y. Yasuda (Tohoku Univ.) I. Yokohama (NTT Corp.) N. Yokoyama (Fujitsu Labs. Ltd.)
- 144 - INTERNATIONAL ADVISORY COMMITTEE C. Y. Chang (National Chiao Tung Univ.) G. Declerck (IMEC) L. Esaki (The Sci. and Tech. Promotion Foundation of Ibaraki) J. S. Harris (Stanford Univ.) K. Kim (Samsung Electronics Co., Ltd.) K. v. Klitzing (Max Planck Inst.) D. L. Kwong (IME) Z. J. Li (Tsinghua Univ.) M. Nakamura (Hitachi, Ltd.) Y. Nishi (Stanford Univ.) K. H. Ploog (Paul Drude Inst.) T. Sugano (Univ. of Tokyo) K. Takahashi (Tokyo Tech) S. Tanaka (ISTEC)
STEERING COMMITTEE Chair: S. Samukawa (Tohoku Univ.) Vice-chair: S. Takagi (Univ. of Tokyo) Secretary: K. Endo (AIST) T. Ono (Tohoku Univ.) Member: T. Endoh (Tohoku Univ.) T. Fukushima (Tohoku Univ.) J. Hashimoto (Oki Semiconductor Miyagi Co., Ltd.) S. Iwamoto (Univ. of Tokyo) N. Matsunaga (Toshiba Corp). T. Matsuzaki (Tohoku Univ.) H. Ohtake (Tohoku Univ.) T. Shinada (Waseda Univ.) E. Soda (Selete) T. Tanaka (Tohoku Univ.) T. Tokumasu (Tohoku Univ.) Y. Uraoka (NAIST) T. Yamamoto (NEC Electronics Corp.) S. Yasuhara (Japan Advanced Chemicals, Ltd.)
- 145 - PROGRAM COMMITTEE
Chair: K. Wada (Univ. of Tokyo) Vice-chair: K. Masu (Tokyo Tech) K. Ohashi (NEC Corp.) S. Chung (National Chiao Tung Univ.) Secretary: T. Kondo (Univ. of Tokyo) K. Uchida (Tokyo Tech) Subcommittee Members: [1] Advanced Gate Stack / Si Processing & Material Science Chair: J. Yugami (Selete) Co-chair: S. Miyazaki (Hiroshima Univ.) Member: H. Fukutome (Fujitsu Labs. Ltd.) H. Hwang (Gwangju Inst. of Sci. & Tech.) M. F. Li (Fudan Univ.) S. Maitrejean (CEA Leti Minatec) B. Mizuno (UJT Lab. Inc.) K. Shiraishi (Univ. of Tsukuba) S. Tsujikawa (Sony Corp.) Y. Tsunashima (Toshiba Corp.) H. Umeda (Renesas Tech. Corp.) I.. Yamamoto (NEC Electronics Corp.) [2] Characterization and Materials Engineering for Interconnect Integration Chair: M. Matsuura (Renesas Tech. Corp.) Co-chair: Y. Hayashi (NEC Electronics Corp.) Member: G. Beyer (IMEC) J. Gambino (IBM) T. Hasegawa (Sony Corp.) S.Hsu (National Tsinghua Univ.) K. Ito (Kyoto Univ.) J. Kodate (NTT Corp.) M. Kodera (Toshiba Corp.) S. Matsumoto (Panasonic Corp.) N. Nakano (Keio Univ.) M. Nihei (Fujitsu Labs. Ltd.) S. Ogawa (Selete) [3] CMOS Devices /Device Physics Chair: H. Wakabayashi (Sony Corp.) Co-chair: K. Shibahara (Hiroshima Univ.) Member: A. Azuma (Toshiba Corp.)
- 146 - F. Boeuf (STMicroelectronics) M. Hane (NEC Electronics America) S. Hayashi (Panasonic Corp.) T. Hiramoto (Univ. of Tokyo) D. Hisamoto (Hitachi, Ltd.) K. Horita (Renesas Tech. Corp.) N. Mori (Osaka Univ.) T. Tanaka (Fujitsu Microelectronics Ltd.) Y. Yeo (National Univ. of Singapore) [4] Advanced Memory Technology Chair: A. Nitayama (Toshiba Corp.) Co-chair: M. Moniwa (Renesas Tech. Corp.) Member: Y. C. Chen (Macronix International Co., Ltd.) T. Eshita (Fujitsu Microelectronics Ltd.) H. Hada (NEC Corp.) K. Hamada (Elpida Memory, Inc.) K. Ishihara (Sharp Corp.) G. H. Koh (Samsung Electronics Co., Ltd) R. Shen (eMemory Tech. Inc.) Y. Shimamoto (Hitachi, Ltd.) M. J. Tsai (ITRI) [5] Advanced Circuits and Systems Chair: S. Kawahito (Shizuoka Univ.) Co-chair: T. Matsuoka (Osaka Univ.) Member: J. C. Guo (National Chiao Tung Univ.) T. Hamasaki (Texas Instruments Japan Ltd.) M. Horiguchi (Renesas Tech. Corp.) S. Ishizuka (Toshiba Corp.) T. Koide (Hiroshima Univ.) T. Komuro (Kanagawa Inst. of Tech.) Y. Sato (NTT Microsystem Integration Labs.) H. Shin (Seoul National Univ.) [6] Compound Semiconductor Circuits, Electron Devices and Device Physics Chair: T. Hashizume (Hokkaido Univ.) Co-chair: M. Kuzuhara (Univ. of Fukui) Member: E. Y. Chang (National Chiao Tung Univ.) K. J. Chen (Hong Kong Univ. of Sci. & Tech.) R. Hattori (Mitsubishi Electric Corp.) S. Kuroda (Eudyna Devices Inc.) K. Maezawa (Univ. of Toyama) G. Meneghesso (Univ. of Padova)
- 147 - Y. Miyamoto (Tokyo Tech) A. Nakagawa (New Japan Radio Co., Ltd.) Y. Ohno (Univ. of Tokushima) K. S. Seo (Seoul National Univ.) S. Tanaka (Shibaura Inst. of Tech.) T. Tanaka (Panasonic Corp.) S. Yamahata (NTT Corp.) [7] Photonic Devices and Device Physics Chair: H. Yamada (Tohoku Univ.) Co-chair: M. Sugawara (Fujitsu Labs. Ltd.) Member: R. Akimoto (AIST) S. J. Chua (National Univ. of Singapore) M. Ezaki (Toshiba Corp.) J. Fujikata (NEC Corp.) M. Gotoda (Mitsubishi Electric Corp.) Y. Ishikawa (The Univ. of Tokyo) H. Isshiki (The Univ. of Electro- Communications) Y. Lee (Hitachi, Ltd.) S. Noda (Kyoto Univ.) O. Wada (Kobe Univ.) [8] Advanced Material Synthesis and Crystal Growth Technology Chair: A. Yamada (Tokyo Tech) Co-chair: H. Hibino (NTT Basic Res. Labs.) Member: H. Asahi (Osaka Univ.) A. Endou (Tohoku Univ.) T. Fukui (Hokkaido Univ.) T. Iwai (Fujitsu Labs. Ltd.) M. Kobayashi (Waseda Univ.) M. Nakada (NEC Corp.) R. Notzel (Eindhoven Univ. of Tech.) Y. Sakuma (NIMS) M. Takahashi (Japan Atomic Energy Agency) E. S. Tok (National Univ. of Singapore) [9] Physics and Applications of Novel Functional Materials and Devices Chair: T. Fujisawa (Tokyo Tech) Co-chair: Y. Takahashi (Hokkaido Univ.) Member: D. G. Austing (Nat'l Res. Council of Canada) H. Gotoh (NTT Corp.) P. W. Li (National Central Univ.)
- 148 - K. Ono (RIKEN) B. G. Park (Seoul National Univ.) Y. Suda (Tokyo Univ. of Agri. and Tech.) M. Tabe (Shizuoka Univ.) Y. Uraoka (NAIST) M. Watanabe (Tokyo Tech) [10] Organic Materials Science, Device Physics, and Applications Chair: K. Kato (Niigata Univ.) Co-chair: H. Usui (Tokyo Univ. of Agri. and Tech.) Member: S. Aramaki (MCRC) S. Aratani (Hitachi, Ltd.) K. Fujita (Kyushu Univ.) S. F. Horng (National Tsing Hua Univ.) H. Kajii (Osaka Univ.) T. Kamata (AIST) Y. Majima (Tokyo Tech) M. Nakamura (Chiba Univ.) C. K. Song (Dong-A Univ.) [11] Micro/Nano Electromechanical and Bio-Systems (Devices) Chair: I. Yamashita (NAIST) Co-chair: H. Tabata (Univ. of Tokyo) Member: K. Ajito (NTT Corp.) S. A. Contera (Univ. of Oxford) T. Nishimoto (Shimadzu Corp.) M. Niwano (Tohoku Univ.) J. Ohta (NAIST) M. Sasaki (Toyota Technological Inst.) K. Sawada (Toyohashi Univ. of Tech.) Y. S. Yang (National Chiao Tung Univ.) [12] Spintronic Materials and Devices Chair: K. Ando (AIST) Co-chair: M. Tanaka (Univ. of Tokyo) Member: K. Ito (Hitachi, Ltd.) K. Itoh (Keio Univ.) H. Kano (Sony Corp.) Y. Ohno (Tohoku Univ.) S. Seo (Samsung Advanced Inst. of Tech.) M. Yamamoto (Hokkaido Univ.)
- 149 - [13] Applications of Nanotubes and Nanowires Chair: K. Ishibashi (RIKEN) Co-chair: J. Motohisa (Hokkaido Univ.) Member: S. Akita (Osaka Prefecture Univ.) N. Aoki (Chiba Univ.) S. Hwang (Korea Univ.) K. Maehashi (Osaka Univ.) K. Nishiguchi (NTT Basic Res. Labs.) Y. Ohno (Nagoya Univ.) S. Sato (Fujitsu Labs. Ltd.) K. Tateno (NTT Corp.) S. J. Wind (Columbia Univ.) [14] Power Electronics Chair: M. Ishiko (Toyota Central R&D Labs., Inc.) Co-chair: N. Usami (Tohoku Univ.) Member: N. Iwamuro (Fuji Electric Device Tech. Co.,Ltd.) Y. Komatu (ECN) A. Masuda (NAIST) S. Matumoto (NTT Energy and Environment Systems Lab.) P. Mawby (Univ. of Warwick) T. Minemoto (Ritsumeikan Univ.) M. Mori (Hitachi, Ltd.) I. Ohmura (Kyushu Inst. of Tech.)
SSDM2009 is subsidized by the following organization: * The Ministry of Education, Culture, Sports, Science and Technology
- 150 - Memo
- 151 - SSDM 2009 Floor Guide, Sendai Kokusai Hotel
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- 153 - Access to Sendai
Sendai is 350 kilometers north of Tokyo, Japan’s capital. If you are coming from abroad, you can fly directly or transfer to a domestic flight to Sendai Airport. You can arrive in Sendai by air or train from any cities in Japan.
Flying in to Sendai Airport from Abroad
Flights to Sendai Airport from overseas are as shown below. Connecting flights from Seoul and China (e.g. Beijing) fly daily to connect Sendai with other countries. Chartered flights fly out of several cities such as Hong Kong and Bangkok. Domestic flights connect ten cities in Japan to Sendai. Passengers landing at Narita, Nagoya or Kansai can transfer to a domestic flight to connect directly to Sendai.
Changchun 1h 40min Sapporo
Beijing 2h 10min
Dalian 2h 10min Sendai Airport
Seoul Komatsu Kobe Narita Hiroshima Nagoya 2h 20min Fukuoka Osaka Kansai
Shanghai 35min 2h
Okinawa Taipei Guam 2h 35min
- 154 - ACCESS TO SENDAI KOKUSAI HOTEL
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)BOFEB"JSQPSU /BSJUB"JSQPSU 23min. Tokyo Monorail )BNBNBUTVDIP4UB JR Narita Express 1 hr . Domestic flight 1hr. 6min. JR Yamanote Line 5PLZP4UB
4FOEBJ"JSQPSU 1hr. 40min. 25min. 35min. Taxi 40min. JR Tohoku Shinkansen Sendai Airport Line Airport Limousine bus 4FOEBJ4UB Foot 5min. 4FOEBJ,PLVTBJ)PUFM
- 155 - ACCESS MAP
West exit Sendai Station Ma E-beans H l l
Metropolitan St. H achi Sendai mim Monterey Sendai Mina Central Sendai H H Sun Route Sendai H i St. mach Sendai Kokusai Hotel nagi Ya (SSDM2009)
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SSDM2009 Conference: Sendai Kokusai Hotel Workshop/ Short Course: Institute of Fluid Science, Tohoku Univ.
■5 minutes on foot from JR Sendai Station ■3 minutes on foot from South Exit (2) Sendai Subway Station ■15 minutes by car from Miyagi I.C.,Tohoku Expressway ■40 minutes by car from Sendai Airport ■2 hours by Shinkansen from Tokyo
- 156 -