US 20050053240A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2005/0053240 A1 Lablans (43) Pub. Date: Mar. 10, 2005

(54) TERNARY AND HIGHER MULTI-VALUE (52) Us. 01...... 380/268 DIGITAL SCRAMBLERS/DESCRAMBLERS

(76) Inventor: Peter Lablans, Morris Township, NJ (57) ABSTRACT (US) Correspondence Address: Ternary (3-value) and higher, multi-value digital scramblers/ Glen M. Diehl descramblers in digital communications. The method and NORTON & DIEHL LLC apparatus of the present invention includes the creation of Suite 110 ternary (3-value) and higher value truth tables that establish 77 Brant Avenue Clark, NJ 07066 (US) ternary and higher value scrambling functions Which are its oWn descrambling functions. The invention directly codes (21) Appl. No.: 10/912,954 by scrambling ternary and higher-value digital signals and directly decodes by descrambling With the same function. A (22) Filed: Aug. 6, 2004 disclosed application of the invention is the creation of composite ternary and higher-value scrambling devices and Related US. Application Data methods consisting of single scrambling devices or func tions combined With ternary or higher value shift registers. (60) Provisional application No. 60/501,335, ?led on Sep. 9, 2003. Another disclosed application is the creation of ternary and higher-value digital signals. Another dis Publication Classi?cation closed application is a composite ternary or higher value scrambling system, comprising an odd number of scram (51) Int. Cl.7 ...... H04L 9/00 bling functions and the ability to be its oWn descrambler. Digital communications Sending Side: Block Diagram

10 Information Source: - voice - video - graphics - data

12 14 / / Transmission AID Converter Coder Modulator K) 16 Patent Application Publication Mar. 10, 2005 Sheet 1 0f 18 US 2005/0053240 A1 Figure 1. Digital communications Sending Side: Block Diagram

10 Information Source: - voice - video - graphics - data

12 14 / Transmission AID Converter Coder Modulator ——-—> / 16 Patent Application Publication Mar. 10, 2005 Sheet 2 0f 18 US 2005/0053240 A1

Figure 2. Digital communications Receiving Side: Block Diagram

Information Target:

- voicevideo O - graphics t‘ - data

Receiving

———-+‘ Demodulator Decoder D/A Converter / / / 17 18 2Q Patent Application Publication Mar. 10, 2005 Sheet 3 0f 18 US 2005/0053240 A1

Figure 3. The Exclusive Or or Modulo-Z adder as scrambling and descrambling function.

A In formula:

' ' ' *} C c ->A # B —-———>B But also:

B A -->C #5 B \ ¢ 0 1 and Patent Application Publication Mar. 10, 2005 Sheet 4 0f 18 US 2005/0053240 A1

Figure 4. ~ A binary scrambler composed of 2 Modulo-2 add functions, a 5-bits shift register and taps from cells 3 and 5 from the shift register.

Binary input sequence

40 ln5 50 ‘i

¢ ¢ ‘

44 £1445 46147 / 481

s5 s4 s3 s2 s1 1 5 bits shift register Line5 Line5 —-> In5 #5 (S3 9* S1)

Scrambled binary output sequence Patent Application Publication Mar. 10, 2005 Sheet 5 0f 18 US 2005/0053240 A1

Figure 5.

A binary descrambler composed of a 5-bit shift register, taps from cells 3 and 5 and two Modulo-Z adder functions.

Scrambled input

Line5

5-bits shift register

‘l Descrambled output Patent Application Publication Mar. 10, 2005 Sheet 6 0f 18 US 2005/0053240 A1 Functions sc1, $02 and sc3 as ternary scrambling functions. B 0 ifC->Asc1 B 0 0 A > ——> c then 2 0 ’ “1 A _’ c sc1 B 1 O-LN-a 2 B B->Asc1C

then sc2 c A—+C$C2B B-rASCZC

ifC-,Asc3B then A—>Csc3B B-+Asc3C

Figure 6. Patent Application Publication Mar. 10, 2005 Sheet 7 0f 18 US 2005/0053240 A1 Block diagram of binary ROM to realize ternary scrambling function sc1. '/ 80

address content Ternary A in binary form Ternary C in binary form

in binary fonn

Clock pulse

Figure 7. Patent Application Publication Mar. 10, 2005 Sheet 8 0f 18 US 2005/0053240 A1

Block diagram of DIA system to generate ternary signals from binary input.

binary ternary input output C

c= 1 0 , = 2

90 \ l Clock

C= 0 1 DIA = 1 -_-w Converter --—>

C= 0 0 c: 0

Figure 8. Patent Application Publication Mar. 10, 2005 Sheet 9 0f 18 US 2005/0053240 A1

Block diagram of AID system to generate binary representation from ternary input.

= 2 C= 1 0 92 \ Clock

_ ternary binary - 1 input c AID output 0 c= o 1 ———————> Converter ’

= o I c= o 0

Figure 9. Patent Application Publication Mar. 10, 2005 Sheet 10 0f 18 US 2005/0053240 A1

Block diagram of ternary scrambler composed of a 5 element shift register with taps at cell 3 and 5 and 2 ternary scrambling functions sc1. Terln=1120100202 \ 100 1 102 112

sc1 sc1 106 107 108 T 109 110 \. a .1

5-element ternary shift register Initial content of shift registeF 0 0 0 0 0

TerOut=2212101020

Figure 10. sc1 | 0 1 2 0 0 2 1 1 2 1 0 2 1 0 2 Patent Application Publication Mar. 10, 2005 Sheet 11 0f 18 US 2005/0053240 A1

Block diagram of ternary descrambler composed of a 5 element shift register with taps at cell 3 and 5 and 2 ternary scrambling functions sc1.

TerLine=2212101020

5-elements ternary shift register Initial content 0 0 0 0 0 1 /

124 125 125 v 127 128 1 $121 $01

120 130 Figure11.

TerDes=1120100202 Patent Application Publication Mar. 10, 2005 Sheet 12 0f 18 US 2005/0053240 A1

Diagram of truth table of n-value scrambling function.

The value of A, B and C can be A ‘ c Integer 0, 1, 2,....m for n-value _D—''86 logic with m= n-1. B

The scrambling properties of truth |f C _, A 5c 3 table sc also apply if the rows are then moved down a number p,eand the A _> C so B lower p rows are moved to the top and of the truth table. B _-> A sc C

B .

sc 0 1 . . . m

0 m m-1 . . 0

1 '“'1 m": I I o

0 A _1 0 m 0 m 1 Figure 12. Patent Application Publication Mar. 10, 2005 Sheet 13 0f 18 US 2005/0053240 A1 Diagram of scrambled signal achieved by applying scrambling function sc1 on a ternary signal and a pre-determined ternary sequence. 150 |-———l |/ Signal ‘a’

MW/m‘n’ =4times standard sequence W Res = (a sc1 n)

Signal a=22222222000000001111111100000000 Sequence n=20010221200102212001022120010221 Sequence Res =21101220100201120221200110020112

0 154 0 / Figure 13. 2 1 Patent Application Publication Mar. 10, 2005 Sheet 14 0f 18 US 2005/0053240 A1

Block diagram of system to generate a spread spectrum ternary scrambled signal, applying ?xed temary sequences and ternary scrambling functions.

?xed sequence of more rapid ternary signal

166 \ clock 168

slow changing_ l scrambled ternary 3'9'"ll ternary signal

-———* $01 ———> . \170 Figure 14. 164 \ 160 Patent Application Publication Mar. 10, 2005 Sheet 15 0f 18 US 2005/0053240 A1

Block diagram of system to recover a signal from a spread spectrum ternary scrambled signal, applying ?xed ternary sequences and ternary scrambling function.

?xed sequence of more rapid ternary signal

186 \ clock 188 scrambled 1 f recovered ternary signal “ ternary signal

Figure 14. 7'184 sc1

Figure 15.

Patent Application Publication Mar. 10, 2005 Sheet 17 0f 18 US 2005/0053240 A1

Diagram of scrambled spread spectrum signal achieved by applying scrambling function fs3 on a 4-value signal ‘a” and a pre-determined 4-value sequence.

4-value signal ‘a’ I _l____‘ \ 200

i ‘n’ is 4 times a <\sequence16 elements 4-value 202

signal a = 3102

Sequence n = 012033210312

sequence Res = 321 3001 230211 03122301 20321 023301 231 003201 1 2301 32

B

fs3 o 1 2 3 o 2 1 o 3 \ Flgure 17. A 1 1 0 3 2 204 2 0 3 2 1 3 3 2 1 0

US 2005/0053240 A1 Mar. 10, 2005

TERNARY AND HIGHER MULTI-VALUE DIGITAL or sequence of binary digits. The input and output of a SCRAMBLERS/DESCRAMBLERS scrambler are .in general and preferably dissimilar. The dissimilarity of the input and the output sequences depends STATEMENT OF RELATED CASES on the input sequence, the length of the shift register, the number and place of taps and applied Modulo-2 add opera [0001] This application claims the bene?t of US. Provi tions and initial content of the shift register. sional Patent Application No. 60/501,335, ?led on Sep. 9, 2003, the entirety of Which is hereby incorporated by [0009] The descrambler has as its input the output of the reference into this document. scrambler. The descrambler reverses the operation of the scrambler and can recover, Without mistakes, the original BACKGROUND OF THE INVENTION uncoded digital message that formed the input to the scram bler. [0002] The present invention relates to telecommunica [0010] The common element in all binary scramblers and tions of digital signals. In particular, the present invention descramblers are the binary Modulo-2 additions. The binary relates to coding a and decoding of the coded logical operation is also knoWn under its binary logic digital signal Without error and loss of information. designation: Exclusive OR or XOR or #. [0003] Digital coding is applied Widely for the transmis [0011] Scramblers and descramblers are currently binary sion of signals over optical, cable, radio connections and methods or devices that are composed of binary XOR other transmission media. Coding is applied to transmitted functions. Binary XOR functions have the property of signals for several reasons. For eXample, coding helps retain Modulo-2 addition. Modulo-2 addition is identical to the quality of the digitally coded signal after transmission. It Modulo-2 subtraction. In general, a binary signal is can also hide the content of the coded message or signal. scrambled by adding it to another knoWn binary signal under Coding can also protect the coded message against interfer Modulo-2 rules. The original binary signal can be recovered ence or jamming, and can increase the capacity of the from the scrambled signal by Modulo-2 subtraction of the transmission medium to alloW the medium to handle a knoWn binary signal from the scrambled signal. Because greater number of messages or signals. Modulo-2 addition and Modulo-2 subtraction are both rep [0004] More particularly, the present invention relates to resented by the binary logic XOR function, binary scram the area of ternary and higher, multi-value digital scrambling bling and descrambling take place by the same binary logic methods and apparatus as Well as descrambling methods and function. While Modulo-2 addition is identical to Modulo-2 apparatus. The method and apparatus of the present inven subtraction, that identity is not true for Modulo-3 and higher tion Which applies methods that generate digital sequences Modulo-n addition and subtraction. It is apparent to the Which are the coded form of digital message to be trans inventor that the more fundamental description of identical mitted or Which form a substantial basis for creating coded scrambling/descrambling functions is that tWo binary inputs messages. Aand B generate a binary output C. If A and C are the inputs to the function, the output B is generated. Or if B and C are [0005] Typical digital transmission systems have transmit the inputs to the function, A is generated as the output. ters and receivers. The original message to be transmitted Binary scrambling functions can also be applied in binary can be any type of signal, such as voice, video, teXt or any Direct Sequence Spread Spectrum coding Where an initial other data format. The signal is digitiZed, coded and then binary digital sequence is combined With a secondary, binary modulated to be transmitted over the transmission medium. sequence With substantially more digits through a binary At the receiving end, the signal is demodulated, decoded and scrambling function. then applied to some device to re-constitute the original message format. [0012] In many cases it Would be bene?cial, either to the performance, quality or capacity of the [0006] The digitiZed message has been generally repre system to transmit modulated digital signals that represent sented in binary (or 2-value) format. This means that the higher value digits. For instance a cable system may transmit signal provided to the coder is a binary signal and the signal 3-value or ternary signals to balance the Direct Current provided to the decoder is also a binary signal. component of the signals in the transmission system. These [0007] There are different Ways to implement binary cod ternary signals can assume one of three states. The use of ing and decoding. In the prior art, a Well established Way to multi-value (greater than 2) signals also can increase the code a binary message is by applying a binary scrambler. A capacity (in information rate, or number of users) of a binary scrambler is an electronic device or an eXecuted communication system. Nevertheless, many systems limit method that has as its input a series or sequence of binary themselves to operating in a binary fashion. This is because digits, Which Will be guided through a ?nite length shift of the availability and pervasiveness of binary technology register or a computer program that acts as such. The content and the lack of ternary and higher multi-value methods and of pre-established cells of the shift register Will be tapped technologies. and connected to an element that Will conduct a speci?c binary operation on tWo binary elements. In the prior art, this [0013] The availability of ternary (or 3-value) methods operation is overWhelmingly Modulo-2 addition. The result (even if eXecuted in binary fashion) Would greatly improve the performance of digital systems. Signal coding is an of the Modulo-2 addition can be fed back into the shift eXample of an area that Would be greatly improved by the register, fed into a neXt Modulo-2 addition or being sent to use of ternary or multi-value scrambling techniques. Also, as the stage of the transmission. higher value scramblers have a greater number of scram [0008] If the input to a binary scrambler is a sequence of bling functions, the application of ternary and higher value binary digits, the output of a binary scrambler is also a series scramblers can make a spread-spectrum signal much harder