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California State University, Northridge Pcie Configuration for Data Transfer at Rate of 2.5-Giga Bytes Per Second (Gbps): for Da CALIFORNIA STATE UNIVERSITY, NORTHRIDGE PCIE CONFIGURATION FOR DATA TRANSFER AT RATE OF 2.5-GIGA BYTES PER SECOND (GBPS): FOR DATA ACQUISITION SYSTEM A graduate project submitted in partial fulfillment of the requirements For the degree of Master of Science in Electrical Engineering By Avani Dave May 2013 The graduate project of Avani Dave is approved: Dr. Emad El Wakil Date Dr. Somnath Chattopadhayay Date Dr. Nagi El Naga, Chair Date California State University, Northridge ii ACKNOWLEDGEMENT I wish to express my appreciation to those who have served on my graduate project. Firstly, I would like to thank Dr. Nagi El Naga for his valuable advice and guidance throughout my project. His constant support and encouragement has helped me learn a great deal all through the project. He was instrumental in providing not only all the guidance but also inspiration that I needed. I also wish to acknowledge special appreciation to Information and Technology Department’s Mr. Emil Henry and Mr. Armando Tellez for their help and support for driver’s installations. Special thanks to Dr. Somnath Chattopadhyay and Dr. Emad El wakil for their valuable comments on my work. I also wish to acknowledge special appreciation and thanks to the best and brightest engineers of Xilinx help and supports, who have helped me throughout my project. Their input, comments and guidance helped immensely in learning the finer details of the subject, grasping new ways of learning concepts and successfully completing this project. Finally, the patience and support from my parents, family and friends has been enormously important to me while I have been engaged in the graduate project. Thanks to all of you. iii TABLE OF CONTENTS SIGNATURE PAGE .......................................................................................................... ii ACKNOWLEDGEMENTS ............................................................................................... iii LIST OF FIGURES ............................................................................................................ v ABSTRACT ...................................................................................................................... vii CHAPTER 1 INTRODUCTION…………………………………………………………1 1.1 Basic concept of data acquisition system…………………………………..………….1 1.2 Objective.. ..................................................................................................................... 2 1.3 Project Outline .............................................................................................................. 3 CHAPTER 2 DATA ACQUISITION SYSTEM FOR 32X32 PHOTO DETECTOR ARRAY…………………………………………………………………………………...4 2.1 Top Level Architecture ................................................................................................. 4 2.2 Detailed Design Implimentation ................................................................................... 5 2.3 Specification and Features ............................................................................................ 6 CHAPTER 3 INTRODUCTION TO PCIE……………………………………………..9 3.1 Background of Computer Bus Systems ........................................................................ 9 3.2 Why to choose PCIE ................................................................................................... 11 3.3 PCIE Basics ................................................................................................................ 12 3.3.1 Working principal ……………………………………………………………….12 3.3.2 Differential Signaling............................................................................................ 13 3.3.3 Lanes ..................................................................................................................... 14 3.3.4 Transmission Rate ................................................................................................. 15 3.4 LogiCore PCIE Block………………………………………………………..............15 3.5 Protocol Layer......……...…………………………………………………………….17 CHAPTER 4 IMPLIMENTATION OF PCIE…………………………………………..18 4.1 Hardware Setup ........................................................................................................... 18 4.2 Driver’s Installation .................................................................................................... 19 4.3 Software Installation ................................................................................................... 20 4.4 Logic Core PCIE Generation..…………………………………………….................22 4.5 Programming ML605……………………………………………………………..….30 CHAPTER 5 TESTING AND VERIFICATION……………………………………….37 5.1 PCIE Functional Testing……………………………………………………...............37 5.2 Simulation ................................................................................................................ ...49 CHAPTER 6 CONCLUSION AND FUTURE SCOPE .................................................. 54 REFERENCES ................................................................................................................. 55 iv LIST OF FIGURES Figure 1.1 Block diagram of Data Acquisition System…………………………………...2 Figure 2.1 Top Level Design of Data Acquisition System…………………………..........4 Figure 2.2 Detailed Design Implementation of data Acquisition system…………………5 Figure 2.3 Pulse Data Transfer……………………………………………………………6 Figure 3.1 Various buses connected to the CPU............................................................... 10 Figure 3.2 Comparison of technology and data transfer rate….………………………....11 Figure 3.3.1 PCIE and motherboard socket connector……………………………..……12 Figure 3.3.2 A Differential signal pair and subtract or…………………………………...13 Figure 3.3.2 B signal pulse and noise subtraction. ........................................................... 13 Figure 3.3.3 A PCIE x1 four-wire lane configuration....……………………..…………..14 Figure 3.3.3 B PCIE lane connectors with speed grad ..................................................... 14 Figure 3.4 Functional Block Diagram and interfaces for logiCORE IP ........................... 15 Figure 3.5 Protocol Layers ................................................................................................ 17 Figure 4.1 PCIE x 8 slot connected to ML605 (Lab server) ............................................. 18 Figure 4.2 Driver’s installation and com-port opening…………………………………..19 Figure 4.3 A Tera-term connections ................................................................................. 20 Figure 4.3 B DIP switch S1 setting (1000) ....................................................................... 20 Figure 4.3 C Compact Flash Card Insertion…………………………………………...…21 Figure 4.3 D Built In System Test menu (BIST) .............................................................. 21 Figure 4.4.1 A Core Generator-New Project .................................................................... 22 Figure 4.4.1 B Select Device Parameter ........................................................................... 23 Figure 4.4.1 C Customizing PCIE Core…………………………………….……..……...23 Figure 4.4.1 D Clock Parameter Setting ........................................................................... 24 Figure 4.4.1 F Base Address Register(BAR) setting ........................................................ 25 Figure 4.4.1 G Vendor ID Setting………………………………...……………………..26 Figure 4.4.1 H Xilinx development Board ML605 selection ........................................... 27 Figure 4.4.1 I Reference Clock Frequency Select ............................................................ 27 Figure 4.4.1 J PCIE core generate .................................................................................... 28 Figure 4.4.1 K Project IP……………………………………………………………..…..28 Figure 4.4.1 L Script to Generate Core ............................................................................. 29 Figure 4.4.1 M Script to Make routed.bit ......................................................................... 29 Figure 4.5 A S1 an S2 switch settings .............................................................................. 30 Figure 4.5 B IMPAC ...………….......................................................................................31 Figure 4.5 C PROM .................................................................................................. …..31 Figure 4.5 D Setting PROM Parameters………………………………………………….32 Figure 4.5 E Setting PROM Parameters ........................................................................... 32 Figure 4.5 F Setting PROM Parameters………………………………………………….32 Figure 4.5 G loading.bit file .............................................................................................. 33 Figure 4.5 H BPI settings .................................................................................................. 33 Figure 4.5 I Generate File…………...…………………………………………………...34 Figure 4.5 J Boundary scans……………………………………………………...............34 Figure 4.5 K Initialize chain……..……………………………………………………….35 Figure 4.5 L Select Device xc6vlx240t……………………………………………….….35 Figure 4.5 M SPI/BPI PROM setting…………………………………………………….36 v Figure 4.5 N Programming Flash…………………………………………………………36 Figure 5.1 A PCI TREE…………………………………………………………………..37 Figure 5.1 B Intel’s x8086 PCIE bridge device ……………….………………………....38 Figure 5.1 C Xilinx’s ML-605 device…………………………………………………….38 Figure 5.1 D Configuration registers……………………………………………………..39 Figure 5.1 E Configuration registers editing……………………………….…………….40 Figure 5.1 F Configuration Register Read……………………………………………….41
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