US 20080057659A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2008/0057659 A1 Forbes et al. (43) Pub. Date: Mar. 6, 2008

(54) HAFNIUM ALUMINIUM OXYNITRIDE Publication Classification HIGH-K DELECTRIC AND METAL GATES (51) Int. Cl. (75) Inventors: Leonard Forbes, Corvallis, OR HOIL 2L/20 (2006.01) (US); Kie Y. Ahn, Chappaqua, NY (US); Arup Bhattacharyya, Essex (52) U.S. Cl...... 438/381 Junction, VT (US) Correspondence Address: (57) ABSTRACT SCHWEGMAN, LUNDBERG & WOESSNER, Electronic apparatus and methods of forming the electronic P.A. P.O. BOX 2938 apparatus include a hafnium aluminum oxynitride film on a MINNEAPOLIS, MN 55402 substrate for use in a variety of electronic systems. The hafnium aluminum oxynitride film may be structured as one (73) Assignee: Micron Technology, Inc. or more monolayers. The hafnium aluminum oxynitride film (21) Appl. No.: 11/514,558 may be formed using atomic layer deposition. Metal elec trodes may be disposed on a dielectric containing a hafnium (22) Filed: Aug. 31, 2006 aluminum oxynitride film.

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2 FORMALAYER OFHFAO USING ATOMICLAYERDEPOSITION 22) NITRDIZETHELAYEROFHFAO TOFORMAFILM OFHFAION FIG. 2A

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HAFNUMALUMNIUM OXYNTRIDE other requirements in microelectronic devices have created HIGH-K DELECTRIC AND METAL GATES the need to use other materials as dielectric regions in a variety of electronic structures. RELATED APPLICATIONS 0001. This application is related to the co-pending and BRIEF DESCRIPTION OF THE DRAWINGS commonly assigned applications U.S. application Ser. No. 0005 FIG. 1 depicts an embodiment of an atomic layer 10/229,903, entitled “ATOMIC LAYER DEPOSITED deposition system for processing a hafnium aluminum HfSiON DIELECTRIC FILMS, filed on 28 Aug. 2002, oxynitride film. U.S. application Ser. No. 11/216,474, entitled “LANTHA 0006 FIG. 2A shows a flow diagram of features of an NUM ALUMINUM OXYNITRIDE DIELECTRIC embodiment for forming a hafnium aluminum oxynitride FILMS,” filed on 31 Aug. 2005, U.S. application Ser. No. film using atomic layer deposition and nitridization. 11/355.490, entitled “CONDUCTIVE LAYERS FOR 0007 FIG. 2B shows a flow diagram of features of an HAFNIUM SILICON OXYNITRIDE FILMS, filed on 16 embodiment for forming hafnium aluminum oxide using Feb. 2006, U.S. application Ser. No. 11/010,529, entitled atomic layer deposition for nitridization to a hafnium alu ATOMIC LAYER DEPOSITED LANTHANUM minum oxynitride film. HAFNIUM OXIDE DIELECTRICS, filed on 13 Dec. 0008 FIG. 3 shows a flow diagram of features of an 2004, and U.S. application Ser. No. 10/352.507, entitled embodiment for forming a hafnium aluminum oxynitride ATOMIC LAYER DEPOSITION OF METAL OXYNI film using atomic layer deposition and oxidation. TRIDE LAYERS AS GATE DIELECTRICS AND SEMI 0009 FIG. 4 shows a flow diagram of features of an CONDUCTOR DEVICE STRUCTURES UTILIZING embodiment for forming hafnium aluminum oxynitride film METAL OXYNITRIDE LAYER, filed on 27 Jan. 2003, using atomic layer deposition and annealing. which applications are incorporated herein by reference. (0010 FIGS.5A-5E illustrate an embodiment of a process 0002 This application is also related to U.S. Patent for forming a metal substituted electrode. Applications filed herewith on the same date. These patent 0011 FIG. 6 illustrates a flow diagram of features of an applications are U.S. application Ser. No. entitled embodiment of a metal Substitution technique. & G ” (Attorney Docket No. 1303.177US1), U.S. appli (0012 FIGS. 7A-7D illustrate an embodiment of a process cation Ser. No. entitled “ATOMIC LAYER for forming a self aligned conductive layer. DEPOSITED SILICON LANTHANIDE OXYNITRIDE 0013 FIG. 8 illustrates an embodiment of a method for FILMS’’ (Attorney Docket No. 1303.179US1), U.S. appli forming a self aligned metal gate on high-K gate dielectrics cation Ser. No. entitled “ATOMIC LAYER containing a hafnium aluminum oxynitride film. DEPOSITED HAFNIUM ILANTHANIDE OXYNITRIDE 0014 FIG. 9 illustrates a wafer containing integrated FILMS’’ (Attorney Docket No. 1303.180US1), U.S. appli circuits having a hafnium aluminum oxynitride film. cation Ser. No. entitled “ (Attorney Docket 0015 FIG. 10 shows an embodiment of a transistor No. 1303.181US1), U.S. application Ser. No. s having a dielectric layer including a hafnium aluminum entitled ATOMIC LAYER DEPOSITED TANTALUM oxynitride film. LANTHANIDE OXYNITRIDE FILMS (Attorney Docket 0016 FIG. 11 shows an embodiment of a floating gate No. 1303.182US1), U.S. application Ser. No. s transistor having a dielectric layer including a hafnium entitled “ ” (Attorney Docket No. 1303.184US1), and aluminum oxynitride film. U.S. application Ser. No. entitled “(Attorney 0017 FIG. 12 shows an embodiment of a capacitor Docket No. 1303.185US1), which patent applications are having a dielectric layer including a hafnium aluminum incorporated herein by reference. oxynitride film. 0018 FIG. 13 depicts an embodiment of a dielectric layer TECHNICAL FIELD having multiple layers including a hafnium aluminum 0003. This application relates generally to semiconductor oxynitride layer. devices and device fabrication and more particularly, 0019 FIG. 14 is a simplified diagram for an embodiment devices having a high-K dielectric. of a controller coupled to an electronic device having a dielectric layer including a hafnium aluminum oxynitride BACKGROUND film. 0020 FIG. 15 illustrates a diagram for an embodiment of 0004. The semiconductor device industry has a market an electronic system including devices with a dielectric film driven need to reduce the size of devices used in products Such as processor chips, mobile telephones, and memory including a hafnium aluminum oxynitride film. devices such as dynamic random access memories DETAILED DESCRIPTION (DRAMs). Currently, the semiconductor industry relies on the ability to reduce or scale the dimensions of its basic 0021. The following disclosure refers to the accompany devices. This device Scaling includes Scaling a dielectric ing drawings that show, by way of illustration, specific layer in devices such as, for example, capacitors and silicon details and embodiments. These embodiments are described based metal oxide semiconductor field effect transistors in sufficient detail to enable those skilled in the art to (MOSFETs), which have primarily been fabricated using practice the present invention. Other embodiments may be silicon dioxide. A thermally grown amorphous SiO pro utilized and structural, logical, and electrical changes may vides an electrically and thermodynamically stable material, be made without departing from the scope of the invention. where the interface of the SiO layer with underlying silicon The various embodiments are not necessarily mutually provides a high quality interface as well as Superior electri exclusive, as some embodiments can be combined with one cal isolation properties. However, increased scaling and or more other embodiments to form new embodiments. US 2008/0057659 A1 Mar. 6, 2008

0022. In the following description, the terms wafer and to be about 7-8 A.Therefore, for future devices to have atg Substrate may be used interchangeably to refer generally to less than about 10 A, other dielectrics than SiO, need to be any structure on which integrated circuits are formed and considered for use as a dielectric region in Such future also to such structures during various stages of integrated devices. circuit fabrication. The term substrate is understood to 0026. In many cases, for a typical dielectric layer, the include a semiconductor wafer. The term substrate is also capacitance is determined as one for a parallel plate capaci used to refer to semiconductor structures during processing tance: CKeoA/t, where K is the dielectric constant, eo is the and may include other layers that have been fabricated permittivity of free space, A is the area of the capacitor, and thereupon. Both wafer and substrate include doped and t is the thickness of the dielectric. The thickness, t, of a undoped semiconductors, epitaxial semiconductor layers material is related to its to for a given capacitance, with Supported by a base semiconductor or insulator, as well as SiO, having a dielectric constant K, 3.9, as other semiconductor structures well known to one skilled in the art. The term conductor is understood to generally include n-type and p-type semiconductors and the term Thus, materials with a dielectric constant greater than that of insulator or dielectric is defined to include any material that SiO, 3.9, will have a physical thickness that can be con is less electrically conductive than the materials referred to siderably larger than a desired t, while providing the as conductors. The following detailed description is, there desired equivalent oxide thickness. For example, an alter fore, not to be taken in a limiting sense. native dielectric material with a dielectric constant of 10 0023 To scale a dielectric region to minimize feature could have a thickness of about 25.6 A to provide at of 10 sizes to provide high density electronic devices, the dielec A, not including any depletion/inversion layer effects. Thus, tric region should have a reduced equivalent oxide thickness a reduced equivalent oxide thickness for transistors can be (t). The equivalent oxide thickness quantifies the electrical realized by using dielectric materials with higher dielectric properties, such as capacitance, of a dielectric in terms of a constants than SiO. representative physical thickness, t, is defined as the thick 0027. The thinner equivalent oxide thickness required for ness of a theoretical SiO layer that would be required to lower device operating Voltages and Smaller device dimen have the same capacitance density as a given dielectric, sions may be realized by a significant number of materials, ignoring leakage current and reliability considerations. but additional fabricating requirements make determining a suitable replacement for SiO, difficult. The current view for 0024. A SiO layer of thickness, t, deposited on a silicon the microelectronics industry is still for silicon-based surface will have at larger than its thickness, t. This t. devices. This may require that the dielectric material results from the capacitance in the surface on which the SiO, employed be grown on a silicon Substrate or a silicon layer, is deposited due to the formation of a depletion/inversion which places significant constraints on the Substitute dielec region. This depletion/inversion region can result in t tric material. During the formation of the dielectric on the being from 3 to 6 Angstroms (A) larger than the SiO, silicon layer, there exists the possibility that a small layer of thickness, t. Thus, with the semiconductor industry driving to someday scale a gate dielectric equivalent oxide thickness SiO could be formed in addition to the desired dielectric. to less than 10 A, the physical thickness requirement for a The result would effectively be a dielectric layer consisting SiO layer used for a gate dielectric may need to be approxi of two sublayers in parallel with each other and the silicon mately 4 to 7 A. Additional requirements on a SiO, layer layer on which the dielectric is formed. In such a case, the would depend on the electrode used in conjunction with the resulting capacitance would be that of two dielectrics in SiO2 dielectric. Using a conventional polysilicon electrode series. As a result, the t of the dielectric layer would be the may result in an additional increase in t for the SiO, layer. sum of the SiO2 thickness and a multiplicative factor of the Thus, designs for future devices may be directed towards a thickness, t, of the dielectric being formed, written as physical SiO, dielectric layer of about 5 A or less. Such a Small thickness requirement for a SiO2 oxide layer creates Thus, if a SiO, layer is formed in the process, the t is again additional problems. limited by a SiO layer. In the event that a barrier layer is 0025 Silicon dioxide is used as a dielectric layer in formed between the silicon layer and the desired dielectric devices, in part, due to its electrical isolation properties in a in which the barrier layer prevents the formation of a SiO, SiO Si based structure. This electrical isolation is due to layer, the t, would be limited by the layer with the lowest the relatively large band gap of SiO (8.9 eV), making it a dielectric constant. However, whether a single dielectric good insulator from electrical conduction. Significant reduc layer with a high dielectric constant or a barrier layer with tions in its band gap may eliminate it as a material for a a higher dielectric constant than SiO is employed, the layer dielectric region in an electronic device. As the thickness of interfacing with the silicon layer should provide a high a SiO layer decreases, the number of atomic layers or quality interface. monolayers of the material decreases. At a certain thickness, 0028. One of the advantages of using SiO, as a dielectric the number of monolayers will be sufficiently small that the layer in a device has been that the formation of the SiO, SiO layer will not have a complete arrangement of atoms as layer results in an amorphous dielectric. Having an amor in a larger or bulk layer. As a result of incomplete formation phous structure for a dielectric provides for reducing prob relative to a bulk structure, a thin SiO, layer of only one or lems of leakage current associated with grain boundaries in two monolayers may not form a full band gap. The lack of polycrystalline dielectrics that provide high leakage paths. a full band gap in a SiO, dielectric may cause an effective Additionally, grain size and orientation changes throughout short between an underlying electrode and an overlying a polycrystalline dielectric can cause variations in the film's electrode. This undesirable property sets a limit on the dielectric constant, along with uniformity and Surface topog physical thickness to which a SiO layer can be scaled. The raphy problems. Materials having a high dielectric constant minimum thickness due to this monolayer effect is thought relative to SiO, may also have a crystalline form, at least in US 2008/0057659 A1 Mar. 6, 2008

a bulk configuration. The best candidates for replacing SiO, the constructed film. Films with nitrogen concentration as a dielectric in a device are those that can be fabricated as twice that of oxygen (for example, approximately 40 atomic a thin layer with an amorphous form and that have high per cent nitrogen, approximately 20 atomic per cent oxygen, dielectric constants. and approximately 40 atomic per cent metal or silicon) have 0029 Capacitor applications have used high-K dielectric a lower bandgap, higher trap density, and transport charac materials, which are insulating materials having a dielectric teristics dominated by Frenkel-Poole conduction. Such constant greater than silicon dioxide. Such high-K dielectric materials may not be well Suited for gate dielectric appli materials include silicon oxynitride (SiON, K-6), alumina cations. However, such films exhibit higher K values. With (Al2O, K-9), and oxide/nitride composites (SiO/SiN increasing oxygen concentration in oxynitride films, the K-6). Other possible candidates include metal oxides (K-8- bandgap is raised, current leakage is reduced, and the low 80), nitrides (K-7-30), oxynitrides (K-6-25), silicates (K-6- frequency K value is also somewhat reduced. In addition 20), carbides (K-6-15), and complex titanates (K->100). In with increasing oxygen concentration, the trap density is one embodiment, the dielectric is a hafnium aluminum reduced, the trap energy depth is increased, and the carrier oxynitride. Factors for selecting appropriate materials transport ceases to be trap-assisted, exhibits tunneling con include physical, chemical and thermal stability as well as duction, and has a weak temperature dependence, if any. In etch-ability and stoichiometric reproducibility. In field effect various embodiments, a dielectric layer includes an oxyni transistor (FET) applications, there are other factors to tride film having approximately 30 atomic 96 oxygen and consider while addressing device scalability. The selected approximately 30-35 atomic 9% nitrogen. In an embodi dielectric should provide stable amorphous and adherent ments, a dielectric layer includes an oxynitride film having films in the thickness range of 1 nm to 100 nm at tempera approximately 30 atomic '% oxygen and approximately 30 tures ranging from room temperature to 1000° C. A rela atomic '% nitrogen. In an embodiment, a dielectric layer tively defect-free composition that is uniform and reproduc includes an oxynitride film having approximately 25-35 ible with a fixed charge density and trap density of less than atomic '% oxygen and approximately 25-40 atomic '% nitro 10' cm' in films of such composition is a factor. A factor gen. With high enough nitrogen content, oxygen-vacancy includes dielectric materials that provide a stable non induced defects in films is negligible when compared with reactive interface with a silicon substrate such that the metal oxides. interface has an interface state density much less than 10' 0031 Silicon oxynitride (SiON) has been used as a gate cm. Such interface state densities may occur when silicon dielectric and gate insulator for a non-volatile FET device. bonds at the interface are saturated with high strength Silicon oxynitride at a composition range of SiON exhibits covalent bonds with molecular elements of the dielectric a dielectric constant of 6.5 and a bandgap of approximately material. Another factor deals with current transport through 6.5 eV compared to a stoichiometric nitride of K=7.5 and a the dielectric that should be controlled by tunneling, which bandgap of 5.1 eV. Aluminum oxynitride (AlON) is is independent of temperature, rather than by trap-assisted expected to have a bandgap greater than 5 eV with a K value thermally dependent transport. The conductivity of the similar to SiON. Compared to SiON, metal oxynitrides such dielectric should be equal to or lower than SiO films when as ZrON, HfCN, LaON, and TaON and other single metal voltage is stressed to a field strength of 5x10° V/cm. To oxynitrides are expected to have a lower bandgap. address the current transport, a dielectric material having a 0032. In various embodiments, bimetal (or metal/silicon) bandgap greater than 5 eV and having an electron and hole oxynitrides based on Si, Al, Hf, La, and Ta are used as barrier height greater than 2 eV at a silicon interface may be dielectric films in a variety of electronic devices and sys considered. An additional factor to consider is using dielec tems. These bimetal oxynitrides may provide a bandgap tric materials with a destructive breakdown strength greater range from 5 eV to greater than 7 eV. Estimates for bandgaps than 6x10° V/cm. Other factors for selecting a dielectric include a bandgap of Si Al-ON of greater than 7 eV, a material for use in a variety of electronic devices, such as for bandgap of Si Hf ON of about 6.9 eV, a bandgap of the dielectric in FETs, relates to processing characteristics. Al Hf ON of about 6.8 eV, a bandgap of Si Ta-ON of Such processing characteristics include compatibility with about 6 eV. a bandgap of Al Ta—ON of about 6 eV. gate material, selective etch-ability, chemical inertness to Bimetal oxynitrides Hf Ta—ON, Hf La ON, Al-La contaminants, dopant and post processing environments ON, Ta-La-ON, and Si La—ON are estimated to (temperature, pressure, ambients), and intrinsic properties exhibit significantly lower bandgaps. The K value for associated with annealing of defects/damages caused by Si Al ON is estimated at approximately 7 to 8, while the post-processing Such as ion-implantation, plasma-radiation, K values for the other oxynitrides of this group are estimated and gate/back-end processing. to be in the range from about 15 to 25. 0030. In various embodiments, mixed metal oxynitrides 0033. In an embodiment, a film of hafnium aluminum (with silicon included as a metal) are constructed as dielec oxynitride may be used as a dielectric layer for application tric films in a variety of electronic devices and systems. in a variety of electronic devices, replacing the use of silicon Most oxynitrides are thermally stable and can integrate into oxide to provide a higher dielectric constant. In various semiconductor device processing. With nitrogen concentra embodiments, a dielectric layer may be constructed contain tion in an oxynitride film at 30% or higher, such oxynitrides ing hafnium aluminum oxynitride formed using atomic layer are chemically inert. With processing conditions controlled deposition with a metal electrode formed in contact with the to provide very low partial pressures of hydrogen and ON dielectric layer. The metal electrode may be formed by ions, oxynitride films with a wide range of nitrogen to atomic layer deposition. The metal electrode may be formed oxygen ratio can be deposited over a silicon Substrate with by Substituting a desired metal material for a previously very low fixed charge and interface states density. On the disposed substitutable material. The metal electrode may be other hand, charge trapping and transport characteristics are formed as a self aligned metal electrode on and contacting dependent on relative ratio of nitrogen to oxygen content in the dielectric layer. The metal electrode may be formed on US 2008/0057659 A1 Mar. 6, 2008 the dielectric layer using a previously disposed sacrificial other aggressively on the Substrate, one ALD cycle can be carbon layer on the dielectric layer and sacrificial carbon performed in less than one second in properly designed flow sidewall spacers adjacent to the sacrificial carbon layer. type reaction chambers. Typically, precursor pulse times 0034. The term hafnium aluminum oxynitride is used range from about 0.5 sec to about 2 to 3 seconds. Pulse times herein with respect to a composition that essentially consists for purging gases may be significantly longer, for example, of hafnium, aluminum, oxygen, and nitrogen in a form that pulse times of about 5 to about 30 seconds. may be stoichiometric, non-stoichiometric, or a combination 0039. In ALD, the saturation of all the reaction and of Stoichiometric and non-stoichiometric. A hafnium alumi purging phases makes the growth self-limiting. This self num oxynitride film may also be referred to as an aluminum limiting growth results in large area uniformity and confor hafnium oxygen nitrogen film or a hafnium aluminum mality, which has important applications for Such cases as oxygen nitrogen film. Other nomenclature for a composition planar Substrates, deep trenches, and in the processing of that essentially consists of hafnium, aluminum, oxygen, and porous silicon and high Surface area silica and alumina nitrogen may be known to those skilled in the art. In an powders. Atomic layer deposition provides control of film embodiment, hafnium aluminum oxynitride is formed Sub thickness in a straightforward manner by controlling the stantially as a stoichiometric hafnium aluminum oxynitride number of growth cycles. film. In an embodiment, hafnium aluminum oxynitride is formed substantially as a non-stoichiometric HfAlON film. 0040. The precursors used in an ALD process may be In an embodiment, hafnium aluminum oxynitride may be gaseous, liquid or solid. However, liquid or Solid precursors formed Substantially as a combination film of non-stoichio should be volatile. The vapor pressure should be high metric hafnium aluminum oxynitride and stoichiometric enough for effective mass transportation. Also, Solid and hafnium aluminum oxynitride. Herein, a hafnium aluminum Some liquid precursors may need to be heated inside the oxynitride composition may be expressed as Hf AlON, HfA atomic layer deposition system and introduced through LON, Hf, Al, ON, or other equivalent form. With respect heated tubes to the Substrates. The necessary vapor pressure to forms that are stoichiometric, non-stoichiometric, or a should be reached at a temperature below the substrate combination of Stoichiometric and non-stoichiometric, temperature to avoid the condensation of the precursors on expressions such as AlN, ALO, ALN, HfoN, AION, AlON, the substrate. Due to the self-limiting growth mechanisms of LaO, AIN., Hfo, HfN HfCN, AION AION, etc. may be ALD, relatively low vapor pressure solid precursors can be used in a similar manner as AlO. In various embodiments, used, though evaporation rates may vary somewhat during a hafnium aluminum oxynitride film may be doped with the process because of changes in their Surface area. elements or compounds other than hafnium, aluminum, 0041. There are several other characteristics for precur oxygen, and nitrogen. sors used in ALD. The precursors should be thermally stable at the Substrate temperature, because their decomposition Atomic Layer Deposition may destroy the Surface control and accordingly the advan tages of the ALD method that relies on the reaction of the 0035. In an embodiment, a hafnium aluminum oxynitride precursor at the Substrate Surface. A slight decomposition, if dielectric film may be formed using atomic layer deposition slow compared to the ALD growth, may be tolerated. (ALD). Forming Such structures using atomic layer deposi tion may allow control of transitions between material 0042. The precursors should chemisorb on or react with layers. As a result of Such control, atomic layer deposited the Surface, though the interaction between the precursor and hafnium aluminum oxynitride dielectric films can have an the Surface as well as the mechanism for the adsorption is engineered transition with a Substrate surface. different for different precursors. The molecules at the 0036 ALD, also known as atomic layer epitaxy (ALE), is Substrate Surface should react aggressively with the second a modification of chemical vapor deposition (CVD) and is precursor to form the desired solid film. Additionally, pre also called “alternatively pulsed-CVD. In ALD, gaseous cursors should not react with the film to cause etching, and precursors are introduced one at a time to the Substrate precursors should not dissolve in the film. Using highly surface mounted within a reaction chamber (or reactor). This reactive precursors in ALD contrasts with the selection of introduction of the gaseous precursors takes the form of precursors for conventional CVD. pulses of each gaseous precursor. In a pulse of a precursor 0043. The by-products in the reaction should be gaseous gas, the precursor gas is made to flow into a specific area or in order to allow their easy removal from the reaction region for a short period of time. Between the pulses, the chamber. Further, the by-products should not react or adsorb reaction chamber may be purged with a gas, where the on the Surface. purging gas may be an inert gas. Between the pulses, the 0044. In a reaction sequence ALD (RS-ALD) process, the reaction chamber may be evacuated. Between the pulses, the self-limiting process sequence involves sequential Surface reaction chamber may be purged with a gas and evacuated. chemical reactions. RS-ALD relies on chemistry between a 0037. In a chemisorption-saturated ALD (CS-ALD) pro reactive surface and a reactive molecular precursor. In an cess, during the first pulsing phase, reaction with the Sub RS-ALD process, molecular precursors are pulsed into the strate occurs with the precursor saturatively chemisorbed at ALD reaction chamber separately. A metal precursor reac the Substrate surface. Subsequent pulsing with a purging gas tion at the Substrate may be followed by an inert gas pulse removes precursor excess from the reaction chamber. to remove excess precursor and by-products from the reac 0038. The second pulsing phase introduces another pre tion chamber prior to pulsing the next precursor of the cursor on the substrate where the growth reaction of the fabrication sequence. desired film takes place. Subsequent to the film growth 0045. By RS-ALD, films can be layered in equal metered reaction, reaction byproducts and precursor excess are sequences that may all be identical in chemical kinetics, purged from the reaction chamber. With favorable precursor deposition per cycle, composition, and thickness. RS-ALD chemistry where the precursors absorb and react with each sequences generally deposit less than a full layer per cycle. US 2008/0057659 A1 Mar. 6, 2008

Typically, a deposition or growth rate of about 0.25 to about num hydride (DMAH), AlC, and other halogenated precur 2.00 A per RS-ALD cycle may be realized. sors and organometallic precursors. Oxidants can include a 0046 Processing by RS-ALD provides continuity at an water-argon mixture formed by bubbling an argon carrier interface avoiding poorly defined nucleating regions that are through a water reservoir, H2O, O, O, and NO to form typical for chemical vapor deposition (<20 A) and physical an embodiment of an aluminum/oxygen sequence, which is vapor deposition (<50 A), conformality over a variety of also referred to as an aluminum sequence. Additional infor Substrate topologies due to its layer-by-layer deposition mation regarding aluminum oxides formed by ALD can be technique, use of low temperature and mildly oxidizing found in U.S. Patent Application Publication processes, lack of dependence on the reaction chamber, 20030207032A1, entitled “METHODS, SYSTEMS, AND growth thickness dependent solely on the number of cycles APPARATUS FOR ATOMIC-LAYER DEPOSITION OF performed, and ability to engineer multilayer laminate films ALUMINUM OXIDES IN INTEGRATED CIRCUITS, with a resolution of one to two monolayers. RS-ALD which is herein incorporated by reference. processes allow for deposition control on the order of 0049. In forming a layer of a metal species, an ALD monolayers and the ability to deposit monolayers of amor sequence may deal with pulsing a reactant precursor to the phous films. Substrate surface on which a metal-containing species has 0047. Herein, a sequence refers to the ALD material been absorbed such that the reactant precursor reacts with formation based on an ALD reaction of a precursor with its the metal-containing species resulting in the deposited metal reactant precursor. For example, forming hafnium nitride and a gaseous by-product that can be removed during the from a HfCl precursor and NH, as its reactant precursor, Subsequent purging/evacuating process. Alternatively, in includes a hafnium/nitrogen sequence. In various ALD forming a layer of a metal species, an ALD sequence may processes that form a nitride or a composition that contains deal with reacting a precursor containing the metal species nitrogen, a reactant precursor that contains nitrogen is used with a Substrate surface. A cycle for Such a metal forming to Supply nitrogen. Herein, a precursor that contains nitrogen sequence may include pulsing a purging gas after pulsing the and that Supplies nitrogen to be incorporated in the ALD precursor containing the metal species to deposit the metal. composition formed, which may be used in an ALD process Additionally, deposition of a semiconductor material may be with precursors supplying the other elements in the ALD realized in a manner similar to forming a layer of a metal, composition, is referred to as a nitrogen reactant precursor. given the appropriate precursors for the semiconductor In the above example, NH is a nitrogen reactant precursor. material. Similarly, an ALD sequence for a metal oxide may be 0050. In an ALD formation of a composition having more referenced with respect to the metal and oxygen. For than two elements, a cycle may include a number of example, an ALD sequence for hafnium oxide may also be sequences to provide the elements of the composition. For referred to as a hafnium/oxygen sequence. In various ALD example, a cycle for an ALD formation of an ABO, com processes that form an oxide or a composition that contains position (where “A” is one element and “B” is a second oxygen, a reactant precursor that contains oxygen is used to element) may include sequentially pulsing a first precursor/a Supply the oxygen. Herein, a precursor that contains oxygen purging gas for the first precursor/a first reactant precursor/ and that Supplies oxygen to be incorporated in the ALD the first reactant precursors purging gas/a second precur composition formed, which may be used in an ALD process Soria purging gas for the second precursor/a second reactant with precursors supplying the other elements in the ALD precursor/the second reactant precursors purging gas, composition, is referred to as an oxygen reactant precursor. which may be viewed as a cycle having two sequences. In With an ALD process using HfCl and water vapor to form an embodiment, a cycle may include a number of sequences hafnium oxide, water vapor is an oxygen reactant precursor. for element A and a different number of sequences for An ALD cycle may include pulsing a precursor, pulsing a element B. There may be cases in which ALD formation of purging gas for the precursor, pulsing a reactant precursor, an ABO, composition uses one precursor that contains the and pulsing the reactant precursors purging gas. An ALD elements A and B. Such that pulsing the AB containing cycle may include pulsing a precursor, evacuating the reac precursor followed by its reactant precursor onto a substrate tant chamber, pulsing a reactant precursor, and evacuating may include a reaction that forms ABO, on the substrate to the reactant chamber. An ALD cycle may include pulsing a provide an AB/oxygen sequence. A cycle of an AB/oxygen precursor, pulsing a purging gas for the precursor and sequence may include pulsing a precursor containing A and evacuating the reactant chamber, pulsing a reactant precur B. pulsing a purging gas for the precursor, pulsing an oxygen Sor, and pulsing the reactant precursor's purging gas and reactant precursor to the A/B precursor, and pulsing a evacuating the reactant chamber. purging gas for the reactant precursor. A cycle may be 0048. Herein, a sequence refers to ALD material forma repeated a number of times to provide a desired thickness of tion based on an ALD reaction of a precursor with its the composition. In an embodiment, a cycle for an ALD reactant precursor. For example, forming tantalum oxide formation of the quaternary composition, hafnium alumi from a TaCls precursor and H2O, as its reactant precursor, num oxygen nitrogen, may include sequentially pulsing a forms an embodiment of a tantalum/oxygen sequence, first precursor/a purging gas for the first precursor/a first which can also be referred to as a tantalum sequence. reactant precursor/the first reactant precursors purging gas/a Additional information regarding tantalum oxides formed second precursor/a purging gas for the second precursor/a by ALD can be found in U.S. patent application Ser. No. second reactant precursor/the second reactant precursors 11/029,757, entitled “ATOMIC LAYER DEPOSITED purging gas/a third precursor/a purging gas for the third HAFNIUM TANTALUMOXIDE DIELECTRICS, which precursor/a third reactant precursor/the third reactant pre is herein incorporated by reference. An aluminum precursor cursors purging gas, which may be viewed as a cycle having can include a variety of precursors, such as trimethylalumi three sequences. In an embodiment, a layer Substantially of num (TMA), trisobutylaluminum (TIBA), dimethylalumi a hafnium aluminum oxynitride composition is formed on a US 2008/0057659 A1 Mar. 6, 2008

Substrate mounted in a reaction chamber using ALD in invention may be practiced on a variety of Such reaction repetitive aluminum/oxygen and hafnium/nitrogen chambers without undue experimentation. Furthermore, one sequences using precursor gases individually pulsed into the of ordinary skill in the art will comprehend the necessary reaction chamber. In an embodiment, a layer Substantially of detection, measurement, and control techniques in the art of a hafnium aluminum oxynitride composition is formed on a semiconductor fabrication upon reading the disclosure. Substrate mounted in a reaction chamber using ALD in 0054. In an embodiment, a hafnium aluminum oxynitride repetitive aluminum/nitrogen and hafnium/oxygen layer may be structured as one or more monolayers. A film sequences using precursor gases individually pulsed into the of hafnium aluminum oxynitride, structured as one or more reaction chamber. In an embodiment, a Substantially monolayers, may have a thickness that ranges from a mono hafnium aluminum oxynitride composition is formed by layer to thousands of angstroms or more. The film may be ALD having approximately 30% nitrogen and 30% oxygen processed using atomic layer deposition. Embodiments of an concentrations in the resultant HfAION dielectric film. In an atomic layer deposited hafnium aluminum oxynitride layer embodiment, a substantially hafnium aluminum oxynitride have a larger dielectric constant than silicon dioxide. Such composition is formed by ALD having approximately 25%- dielectric layers provide a significantly thinner equivalent 35% nitrogen and 25%-35% oxygen concentrations in the oxide thickness compared with a silicon oxide layer having resultant HfAION dielectric film. In an embodiment, the the same physical thickness. Alternatively, such dielectric nitrogen is less than 40%. In an embodiment, the oxygen is layers provide a significantly thicker physical thickness than less than 40%. a silicon oxide layer having the same equivalent oxide 0051 FIG. 1 shows an embodiment of an atomic layer thickness. This increased physical thickness aids in reducing deposition system 100 for processing a dielectric film con leakage current. taining a Hf, Al, ON, layer. The elements depicted are those 0055 Prior to forming the hafnium aluminum oxynitride elements necessary for discussion of various embodiments film using ALD, the Surface on which the hafnium aluminum for forming HfAION such that those skilled in the art may oxynitride film is to be deposited may undergo a preparation practice the present invention without undue experimenta stage. The Surface may be the Surface of a Substrate for an tion. A substrate 110 is located inside a reaction chamber 120 integrated circuit. In an embodiment, the Substrate used for of ALD system 100. Also located within reaction chamber forming a transistor may include a silicon or silicon con 120 is a heating element 130, which is thermally coupled to taining material. In other embodiments, silicon germanium, substrate 110 to control the substrate temperature. A gas germanium, gallium arsenide, silicon-on-Sapphire Sub distribution fixture 140 introduces precursor gases to the strates, or other suitable substrates may be used. A prepa Substrate 110. Each precursor gas originates from individual ration process may include cleaning the Substrate and form gas sources 150-155 whose flow is controlled by mass-flow ing layers and regions of the Substrate, such as drains and controllers 156-161, respectively. Gas sources 150-155 pro Sources, prior to forming a gate dielectric in the formation of vide a precursor gas either by storing the precursor as a gas a metal oxide semiconductor (MOS) transistor. Alterna or by providing a location and apparatus for evaporating a tively, active regions may be formed after forming the Solid or liquid material to form the selected precursor gas. dielectric layer, depending on the over-all fabrication pro Furthermore, additional gas sources may be included, one cess implemented. In an embodiment, the Substrate is for each metal precursor employed and one for each reactant cleaned to provide an initial substrate depleted of its native precursor associated with each metal precursor. oxide. In an embodiment, the initial Substrate is cleaned also 0052 Also included in the ALD system are purging gas to provide a hydrogen-terminated Surface. In an embodi sources 163, 164, each of which is coupled to mass-flow ment, a silicon substrate undergoes a final hydrofluoric (HF) controllers 166, 167, respectively. Furthermore, additional rinse prior to ALD processing to provide the silicon Sub purging gas sources may be constructed in ALD system 100, strate with a hydrogen-terminated Surface without a native one purging gas source for each precursor gas. For a process silicon oxide layer. that uses the same purging gas for multiple precursor gases, 0056 Cleaning immediately preceding atomic layer less purging gas sources are required for ALD system 100. deposition aids in reducing an occurrence of silicon oxide as Gas sources 150-155 and purging gas sources 163-164 are an interface between a silicon-based substrate and a hafnium coupled by their associated mass-flow controllers to a com aluminum oxynitride dielectric formed using the atomic mon gas line or conduit 170, which is coupled to the layer deposition process. The material composition of an gas-distribution fixture 140 inside reaction chamber 120. interface layer and its properties are typically dependent on Gas conduit 170 is also coupled to vacuum pump, or exhaust process conditions and the condition of the substrate before pump, 181 by mass-flow controller 186 to remove excess forming the dielectric layer. Though the existence of an precursor gases, purging gases, and by-product gases at the interface layer may effectively reduce the dielectric constant end of a purging sequence from gas conduit 170. associated with the dielectric layer and its substrate interface 0053 Vacuum pump, or exhaust pump, 182 is coupled by layer, a SiO2 interface layer or other composition interface mass-flow controller 187 to remove excess precursor gases, layer may improve the interface density, fixed charge den purging gases, and by-product gases at the end of a purging sity, and channel mobility of a device having this interface sequence from reaction chamber 120. For convenience, layer. control displays, mounting apparatus, temperature sensing 0057 The sequencing of the formation of the regions of devices, Substrate maneuvering apparatus, and necessary an electronic device. Such as a transistor, being processed electrical connections as are known to those skilled in the art may follow typical sequencing that is generally performed in are not shown in FIG. 1. The use, construction and funda the fabrication of such devices as is well known to those mental operation of reaction chambers for deposition of skilled in the art. Included in the processing prior to forming films are understood by those of ordinary skill in the art of a dielectric may be the masking of Substrate regions to be semiconductor fabrication. Embodiments of the present protected during the dielectric formation, as is typically US 2008/0057659 A1 Mar. 6, 2008

performed in semiconductor fabrication. In an embodiment, ment, H may be pulsed along with the precursor to reduce an unmasked region includes a body region of a transistor; carbon contamination in the deposited film. After pulsing the however, one skilled in the art will recognize that other aluminum-containing precursor and purging the reaction semiconductor device structures may utilize this process. chamber of excess precursor and by-products from pulsing 0058. In various embodiments, between each pulsing of the precursor, a reactant precursor may be pulsed into the a precursor used in an atomic layer deposition process, a reaction chamber. To form AlN, a nitrogen reactant precur purging gas may be pulsed into the ALD reaction chamber. sor is pulsed. A number of precursors containing nitrogen Between each pulsing of a precursor, the ALD reactor may be used to provide nitrogen. Such nitrogen-containing chamber may be evacuated using vacuum techniques as is precursors include, but are not limited to, nitrogen, ammonia known by those skilled in the art. Between each pulsing of (NH), tert-butylamine (CHN), allylamine (CHN), and a precursor, a purging gas may be pulsed into the ALD 1,1-dimethylhydrazine ((CH)NNH). In an embodiment, reaction chamber and the ALD reactor chamber may be the Substrate is maintained at a temperature ranging from evacuated. about 400° C. to about 500° C. using tert-butylamine or 0059. In an embodiment, an ALD cycle for forming allylamine as a nitrogen precursor. In an embodiment, NH HfAION includes sequencing component-containing precur may be pulsed with the tert-butylamine and the allylamine. sors in the order of aluminum, oxygen, hafnium, and nitro The addition of NH may enhance the deposition rate at gen with appropriate purging between the different compo lower temperatures. In various embodiments, use of the nent-containing precursors. Full coverage or partial individual aluminum-containing precursors is not limited to coverage of a monolayer on a Substrate Surface may be the temperature ranges of the above example embodiments. attained for pulsing of a metal-containing precursor. In an Further, forming aluminum nitride by atomic layer deposi embodiment, an ALD cycle for forming HfAlON includes tion is not limited to the abovementioned precursors. In sequencing the component-containing precursors in various addition, the pulsing of the aluminum precursor may use a permutations. In an embodiment, an ALD cycle to form pulsing period that provides uniform coverage of a mono hafnium aluminum oxynitride includes a number, X, of layer on the Surface or may use a pulsing period that aluminum/oxygen sequences and a number, y, of hafnium/ provides partial coverage of a monolayer on the Surface nitrogen sequences. In an embodiment, an ALD cycle to during a aluminum/nitrogen sequence. form hafnium aluminum oxynitride includes a number, X, of 0062. In various embodiments, after pulsing the alumi aluminum/nitrogen sequences and a number, y, of hafnium/ num-containing precursor and purging the reaction chamber oxygen sequences. In an embodiment, the number of of excess precursor and by-products from pulsing the pre sequences X and y is selected to engineer the relative cursor, a reactant precursor may be pulsed into the reaction amounts of hafnium, aluminum, oxygen, and nitrogen. In an chamber. The reactant precursor may be an oxygen reactant embodiment, the number of sequences X and y is selected to precursor that may include, but is not limited to, one or more form a nitrogen-rich hafnium aluminum oxynitride. In an of water, atomic oxygen, molecular oxygen, oZone, hydro embodiment, the number of sequences X and y are selected gen peroxide, a water-hydrogen peroxide mixture, alcohol, to form an oxygen-rich hafnium aluminum oxynitride. The or nitrous oxide. In addition, the pulsing of the aluminum hafnium aluminum oxynitride may be engineered as an precursor may use a pulsing period that provides uniform aluminum-rich dielectric relative to the amount of hafnium coverage of a monolayer on the Surface or may use a pulsing in the dielectric. The hafnium aluminum oxynitride may be period that provides partial coverage of a monolayer on the engineered as a hafnium-rich dielectric relative to the Surface during an aluminum sequence. amount of aluminum in the dielectric. The pulsing of the 0063 A number of precursors containing hafnium may be individual component-containing precursors may be per used to provide the hafnium to a Substrate for an integrated formed independently in a non-overlapping manner using circuit. In an embodiment, a precursor containing hafnium the individual gas sources 150-155 and flow controllers may include anhydrous hafnium nitride, Hf(NO). In an 156-161 of ALD system 100 of FIG. 1. embodiment using a Hf(NO) precursor on a hydrogen 0060 Each precursor may be pulsed into the reaction terminated silicon, the Substrate temperature may be main chamber for a predetermined period, where the predeter tained at a temperature ranging from about 160° C. to about mined period can be set separately for each precursor. 180°C. In an embodiment, a hafnium precursor may include Additionally, for various ALD formations, each precursor HfCl4. In an embodiment using a HfCl precursor, the may be pulsed into the reaction chamber under separate Substrate temperature may be maintained at a temperature environmental conditions. The Substrate may be maintained ranging from about 180° C. to about 600°C. In an embodi at a selected temperature and the reaction chamber main ment using a HfCl precursor, the substrate temperature may tained at a selected pressure independently for pulsing each be maintained at a temperature ranging from about 300° C. precursor. Appropriate temperatures and pressures may be to about 940° C. In an embodiment, a hafnium precursor maintained, whether the precursor is a single precursor or a may be Hfla. In an embodiment using a Hfla precursor, the mixture of precursors. Substrate temperature may be maintained at a temperature of 0061. In an embodiment, ALD AIN may be formed using about 300° C. Hafnium oxide may be grown by ALD using a number of precursors containing aluminum to provide the a Hf N(CH)(CHs), which may be known as a homolep aluminum to a Substrate for an integrated circuit. An alumi tic tetrakis(dialkylamino) hafnium(IV) compound, and num precursor can include a variety of precursors, such as water as an oxygen reactant. Other types of tetrakis(dialky trimethylaluminum (TMA), trisobutylaluminum (TIBA), lamino) hafnium compounds may also be used, such as dimethylaluminum hydride (DMAH), A1C, and other halo hafnium tetrakis dimethylamine, Hf N(CH), or hafnium genated precursors and organometallic precursors. In an tetrakis diethylamine, Hf N(CHs), as a hafnium-contain embodiment, an aluminum-containing precursor is pulsed ing precursor. In various embodiments, use of the individual onto a Substrate in an ALD reaction chamber. In an embodi hafnium-containing precursors is not limited to the tempera US 2008/0057659 A1 Mar. 6, 2008

ture ranges of the above example embodiments. In addition, in processing a hafnium aluminum oxynitride dielectric for the pulsing of the hafnium precursor may use a pulsing a given application without undue experimentation. period that provides uniform coverage of a monolayer on the Surface or may use a pulsing period that provides partial Atomic Layer Deposition and Nitridization coverage of a monolayer on the Surface during a hafnium 0067 FIG. 2A shows a flow diagram of features of an Sequence. embodiment for forming HfAION using atomic layer depo 0064. In various embodiments, nitrogen may be used as sition and nitridization. At 210, a layer of HfAlO is formed a purging gas and a carrier gas for one or more of the using atomic layer deposition. At 220, the layer of HfAlO is sequences used in the ALD formation of hafnium aluminum subjected to a nitridization to form a HfAION film. The oxynitride. Alternatively, hydrogen, argon gas, or other inert nitridization may be a high temperature nitridization. In the gases may be used as the purging gas. Excess precursor gas nitridization process, active nitrogen may be introduced by and reaction by-products may be removed by the purge gas. microwave plasma. In the nitridization process, active nitro Excess precursor gas and reaction by-products may be gen may be introduced by microwave plasma. In the nitrid removed by evacuation of the reaction chamber using vari ization process, active nitrogen may be introduced by a NH ous vacuum techniques. Excess precursor gas and reaction anneal. A high temperature nitridization is a nitridizing by-products may be removed by the purge gas and by process that is performed at temperatures equal to or above evacuation of the reaction chamber. 500°C. In various embodiments, HfAlO may be formed by 0065. In an embodiment, after repeating a selected num atomic layer deposition using ALD cycles of aluminum/ ber of ALD cycles, a determination is made as to whether the oxygen sequences and hafnium/oxygen sequences. Depend number of cycles equals a predetermined number to form the ing on the amounts of aluminum, hafnium, and oxygen to be desired hafnium aluminum oxynitride layer. If the total provided in the HfAlO film, the ALD cycle can be selected number of cycles to form the desired thickness has not been from a number of different permutations of aluminum/ completed, a number of cycles is repeated. In an embodi oxygen sequences and hafnium/oxygen sequences. ment, the thickness of a hafnium aluminum oxynitride layer 0068 FIG. 2B shows a flow diagram of features of an formed by atomic layer deposition is determined by a fixed embodiment for forming HfAIO using atomic layer deposi growth rate for the pulsing periods and precursors used, set tion for nitridization to a HfAlON film. At 230, a layer of at a value Such as N nm/cycle, and the number of cycles aluminum oxide, e.g., Al-O is formed on a substrate by conducted. In an embodiment, depending on the precursors atomic layer deposition. At 240, a layer of hafnium oxide is used for ALD formation of a HfAlON film, the process is formed by atomic layer deposition on the layer of aluminum conducted in an ALD window, which is a range of tempera oxide. At 250, the layers of aluminum oxide and hafnium tures in which the growth rate is Substantially constant. In an oxide are annealed to form a layer of HfAlO. The order of embodiment, if such an ALD window is not available, the forming AlO and Hf) may be interchanged. The layer of ALD process is conducted at the same set of temperatures HfAlO may be nitridized to form HfAION. Alternatively, the for each ALD sequence in the process. For a desired hafnium layers of aluminum oxide and hafnium oxide may be nitrid aluminum oxynitride layer thickness, t, in an application, the ized during the annealing process. In an embodiment, alter ALD process is repeated for t?N total cycles. Once the t/N nating layers of ALD aluminum oxide and ALD hafnium cycles have completed, no further ALD processing for the oxide may be formed to a desired thickness prior to nitrid hafnium aluminum oxynitride layer is required. In an ization. In an embodiment, a layer of ALD aluminum oxide embodiment, a hafnium aluminum oxynitride layer pro and a layer of ALD hafnium oxide may be formed, each to cessed at relatively low temperatures associated with atomic a desired thickness, the layers of ALD aluminum oxide and layer deposition provides an amorphous layer. ALD hafnium oxide nitridized to form a HfLnON layer. 0066. In an embodiment, a HfAION film may be grown Then, a layer of ALD aluminum oxide and a layer of ALD to a desired thickness by repetition of a process including hafnium oxide may be formed on the HfAlON layer, the atomic layer deposition of layers of AlO and HfN and/or layers of ALD aluminum oxide and ALD hafnium oxide layers of Hf() and AlN followed by annealing. In an embodi nitridized to form a HfAlON layer on and contiguous with ment, a base thickness may be formed according to various the previously formed HfAION layer. This process may be embodiments such that forming a predetermined thickness continued until the desired thickness of HfAlON is formed. of a HfAION film may be conducted by forming a number 0069. In an embodiment, ALD AIO may be formed using of layers having the base thickness. As can be understood by a number of precursors containing aluminum to provide the one skilled in the art, determining the base thickness aluminum to a substrate for an integrated circuit. Such depends on the application and can be determined during aluminum-containing precursors include, but are not limited initial processing without undue experimentation. Relative to, trimethylaluminum (TMA), trisobutylaluminum (TIBA), amounts of hafnium, aluminum, oxygen, and nitrogen in a dimethylaluminum hydride (DMAH), AIC, and other halo HfAION film may be controlled by regulating the relative genated precursors and organometallic precursors. After thicknesses of the individual layers of oxides and nitrides pulsing the aluminum-containing precursor and purging the formed. In addition, relative amounts of hafnium, aluminum, reaction chamber of excess precursor and by-products from oxygen, and nitrogen in a HfAION film may be controlled pulsing the precursor, an oxygen reactant precursor may be by forming a layer of HfAlON as multiple layers of different pulsed into the reaction chamber. The oxygen reactant base thickness and by regulating the relative thicknesses of precursor may include, but is not limited to, one or more of the individual layers of oxides and nitrides formed in each water, atomic oxygen, molecular oxygen, oZone, hydrogen base layer prior to annealing. As can be understood by those peroxide, a water-hydrogen peroxide mixture, alcohol, or skilled in the art, particular effective growth rates for the nitrous oxide. After pulsing the oxygen-containing precursor engineered hafnium aluminum oxynitride film can be deter the reaction chamber may be purged of excess precursor and mined during normal initial testing of the ALD system used by-products. In addition, the pulsing of the precursors may US 2008/0057659 A1 Mar. 6, 2008 use pulsing periods that provide uniform coverage of a after pulsing the hafnium-containing precursor and purging monolayer on the Surface or may use pulsing periods that the reaction chamber of excess precursor and by-products provide partial coverage of a monolayer on the Surface from pulsing the precursor, a reactant precursor may be during an aluminum/oxygen ALD cycle. pulsed into the reaction chamber. The reactant precursor 0070. In an embodiment, ALD HfC) may be formed may be a nitrogen reactant precursor including, but not using a number of precursors containing hafnium to provide limited to, ammonia (NH). Other nitrogen reactant precur the hafnium to a substrate for an integrated circuit. Such sors that may be used include nitrogen-containing compo hafnium-containing precursors include, but are not limited sitions that do not include oxygen. In various embodiments, to, a hafnium halide, such as Hf 1 and Hfl. Hf(NO), use of the individual hafnium-containing precursors is not Hf N(CH)(CHs), Hf N(CH), and Hf N(CHs). After pulsing the hafnium-containing precursor and purging limited to the temperature ranges of the above embodiments. the reaction chamber of excess precursor and by-products Further, forming hafnium nitride by atomic layer deposition from pulsing the precursor, an oxygen reactant precursor is not limited to the abovementioned precursors. In addition, may be pulsed into the reaction chamber. The oxygen the pulsing of the hafnium precursor may use a pulsing reactant precursor may include, but is not limited to, one or period that provides uniform coverage of a monolayer on the more of water, atomic oxygen, molecular oxygen, oZone, Surface or may use a pulsing period that provides partial hydrogen peroxide, a water-hydrogen peroxide mixture, coverage of a monolayer on the Surface during a hafnium alcohol, or nitrous oxide. In addition, the pulsing of the Sequence. precursors may use pulsing periods that provide uniform 0074. In an embodiment, ALD AIN may be formed using coverage of a monolayer on the Surface or may use pulsing a number of precursors containing aluminum to provide the periods that provide partial coverage of a monolayer on the aluminum to a substrate for an integrated circuit. Such surface during an ALD cycle forming HfC). aluminum-containing precursors include, but are not limited 0071. In various embodiments, nitrogen may be used as to, trimethylaluminum (TMA), triethylaluminum, trisobuty a purging gas and a carrier gas for one or more of the laluminum (TIBA), dimethylaluminum hydride (DMAH), sequences. Alternatively, hydrogen, argon gas, or other inert A1C, aluminum sec-butoxide, aluminum tribromide, alumi gases may be used as the purging gas. Excess precursor gas num trichloride, diethylaluminum ethoxide, tris(ethylmethy and reaction by-products may be removed by the purge gas. lamido)aluminum, and other halogenated precursors and Excess precursor gas and reaction by-products may be organometallic precursors. In an embodiment, the Substrate removed by evacuation of the reaction chamber using vari may be maintained at a temperature ranging from 180° C. to ous vacuum techniques. Excess precursor gas and reaction about 425°C. In an embodiment, H may be pulsed along by-products may be removed by the purge gas and by with the precursor or the precursor to reduce carbon con evacuation of the reaction chamber. tamination in the deposited film. After pulsing the alumi num-containing precursor and purging the reaction chamber Atomic Layer Deposition and Oxidation of excess precursor and by-products from pulsing the pre 0072 FIG. 3 shows a flow diagram of features of an cursor, a reactant precursor may be pulsed into the reaction embodiment for forming HfAlON using atomic layer depo chamber. To form AlN, a nitrogen reactant precursor is sition and oxidation. At 310, a layer of HfN is formed by pulsed. A number of precursors containing nitrogen may be atomic layer deposition. At 320, a layer of AlN is formed by used to provide nitrogen. Such nitrogen-containing precur atomic layer deposition on the layer of HfN. HfN and AlN sors include, but are not limited to, nitrogen, ammonia films may be alternately deposited in adjacent layers, in (NH), tert-butylamine (CHN), allylamine (CHN), and which either nitride layer may be deposited as the starting 1,1-dimethylhydrazine ((CH)NNH). In an embodiment, layer. At 330, the layers of AlN and HfN are annealed. At the Substrate is maintained at a temperature ranging from 340, the annealed layers of AlN and HfN are oxidized to about 400° C. to about 500° C. using tert-butylamine or form HfAlON. In an embodiment, the annealing and oxi allylamine as a nitrogen precursor. In an embodiment, NH dation may be performed together. The layers of AlN and may be pulsed with the tert-butylamine and the allylamine. HfN may be annealed and oxidized by rapid thermal oxi The addition of NH may enhance the deposition rate at dation to form HfAlON. lower temperatures. In various embodiments, use of the 0073. In an embodiment, ALD HfN may be formed using individual aluminum-containing precursors is not limited to a number of precursors containing hafnium to provide the the temperature ranges of the above example embodiments. hafnium to a Substrate for an integrated circuit. To form Further, forming aluminum nitride by atomic layer deposi hafnium nitride by atomic layer deposition, a hafnium tion is not limited to the abovementioned precursors. In containing precursor is pulsed onto a Substrate in an ALD addition, the pulsing of the aluminum precursor may use a reaction chamber. A number of precursors containing pulsing period that provides uniform coverage of a mono hafnium may be used to provide the hafnium to a substrate layer on the Surface or may use a pulsing period that for an integrated circuit. The hafnium-containing precursor provides partial coverage of a monolayer on the Surface may be a hafnium halide precursor, such as HfC1 or Hfla. In during an aluminum/nitrogen sequence. addition to halide precursors, the hafnium nitride may be 0075. In various embodiments, nitrogen may be used as grown by ALD using Hf N(CH)(CH3). In an embodi a purging gas and a carrier gas for one or more of the ment, the Substrate may be held at a temperature ranging sequences. Alternatively, hydrogen, argon gas, or other inert from about 150° C. to about 300° C. Other types of gases may be used as the purging gas. Excess precursor gas tetrakis(dialkylamino) metal compounds may also be used, and reaction by-products may be removed by the purge gas. Such as hafnium tetrakis dimethylamine, Hf N(CH), or Excess precursor gas and reaction by-products may be hafnium tetrakis diethylamine, Hf N(CHs), as a removed by evacuation of the reaction chamber using vari hafnium-containing precursor. In various embodiments, ous vacuum techniques. Excess precursor gas and reaction US 2008/0057659 A1 Mar. 6, 2008 by-products may be removed by the purge gas and by hydrogen peroxide, a water hydrogen peroxide mixture, evacuation of the reaction chamber. alcohol, or nitrous oxide. In various embodiments, the order of pulsing the precursors may vary. Further, forming Atomic Layer Deposition and Annealing hafnium oxynitride by atomic layer deposition is not limited 0076 FIG. 4 shows a flow diagram of features of an to the abovementioned precursors. In addition, the pulsing of embodiment for forming HfAlON using atomic layer depo the precursors may use pulsing periods that provide uniform sition and annealing. At 410, a layer of HfCN is formed coverage of a monolayer on the surface or may use pulsing using atomic layer deposition. At 420, a layer of AlON is periods that provide partial coverage of a monolayer on the formed using atomic layer deposition on the layer of HfCN. surface during an ALD cycle forming HfCN. At 430, the layers of HfoN and AION are annealed to form I0079. In various embodiments, nitrogen may be used as a layer of HfAION. HfON and AION films may be alter a purging gas and a carrier gas for one or more of the nately deposited in adjacent layers, in which either oxyni sequences. Alternatively, hydrogen, argon gas, or other inert tride layer may be deposited as the starting layer. gases may be used as the purging gas. Excess precursor gas 0077. In an embodiment, ALD AION may be formed and reaction by-products may be removed by the purge gas. using a number of precursors containing aluminum to pro Excess precursor gas and reaction by-products may be vide the aluminum to a substrate for an integrated circuit. removed by evacuation of the reaction chamber using vari After pulsing the aluminum-containing precursor and purg ous vacuum techniques. Excess precursor gas and reaction ing the reaction chamber of excess precursor and by-prod by-products may be removed by the purge gas and by ucts from pulsing the precursor, a reactant precursor may be evacuation of the reaction chamber. pulsed into the reaction chamber. A nitrogen reactant pre cursor may be pulsed. A number of precursors containing Dielectric Structures nitrogen may be used to provide nitrogen. Such nitrogen 0080. In various embodiments, either before or after containing precursors include, but are not limited to, nitro forming a HfAlON film, other dielectric layers such as HfC), gen, ammonia (NH), tert-butylamine (CHN), allylamine AlO, HfoN, AlON, dielectric nitride layers, dielectric metal (CH4N), and 1,1-dimethylhydrazine ((CH), NNH). After silicates, insulating metal oxides, or combinations thereof pulsing the nitrogen-containing precursor and purging the are formed as part of a dielectric layer or dielectric stack. In reaction chamber of excess precursor and by-products from an embodiment, these one or more other layers of dielectric pulsing the precursor, an oxygen reactant precursor may be material may be provided in stoichiometric form, in non pulsed into the reaction chamber. The oxygen reactant Stoichiometric form, or a combination of stoichiometric precursor may include, but is not limited to, one or more of dielectric material and non-stoichiometric dielectric mate water, atomic oxygen, molecular oxygen, ozone, hydrogen rial. In an embodiment, depending on the application, a peroxide, a water-hydrogen peroxide mixture, alcohol, or dielectric stack containing a HfAlON film includes a silicon nitrous oxide. In various embodiments, the order of pulsing oxide layer. In an embodiment, the dielectric layer is formed the precursors may vary. In various embodiments, forming as a nanolaminate. An embodiment of a nanolaminate aluminum oxynitride by atomic layer deposition is not includes a layer of a hafnium oxide and a HfAION film, a limited to the abovementioned precursors. In addition, the layer of hafnium oxynitride and a HfalON, film, a layer of pulsing of the precursors may use pulsing periods that aluminum oxide and a HfAION, film, a layer of aluminum provide uniform coverage of a monolayer on the surface or oxynitride and a HfAlON film, layers of hafnium oxide, may use pulsing periods that provide partial coverage of a aluminum oxide, hafnium oxynitride, and aluminum oxyni monolayer on the surface during an ALD cycle forming tride along with a HfAlON film, or various other combi AlON. nations. In an embodiment, a dielectric layer is formed 0078. In an embodiment, ALD HfCN may be formed substantially as the hafnium aluminum oxynitride film. using a number of precursors containing hafnium to provide 0081. In various embodiments, the structure of an inter the hafnium to a substrate for an integrated circuit. Such face between a dielectric layer and a substrate on which it is hafnium-containing precursors include, but are not limited disposed is controlled to limit the inclusion of silicon oxide, to, a hafnium halide, such as HfC1 or Hf, Hf N(CH) since a silicon oxide layer would reduce the effective dielec (C2Hs), hafnium tetrakis dimethylamine, Hf N(CH), tric constant of the dielectric layer. In an embodiment, the or hafnium tetrakis diethylamine, Hf N(CHs). In various material composition and properties for an interface layer embodiments, after pulsing the hafnium-containing precur are dependent on process conditions and the condition of the Sor and purging the reaction chamber of excess precursor substrate before forming the dielectric layer. In an embodi and by-products from pulsing the precursor, a nitrogen ment, though the existence of an interface layer may effec reactant precursor may be pulsed into the reaction chamber. tively reduce the dielectric constant associated with the A number of precursors containing nitrogen may be used to dielectric layer and its substrate, the interface layer, such as provide nitrogen. In an embodiment, NH may be used as the a silicon oxide interface layer or other composition interface nitrogen-containing precursor. Other nitrogen reactant pre layer, may improve the interface density, fixed charge den cursors that may be used include nitrogen-containing com sity, and channel mobility of a device having this interface positions that do not include oxygen. In an embodiment, the layer. nitrogen-containing precursor may also include oxygen. I0082 In an embodiment, a hafnium aluminum oxynitride After pulsing the nitrogen-containing precursor and purging layer is doped with other elements. The doping may be the reaction chamber of excess precursor and by-products employed to enhance the leakage current characteristics of from pulsing the precursor, an oxygen reactant precursor the dielectric layer containing the HfAION film by provid may be pulsed into the reaction chamber. The oxygen ing a disruption or perturbation of the hafnium aluminum reactant precursor may include, but is not limited to, one or Oxynitride structure. In an embodiment, such doping is more of water, atomic oxygen, molecular oxygen, ozone, realized by substituting a sequence of one of these elements US 2008/0057659 A1 Mar. 6, 2008 11 for a hafnium sequence, an aluminum sequence, or various Surface or may use a pulsing period that provides partial combinations of sequences. The choice for Substitution may coverage of a monolayer on the Surface. The tantalum layer depend on the form of the hafnium aluminum oxynitride may be structured as one or more monolayers. The tantalum structure with respect to the relative amounts of hafnium layer may have a thickness ranging from a monolayer to atoms and aluminum atoms desired in the oxide. In an thousands of angstroms or more. embodiment, to maintain a Substantially hafnium aluminum I0086. In an embodiment, a metal nitride layer may be oxynitride, the amount of dopants inserted into the oxyni deposited by atomic layer deposition using a precursor tride are limited to a relatively small fraction of the total containing the metal to be deposited and a reactant precursor number of hafnium and aluminum atoms. containing nitrogen in an ALD cycle. In an example embodi 0083. After forming a dielectric having a hafnium alu ment, a titanium nitride layer may be formed with a HfAlON minum oxynitride layer, other material may be formed upon film by atomic layer deposition using a titanium-containing the hafnium aluminum oxynitride layer. In an embodiment, precursor. A nitrogen-containing precursor may be used as the other material is a conductive material. The conductive the reactant precursor for the titanium-containing precursor. material may be used as an electrode. Such electrodes may The titanium-containing precursor and the nitrogen-contain be used as capacitor electrodes, control gates in transistors, ing precursor may be selected Such that their use does not or floating gates in floating gate transistors. In an embodi form a titanium oxide in the layer of titanium nitride being ment, the conductive material is a metal or conductive metal formed. The titanium-containing precursor and the nitrogen nitride. In an embodiment, the conductive material is a containing precursor may be selected Such that these pre conductive semiconductor material. In an embodiment, the cursors do not include oxygen as an elemental component. conductive material is formed by ALD processes. In an In an embodiment, a titanium halide precursor, such as embodiment, the conductive material is formed by a substi TiCl, Tila, or TiF may be used with NH as a reactant tution process. In an embodiment, the conductive material is precursor. In an embodiment, a TiCl, precursor may be used formed in a self-alignment process. with a NH reactant precursor. In an embodiment, the Substrate temperature may be held at a temperature ranging Atomic Layer Deposition of Conductive Layers from about 380° C. to about 500° C. In an embodiment, the Substrate temperature may be held at a temperature less than 0084. In various embodiments, a conductive layer may be 600° C. After pulsing a titanium-containing precursor and deposited by atomic layer deposition on a layer of HfAlON after pulsing its reactant precursor, the reaction chamber or on a dielectric layer containing a layer of HfAlON. A may be purged of excess precursor and/or by-products. In metal layer may be deposited by atomic layer deposition in various embodiments, use of the individual titanium-con an ALD cycle having a halide precursor containing the metal taining precursors is not limited to the temperature ranges of to be deposited and a reactant precursor containing hydro the above example embodiments. Further, forming titanium gen. Metal layer formation by ALD is not limited to halide nitride by atomic layer deposition is not limited to the precursors and hydrogen reactant precursors. In various abovementioned precursors, but may include precursors embodiments, precursors may be selected to form ALD containing oxygen. In addition, the pulsing of the titanium conductive layers such as aluminum (Al), tungsten (W), precursor may use a pulsing period that provides uniform molybdenum (Mo), gold (Au), silver (Ag), gold alloy, silver coverage of a monolayer on the Surface or may use a pulsing alloy, copper (Cu), platinum (Pt), rhenium (Re), ruthenium period that provides partial coverage of a monolayer on the (Ru), rhodium (Rh), nickel (Ni), osmium (Os), palladium Surface. The titanium nitride layer may be structured as one (Pd), iridium (Ir), cobalt (Co), germanium (Ge), or metallic or more monolayers. The titanium nitride layer may have a nitrides such as WN, TiN or TaN. Formation of ALD thickness ranging from a monolayer to thousands of ang conductive layers is not limited to the abovementioned StrOnS Or more. materials. 0085. In an example embodiment, a tantalum layer may Metal Substitution be formed on a HfAION film by atomic layer deposition using a tantalum-containing precursor. In an embodiment, a I0087 FIGS.5A-5E illustrate an embodiment of a process tantalum halide precursor, such as TaF5 or TaCls, may be for forming a metal substituted electrode in place of a used with hydrogen as a reactant precursor. In an embodi previously deposited material on a dielectric containing ment, a TaCls precursor may be used with an atomic hydro HfAlON. Though a transistor is discussed with reference to gen reactant precursor. The atomic hydrogen reactant pre FIGS. 5A-5E, such a process may be used with respect to cursor may be provided using a plasma. In an embodiment, other embodiments of device configurations. FIG. 5A shows the substrate temperature may be held at a temperature a substrate 501 and shallow trench isolation (STI) regions ranging from about 250° C. to about 400° C. The hydrogen 502. The substrate 501 can be a semiconductor waferas well reactant precursor reacts at the Substrate to remove the as structures having one or more insulative, semi-insulative, halogen, which forms the selected tantalum halide precursor, conductive, or semiconductive layers and materials. Thus, leaving tantalum on the Substrate Surface. After pulsing a for example, the Substrate can include silicon-on-insulator, tantalum-containing precursor and after pulsing its reactant silicon-on-Sapphire, and other structures upon which semi precursor, the reaction chamber may be purged of excess conductor devices are formed. precursor and/or by-products. In various embodiments, use I0088 FIG. 5B further shows a gate dielectric layer 503 of the individual tantalum-containing precursors is not lim formed on the substrate 501, and a gate substitutable layer ited to the temperature ranges of the above example embodi 504 formed on the gate dielectric layer 503. The gate ments. Further, forming tantalum by atomic layer deposition dielectric layer may include a dielectric layer containing is not limited to the abovementioned precursors. In addition, HfAlON in addition to other insulative material or a dielec the pulsing of the tantalum precursor may use a pulsing tric layer essentially of HfAlON. The use of such a high-K period that provides uniform coverage of a monolayer on the dielectric increases the capacitance, which is useful for US 2008/0057659 A1 Mar. 6, 2008

nanoscale integrated circuits. In various embodiments the used between the floating gate and the Substrate, and gate dielectric includes stacked layers comprising one or between the control gate and the floating gate in these more high-K dielectric materials. As described in more detail nonvolatile devices. below, the material of the gate substitutable layer 504 is 0.095 FIG. 6 illustrates a flow diagram of features of an selected with respect to the desired gate material to allow the embodiment of a metal Substitution technique. At 612, a gate gate material to replace the gate Substitutable layer. This dielectric is formed on a substrate. The gate dielectric process forms a gate of the desired gate metal where the includes a HfAION film. At 613, a layer of gate substitutable Substitutable material was positioned on the gate dielectric. material is formed on the gate dielectric. Examples of gate I0089. As shown in FIG. 5C, portions of the gate dielectric Substitutable material include polysilicon, germanium, sili layer 503 and the gate substitutable layer 504 are removed con-germanium, and carbon. At 614, Source/drain regions to define a gate 505. Sidewalls or spacers 506 are formed are formed. A layer of gate material is formed at 615 on the along the gate 505. Source/drain regions 507 are also gate Substitutable material. Examples of Such metals include formed. Source/drain regions 507 can be formed using gold, silver, and aluminum. Other metals may be used. At conventional ion implantation and Subsequent annealing. 616, the gate material is substituted for the layer of gate These annealing temperatures can pose problems for alumi substitutable material. num gates and other metal gates that have melting tempera 0096. A metal substitution reaction substitutes or replaces tures less than the anneal temperature for the source/drain the Substitutable material (e.g. silicon, germanium, silicon regions. germanium, carbon) with a metal. After the Substitution, the resulting gate structure includes Substantially all of the 0090 FIG.5D shows an insulative fill layer 508 provided desired metal. Small amounts of the substitutable material to match the thickness of the gate Stack. A planarization may remain in the gate structure. The Substitution reaction procedure. Such as chemical-mechanical polishing, can be can be induced by heating the integrated circuit assembly to used to provide an even surface across the fill layer 508 and a desired temperature in a vacuum, nitrogen, argon, forming the gate substitutable layer 504. A metal layer 509, formed gas or other non-oxidizing atmosphere. Heating causes of material intended to be the gate material, is deposited over diffusion of the metal layer 509 into the substitutable layer. the gate substitutable layer 504 and the fill layer 508. The The annealing temperature for the Substitution is less than metal layer 509 is also referred to herein as a layer of gate the eutectic (lowest melting) temperature of materials material. Various deposition processes, such as evaporation, involved in the substitution for the reaction for substitution sputtering, chemical vapor deposition, or atomic layer depo to occur. In an embodiment, to form a gold gate, a metal sition, may be used to form the metal layer 509. The volume layer may be formed from gold and annealed at approxi of layer 509 is significantly larger than the volume of the mately 300° C. to substitute the gold for a silicon substitut substitutable material left on the wafer. able structure. In an embodiment, to form a silver gate, a 0091. After the metal layer 509 is deposited on the gate metal layer may be formed from silver and annealed at Substitutable layer, a metal-substitution reaction is induced. approximately 500-600° C. to substitute the silver for a The reaction can be provided by annealing the structure in silicon Substitutable structure. A polysilicon and germanium a non-oxidizing atmosphere Such as a nitrogen gas or a substitutable material may be used, which reduces the forming gas. The heating urges diffusion or dissolution of anneal temperature. the intended gate material in metal layer 509 for the sub 0097. According to various embodiments, the gate sub stitutable material 504. The substitution process is bounded Stitutable material 504 shown in FIGS 5A-5E includes by the spacers 506 and the gate dielectric 503. polysilicon. In some embodiments, the gate Substitutable 0092. At the conclusion of the substitution reaction, the material includes germanium. Some embodiments use sili residual metal of layer 509 and the substitutable material con-germanium with a percentage of silicon in the range may be removed such as may be achieved using conven from 0% to 100% as the gate substitutable material 504. tional planarization. FIG. 5E shows the resulting low-resis Some embodiments use carbon as the gate Substitutable tance gate structure. The illustrated Structure includes a material 504. With respect to various embodiments which metal substituted gate 510 formed by the substitution of the use polysilicon, germanium, or silicon-germanium as the metal of layer 509. The metal substituted gate 510 may gate substitutable material 504, a replacement metal for the include a small amount of the gate Substitutable material that Substituted gate may include aluminium, silver, gold, an did not diffuse above the planarization level 511. Such small alloy of silver, an alloy of gold as the replacement metal, or amounts of the gate Substitutable material do not signifi combinations thereof. In various embodiments, with carbon cantly affect the conductivity of the metal substituted gate used as the gate substitutable material 504, a replacement 510, and thus do not significantly affect the performance of metal for the Substituted gate may include gold, silver, an the device. alloy of gold, an alloy of silver, copper, platinum, rhenium, 0093 Drain and source contacts (not shown) can be ruthenium, rhodium, nickel, osmium, palladium, iridium, formed, as well as interconnects to other transistors or cobalt, germanium, or combinations thereof. components, using conventional techniques. Another heat 0.098 Various embodiments form an integrated circuit treatment may occur after packaging the integrated circuit in structure using two or more Substitution reactions. Rela a protective housing in an attempt to minimize the resistivity tively higher temperature Substitution processes can be of the metal gate contacts and other metal interconnections. performed before relatively lower temperature substitution 0094. The metal gate substitution technique, as disclosed processes. One application for multiple Substitution reac herein, can be applied to MOS devices, as generally illus tions is to independently adjust work functions of NMOS trated in FIG. 5E, as well as to form metal floating gates and PMOS transistors in CMOS integrated circuits. Multiple and/or metal control gates in nonvolatile devices. Addition substitution reactions are not limited to this CMOS inte ally, various high-K dielectrics having a HfAION film can be grated circuit application. Additional information regarding US 2008/0057659 A1 Mar. 6, 2008 metal Substitution can be found in U.S. patent application the integrated circuit in a protective housing in an attempt to Ser. No. 11/176,738 filed Jul. 7, 2005, entitled “METAL minimize the resistivity of the metal gate contacts and other SUBSTITUTED TRANSISTOR GATES, which is herein metal interconnections. incorporated by reference. 0104 FIGS. 7A-7D illustrate two replacement processes for the formation of planar self aligned metal gate transis Self Aligned Metal Technique tors, one for disposable sidewall spacers and the other for the 0099 FIGS. 7A-7D illustrate an embodiment of a process gate material itself. The metal gate replacement technique, for forming a self aligned conductive layer Such as a metal as disclosed herein, can be applied to MOS devices, as gate for a transistor structure. FIG. 7A illustrates a high-K generally illustrated in FIGS. 7A-7D, as well as to form gate dielectric 710 containing HfAION formed on a sub metal floating gates and/or metal control gates in nonvolatile strate 701. The substrate 701 can be a semiconductor wafer devices. Additionally, various high-K dielectrics can be used as well as structures having one or more insulative, semi between the floating gate and the substrate, and between the insulative, conductive, or semiconductive layers and mate control gate and the floating gate in these nonvolatile rials. Thus, for example, the Substrate can include silicon devices. on-insulator, silicon-on-Sapphire, and other structures upon 0105 FIG. 8 illustrates an embodiment of a method 800 which semiconductor devices are formed. for forming a self aligned metal gate on high-K gate dielec 0100. In FIG. 7A, a sacrificial gate 703 is formed of trics containing HfAlON. According to various embodi amorphous carbon on the high-K gate dielectric 710. In ments, a high-K gate dielectric containing HfAION is formed various embodiments, an etch barrier 708 is formed over the on a substrate, at 802. At 804, a sacrificial carbon gate is sacrificial gate and the dielectric. The etch barrier 708 formed on the gate dielectric. At 806, sacrificial carbon includes silicon nitride or aluminium oxide, and can be sidewall spacers are formed adjacent to the sacrificial carbon formed using a deposition process, according to various gate. At 808 source/drain regions for the transistor are embodiments. Sacrificial sidewall spacers 706 are added formed, using the sacrificial carbon sidewall spacers to adjacent the sacrificial gate 703. In various embodiments, define the Source? drain regions. The sacrificial carbon side the spacers 706 are formed of amorphous carbon by depo wall spacers are replaced with non-carbon sidewall spacers sition and conventional direct etch techniques. An ion at 810. At 812, the sacrificial carbon gate is replaced with a implantation 730 and high temperature anneal are used to desired metal gate material to provide the desired metal gate form source/drain regions 702 in areas defined by the material on the gate dielectric. sacrificial sidewall spacers 706. These annealing tempera 0106. In various embodiments, source/drain extensions tures can pose problems for aluminum gates and other metal may be formed after removing the carbon sidewall spacers gates that have melting temperatures less than the anneal and before replacing with non-carbon sidewall spacers. An temperature for the source? drain regions. etch barrier is used in various embodiments to separate the 0101. In FIG. 7B, the sacrificial sidewall spacers (706 in sacrificial carbon gate from the sacrificial carbon sidewall FIG. 7A) have been removed. Various embodiments use a spacers. In various embodiments, the carbon sacrificial gate plasma Oxidation process to remove the sacrificial sidewall may be replaced with aluminum (Al), tungsten (W), molyb spacers. In addition, the etch barrier (708 in FIG. 7A) has denum (Mo), gold (Au), silver (Ag), gold alloy, silver alloy, been removed. In various embodiments, a light dose ion copper (Cu), platinum (Pt), rhenium (Re), ruthenium (Ru), implantation 740 is used to form source/drain extensions rhodium (Rh), nickel (Ni), osmium (Os), palladium (Pd), 742 in the substrate 701. The extensions 742 can be annealed iridium (Ir), cobalt (Co), germanium (Ge), or metallic at lower temperatures and in shorter times than the more nitrides such as WN, TiN or TaN covered by metals. The heavily doped source/drain regions 702. According to vari high-K gate dielectric formed at 802 may be one of a number ous embodiments, source/drain extensions for the transistor of high-K gate dielectrics containing HfAlON. may be formed with doping the substrate to a depth of 30 nm 0107. In various embodiments, construction of an inte or less. grated circuit structure includes a dielectric containing HfA 0102. In FIG. 7C, conventional or non-carbon sidewall 1ON on which is disposed a self-aligned metal electrode. spacers 756 are formed and the whole structure is back filled Additional information regarding a self-aligned metal elec with an oxide fill 758, such as silicon dioxide, and pla trode used as a transistor gate can be found in U.S. patent narized. A planarization procedure. Such as chemical-me application Ser. No. 11/216,375, filed 31 Aug. 2005, entitled chanical polishing, can be used to provide an even Surface. SELFALIGNED METAL GATES ON HIGH-K DIELEC In various embodiments, the conventional sidewall spacers TRICS, which is herein incorporated by reference. are formed with silicon nitride. Device Structures (0103) In FIG. 7D, the sacrificial gate (703 in FIG. 7C) is removed and replaced by the deposition of a metal layer 760. 0.108 FIG. 9 illustrates an embodiment of a wafer 940 In various embodiments, the sacrificial gate is removed containing integrated circuits having one or more dielectric using a plasma oxidation process. Various deposition pro layers that include a hafnium aluminum oxynitride film. cesses. Such as evaporation, sputtering, chemical vapor Conductive electrodes may be disposed on such dielectrics deposition, or atomic layer deposition, may be used to form in a number of configurations such as capacitors, transistors, the metal layer 760. The structure is planarized (not shown) or elements of a memory. The conductive electrodes may be using a planarization procedure. Such as chemical-mechani metal electrodes, conductive metal nitride electrodes, and/or cal polishing, resulting in the self aligned metal gate over the conductive metal oxide electrodes. The conductive elec high-K gate dielectric insulator 710. Drain and source con trodes may be atomic layer deposited electrodes. Metal tacts (not shown) can be formed, as well as interconnects to electrodes may be metal substituted electrodes and/or self other transistors or components, using conventional tech aligned metal electrodes formed in accordance with the niques. Another heat treatment may occur after packaging teachings of embodiments discussed herein. A common US 2008/0057659 A1 Mar. 6, 2008

wafer size is 8 inches in diameter. However, wafers are the sequencing of the various elements of the process for capable of being fabricated in other sizes, and embodiments forming a transistor is conducted with fabrication processes of wafers containing a hafnium aluminum oxynitride film known to those skilled in the art. In an embodiment, tran are not limited to a particular size. A number of dies can be sistor 1000 is a MOSFET transistor. In an embodiment, formed on a wafer. A die 941 is an individual pattern on a transistor 1000 is a germanium MOSFET structure. In an Substrate that contains circuitry to perform a specific func embodiment, transistor 1000 is a silicon MOSFET structure. tion. A semiconductor wafer typically contains a repeated In an embodiment, transistor 1000 is a silicon-germanium pattern of Such dies containing the same functionality. A die is typically packaged in a protective casing (not shown) with (SiGe) MOSFET structure. In an embodiment, transistor leads extending therefrom (not shown) providing access to 1000 is a gallium arsenide MOSFET structure. In an the circuitry of the die for communication and control. embodiment, transistor 1000 is a NMOS transistor. In an 0109. Applications containing electronic devices having embodiment, transistor 1000 is a PMOS transistor. Transis dielectric layers containing hafnium aluminum oxynitride tor 1000 is not limited to the arrangement illustrated in FIG. film include electronic systems for use in memory modules, 10. For example, transistor 1000 may be structured as a device drivers, power modules, communication modems, vertical transistor. In an embodiment, use of a gate dielectric processor modules, and application-specific modules, which containing hafnium aluminum oxynitride is not limited to may include multilayer, multichip modules. Such dielectric silicon-based substrates, but is used with a variety of semi layers may be configured as multiple layers containing at conductor Substrates. least one layer of HfAlON or configured substantially as a 0113 FIG. 11 shows an embodiment of a floating gate HfAION layer. In addition, such dielectric layers may be transistor 1100 having a dielectric layer containing a HfA configured in contact with a metal electrode. Such circuitry 1ON film. In an embodiment, the HfAION film is structured can be a Subcomponent of a variety of electronic systems, as one or more monolayers. In an embodiment, the HfAlON Such as a clock, a television, a cell phone, a personal film is formed using atomic layer deposition techniques. In computer, an automobile, an industrial control system, an an embodiment, transistor 1100 includes a silicon-based aircraft, and others. substrate 1110 with a source 1120 and a drain 1130 separated 0110 FIG. 10 shows an embodiment of a transistor 1000 by a body region 1132. Body region 1132 between source having a dielectric layer 1040 containing a HfAlON film. In 1120 and drain 1130 defines a channel region having a an embodiment, transistor 1000 includes a source region channel length 1134. Located above body region 1132 is a 1020 and a drain region 1030 in a silicon-based substrate stack 1155 including a gate dielectric 1140, a floating gate 1010 where source and drain regions 1020, 1030 are sepa 1152, a floating gate dielectric 1142 (integrate dielectric rated by a body region 1032. Body region 1032 defines a 1142), and a control gate 1150. An interfacial layer may form channel having a channel length 1034. In an embodiment, a between body region 1132 and gate dielectric 1140. In an gate dielectric 1040 is disposed on substrate 1010 with gate embodiment, such an interfacial layer is limited to a rela dielectric 1040 formed as a dielectric layer containing tively small thickness compared to gate dielectric 1140, or to HfAION. In an embodiment, gate dielectric 1040 is realized a thickness significantly less than gate dielectric 1140 as to as a dielectric layer formed substantially of HfAION. In an be effectively eliminated. embodiment, gate dielectric 1040 is constructed as multiple 0114. In an embodiment, gate dielectric 1140 includes a dielectric layers, that is, as a dielectric Stack, containing at dielectric containing an atomic layer deposited HfAlON least one HfAlON film and one or more layers of insulating film formed in embodiments similar to those described material other than hafnium aluminum oxynitride film. In an herein. In an embodiment, gate dielectric 1140 is realized as embodiment, the HfAlON film is structured as one or more a dielectric layer formed substantially of HfAlON. In an monolayers. An embodiment of a HfAION film is formed embodiment, gate dielectric 1140 is a dielectric stack con using atomic layer deposition. In an embodiment, gate taining at least one HfAION film and one or more layers of dielectric 1040 may be realized as a gate insulator in a other insulating materials. silicon-based structure. 0.115. In an embodiment, floating gate 1152 is formed on 0111. In an embodiment, a gate 1050 is formed on and and contacts gate dielectric 1140. In an embodiment, floating contacts gate dielectric 1040. In an embodiment, gate 1050 gate 1152 includes conductive material. In an embodiment, includes conductive material. In an embodiment, gate 1050 floating gate 1152 is structured as one or more monolayers. includes a conductive material structured as one or more In an embodiment, floating gate 1152 is an ALD layer. In an monolayers. In an embodiment, the conductive material embodiment, floating gate 1152 is a substituted metal layer. layer is an ALD conductive material layer. In an embodi In an embodiment, floating gate 1152 is a self-aligned metal ment, the conductive material layer is a Substituted metal layer. In an embodiment, the thickness of the floating gate layer. In an embodiment, the conductive material layer is a layer ranges from a monolayer to thousands of angstroms or self-aligned metal layer. In an embodiment, the thickness of O. the conductive layer ranges from a monolayer to thousands 0116. In an embodiment, floating gate dielectric 1142 of angstroms or more. includes a dielectric containing a HfAlON film. In an 0112 An interfacial layer may form between body region embodiment, the HfAlON film is structured as one or more 1032 and gate a dielectric 1040. In an embodiment, an monolayers. In an embodiment, the HfAION is formed interfacial layer is limited to a relatively small thickness using atomic layer deposition techniques. In an embodiment, compared to gate dielectric 1040, or to a thickness signifi floating gate dielectric 1142 is realized as a dielectric layer cantly less than gate dielectric 1040 as to be effectively formed substantially of HfAlON. In an embodiment, float eliminated. In an embodiment, forming the Substrate and the ing gate dielectric 1142 is a dielectric stack containing at Source and drain regions is performed using standard pro least one HfAION film and one or more layers of other cesses known to those skilled in the art. In an embodiment, insulating materials. US 2008/0057659 A1 Mar. 6, 2008

0117. In an embodiment, control gate 1150 is formed on dielectric layer 1220 is a dielectric stack containing at least and contacts floating gate dielectric 1142. In an embodiment, one HfAlON film and one or more layers of other insulating control gate 1150 includes conductive material. In an materials. Embodiments for a hafnium aluminum oxynitride embodiment, control gate 1150 is structured as one or more film may include, but are not limited to, a capacitor in a monolayers. In an embodiment, the control gate 1150 is an DRAM and capacitors in analog, radio frequency (RF), and ALD layer. In an embodiment, control gate 1150 is a mixed signal integrated circuits. Mixed signal integrated substituted metal layer. In an embodiment, control gate 1150 circuits are integrated circuits that may operate with digital is a self-aligned metal layer. In an embodiment, the thick and analog signals. ness of the control gate layer 1150 ranges from a monolayer to thousands of angstroms or more. In an embodiment, I0121 FIG. 13 depicts an embodiment of a dielectric control gate 1150 is structured as one or more monolayers. structure 1300 having multiple dielectric layers 1305-1, 0118. In an embodiment, both gate dielectric 1140 and 1305-2... 1305-N, in which at least one layer is a hafnium floating gate dielectric 1142 are formed as dielectric layers aluminum oxynitride layer. In an embodiment, layers 1310 containing a HfAION film structured as one or more mono and 1320 provide means to contact dielectric layers 1305-1, layers. In an embodiment, control gate 1150 and floating 1305-2 . . . 1305-N. In an embodiment, each layer 1310, gate 1152 are formed as conductive layers. In an embodi 1320 or both layers are conductive layers. In an embodi ment, the control gate 1150 and floating gate 1152 are ment, layers 1310 and 1320 are electrodes forming a capaci structured as one or more monolayers. In an embodiment, tor. In an embodiment, layer 1310 is a body region of a control gate 1150 and floating gate 1152 are ALD layers. In transistor with layer 1320 being a gate. In an embodiment, an embodiment, control gate 1150 and floating gate 1152 are layer 1310 is a floating gate electrode with layer 1320 being Substituted metal layers. In an embodiment, control gate a control gate. 1150 and floating gate 1152 are self-aligned metal layers. In 0.122. In an embodiment, dielectric structure 1300 an embodiment, gate dielectric 1140, floating gate dielectric includes one or more layers 1305-1, 1305-2 . . . 1305-N as 1142, control gate 1150, and floating gate 1152 are realized dielectric layers other than a HfAION layer, where at least by embodiments similar to those described herein, with the one layer is a HfAION layer. In an embodiment, dielectric remaining elements of the transistor 1100 formed using layers 1305-1, 1305-2 . . . 1305-N include a HfC) layer, an processes known to those skilled in the art. In an embodi AlO layer, a HfCN layer, an AION layer, or various com ment, gate dielectric 1140 forms a tunnel gate insulator and binations of these layers. In an embodiment, dielectric layers floating gate dielectric 1142 forms an inter-gate insulator in 1305-1, 1305-2... 1305-N include an insulating metal oxide flash memory devices, where gate dielectric 1140 and float layer. In an embodiment, dielectric layers 1305-1, 1305-2. ing gate dielectric 1142 may include an hafnium aluminum ... 1305-N include an insulating nitride layer. In an embodi oxynitride film structured as one or more monolayers. Float ment, dielectric layers 1305-1, 1305-2. . . 1305-N include ing gate transistor 1100 is not limited to the arrangement an insulating oxynitride layer. In an embodiment, dielectric illustrated in FIG. 11. For example, floating gate transistor layers 1305-1, 1305-2 . . . 1305-N include an insulating 1100 may be structured as a vertical transistor. Such struc silicate layer. tures are not limited to silicon-based substrates, but may be I0123 Various embodiments for a dielectric layer contain used with a variety of semiconductor Substrates, such as for ing a hafnium aluminum oxynitride film structured as one or but not limited to germanium floating gate transistors, SiGe more monolayers may provide for enhanced device perfor floating gate transistors, and gallium arsenide floating gate mance by providing devices with reduced leakage current. transistors. Such improvements in leakage current characteristics may 0119 FIG. 12 shows an embodiment of a capacitor 1200 be attained by forming one or more layers of a hafnium having a dielectric layer containing a hafnium aluminum aluminum oxynitride in a nanolaminate structure with other oxynitride film 1220 and having an electrode 1230. Embodi metal oxides, non-metal-containing dielectrics, or combina ments of a hafnium aluminum oxynitride film 1220 struc tions thereof. The transition from one layer of the nanolami tured as one or more monolayers may also be applied to nate to another layer of the nanolaminate provides disruption capacitors in various integrated circuits, memory devices, to a tendency for an ordered structure in the nanolaminate and electronic systems. In an embodiment for a capacitor stack. The term "nanolaminate” means a composite film of 1200 illustrated in FIG. 12, a method includes forming a first ultra thin layers of two or more materials in a layered Stack. conductive layer 1210, forming a dielectric layer 1220 Typically, each layer in a nanolaminate has a thickness of an containing a hafnium aluminum oxynitride film structured as order of magnitude in the nanometer range. Further, each one or more monolayers on first conductive layer 1210, and individual material layer of the nanolaminate may have a forming a second conductive layer 1230 on dielectric layer thickness as low as a monolayer of the material or as high 1220. In various embodiments, second conductive layer as 20 nanometers. In an embodiment, a Hf)/HfAlON nano 1230, first conductive layer 1210, or both second and first laminate contains alternating layers of a HfC) and HfAlON. conductive layers 1230, 1210 are ALD conductive material In an embodiment, a HfGN/HfAlON nanolaminate contains layers, Substituted metal layers, self-aligned metal layers, or alternating layers of a HfCN and HfAlON. In an embodi a combination thereof. In an embodiment, the thickness of ment, a AION/HfAlON nanolaminate contains alternating the conductive layer ranges from a monolayer to thousands layers of AION and HfAION. In an embodiment, a AlO/ of angstroms or more. HfAlON nanolaminate contains alternating layers of AIO 0120 In an embodiment, dielectric layer 1220, contain and HfAlON. In an embodiment, a Hf)/AION/AIO/HfON/ ing a HfAION film, and conductive layers 1210, 1220 are HfAlON nanolaminate contains various permutations of formed using various embodiments described herein. In an hafnium oxide layers, aluminum oxynitride layers, alumi embodiment, dielectric layer 1220 is realized as a dielectric num oxide layers, hafnium oxynitride layers, and hafnium layer formed substantially of HfAION. In an embodiment, aluminum oxynitride layers. US 2008/0057659 A1 Mar. 6, 2008

0124. In an embodiment, the sequencing of the layers in address, data, or control, the use of which is regulated by dielectric structure 1300 structured as a nanolaminate controller 1505. In an embodiment, electronic apparatus depends on the application. The effective dielectric constant 1535 is additional memory configured in a manner similar to associated with nanolaminate structure 1300 is that attrib memory 1525. In an embodiment, additional peripheral utable to N capacitors in series, where each capacitor has a device or devices 1545 are coupled to bus 1515. In an thickness defined by the thickness and composition of the embodiment, peripheral devices 1545 include displays, corresponding layer. In an embodiment, by selecting each additional storage memory, or other control devices that may thickness and the composition of each layer, a nanolaminate operate in conjunction with controller 1505. In an alternative structure is engineered to have a predetermined dielectric embodiment, peripheral devices 1545 may include displays, constant. Embodiments for structures such as nanolaminate additional storage memory, or other control devices that may structure 1300 may be used as nanolaminate dielectrics in operate in conjunction with memory 1525, or controller flash memory devices as well as other integrated circuits. In 1505 and memory 1525. In an embodiment, controller 1505 an embodiment, a layer of the nanolaminate structure 1300 is a processor. In an embodiment, one or more of controller is used to store charge in a flash memory device. The charge 1505, memory 1525, bus 1515, electronic apparatus 1535, or storage layer of a nanolaminate structure 1300 in a flash peripheral devices 1545 include an embodiment of a dielec memory device may be a silicon oxide layer. tric layer having a HfAION film structured as one or more 0125. In an embodiment, transistors, capacitors, and monolayers with an electrode. In an embodiment, system other devices include dielectric films containing a layer of a 1500 includes, but is not limited to, information handling hafnium aluminum oxynitride composition with an elec devices, telecommunication systems, and computers. trode. In an embodiment, the hafnium aluminum oxynitride I0128. In an embodiment, memory 1525 is realized as a layer is an atomic layer deposited hafnium aluminum oxyni memory device containing a HfAION film structured as one tride layer. In an embodiment, the electrode is an atomic or more monolayers with an electrode. In an embodiment, a layer deposited electrode. In an embodiment, the electrode is HfAlON structure with a conductive layer is formed in a a substituted metal layer. In an embodiment, the electrode is memory cell of a memory array. In an embodiment, such a a self-aligned metal layer. In an embodiment, dielectric films structure is formed in a capacitor in a memory cell of a containing a hafnium aluminum oxynitride layer with an memory array. In an embodiment, Such a structure is formed electrode are implemented into memory devices and elec in a transistor in a memory cell of a memory array. In an tronic systems including information handling devices. In embodiment, it will be understood that embodiments are various embodiments, information handling devices include equally applicable to any size and type of memory circuit wireless systems, telecommunication systems, and comput and are not intended to be limited to a particular type of ers. In various embodiments, such electronic devices and memory device. Memory types include a DRAM, SRAM electronic apparatus are realized as integrated circuits. (Static Random Access Memory) or Flash memories. Addi 0126 FIG. 14 illustrates a block diagram for an elec tionally, the DRAM could be a synchronous DRAM com tronic system 1400 with one or more devices having a monly referred to as SGRAM (Synchronous Graphics Ran dielectric structure including a HfAlON film with an elec dom. Access Memory), SDRAM (Synchronous Dynamic trode. Electronic system 1400 includes a controller 1405, a Random Access Memory), SDRAM II, and DDR SDRAM bus 1415, and an electronic device 1425, where bus 1415 (Double Data Rate SDRAM), as well as other emerging provides electrical conductivity between controller 1405 and DRAM technologies. electronic device 1425. In various embodiments, controller I0129. Although specific embodiments have been illus 1405 includes an embodiment of a HfAION film with an trated and described herein, it will be appreciated by those electrode. In various embodiments, electronic device 1425 of ordinary skill in the art that any arrangement that is includes an embodiment of a HfAION film with an elec calculated to achieve the same purpose may be substituted trode. In various embodiments, controller 1405 and elec for the specific embodiments shown. It is to be understood tronic device 1425 include embodiments of a HfAlON film that the above description is intended to be illustrative, and with an electrode. In an embodiment, electronic system 1400 not restrictive, and that the phraseology or terminology includes, but is not limited to, fiber optic systems, electro employed herein is for the purpose of description and not of optic systems, and information handling systems such as limitation. Combinations of the above embodiments and wireless systems, telecommunication systems, and comput other embodiments will be apparent to those of skill in the CS. art upon studying the above description. 0127 FIG. 15 depicts a diagram of an embodiment of a What is claimed is: system 1500 having a controller 1505 and a memory 1525. 1. A method, comprising: In an embodiment, controller 1505 includes a HfAlON film forming, using atomic layer deposition, a HfAION dielec with an electrode. In an embodiment, memory 1525 includes tric layer on a Substrate; and a HfAION film structured as one or more monolayers with forming a metal gate on the Substrate. an electrode. In an embodiment, controller 1505 and 2. The method of claim 1, whereinforming the metal gate memory 1525 each include a HfAION film with an elec includes forming the metal gate on and contacting the trode. In an embodiment, system 1500 also includes an dielectric layer. electronic apparatus 1535 and a bus 1515, where bus 1515 3. The method of claim 2, whereinforming a metal gate provides electrical conductivity between controller 1505 and includes forming a metal gate of a transistor. electronic apparatus 1535 and between controller 1505 and 4. The method of claim 3, wherein forming a metal gate memory 1525. In an embodiment, bus 1515 includes an of a transistor includes forming a gate of a silicon MOSFET. address bus, a data bus, and a control bus, each indepen 5. The method of claim 3, whereinforming a metal gate dently configured. In an alternative embodiment, bus 1515 of a transistor includes forming a gate of a germanium uses common conductive lines for providing one or more of MOSFET. US 2008/0057659 A1 Mar. 6, 2008

6. The method of claim 3, whereinforming a metal gate 24. The method of claim 20, wherein nitridizing the of a transistor includes forming a gate of a SiGe MOSFET. HfAlO to form HfAlON includes introducing nitrogen by a 7. The method of claim 2, wherein forming a metal gate NH anneal. includes forming an electrode of a capacitor. 25. The method of claim 20, whereinforming a layer of 8. The method of claim 2, whereinforming the dielectric HfAlO includes: layer includes structuring a memory storage capacitor. forming a layer of hafnium oxide by atomic layer depo 9. The method of claim 8, whereinforming the dielectric sition; layer and forming the metal gate include connecting the forming a layer of aluminum oxide by atomic layer dielectric layer and metal electrode in an analog integrated deposition; and circuit. annealing the layer of hafnium oxide with the layer of 10. The method of claim 2, wherein forming the metal aluminum oxide to form HfAlO. gate includes structuring the metal gate as a capacitor in a 26. A method comprising: RF integrated circuit. forming a dielectric layer on a Substrate, the dielectric 11. The method of claim 2, whereinforming the dielectric layer including a layer of HfAlON, the layer of HfA layer structured as a tunnel gate insulator in a flash memory, 1ON formed using atomic layer deposition including: and wherein forming the metal gate includes forming a forming a layer of HfN by atomic layer deposition; floating gate in the flash memory. forming a layer of AlN by atomic layer deposition: 12. The method of claim 2, whereinforming the dielectric annealing the layer of HfN with the layer of AlN: layer structured as an inter-gate insulator in a flash memory, oxidizing the layers of HfN and LaN to form HfAlON: and whereinforming the metal gate includes structuring the and metal gate as a control gate in the flash memory. forming a metal gate on the Substrate. 13. The method of claim 2, whereinforming the dielectric 27. The method of claim 26, whereinforming a metal gate layer includes forming a nanolaminate dielectric in a NROM includes the metal gate being on and contacting the dielec flash memory. tric layer. 14. The method of claim 1, wherein forming a metal gate 28. The method of claim 26, wherein the annealing and on and contacting the dielectric layer includes forming the the oxidizing are performed together. metal gate by atomic layer deposition. 29. The method of claim 26, wherein the layer of HfN and 15. A method, comprising: the layer of AlN are annealed and oxidized by rapid thermal forming, using atomic layer deposition, a HfAlON dielec oxidation to form HfAlON. tric layer on a Substrate; and 30. The method of claim 26, wherein the method includes Substituting a desired metal material for previously dis forming alternating layers of HfN and AlN prior to anneal posed Substitutable material to form a metal gate on the 1ng. Substrate. 31. A method comprising: 16. The method of claim 15, whereinforming the dielec forming a dielectric layer on a Substrate, the dielectric tric layer includes forming a nanolaminate dielectric in a layer including a layer of HfAlON, the layer of HfA NROM flash memory. 1ON formed using atomic layer deposition including: 17. The method of claim 15, whereinforming the dielec forming a layer of HfoN by atomic layer deposition; tric layer structured as a tunnel gate insulator in a flash forming a layer of AlON by atomic layer deposition: memory, and wherein forming the metal gate includes annealing the layer of HfoN with the layer of AlON to forming a floating gate in the flash memory. form HfAlON; and 18. The method of claim 15, wherein substituting a forming a metal electrode on and contacting the dielectric desired metal material includes Substituting aluminum for layer. carbon. 32. The method of claim 31, wherein the method includes 19. The method of claim 15, wherein substituting a forming alternating layers of HfoN and AION prior to desired metal material includes Substituting tanatalum for annealing. carbon. 33. A method comprising: 20. A method comprising: forming a dielectric layer on a Substrate, the dielectric forming a dielectric layer on a Substrate, the dielectric layer including a layer of HfAlON, the layer of HfA layer including a layer of HfAlON, the layer of HfA 1ON formed using atomic layer deposition; and 1ON formed using atomic layer deposition including: forming a metal electrode on and contacting the dielectric forming a layer of HfAIO using atomic layer deposition; layer, the metal electrode formed by: nitridizing the HfAIO to form HfAlON; and forming a layer of substitutable material on the dielectric Substituting a desired metal material for previously dis layer, the Substitutable material including one or more posed Substitutable material to form a metal gate on the materials selected from the group consisting of carbon, Substrate. polysilicon, germanium, and silicon-germanium; and 21. The method of claim 20, wherein substituting the substituting a desired metal material for the substitutable desired metal includes forming a metal gate on and contact material to provide the metal electrode on the dielectric ing the dielectric layer. layer. 22. The method of claim 20, wherein nitridizing the 34. The method of claim 33, wherein the method includes HfAIO to form HfAION includes nitridizing at high tem forming a layer of the desired metal material on the layer of peratures. Substitutable material and heating the layers at a temperature 23. The method of claim 20, wherein nitridizing the below the eutectic temperature of the desired metal material. HfALO to form HfAlON includes introducing nitrogen by a 35. The method of claim 33, whereinforming a layer of microwave plasma. Substitutable material includes forming a carbon structure. US 2008/0057659 A1 Mar. 6, 2008 18

36. The method of claim 35, wherein substituting a 38. The method of claim 37, wherein substituting a desired metal material for the substitutable material includes desired metal material for the substitutable material includes Substituting for the carbon structure one or more materials from the group consisting of gold, silver, a gold alloy, a Substituting for the carbon structure one or more materials silver alloy, copper, platinum, rhenium, ruthenium, rhodium, from the group consisting of aluminum, copper, silver, gold, nickel, osmium, palladium, iridium, and cobalt. 37. The method of claim 33, wherein forming a layer of and alloys of silver and gold. Substitutable material includes forming one or more of polysilicon, germanium, or silicon-germanium. k . . . .