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A Transitive Closure Algorithm for Test Generation

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A Transitive Closure Algorithm for Test Generation A Transitive Closure Algorithm for Test Generation Srimat T. Chakradhar, Member, IEEE, Vishwani D. Agrawal, Fellow, IEEE, and Steven G. Rothweiler Abstract-We present a transitive closure based test genera- Cox use reduction lists to quickly determine necessary as- tion algorithm. A test is obtained by determining signal values signments [5]. that satisfy a Boolean equation derived from the neural net- These algorithms solve two main problems: (1) they work model of the circuit incorporating necessary conditions for fault activation and path sensitization. The algorithm is a determine logical consequences of a partial set of signal sequence of two main steps that are repeatedly executed: tran- assignments and (2) they determine the order in which sitive closure computation and decision-making. To compute decisions on fixing signals should be made. the transitive closure, we start with an implication graph whose In spite of making extensive use of the circuit structure vertices are labeled as the true and false states of all signals. A directed edge (x, y) in this graph represents the controlling in- and function, most algorithms have several shortcomings. fluence of the true state of signal x on the true state of signal y First, they do not guarantee the identification of all logi- that are connected through a wire or a gate. Since the impli- cal consequences of a partial set of signal assignments. In cation graph only includes local pairwise (or binary) relations, other words, local conditions are easier to identify than it is a partial representation of the netlist. Higher-order signal the global ones. It is, however, desirable to identify all relationships are represented as additional ternary relations. The transitive closure of the implication graph contains global such consequences so that a branch-and-bound method can pairwise logical relationships among all signals. Some signal effectively avoid signal assignments that will not lead to dependencies result in conflicts, and, hence, identify redundan- a test vector. This may also result in an earlier detection cies. Other dependencies like fixations, identifications, and ex- of redundant faults. Second, they do not establish the clusions are also determined from the transitive closure. Sen- complexity of determining the logical consequences, and sitization of physical and logical dominators, unique path sensitization, static and dynamic learning, and other tech- it is unclear if it is at all possible to determine all the niques that are useful in determining necessary signal assign- consequences using reasonable amount of resources. ments are implicit in the process. A key feature of the algo- Third, these techniques may not be easily parallelizable. rithm is that dependencies derived from the transitive closure We have suggested the use of transitive closure in our are used to reduce ternary relations to binary relations that in earlier work [6], [7]. In the present work, we give a com- turn dynamically update the transitive closure. The signals are either determined from the transitive closure or are enumer- plete test generation algorithm based on transitive clo- ated until the Boolean equation is satisfied. We present exper- sure. Preliminary results on this work were reported in an imental results on the ISCAS 1985 and the combinational parts earlier paper [SI. Starting with the energy minimization of ISCAS 1989 benchmark circuits demonstrating efficient test formulation [9], we derive a Boolean equation represent- generation and redundancy identification. Results on four state- ing the circuit function and the conditions for fault acti- of-the-art production VLSI circuits are also reported. vation and path sensitization. A test is found by deter- mining a set of signals that satisfy this equation. We I. INTRODUCTION further represent the Boolean relations in the equation by OME OF THE BEST known algorithms for test gen- an implication graph (IG) whose vertices are the true and Seration published to date use various types of analyses complemented states of the signals. For example, directed to speed up the basic branch-and-bound search process. edge (x, 7) in the graph represents the controlling influ- For example, in the FAN algorithm, Fujiwara and Shi- ence of the true state signal x on the false state of signal mono [l] use multiple backtrace to quickly discover any y. The variables x and y are associated with the same gate possible conflicts. In the TOPS algorithm [Z], Kirkland or signal net in the circuit. Since IG includes only pair- and Mercer rely on prior identification of dominators. In wise (or binary) relations, it is a partial representation of SOCRATES [3], Schulz and Auth employ static and dy- the netlist. The transitive closure of IG contains pairwise namic learning largely based on local simulation. More logical relationships among all signal pairs. These rela- recently, in the EST algorithm [4], Giraldi and Bushnell tionships either force values on some signals or indicate store groups of signal states for future use. Rajski and contradictory requirements caused by a redundant fault. If signals thus determined satisfy the Boolean equation, we have a test. Otherwise, we enter the decision-making phase, fix an unassigned signal, and update the transitive Manuscript received May 26, 1992; revised October 15, 1992. This pa- per was recommended by Associate Editor S. Seth. closure to determine logical consequences of this deci- S. T. Chakradhar and S. G. Rothweiler are with the NEC Research In- sion. stitute. Princeton. NJ 08540. Four basic conclusions are obtained from transitive clo- V. D. Agrawal is with the AT&T Bell Laboratories, Murray Hill, NJ 07974. sure. These are contradiction (an impossible signal rela- IEEE Log Number 9207803. tion),$xation (a 0 or a 1 value for a signal), identijication 0278-0070/93$03.00 0 1993 IEEE I 1016 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 12, NO. 7, JULY 1993 (two signals must assume identical value), and exclusion transitive closure and using fast matrix multiplication (two signals must not assume certain states). Only the first methods. An alternative method for deriving all logical three of these conclusions were given in the previous work conclusions in linear expected-time complexity has also [6]. In the process of test generation, as soon as a signal been proposed 1141. There are efficient algorithms for is assigned, transitive closure immediately gives all log- computing the transitive closure of sparse graphs [ 121. ical consequences. A novel feature of our method is that The computation of transitive closure can easily be ac- the transitive closure is dynamically updated by adding celerated through parallel processing since it belongs to new relations which are reduced to binary form. If a con- class NC, a hierarchy of problems solvable by determin- tradiction is found, the signal assignment is changed. If istic algorithms that operate in polylog time using a no assignment can be made without contradiction then the polynomial-bounded number of processors. If A is the ad- fault is considered redundant. For detectable faults, con- jacency matrix of graph G, the transitive closure of G can tradictions avoid long backtracks. Results illustrate the ef- be obtained by squaring the adjacency matrix logz n times, fectiveness of transitive closure both in finding redundant where n is the number of vertices in graph G. It is known faults and in reducing the number of backtracks. We give [ 121 that n x n matrix multiplication can be performed in details of the transitive closure method of test generation, 0 (log, n) time using 0 (n2.376) processors. Thus, transi- describe an implementation, and discuss results on the tive closure can be computed in polylog time using the benchmark circuits. same number of processors. If fewer processors are avail- In our earlier work [9], we presented an energy min- able, it is still possible to design an efficient parallel al- imization formulation of the test generation problem and gorithm. Recently, a constant-time algorithm has been discussed two approaches based on simulated annealing proposed for computing transitive closure on a processor and neural networks. The energy minimization formula- array with reconfigurable bus system [ 151. tion has similarities to another formulation known as Boolean satisfiability [IO]. In the test generation proce- 111. CIRCUITREPRESENTATION dure based on Boolean satisfiability [ 1 11 that has appeared We represent the digital circuit as a set of binary and in the literature, the satisfiability conditions are divided ternary relations [IO]. As an example, consider the NAND into two groups. The first group, containing only 2-SAT gate shown in Fig. 1. Since c = ab, it is easy to see that terms, is used for constructing an implication graph. Sig- the equation F,,,, = c 8 = 0 is satisfied only by those nal contradictions are determined by finding the strongly values of a, 6, and c that satisfy the NAND gate function. connected components in this implication graph. Even Here, denotes the logical exclusive-oR (XOR) opera- though we start with an implication graph, our method 8 tion. We will refer to F,,,, as the Boolean false function. differs in several ways. First, we compute transitive clo- An analogous Boolean truth finction can also be used sure which identifies various forms of signal dependen- [lo]. Using Boolean algebra, we can rewrite F,,,,, as fol- cies stated earlier, in addition to finding contradictions. lows: The examples in Section V illustrate some of the advan- tages of this technique over other methods 131, [ 111. Sec- F,,,,, = a? + 62 + abc = 0 (1) ond, we dynamically update the transitive closure by in- corporating higher-order terms reduced to binary relations where + denotes the logical OR operation. A similar for- due to signal dependencies. We present experimental re- mulation is possible for representing the NAND gate as an sults for ISCAS '85 and '89 benchmark circuits.
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