A Transitive Algorithm for Test Generation

Srimat T. Chakradhar, Member, IEEE, Vishwani D. Agrawal, Fellow, IEEE, and Steven G. Rothweiler

Abstract-We present a transitive closure based test genera- Cox use reduction lists to quickly determine necessary as- tion algorithm. A test is obtained by determining signal values signments [5]. that satisfy a Boolean equation derived from the neural net- These algorithms solve two main problems: (1) they work model of the circuit incorporating necessary conditions for fault activation and path sensitization. The algorithm is a determine logical consequences of a partial of signal sequence of two main steps that are repeatedly executed: tran- assignments and (2) they determine the order in which sitive closure computation and decision-making. To compute decisions on fixing signals should be made. the transitive closure, we start with an implication graph whose In spite of making extensive use of the circuit structure vertices are labeled as the true and false states of all signals. A directed edge (x, y) in this graph represents the controlling in- and function, most algorithms have several shortcomings. fluence of the true state of signal x on the true state of signal y First, they do not guarantee the identification of all logi- that are connected through a wire or a gate. Since the impli- cal consequences of a partial set of signal assignments. In cation graph only includes local pairwise (or binary) relations, other words, local conditions are easier to identify than it is a partial representation of the netlist. Higher-order signal the global ones. It is, however, desirable to identify all relationships are represented as additional ternary relations. The transitive closure of the implication graph contains global such consequences so that a branch-and-bound method can pairwise logical relationships among all signals. Some signal effectively avoid signal assignments that will not lead to dependencies result in conflicts, and, hence, identify redundan- a test vector. This may also result in an earlier detection cies. Other dependencies like fixations, identifications, and ex- of redundant faults. Second, they do not establish the clusions are also determined from the transitive closure. Sen- complexity of determining the logical consequences, and sitization of physical and logical dominators, unique path sensitization, static and dynamic learning, and other tech- it is unclear if it is at all possible to determine all the niques that are useful in determining necessary signal assign- consequences using reasonable amount of resources. ments are implicit in the process. A key feature of the algo- Third, these techniques may not be easily parallelizable. rithm is that dependencies derived from the transitive closure We have suggested the use of transitive closure in our are used to reduce ternary relations to binary relations that in earlier work [6], [7]. In the present work, we give a com- turn dynamically update the transitive closure. The signals are either determined from the transitive closure or are enumer- plete test generation algorithm based on transitive clo- ated until the Boolean equation is satisfied. We present exper- sure. Preliminary results on this work were reported in an imental results on the ISCAS 1985 and the combinational parts earlier paper [SI. Starting with the energy minimization of ISCAS 1989 benchmark circuits demonstrating efficient test formulation [9], we derive a Boolean equation represent- generation and redundancy identification. Results on four state- ing the circuit function and the conditions for fault acti- of-the-art production VLSI circuits are also reported. vation and path sensitization. A test is found by deter- mining a set of signals that satisfy this equation. We I. INTRODUCTION further represent the Boolean relations in the equation by OME OF THE BEST known algorithms for test gen- an implication graph (IG) whose vertices are the true and Seration published to date use various types of analyses complemented states of the signals. For example, directed to speed up the basic branch-and-bound search process. edge (x, 7) in the graph represents the controlling influ- For example, in the FAN algorithm, Fujiwara and Shi- ence of the true state signal x on the false state of signal mono [] use multiple backtrace to quickly discover any y. The variables x and y are associated with the same gate possible conflicts. In the TOPS algorithm [Z], Kirkland or signal net in the circuit. Since IG includes only pair- and Mercer rely on prior identification of dominators. In wise (or binary) relations, it is a partial representation of SOCRATES [3], Schulz and Auth employ static and dy- the netlist. The transitive closure of IG contains pairwise namic learning largely based on local simulation. More logical relationships among all signal pairs. These rela- recently, in the EST algorithm [4], Giraldi and Bushnell tionships either force values on some signals or indicate store groups of signal states for future use. Rajski and contradictory requirements caused by a redundant fault. If signals thus determined satisfy the Boolean equation, we have a test. Otherwise, we enter the decision-making phase, fix an unassigned signal, and update the transitive Manuscript received May 26, 1992; revised October 15, 1992. This pa- per was recommended by Associate Editor S. Seth. closure to determine logical consequences of this deci- S. T. Chakradhar and S. G. Rothweiler are with the NEC Research In- sion. stitute. Princeton. NJ 08540. Four basic conclusions are obtained from transitive clo- V. D. Agrawal is with the AT&T Bell Laboratories, Murray Hill, NJ 07974. sure. These are contradiction (an impossible signal rela- IEEE Log Number 9207803. tion),$xation (a 0 or a 1 value for a signal), identijication

0278-0070/93$03.00 0 1993 IEEE I

1016 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 12, NO. 7, JULY 1993

(two signals must assume identical value), and exclusion transitive closure and using fast matrix multiplication (two signals must not assume certain states). Only the first methods. An alternative method for deriving all logical three of these conclusions were given in the previous work conclusions in linear expected-time complexity has also [6]. In the process of test generation, as soon as a signal been proposed 1141. There are efficient algorithms for is assigned, transitive closure immediately gives all log- computing the transitive closure of sparse graphs [ 121. ical consequences. A novel feature of our method is that The computation of transitive closure can easily be ac- the transitive closure is dynamically updated by adding celerated through parallel processing since it belongs to new relations which are reduced to binary form. If a con- class NC, a hierarchy of problems solvable by determin- tradiction is found, the signal assignment is changed. If istic algorithms that operate in polylog time using a no assignment can be made without contradiction then the polynomial-bounded number of processors. If A is the ad- fault is considered redundant. For detectable faults, con- jacency matrix of graph G, the transitive closure of G can tradictions avoid long backtracks. Results illustrate the ef- be obtained by squaring the adjacency matrix logz n times, fectiveness of transitive closure both in finding redundant where n is the number of vertices in graph G. It is known faults and in reducing the number of backtracks. We give [ 121 that n x n matrix multiplication can be performed in details of the transitive closure method of test generation, 0 (log, n) time using 0 (n2.376) processors. Thus, transi- describe an implementation, and discuss results on the tive closure can be computed in polylog time using the benchmark circuits. same number of processors. If fewer processors are avail- In our earlier work [9], we presented an energy min- able, it is still possible to design an efficient parallel al- imization formulation of the test generation problem and gorithm. Recently, a constant-time algorithm has been discussed two approaches based on simulated annealing proposed for computing transitive closure on a processor and neural networks. The energy minimization formula- array with reconfigurable bus system [ 151. tion has similarities to another formulation known as Boolean satisfiability [IO]. In the test generation proce- 111. CIRCUITREPRESENTATION dure based on Boolean satisfiability [ 1 11 that has appeared We represent the digital circuit as a set of binary and in the literature, the satisfiability conditions are divided ternary relations [IO]. As an example, consider the NAND into two groups. The first group, containing only 2-SAT gate shown in Fig. 1. Since c = ab, it is easy to see that terms, is used for constructing an implication graph. Sig- the equation F,,,, = c 8 = 0 is satisfied only by those nal contradictions are determined by finding the strongly values of a, 6, and c that satisfy the NAND gate function. connected components in this implication graph. Even Here, denotes the logical exclusive-oR (XOR) opera- though we start with an implication graph, our method 8 tion. We will refer to F,,,, as the Boolean false function. differs in several ways. First, we compute transitive clo- An analogous Boolean truth finction can also be used sure which identifies various forms of signal dependen- [lo]. Using Boolean algebra, we can rewrite F,,,,, as fol- cies stated earlier, in addition to finding contradictions. lows: The examples in Section V illustrate some of the advan- tages of this technique over other methods 131, [ 111. Sec- F,,,,, = a? + 62 + abc = 0 (1) ond, we dynamically update the transitive closure by in- corporating higher-order terms reduced to binary relations where + denotes the logical OR operation. A similar for- due to signal dependencies. We present experimental re- mulation is possible for representing the NAND gate as an sults for ISCAS '85 and '89 benchmark circuits. Our energy function where a, b, and c were treated as arith- method identifies all redundant faults in these circuits, and metic variables [ 161. The function F,,,, assumes the value a majority of them are identified without any search. 0 only when all the three terms in equation (1) simulta- neously become 0. The term ZC assumes the value 0 under 11. TRANSITIVECLOSURE any one of the following conditions: (1) a = 1, (2) a = Given a directed graph G = (V, E) with vertex set V 1 and c = 1, (3) c = 1, or (4) C = 1 and a = 1. Conditions

= {XI, * * , x,}, and edge set E, we wish to find out 1 and 2 are equivalent to the binary a * c, where whether there is a path in G from x, to x, for all vertex * denotes logical implication. Conditions 3 and 4 are pairs x,, x, E V. The transitive closure [ 121 of G is defined equivalent to the 2 * a. The term 62 sim- as the graph G* = (V, E*), where E* = {(x,, xJ):there ilarly results in the binary relations 6 * c and C =) b. The is a path from vertex x, to vertex xJ in G}. term abc does not produce any binary relations. However, Computing transitive closure is an important step in if any one of the signals assumes a known value, this term many parallel algorithms related to directed graphs [ 131. will reduce to a binary relationship. A similar analysis can An important application of transitive closure is in deriv- be performed for all other Boolean gates. The false func- ing all logical conclusions implied by a set of binary re- tion for a digital circuit is the logical OR of the false func- lations. It has many other applications. tions for all gates. We write a Boolean equation by equat- Finding the transitive closure of a graph G having n ing this false function to 0. The problem of determining vertices requires 0(n3) operations in the worst case 1121. a signal assignment that satisfies this Boolean equation is This complexity could be reduced to 0(n249) by exploit- equivalent to minimizing the energy function of the digi- ing the equivalence between matrix multiplication and tal circuit [ 101. I

CHAKRADHAR er U/.: A TRANSITIVE CLOSURE ALGORITHM 1017

b b d Fig. I. A NAND gate Fig.- 4. An example circuit

visualized as construction of a faulty circuit copy, as shown in Fig. 5. The Boolean false function for the mod- ified circuit is given by the logical OR of the false func- tions for the gates c, d, and d’ (we address a gate by the name of its output signal). Furthermore, signals c and c’ are constrained to assume the logic values 1 and 0, re- Fig. 2. Implication graph for NAND gate. spectively. All the functional constraints can be deter- mined from the netlist of the circuit in time complexity aZbzcF that is linear in the number of signals. Structural Constraints: We assign a binary variable, a100000 called the path variable, s,, to every signal x that lies on z010010 a path from the fault site to the primary output. This vari- -bOOlOOO able assumes the logic value 1 only when the fault on x is bOOOllO observable at the primary output. In our example, signals c000010 c and d are assigned the binary variables s, and sd. There z101001 are two types of structural constraints. Both can be de- Fig. 3. Transitive closure of the NAND gate rived from the netlist of the circuit in time complexity that is linear in the number of signals. First, an input fault on a gate is observable only if the gate output fault is ob- It is convenient to represent the binary relations as a servable. Note that the converse need not be true. In our directed graph, also called an implication graph [17]. Im- example, ifs, = 1, then sd must assume the value 1. This plication graphs have been used earlier by us [7] and oth- constraint is expressed as follows: s,Sd = 0. These path ers [ 1 1 [ 181. The implication graph for the NAND gate, 1, variables and the above constraint are similar to the active as shown in Fig. 2, contains vertices for true and false line variables used by others [ 111. We, however, propose states of variables. Thus, the vertex set is (a, b, c, a, b, an additional constraint that significantly improves the C}. Equation ZC = 0 is expressible as binary relations Z performance of our test generation system. If the fault has * c and C a that are represented as arcs (2, c) and (F, - propagated to the output of a gate, it must have propa- a), respectively. Similarly, bC = 0 adds the arcs (b, c) gated to one or more gate inputs. In our example, since and (T, b) to the IG. The transitive closure of this impli- the fault propagates to only one input of gate d, if sd = cation graph is shown by its adjacency matrix in Fig. 3. 1, then s, = 1. This constraint is expressed as sdS, = 0. It can be determined using standard graph-theoretic tech- Although not applicable in the present example, if signals niques [ 121. Incidentally, in this case, the implication b and c had path variables, then we would have included graph also happens to be its own transitive closure. the constraint sdSbF, = 0. For a stem fault to be observ- able, the fault must propagate through one or more of the IV. PROBLEMFORMULATION branches. This case is not applicable in the present ex- We formulate test generation as an energy minimiza- ample. Second, if the path variable associated with signal tion problem. We illustrate our method by an example. x is true, then signal x must assume different values in the Consider the circuit shown in Fig. 4. We will derive a test fault-free and faulty circuits. If we denote the faulty cir- for an s-a-0 fault on signal e. cuit value as x’, this constraint is expressed as follows: First, we derive two types of constraints to be repre- s,(xx’ + XX‘) = 0. Notice that this condition cannot be sented in the IG: (1) Functional constraints that depend expressed as binary relations. For the fault to be observ- upon the function of gates used in the circuit. (2) Struc- able, the path variables associated with the fault site and tural constraints that depend on the specific interconnec- the primary output are constrained to be 1. Therefore, in tion topology of gates and are independent of the gate our example, s, = sd = 1. types used in the circuit. In summary, the functional constraints are: Zc + bZ + Functional Constraints: Signals that lie on a path from abc = 0, 62 + Fd + bcd = 0 and bd’ + c’d’ + bc‘d’ the fault site to a primary output may assume different = 0. The structural constraints are: s,Sd = sdSc = s, (cc’ values in the fault-free and faulty circuits. Therefore, ad- + CC’) = Sd(dd’ + 22’) = 0. ditional binary variables are assigned to these signals. In The logical OR of the functional and structural con- our example, signals c and d lie on the path from the fault straints is the Boolean false function for the circuit with site to the primary output and we assign two binary vari- fault. Any signal assignment that satisfies the Boolean ables c’ and d’, respectively. Conceptually, this can be false function is a test for the fault. Since we are deriving 1018 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 12, NO. 7, JULY 1993

Contradiction and fixation relationships express con- straints on a single signal in the circuit. Identification and exclusion relationships express dependencies between a pair of signals. U Fig. 5. Modified circuit for fault on c. 5.1. Contradiction This is a global dependency among signals that cannot be satisfied. For example, consider the circuit shown in Fig. 8. The implication graph for this circuit is shown in Fig. 9(a). Suppose we wish to determine if there is an input vector that will set signal c to logic value 1. We include the constraint c = 1 in the implication graph by adding the arc (E, c). The updated implication graph is Fig. 6. Implication graph for circuit in Fig. 5 shown in Fig. 9(b). If we compute the transitive closure of the updated implication graph, we observe that both a 7i b 5 d 2 d' 2 arcs (C, c) and (c, C) are present in the transitive closure. allllllll The arc (Z,c) implies that C = 0 and the arc (c,C) implies 7i01000000 that c = 0. Since signal c cannot simultaneously assume bOllOOllO the value 0 and 1, no input vector exists that will set sig- - nal c to 1. bOlllllll In general, a signal x must simultaneously assume 0 -dOlllllll and 1 values when the transitive closure consists of both dOllOOllO arcs (x, X) and (X, x). If this situation occurs before the -d'01100110 search process begins or after the search space has been d'01111111 implicitly exhausted, the fault is redundant. If a contra- Fig. 7. Transitive closure of implication graph in Fig. 6. diction occurs during the search process, we must back- track to the previous choice. It is possible to detect difficult redundant faults using a test for the s-a-0 fault on signal c, c = 1, c' = 0, s, = contradiction analysis. Section 7.4 illustrates the detec- sd = 1 and our constraint set reduces to: ab = 0, bd + tion of a difficult redundant fault that may not be detect- db = 0, d' + bd' = 0 and dd ' + dp = 0. All the terms able using conventional techniques like learning [3] or re- can be expressed as binary relations. The implication duction lists [5]. graph is shown in Fig. 6. It contains vertices for variables and their_-_ complements. Here, the vertex set is (a, b, d, 5.2. Fixation d', a, b, d, d'}.The constraint ab = 0 is expressible as This is a global dependency where a certain signal must a pair of binary relations a * b and b * a that are rep- assume a fixed value in any set of signal assignments that resented as arcs (a,6) and (b,a), respectively. Arcs cor- will satisfy all signal dependencies in the circuit. As an responding to the other terms are similarly derived. example, consider again the circuit shown in Fig. 8 and The transitive closure of the implication graph is shown the implication graph in Fig. 9(a). If we compute the tran- in Fig. 7. This can be computed using standard graph- sitive closure of the implication graph, we observe that it theoretic techniques [ 121. consists of the arc (c, C). Furthermore, it does not have The main use of transitive closure in test generation is any other arcs between literals c and C. Arc (c, C) implies to determine global signal dependencies. Transitive clo- that c = 0 and, hence, we can fix signal c to 0. sure finds relationships between signals that may seem In general, a signal x can be fixed to the value 0 if the structurally unrelated. This is demonstrated by examples transitive closure consists of the arc (x, X) and there are in Sections V and VII. In the next section, we classify no other arcs between literals x and X. Similarly, if the signal dependencies into four categories and illustrate the transitive closure only consists of the arc (2,x) then the use of transitive closure in deriving such dependencies. signal x can be fixed at 1. A more interesting case of fix- Section VI presents a test generation algorithm entirely ation is illustrated in Section 7.2. based on transitive closure computations on directed graphs. 5.3. Ident$cation This is a global dependency where certain pairs of sig- v. GLOBALSIGNAL DEPENDENCIESFROM TRANSITIVE nals must assume the same value. Once again, consider CLOSURE the circuit of Fig. 8 and its implication graph (Fig. 9(a)). Signal dependencies contained in the transitive closure If we compute the transitive closure of the implication of the implication graph can be grouped into four classes: graph, we observe that it consists of the arcs (a, 6)and contradiction, fixation, identijcation, and exclusion. (6, a). This implies that literals a and 6 must assume the I

CHAKRADHAR er al.: A TRANSITIVE CLOSURE ALGORITHM 1019

Fig. 8. An example to illustrate contradiction. - Fig. 10. Identification example. n

(a) (b) Fig. 9. Implication graph of circuit in Fig. 8. (a) Implication graph. (b) Updated implication graph. (a) (b) same value in any signal assignment that satisfies all de- Fig. 11. Implication graph of identification example. (a) Simplified func- pendencies in the circuit. tional constraints. (b) Updated implication graph. Identifications can lead to fixations or contradictions. As an example, consider the circuit shown in Fig. 10. The the transitive closure consists of the arcs (x, y) and ( L, 3) functional constraint for the XOR gate c is ?(ab + ab) + and no other arcs between the variables x and y, then the c(ab = 0. Similarly, functional ccnstraint for the + 56) Combination x = 1 and y = 0 is excluded. This is because XNOR gate d is d(ab sib) d(ab ab) = 0 and the + + + these arcs imply that xy = 0 and the above combination functional constraint for the OR gate e is CZ + de + Fae does not satisfy this relationship. = 0. As an example, consider the portion of a circuit shown Suppose signal c is fixed to the value 0. We will show in Fig. 12. Suppose that during test generation for some that, using identifications, signals d and e can be fixed to fault, signals g andfhave been assigned the values 1 and the value 1. 0, respectively. Due to these signal assignme$, the For c = 0, the simplified functional constraints a'e ab functional _constraints of gate g and f simplify to de = 0 + sib = 0, d(ab + sib) d(ab sib) = 0, and de = + + and bc + b? = 0. The functional constraints for gates d 0. The implication graph for these constraints is shown in and e are Zd + bd + abd = 0 and E + Ce + ace = 0. Fig. 1 l(a). Incidentally, in this case, the implication graph The implication graph for the binary relations in these also happens to be its own transitive closure. Since the functional constraints is shown in Fig. 13. If we compute transitive closure consists of the arcs (a, b) and (b, a), the transitive closure of the implication graph, we observe signals a and b must assume the same value. Similarly, that signals b and c must assume the same value. _Fur- signals d and e must assume the same value. Since signals thermore, the transitive closure congsts of the arcs (d, e) a and b assume the same value, the functional constraint and (e, d)that imply the constraint de = 0. Therefore, d d(ab ab) d(ab sib) = 0 can be simplified to da + + + + e = 1. Using the identification of signals b and c and dsi = 0. We include the constraints da = 0 and dsi = + the fact that d e = 1, the ternary relations abd = 0 and 0 in the implication graph. The updated implication graph + ace = 0 can be simplified to ab = 0. is shown in Fig. ll(b). If we compute the transitive clo- We include the constraint ab = 0 in the implication sure of the updated implication graph, we observe that it graph. The updated implication graph is shown in Fig. consists of the arc d)and no other arcs between literals (a, 14. If we compute the transitive closure of the updated d and Therefore, signal d can be fixed to 1. Similarly, d. implication graph, we observe that signals d and e are the transitive closure consists of the arcs e) and no (e, fixed to the value 1. other arcs between literals e and Therefore, signal e e. Note that, again, it is not possible to uniquely deter- can be fixed to 1. mine the value of signals d and e using prior approaches Note that it is not possible to uniquely determine the [3], [l I]. In general, if the transitive closure consists of value of signal e using prior approaches [3], [ 111. In gen- the arcs (x, y) and ( y, but no other arcs between literals eral, if the transitive closure consists of the arcs (x, y) and X) x, 3, y, and y, then the only constraint between variables ( y, x), literals x and y must assume the same value. x and y is xj = 0. Therefore, x and y can assume any combination of values except the combination x = 1 and 5.4. Exclusion y = 0. This implies that (X + y) = 1 and the ternary relations can be further simplified. Note that the use of This is a global dependency where certain pairs of lit- exclusion is reminiscent of double cube extraction in logic erals cannot assume a certain combination of values. If minimization algorithms [ 191. +, I Fig. 12. Exclusion example.

I No Transitive closure

variable at top of stack tried ? .-

I I Pop stack Fig. 13. Implication graph of exclusion example. Fig. 15. Algorithm flow.

closure and determine global dependencies. If there is a contradiction, we backtrack to step 3 and make an alternative choice. If the signal assignments sat- isfy the Boolean equation, we have a test. Other- wise, ternary relations that have been reduced to bi- nary relations due to current set of signal

I I assignments are added to the transitive closure and Fig. 14. Updated implication graph of exclusion example. we go to step 2. Continuing the test generation example of Section IV, VI. TEST GENERATIONALGORITHM the transitive closure in Fig. 7 contains the arc (a,a) and, Fig. 15 shows the flow chart of the test generation al- therefore, a = 0. Similarly, b = d’ = 1 and d = 0. Since gorithm. Test generation proceeds as follows: all primary input signals have been determined, we do not need the search phase. The vector a = 0, b = 1 is a test 1. Derive functional and structural constraints for the for the fault c s-a-0. fault in the form of a Boolean equation. 2. Determine the transitive closure of constraints ex- VII. FINDINGNECESSARY ASSIGNMENTS pressible as binary relations and identify global de- pendencies (described in Section V). If a contradic- The techniques of implication, justification, static tion is detected, the fault is redundant. If signal learning, dynamic learning, and sensitization of domina- values, thus determined, satisfy the Boolean equa- tors are implicit in the transitive closure method. Also, as tion, we have a test. Otherwise, a partial set of sig- we will explain, logical dominators are implicitly sensi- nal values determined thus far may reduce some of tized. Furthermore, it is possible to detect difficult redun- the ternary relations to binary relations. We include dancies that may not be detectable by other techniques. these relations in the transitive closure and identify new global dependencies. We continue this process 7.1. Implicit Implication and Justijication until no ternary relation reduces to a binary relation. Consider the circuit shown in Fig. 16. The Boolean 3. Make a heuristic choice on an unassigned decision false function for this circuit, which is the logical OR of variable. A possible heuristic is described in Section the false functions for gates d, e,- andf,-- - consists of the VIII. Assigning a variable may cause some of the following two-variable terms: ad, bd, be, ZZ, d7, and ternary relations to become binary relations. A stack F7. The binary relations arising from these terms are rep- is used to ensure that the search space will, if nec- resented in the implication graph shown in Fig. 17. This essary, be implicitly enumerated during the branch- graph also happens to be its own transitive closure. The and-bound phase. adjacency matrix of the transitive closure is shown in Fig. 4. Include the new binary relations in the transitive 18. I

CHAXRADHAR ef al.: A TRANSITIVE CLOSURE ALGORITHM 1021

an\n

Fig. 16. A circuit used to illustrate computation of necessary assignments.

Fig. 19. Implication graph of circuit in Fig. 16 with d = 0

aabzczdzeEf7 a100000000000 E111000110010 Fig. 17. Implication graph of circuit in Fig. 16 -bOOlOOOOOOOOO blOllOOlllOlO aEb&czdaei?fT c000010000000 a100000000000 z000001001000 E010000100000 -dlOlOOOllOOlO dlOlOOOOlOOlO -bOOlOOOOOOOOO bOOOlOOlOlOOO e000000001000 c000010000000 E001010000110 z000001001000 -fOOOOOOOOOOlO flOlOOOlllOll -dOOOOOOlOOOOO dlOlOOOOlOOlO Fig. 20. Transitive closure of implication graph in Fig. 19. e000000001000 E001010000110 7.2. Transitive Closure Does More than Implication -fOOOOOOOOOOlO and Justification fOOOOOOlOlOOl Consider the case when signal f in the circuit of Fig. Fig. 18. Transitive closure of implication graph in Fig. 17. 16 is assigned the value 1. This results in the addition of the arc ( 7, f)to the implication graph leading to Fig. 2 1. The transitive closure method will fix signal b to logic Suppose d = 0. Forward implication will result inf = value 1, as explained below. It is important to note that, 1 and justification will result in a = b = 1. This is im- given f = 1, conventional implication and justification plicitly determined in the transitive closure method: procedures will not be able to conclude that signal b 1. Include the relation d = 0 into the implication graph should be fixed at 1. of Fig. 17 by adding the arc (d, 2). The updated Iff = 1, the three-variable term defin the false function implication graph is shown in Fig. 19. of the gatefreduces to de. Inclusion of the relations 7 = 2. Construct the transitive closure of the updated im- 0 and de = 0 will result in the addition of the following plication graph. The adjacency matrix of the up- arcs to the IG of Fig. 17: (7,f), (d, e), and (e, 2). The dated transitive closure is shown in Fig. 20. We can updated implication graph is shown in Fig. 21 and the directly derive the updated transitive closure from corresponding transitive closure adjacency matrix is given the transitive closure shown in Fig. 18 as follows. in Fig. 22. As explained earlier, we can also construct the The addition of the arc (d, z) will allow all ances- updated transitive closure by incrementally changing the tors of d to reach all descendants of d. The ancestors transitive closure shown in Fig. 18. of d, i.e., vertices si, b, and 7,are the vertices with Notice that the updated transitive closure (Fig. 22) has a 1 in column d in Fig. 18 and the descendants of a 1 in row 7; and column b. Thus, b implies b. But b does z, i.e., vertices a , b, andf, are the vertices with a not imply b. The arc (6, b), therefore, indicates the re- lation b = 0. Hence, b must be fixed at 1 as a consequence -1 in row d. For example, vertex b (an ancestor of d), that in Fig. 18 could only reach d and e, can of originally fixing f = 1. now also reach vertices a, b, d, andf(see Fig. 20). 3. Derive logical conclusions from the updated tran- 7.3. Implicit Sensitization of Physical and Logical sitive closure. In Fig. 20, there is an arc (a, a) but Dominators there is no arc (a, si). Thus, a = 1 is the only value Dominators are gates through which the fault must that can satisfy the arc (si, a) (note that this arc can propagate in order to be observable [2]. We refer to such only result from the relation = 0). Similarly, we gates as physical dominators. As an example, consider the can conclude that b = f = 1. fault b s-a-0 in the circuit of Fig. 16. It is easy to see that I

1022 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 12, NO. 7. JULY 1993

e' f'

L 1 :sf Fig. 2 1. Implication graph of circuit in Fig. 16 with f = 1. Fig. 23. Modified circuit for fault b s-a-0 in Fig. 16.

aZibZcEdZeFf7 a100000000000 E011010100110 -bOOlOOOOOOOOO blOlllOlllllO c000010000000 c101001011010 -dOOlOlOlOOllO dlOlOOOOlOOlO e101000011010 ~001010000110 -fOOOOOOOOOOlO Fig. 24. A circuit with redundant fault k s-a-I flOlOlOllllll Fig. 22. Transitive closure of implication graph in Fig. 21. TABLE I BINARYRELATIONS FOR CIRCUITIN FIG.24 (k = 0)

~~ the fault must propagate through gate f to be observable Gate Binary Relations at the output of the circuit, and thus f is identified as a physical dominator., When signal a is assigned the value C ac = 0 and 57 = 0 d bd = 0 and = 0 0, the fault must propagate through gate e to reach an __ 62 e ae = Oand62 = 0 output. Gate e is now a logical dominator. f if = 0 and ;if = 0 The transitive closure method implicitly identifies and g 8g = Oandcg = 0 sensitizes many physical and logical denominators. We h 77; = 0 and 27; = 0 illustrate these features by an example. The physical i 27 = OandfT = 0 = 0 and = 0 dominators of fault b s-a-0 are determined purely from the i 27 &7 k = 0 and; = 0 structural constraints, as expressed by these path vari- ables: s,Sd = 0, s,S, = 0, sdSf = 0, seSf = 0, and Sb?dSe = 0. The last constraint ensures that the stem fault on b fault. Conceptually, we can visualize the circuit with fault propagates to either signal d or e or both in order to be as the modified circuit shown in Fig. 23. By including the observable at the primary output. Initially, sb is set to 1 functional and structural constraints in the Boolean false since we assume that the fault on stem b is observable. function of the faulty circuit, and by computing the tran- This will reduce the ternary relation Sb?ddSe = 0 to the sitive closure of the binary relations, we see that s, = 1 binary relation SdSe = 0. It can easily be verified that the andc = 1. transitive closure of these binary relations fixes sf to 1. Therefore, gate f is a dominator. Note that f will be iden- 7.4. Redundancy Identijication tified as a dominator of the fault even if this circuit was Consider the circuit shown in Fig. 24. By simulating embedded in a larger circuit. the circuit for all possible combinations of a and b, it can As an example of identification and sensitization of log- be verified that the fault k s-a-1 is redundant. Since the ical dominators, consider the case when signal a is set to fault is on the primary output, we simply have to justify logic value 0. Since the fault on stem b cannot propagate the value 0 on signal k. The binary relations obtained from to gate d, gate e becomes the logical dominator. Further- the Boolean false function of the circuit are listed in Table more, signal c must be set to 1 to sensitize the logical I. The Boolean false function for gate k is 7 + 7 since k dominator e. The identification of e as the logical domi- = 0. Therefore, gate k contributes the relations 7 = 0 and nator and the assignment c = 1 is implicitly determined 7 = 0 to the Boolean false function of the entire circuit. by the transitive closure method, even in the case when Binary relations contributed by other gates can be simi- the circuit is part of a larger circuit and there are multiple larly derived. paths from signalfto the primary output. To see this, we If we represent these relations as an implication graph construct the Boolean false function for the circuit with and compute the transitive closure, both arcs (a, 5) and I

CHAKRADHAR er al.: A TRANSITIVE CLOSURE ALGORITHM 1023

(5, a) will be present in the transitive closure. This indi- transitive closure of the implication graph and de- cates a contradiction and, therefore, no assignment of sig- rive new global signal dependencies. If no contra- nal values will satisfy the Boolean equation for the circuit diction occurs, check if these dependencies may re- with k = 0. We conclude that the fault is redundant. duce some of the ternary relations to binary relations. Include these relations in the implication graph and update the transitive closure. If still no VIII. IMPLEMENTATIONAND EXPERIMENTALRESULTS contradiction occurs, go to step 5. Otherwise, in We implemented the proposed test generation tech- case of a contradiction, backtrack: if both values of nique in a prototype C language program called TRANand the last decision literal have resulted in contradic- used it to generate tests and identify redundancies in the tions, we back up to the previous decision literal. ISCAS '85 [20] and '89 [21] benchmark circuits. In the Otherwise, we assign the next value to the last de- next section, we present results on a sample of production cision literal and repeat step 6. If there are no de- VLST circuits on which the program has been used. cision literals left, we have implicitly exhausted the search space and the fault is classified as redundant.

8.1, Implementation Steps 1 and 2 of our implementation correspond to step The part of the prototype that generates a test for a given 1 of the test generation procedure outlined in Section VI. fault or classifies it as redundant executes the following Step 3 in the implementation corresponds to step 2 of the steps: test generation procedure. Steps 4 and 5 describe a spe-

and 0(1) to signals at the fault si;e in the fault-free procedure. and faulty parts, respectively, for an s-a-O(1) fault. 2. Construct the implication graph and the set of ter- 8.2. Eficient Transitive Closure Computation nary relations as discussed in Section IV. 3. Compute the transitive closure of the implication In the test generation algorithm, since the transitive graph and derive global signal dependencies. If a closure is repeatedly computed, there is a need for an ef- contradiction occurs, classify the fault as redun- ficient method for its computation. The worst-case com- dant. Otherwise, the derived global signal depen- plexity of conventional transitive closure algorithms [22] dencies may reduce some of the ternary relations is 0(n2)space and 0(n3)time where n is the number of into binary relations. Include these relations in the vertices in the graph. We develop a fast algorithm for implication graph and update the transitive closure. transitive closure computation by exploiting the special 4. Determine a literal expansion order for the branch- structure of implication graphs. In our application, impli- and-bound process: several expansion orders are cation graphs are sparse and they have the duality prop- possible. We consider a topological ordering of the erty [17]. Sparsity means that the graph contains a very literals in the implication graph. In such an order- small number of edges compared to a fully connected ing, we make a decision on a literal before any of graph. We, therefore, use edge-based algorithms. Duality its children in the implication graph are considered means that if the graph contains an arc from x to y then it as decision literals. Furthermore, the children are will also contain an arc from 7 to X. As a result, if a set arranged in an order such that the child that appears of vertices belong to a strongly connected component [22], in more terms of the ternary relations is considered then the set of complemented nodes will also belong to before the others. another strongly connected component. A strongly con- Pick the next decision literal in the order determined nected component is a set of vertices that are reachable in step 4 and assign a value to the literal: we aban- from each other. don the search after a pre-assigned backtrack limit Our algorithm has 0 (n) space complexity and appears is reached. We divide the backtrack limit among two to run (empirical observation), even without any paral- search policies. In the first policy, we assign the lelization, in linear expected time complexity. We take value 1 to a literal and if the test generation algo- advantage of sparsity and duality in computing the tran- rithm backtracks to this literal, we then assign the sitive closure of the implication graph. The key idea in value 0. In the second policy, we first assign the our implementation is that we never explicitly compute value 0 to the literal and if the test generation al- the transitive closure but derive the necessary logical con- gorithm backtracks to this literal, we then assign the clusions (contradictions, identifications, fixations, and value 1. The two schemes will result in the explo- exclusions) by finding the strongly connected components ration of disjoint subtrees in the entire search space. and condensation of the implication graph. This is a di- Determine all literals in the implication graph that rected acyclic graph that contains exactly one vertex for are implied by the decision literal. If the signal as- every strongly-connected component in the implication signments thus far satisfy the Boolean equation, stop graph. In the condensation graph, there is an arc from with a test for the fault. Otherwise, compute the vertex x to vertex y if there is an arc from any vertex of I

1024 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 12, NO. 7, JULY 1993 the strongly connected component represented by x to any cuit preprocessing, learning, or detailed structural analy- vertex of the strongly connected component represented sis (for example, identification of dominators or identifi- by y. The procedure for deriving logical conclusions is as cation of fan-out stem dominance relationships [23])was follows: performed. Results on the ISCAS '85 and '89 benchmark circuits obtained on a SUN Sparc 2 workstation are sum- 1. Compute strongly connected components. All con- marized in Tables I1 and 111, respectively. We assume scan tradictions and identifications are determined from design for the ISCAS '89 benchmarks. Therefore, we re- the strongly connected components. quire test generation only for the combinational logic. All 2. Construct the condensation graph [22]. global dependencies were derived from the transitive clo- 3. Determine the transitive closure of the condensation sure. Only faults that remain undetected after random test graph. All fixations and exclusions are derived from the transitive closure. generation were processed by the transitive closure based test generation method. Using the duality in the implication graph we modify In both tables, RTG Det Flts is the number of faults the basic algorithm using depth-first search for computing detected by the random test generation phase and RTG strongly connected components [22]. In our procedure, a CPU sec is the time spent in random test generation. For strongly connected component and its dual are simulta- most circuits, we generate random vectors until two suc- neously identified. Due to this modification, our algo- cessive fault simulation runs (64 vectors) do not detect rithm runs almost twice as fast as an implementation of any additional fault. However, for circuits marked with 'f the basic algorithm in which the dual is separately iden- or $, we continued the random phase until five consecu- tified. tive fault simulation runs (320 vectors) did not detect any To determine fixations, we focus on the arcs (x, X) or additional fault. The limit was raised since these circuits (i,x) in the transitive closure of the condensation graph. are an order of magnitude bigger than the rest. In our implementation, we do not compute the entire tran- Under the column Transitive Closure Algorithm, Der sitive closure of the condensation graph since we are only Flts is the number of faults detected by the proposed de- interested in determining whether or not a path exists from terministic test generation method and Red Flts is the a literal to its complement. Since the condensation graph number of faults that were proved redundant. Ab Flts is also exhibits duality, its transitive closure has either the the number of faults for which the program will require arc (x, X) or (X,x) but not both. We can precisely deter- more backtracks than prescribed by the backtrack limit. mine which one of these arcs is not present in the transi- Our method does not abort on any fault in the ISCAS '85 tive closure, as follows: We compute the topological or- and '89 benchmark circuits. The backtrack limit was set dering of the vertices in the condensation graph. If vertex to 20 (10 backtracks per policy used in step 5, Section x appears before X in the topological order, the arc (X, x) 8.1) for all circuits except those marked with $. For these does not exist in the transitive closure of the condensation circuits, the backtrack limit was raised to 200 (100 back- graph. Similarly, if vertex X appears before x in the to- tracks per policy used in step 5) since they are an order pological order, the arc (x, X) does not exist in the tran- of magnitude bigger than the other circuits. Backtracks is sitive closure of the condensation graph. We determine if the total number of backtracks during the processing of there exists a path from a literal to its complement by con- all faults remaining after random test generation. CPU sec ducting a depth-first search from the literal. Conventional is the total processing time (excluding fault simulation transitive closure algorithms may require n depth-first time) of the transitive closure based test generation phase searches to determine all fixations, where n is the number for all faults remaining after the random test generation of vertices in the condensation graph. However, due to phase. The fault simulation time during the deterministic duality in the condensation graph, we require only n/2 test generation phase is indicated in column Fsim sec. depth-first searches and we can determine all fixations al- All vectors were verified via fault simulation. The fault most twice as fast as the conventional transitive closure coverage obtained is indicated in column Flt Cov %. The algorithm. fault coverage given in Tables I1 and I11 assumes that only aborted faults were not covered by the generated vectors. 8.3. Results Since our method does not abort on any fault in the bench- The TRANsystem also includes a random vector gen- mark circuits, we obtain full coverage for all circuits. The erator and a fault simulator. The first phase of the system total number of test vectors (random plus deterministic randomly generates vectors for fault simulation. We use tests) is shown in column No. of Vec. No effort was made a parallel pattern single fault simulator. All vectors that to reduce the number of test vectors. do not improve fault coverage are dropped. The random Number of backtracks is a key parameter that deter- phase is followed by deterministic test generation based mines the performance of the test generator. As shown in on transitive closure computations. Fault simulation is Tables I1 and 111, many redundant faults were identified performed after every test vector to eliminate other de- without any backtracks. These redundancies were identi- tected faults. fied even before the branch and bound phase of the algo- The present test generation system does not determine rithm begins (Fig. 15). These results can be further en- or use exclusion dependencies (Section V). Also, no cir- hanced by including the exclusion dependency presented I

1025 CHAKRADHAR ef al.: A TRANSITIVE CLOSURE ALGORITHM

TABLE I1 EXPERIMENTALRESULTS ON ISCAS 85 CIRCUITS

RTG Transitive Closure Algorithm Flt No. Circuit Total Det CPU Det Red Ab Back- CPU Fsim cov of Name Flts Flts sec Flts Flts Flts tracks sec sec % Vec. c432 524 5 19 0.6 1 4 0 0 0.2 0.0 100 74 c499 758 749 1.3 1 8 0 0 0.5 0.0 I00 70 c880 942 913 1 .8 29 0 0 0 1.1 1.1 100 104 c 1355 1574 1537 3.3 29 8 0 0 3.3 0.1 1 00 106 c1908 1879 1837 5.3 35 7 0 0 7.3 0.4 I00 I89 c2670 2595 2160 10.5 320 115 0 418 82.4 2.3 100 185 c3540 3428 3263 11.5 34 131 0 0 12.4 I .0 I00 264 c5315t 5350 5285 27.8 6 59 0 11 4.3 0.2 100 197 c6288t 7744 7710 37.3 0 34 0 0 0.7 0.0 I00 52 c7552t 7548 7023 48. I 394 131 0 744 250.3 9.6 I00 352

TABLE 111 EXPERIMENTALRESULTS ON ISCAS 89 CIRCUITS

RTG Transitive Closure Algorithm Flt No. Circuit Total Det CPU Det Red Ab Back- CPU Fsim cov of Name Flts Flts sec Flts Flts Flts tracks sec sec % Vec

s27 32 32 0.0 0 0 0 0 0.0 0.0 100 15 s208 215 204 0.2 11 0 0 0 0.1 0.0 100 47 s298 308 308 0.2 0 0 0 0 0.0 0.0 100 55 s344 342 341 0.3 1 0 0 0 0.0 0.0 100 36 s349 350 347 0.3 I 2 0 0 0.0 0.0 100 36 s382 399 398 0.3 1 0 0 0 0.0 0.0 100 54 s386 384 357 0.6 27 0 0 0 0.2 0. I 100 100 s400 424 417 0.3 1 6 0 0 0.0 0.0 100 52 s420 430 392 0.6 38 0 0 0 0.9 0.1 100 85 s444 474 460 0.4 0 14 0 0 0.0 0.0 100 49 s510 564 564 0.5 0 0 0 0 0.0 0.0 100 76 s526 555 527 0.5 27 1 0 0 0.4 0.1 100 116 s64 1 467 445 0.8 22 0 0 0 1.2 0.1 100 101 s713 58 I 52 1 1.1 22 38 0 0 I .8 0.2 100 102 s820 850 773 1.6 77 0 0 0 0.7 0.2 100 196 s832 870 776 1.6 80 14 0 0 I .0 0.2 100 197 ~838 857 714 1.7 143 0 0 0 7.6 0.7 100 152 s953 1079 937 1.9 142 0 0 0 I .4 0.4 100 132 SI 196 1242 1127 2.4 115 0 0 0 5.6 0.7 100 240 s1238 1355 1157 2.7 129 69 0 18 13.7 1 .0 100 255 s1423 1515 1470 4.4 31 14 0 0 3.8 0.3 100 130 s1488 1486 1470 2.5 16 0 0 0 0.7 0.2 100 214 s1494 1506 1478 2.7 16 12 0 0 0.8 0.2 I00 213 s5378f 4603 4434 30.3 129 40 0 0 37.0 5.7 100 432 s9234f 6927 5663 113.4 812 452 0 4578 632.0 58.3 100 666 s3207f 9815 8488 188.2 1I76 151 0 445 495.6 122.7 100 744 s 1%SO$ 11725 10581 215.2 755 389 0 0 823.4 138.9 100 722 s35932f 39094 35110 1586.4 0 3984 0 0 30.6 0.0 100 79 s38417t 31180 28467 1505.6 2548 I65 0 8 2100.2 1472.4 100 1601 s38584f 36303 34073 1364.8 724 1506 0 243 646.0 473.0 100 1240

in Section V which is not implemented in the present TABLE IV work. CHARACTERISTICSOF PRODUCTION VLSI CIRCUITS Circuit Gates Inputs Outputs Tri-state 1/0 Buffers

IX. TEST GENERATIONRESULTS FOR PRODUCTION cktl 4580 551 654 0 80 VLSI CIRCUITS ckt2 47434 2131 2304 9 10 ckt3 50716 3442 3557 17 10 8 11 The TRANsystem has been used to generate test vectors ckt4 124494 2147 2328 for production VLSI circuits. These circuits were de- signed using the full-scan design methodology. The char- circuit. The number of inputs and outputs of the combi- acteristics of four example cases are shown in Table IV. national logic are shown under columns Inputs and Out- The column Gates shows the number of logic gates in the puts, respectively. I

1026 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 12, NO. 7. JULY 1993

c- c- TRI-STATE BUFFER UO-BUFFER Fig. 25. Logic diagrams of tri-state and 1/0 buffer

Fig. 26. Truth table of tri-state buffer.

TABLE V TESTGENERATION RESULTS FOR PRODUCTIONVLSI CIRCUITS

RTG Transitive Closure Algorithm Flt No. Circuit Total Det CPU Det Red Ab Back- CPU Fsim Cov Of Name Flts Flts sec Flts Flts Flts tracks sec sec % Vec

ckt I 6570 4442 23.1 I649 479 0 14 576.9 331.8 100 756 ckt2 55610 45343 2858.5 7305 2962 0 1613 19610.4 32551.1 100 5063 ckt3 63633 54980 1152.5 2272 6381 0 1052 6508.6 11014.5 100 2835 ckt4 109781 80541 11891.8 9643 19597 0 3778 75458.0 57794.3 100 5526

Many real circuits contain tri-state buffers and I/O was used. TRANaborted on very few faults (none in cktl , buffers. The logic diagrams for these primitives are shown and less than 8 faults each for ckt2, ckt3, and ckt4). In in Fig. 25. The tri-state buffer has two inputs, a and c, the second pass, only the faults aborted in the first pass and one output signal b. Its truth table is shown in Fig. were targeted. The backtrack limit was raised to 100 and 26. Signals a and b assume identical values whenever the TRANidentified all previously aborted faults as redun- control signal c has the value 1. If c = 0, then in the test dant. The CPU seconds shown under Transitive Closure generation model the value on signal a is considered ir- Algorithm in Table V include the run times for both relevant (indicated as X) because it does not affect the passes. TRANwas able to achieve 100% coverage for all output signal b. Also, signal b will be in the high imped- circuits. The fault simulator used in TRANduring deter- ance state (indicated as Z). The 1/0 buffer consists of a ministic test generation is a single-vector single-fault sim- tri-state buffer and a non-inverting buffer. It has two input ulator. This accounts for the large fault simulation time signals a and c, and two output signals b and d. The two for some circuits in the transitive closure phase. output signals always have identical logic values. When- ever signal c = 1, the output signals assume the value of X. CONCLUSION signal a. However, when input c = 0, the value on signal a is considered irrelevant and signal b assumes the high- The graph theoretic concept of transitive closure as ap- impedance state. Thus, signal b can be driven to any logic plied to test generation has several advantages. First, the value applied by an external source and signal d will as- transitive closure is a single tool that replaces the entire sume the same value as that of b. TRANcontains special bag of tricks used to speed up branch-and-bound search. energy function models for these primitives. The number Second, our technique determines all logical conse- of tri-state and 1/0 buffers is shown under columns Tri- quences based on painvise signal relationships for a par- state and I/O buffers, respectively. The largest circuit, tial set of signal assignments and provides a good frame- ckt4, is a half-million-transistor chip. work for reasoning about signal relationships in the Table V shows the test generation results. The column circuit. Third, the parallelization of transitive closure descriptions are the same as in Tables I1 and 111. Faults computation, though not attempted in the present work, on the control signals of tri-state or 1/0 buffers are not is easily possible [ 151. Therefore, it can be effectively modeled. This is because the detection of control line fault used to identify necessary assignments in parallel test will require two vectors and, hence, is beyond the capa- generation methods. bility of a combinational circuit test generator. After the While we present a new algorithm completely based on random vector phase, the test generation was performed transitive closure, the technique of transitive closure can in two passes. In the first pass, a backtrack limit of 10 also be included in any existing test generation algorithm. I

1027 CHAKRADHAR er al.: A TRANSITIVE CLOSURE ALGORITHM

ourtransitive closure can also be included in any existing current decomposition and factorization of Boolean expressions,” Tech. Rep. TR-91-2R, VLSI Design Lab., Dep. Elect. Eng., McGill test generation algorithm. Our transitive closure frame- University, 1991, work can be effectively used to solve other combinatorial 1201 F. Brglez and H. Fujiwara, “A neutral netlist of 10 combinatorial optimization problems of digital circuits like logic min- benchmark circuits and a target translator in FORTRAN,” in Proc. IEEE In/. Symp. Circuits and Syst., pp. 663-698, June 1985. imization, test generation [24i9 timing OP- ._1211 F. Brglez. D. Bryan, and K. Kozminski, “Combinational profiles of timization. These oDtimization Droblems can be formu- sequential benchmark circuits,” in Proc. IEEE Int. Symp. Circuits

using the transitive closure framework. 1231 M. H. Schulz, E. Trischler, and T. M. Sarfert, “SOCRATES: A highly efficient automatic test pattern generation system,” IEEE Truns. Computer-Aided Design, vol. 7, pp. 126-136, Jan. 1988. ACKNOWLEDGMENT 1241 S. T. Chakradhar, M. A. Iyer, and V. D. Agrawal, “Energy min- imization based delay testing,” in Proc. European Design Automa- The authors thank Mike Bushnell for useful discussions conf., pp. 280-284, Mar, ]992. and for suggesting the example in Fig. 24.

REFERENCES

[I] H. Fujiwara and T. Shimono, “On the acceleration of test generation algorithms,” IEEE Trans. Computers, vol. C-32, pp. 1137-1 144, December 1983. Srimat T. Chakradhar (S’88-M’90) received the [2] T. Kirkland and M. R. Mercer, “A topological search algorithm for B.E. degree in electronics and control engineering ATPG,” in Proc. 24th ACM/IEEE Design Aulomation Conf., pp. from the University of Gujarat, India, and M.S. 502-508, June 1987. and Ph.D. degrees in computer science from Rut- 131 M. H. Schulz and E. Auth, “Improved deterministic test pattern gen- gers University, New Brunswick, NJ, in 1984, eration with applications to redundancy identification,” IEEE Trans. 1986, and 1990, respectively Computer-Aided Design, vol. 8, pp. 811-816, July 1989. He is with the Computers and Communications (41 J. Giraldi and M. L. Bushnell, “EST: The new frontier in automatic Research Laboratory of NEC at Princeton, NJ. test-pattern generation,” in Proc. 271h ACMIIEEE Design Automa- During 1989, he worked as a consultant in the tion Conf., pp. 667-672, June 1990. Computing Science Research Center at the AT&T 151 J. Rajski and H. Cox, “A method to calculate necessary assignments Bell Laboratories, Murray Hill, NJ. His current in algorithmic test pattern generation,” in Proc. IEEE Int. Test Conf., research interests include computer-aided design, digital testing, parallel pp. 25-34. Sept. 1990. processing, , and combinatorial optimization. He has co- [6] S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell, NeuralModels authored a book, Neural Network Models and Algorithms for Digital Test- und Algorithms for Digital Testing. Boston: Kluwer Academic, ing (Kluwer Academic, 1991). He was the Program Chair of the Sixth In- 1991. ternational Conference on VLSI Design, 1993, and will be the General 171 S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell, “Automatic Chair of the Seventh International Conference of VLSI Design, 1994. test generation using quadratic 0-1 programming,” in Proc. 27th Dr. Chakradhar is a member of the ACM and the VLSI Society of India. ACMIIEEE Design Automation Conf., pp. 654-659, June 1990. [8] S. T. Chakradhar and V. D. Agrawal, “A transitive closure based algorithm for test generation,” in Proc. 28th ACM/IEEE Design Au- tomation Conf., pp. 353-358, June 1991. 191 S. T. Chakradhar, M. L. Bushnell. and V. D. Agrawal, “Toward massively parallel automatic test generation,” IEEE Trans. Com- puter-Aided Design, vol. 9, pp. 981-994, Sept. 1990. [IO] S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell, “Neural net Vishwani D. Agrawal (S’68-M’7O-SM’SO-F’86) and boolean satisfiability models of logic circuits,” IEEE Design and received the B.Sc. degree from the University of Tesr of Computers, vol. 7, pp. 54-57, Oct. 1990. Allahabad, Allahabad, India, the B.E. degree from [ 1 I] T. Larrabee, “Test generation using Boolean satisfiability,” IEEE the University of Roorkee, Roorkee, India, the Trans. Computer-Aided Design, vol. I I, pp. 4-15, Jan. 1992. M.E. degree from the Indian Institute of Science, [I21 T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Bangalore, India, and the Ph.D. degree from the Algorithms. McGraw-Hill, New York, 1990. University of Illinois at Urbana-Champaign, in 1131 S. R. Pawagi, P. S. Gopalakrishnan, and I. V. Raniakrishnan, “Com- 1960, 1964, 1966, and 1971, respectively. puting dominators in parallel,” Inform. Process. Let/., vol. 24, no. He is a Distinguished Member of Technical 4. pp. 217-221, 1987. Staff at the AT&T Bell Laboratories in Murray [I41 P. Hansen. B. Jaumard, and M. Minoux, “A linear expected-time Hill, NJ. He is also a Visiting Professor in the algorithm for deriving all logical conclusions implied by a set of Department of Electrical and Computer Engineering at Rutgers University, Boolean inequalities,” Muth. Progrumming, vol. 34, pp. 223-23 1, New Brunswick, NJ. Mar. 1986. He has over twenty years of experience in the field of VLSI computer- 1151 B. F. Wang and G. H. Chen, “Constant time algorithms for the tran- aided design and testing. His research at AT&T includes pioneering work sitive closure and some related graph problems on processor arrays on testability analysis, statistical test methods, simulation-based test gen- with reconfigurable bus systems,” IEEE Trans. Parallel and Dist. eration, and neural network applications to testing. S.vst.. vol. 1, pp. 500-507, Oct. 1990. He is the founding Editor-in-Chief of the Journal of Electronic Testing: 1161 S. T. Chakradhar, “Neural network models and optimization meth- Theory and Applications (JETTA) and a former Editor-in-Chief (1985-87) ods for digital testing,” Ph.D. dissertation, Dep. Comp. Sci., Rut- of the IEEE Design & Test of Computers magazine. He has served on nu- gers Univ., New Brunswick. NJ, 1990. merous conference program committees and is Co-founder and Steering 1171 B. Aspvall, M. F. Plass, and R. E. Tarjan, “A linear-time algorithm Committee Chairman of the annual International Conferences on VLSI De- for testing the truth of certain quantified Boolean formulas,” Inform. sign held in India. He was General Co-chair of the fourth symposium in Process. Lett., vol. 3, pp. 121-123. Mar. 1979. that series. In 1989, he was elected to serve a two-year term on the board 1181 A. Billionnet and B. Jaumard, “A decomposition method for mini- of governors of the IEEE Computer Society. He has published over 150 mizing quadratic pseudo Boolean function,” Op. Res. Lett., vol. 8, papers and has coauthored three books, Test Generation for VLSI Chips pp. 161-163, June 1989. (IEEE Computer Society Press, 1988). Unified Methods for VLSI Simula- 1191 J. Rajski and J. Vasudevamurthy, ”The testability preserving con- /ion and Test Generation (Kluwer Academic, 1989) and Neural Models and I

1028 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 12, NO. I, JULY 1993

Algorithmsfor Digiral Testing (Kluwer Academic, 1991). He holds or has Steven G. Rothweiler received the B.S. degree applied for six U.S. patents in the area of testing. He has given invited from Rutgers University, NJ, in 1985, both in lecturers on VLSI testing and has served as examiner and co-adviser for electrical engineering. His interests are in VLSI Ph.D. dissertations at universities in the United States and abroad. CAD, programming languages, particularly lan- Dr. Agrawal is a Fellow of the IEEE and the IETE (India), and a member guages for high-level and RTL synthesis, and ap- of the ACM and the VLSI Society of India (VSI). His awards include the plications programming. Other interests include Best Applications Paper Award (1979) from the IEEE Antennas and Prop- logic synthesis for performance and testability, agation Society, Best Paper Award (1982) from the International Test Con- performance optimization, and sequential testing. ference, Best Presentation Award (1985) and Best Paper Award (1988) from Mr. Rothweiler is with the Computers and the International Conference on Computer Design, Best Paper Award (1987) r! Communications Research Laboratory of NEC at from the AT&T Conference on Electronic Testing, Honorable Mention I' Princeton, NJ. He is involved in the implemen- Award (1992) from the 5th International Conference on VLSI Design, Out- tation of a number of successful VLSI CAD programs. He has also worked standing Contribution Award (1988) and Meritorious Service Award (1989) at AT&T Bell Laboratories, Murray Hill, NJ, during 1985-90 as a con- from the IEEE Computer Society. He is listed in the 46th edition of Mur- sultant on various synthesis projects, both high-level and RTL. In 1990, pis Who's Who in Arnerim. he spent four months working for Stardent Computer, Inc., Boston, MA.