NEPP Processor Enclave: Post COVID Update Edward J. Wyrwas Steve Guertin [email protected] [email protected] 301-286-5213 818-321-5337 SSAI, Inc, work performed for NASA JPL Caltech NASA GSFC, NEPP This work was sponsored by: NASA Electronic Parts and Packaging (NEPP) Program To be presented at the NASA Electronic Part and Packaging (NEPP) Program’s Electronic Technology Workshop 2021 1 by Edward Wyrwas (SSAI) and Steve Guertin (JPL) NEPP Team Members Ed Wyrwas [email protected] Carl Szabo [email protected] Scott Stansberry [email protected] Alyson Topper [email protected] Steve Guertin* [email protected] SSAI, Inc work performed for NASA GSFC NEPP * JPL Caltech To be presented at the NASA Electronic Part and Packaging (NEPP) Program’s Electronic Technology Workshop 2021 2 by Edward Wyrwas (SSAI) and Steve Guertin (JPL) Acronyms • Advanced Micro Devices (AMD) • Machine Learning (ML) • Application Specific Integrated Circuit (ASIC) • Mean time to failure (MTTF) • Artificial Intelligence (AI) • Multi-Bit Upset (MBU) • Advanced RISC Machine (ARM) • National Aeronautic and Space Administration (NASA) • Automated Test Equipment (ATE) • NASA Electronic Parts and Packaging (NEPP) • Board Level Adapter Plate (BLAP) • Numerical Python (NumPy) • Body of Knowledge (BOK) • Open Compute Language (OpenCL) • Complementary metal oxide semiconductor (CMOS) • Open Graphics Language (OpenGL) • Commercial off-the-shelf (COTS) • Operating System (OS) • Compute Unified Device Architecture (CUDA) • Printed Circuit Board Assembly (PCBA) • Dual Data Rate (DDR) • Procurement Request (PR) • Device under test (DUT) • RApid Machine-lEarned Triage (RAMjET) • Electrical, Electronic and Electromechanical (EEE) • Single-Bit Upset (SBU) • Field programmable gate array (FPGA) • Scientific Python (SciPy) • Fin Field-effect transistor (FinFET) • Single-Event Effect (SEE) • General Purpose Input / Output (GPIO) • Single-Event Functional Interrupt (SEFI) • Graphics Processing Unit (GPU) • Single-Event Upset (SEU) • High Performance Computing (HPC) • Single-Event Upset Cross-Section (σSEU) • Input / Output (IO) • Simultaneous Localization And Mapping (SLAM) • Intellectual Property (IP) • System on Chip (SOC) • Linear energy transfer (LET) • System on Module (SOM) • Key Process Indicators (KPI) • Transiting Exoplanet Survey Satellite (TESS) • LINear equations software PACKage (LinPack) • Technical Operation Report (TOR) To be presented at the NASA Electronic Part and Packaging (NEPP) Program’s Electronic Technology Workshop 2021 3 by Edward Wyrwas (SSAI) and Steve Guertin (JPL) FY20-22 Hardware Roadmap • FPGA Co-Processor Devices • Neural Network Devices – Xilinx Zynq – Google TPU (rev 1, rev 3) – Xilinx MPSOC – Intel (Movidius/Nervana/Loihi) – Xilinx Versal – RockChip Rk1808, Rk3399Pro • Low Power Microprocessors – Nepes NM500 – AMD Ryzen 3 1200, 2200G – ARM Ethos-U55, U65 (NXP i.MX 8M Plus kit) – Intel Core i7 6500U (Purism Librem) – Sipeed Maix – Intel Core i7 10710U Comet Lake – Amlogic S905X3 (ODROID-C4 kit) (Purism Librem, expected Q3) – Gyrfalcon Lightspeeur AI • SOCs with GPUs – Xilinx Alveo – AMD Ryzen Low Power – Texas Instruments Sitara AM57x R1102G, v1202B, R1305G, R1606 – Kneron KL520, KL720 – NVIDIA Jetson TX2, TX2i, Nano – SimpleMachines – NVIDIA Xavier AGX, NX, AGXi (expected Q3) • Graphics Processing Units (discrete) • Low Power SOCs – AMD Radeon e9173 – NXP i.MX 8 QuadMax, Pro – NVIDIA GTX 1050 – Edgeless EAI Series – Allwinner F1C200s Red font devices were prepared for SEE – Samsung Exynos testing during COVID in FY20 and FY21. – Qualcomm Snapdragon Green font indicates procurement in FY21. – RISC-V (several candidates tracked) Blue font indicates procurement in FY22. – Raspberry Pis (*Guertin JPL) To be presented at the NASA Electronic Part and Packaging (NEPP) Program’s Electronic Technology Workshop 2021 4 by Edward Wyrwas (SSAI) and Steve Guertin (JPL) FY22: Processor Enclave Testing Description: FY22 Plans: – This is a task over all device topologies and processes – Finish development of universal test suite which includes math – The intent is to determine inherent radiation tolerance and (FFT, LinPack, Pi), output buffer (colors), memory hierarchy sensitivities and neural networks – Identify challenges for future radiation hardening efforts – Investigate new failure modes and effects – Probable test structures for SEE and TID are COTS from: – Testing includes total dose, single event and reliability. – NVIDIA (<16nm) Test vehicles will include CPU, SOC and GPU devices from NVIDIA – AMD (<14nm) and other vendors as available – Intel (~10nm) – Compare to previous generations – Samsung (<14nm) – Investigate failure modes/compensation for increased power – Others (<45nm) consumption – Tests: characterization pre-rad, during and post-rad Schedule: Deliverables: – Test reports and quarterly reports Microelectronics FY20-21FY 21 – Expected submissions for publications T&E S O N D J F M A M J J A – Cold plate and board level adapters On-going discussions for test samples DesignGPU Test& Fabrication Development of Cold Plate Parts NASA and Non-NASA SEESEE and Testing TID testing Analysis and Comparison Organizations/Procurements: – Source procurements: – Proton (MGH, Provision) Lead Center/PI: GSFC/SSAI/Wyrwas – Heavy Ions (LBNL, TAMU) Co-Is: Steve Guertin + Scott Stansberry – TID (GSFC) – Laser (NRL) To be presented at the NASA Electronic Part and Packaging (NEPP) Program’s Electronic Technology Workshop 2021 5 by Edward Wyrwas (SSAI) and Steve Guertin (JPL) FY22: AI & Machine Learning Devices Description: FY22 Plans: – This is a task over all device topologies and processes – Deploy AI and Machine Learning test suite developed in FY20, – The intent is to determine inherent radiation tolerance and making refinements where necessary sensitivities and provide a baseline of current market offerings – Identify challenges for future radiation hardening efforts – Probable test structures for SEE: – Investigate new failure modes and effects – USB and other peripheral bus devices – Testing includes total dose, single event and reliability. – 45nm down to 7nm Test vehicles will include ‘simple interface’ devices with USB or similar connectivity. – Tests: – Identifies viable suppliers and provide insight into product – Electrical characterization pre-rad, during and post-rad obsolescence roadmaps – Functional testing with AI/ML accuracy and other KPI – Investigate failure modes and mitigation strategies for increased power consumption and latch up events Schedule: Deliverables: – Test reports and quarterly reports Microelectronics FY20-21FY 21 – Expected submissions for publications T&E S O N D J F M A M J J A – Additional cold plate and board level adapters On-going discussions for test samples GPUScience Test community Development collaborations NASA and Non-NASA SEESEE and Testing TID testing Analysis and Comparison Organizations/Procurements: – Source procurements: – Proton (MGH, Provision) Lead Center/PI: GSFC/SSAI/Wyrwas – Heavy Ions (LBNL, TAMU) Co-Is: Alyson Topper + Scott Stansberry – TID (GSFC) – Laser (NRL) To be presented at the NASA Electronic Part and Packaging (NEPP) Program’s Electronic Technology Workshop 2021 6 by Edward Wyrwas (SSAI) and Steve Guertin (JPL) Evaluation Timeline *Radiation Testing (RT) *Cold Block (CB) Adapter Development *Test Feasibility Evaluation (FE) Microprocessors *Continuation or RT – ≤14nm++ Intel (Intel) ………………………………… RT *Termination or – ≤10nm AMD (Global) ………………………………… Microprocessors with embedded GPUs RT – 14nm++ Intel (Intel) ………………………………… RT – ≤ 10nm AMD (Global) ………………………………… – 10nm Qualcomm 835 (Samsung) ………………… GPUs CB CB RT – 14/16nm NVIDIA GTX 1050/1080 (TSMC) ………… – 14nm AMD Radeon RX580/Vega (Global) ……….. FE – 14nm Intel Discrete GPU (Intel) …………………… – 14nm Low Power, AMD Radeon e917x (Global) … – 12nm NVIDIA RTX 2080 (TSMC) …………………… System on Chip RT – 20nm NVIDIA Tegra X1 (TSMC) …………………….. RT – 16nm NVIDIA Tegra X2 (TSMC) …………………….. FE CB RT – 12nm NVIDIA Tegra Xavier (TSMC) ………………… – ≤ 10nm Qualcomm Snapdragon (Samsung) ……….. FE CB Neural Network Devices RT – Google TPU……………………..…………………….. FE – Many, many others……………..…………………….. FE FY19 FY20 FY21+ Math Tests Math & AI To be presented at the NASA Electronic Part and Packaging (NEPP) Program’s Electronic Technology Workshop 2021 7 by Edward Wyrwas (SSAI) and Steve Guertin (JPL) NEPP Software - Recap • Software stack from vendor is comprised of Linux, PCBA carrier board drivers and hardware initializers, and some health prognostic tools Vendor Software Stack • Software stack from NASA NEPP is comprised of – 2x Mathematics tests (CUDA, OpenCL) – 1x Graphics buffer test (OpenGL) – 1x Linear Algebra test (Linpack) – 4x Artificial Intelligence tests NASA NEPP (Python including SciPy and NumPy, Keras Software Stack and TensorFlow 2.0) • Android OS applications for Math and Graphics are in development too. The TensorFlow Lite one is complete. To be presented at the NASA Electronic Part and Packaging (NEPP) Program’s Electronic Technology Workshop 2021 8 by Edward Wyrwas (SSAI) and Steve Guertin (JPL) Microsoft Teams Channel - Recap • “NEPP – Processor Enclave” – NASA users can join with the team code: 1a2iu5y • Contains many wiki and files which cover: – Set up, wiring and programming instructions for various devices and single board computers – Troubleshooting • We discuss SOTA device landscapes in the chat – New COTS devices and development kits – New architectures and technology demos – Press