Copper Interconnect Technology Tapan Gupta

Copper Interconnect Technology

123 Tapan Gupta Radiation Monitoring Devices, Inc. Watertown, MA USA [email protected]

ISBN 978-1-4419-0075-3 ISBN 978-1-4419-0076-0 (eBook) DOI 10.1007/978-1-4419-0076-0 Springer Dordrecht Heidelberg London New York

Library of Congress Control Number: 2009928021

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Cover illustration: Figures on front cover reproduced with permission from IBM

Printed on acid-free paper

Springer is part of Springer Science+Business Media (www.springer.com) Dedicated to the memory of my father, Dr. Gopeswar Gupta, and mother, Dr. Kanak Lata Gupta & To The Godfather of Modern Electronics, Dr. John F. Bardeen Preface

The frontiers of knowledge are advancing at an ever-increasing rate. Today’s discov- eries will tomorrow be part of the toolbox of every researcher. By analogy, the pro- cess of advancing the line of settlements, and cultivating and civilizing new territory, takes place in stages, and the industry, which has brought a revolu- tion in modern civilization, is a vivid example. The intellectual foment that marked its beginnings has changed the way we view the physical world forever. Since the creation of the in 1960 there has been a continuous reduction in the size of circuits and thus the feature size of devices. Following Moore’s famous prediction, the number of devices manufactured on a single chip has exceeded the expectation of very large-scale integrated (VLSI) circuits. As a result, new materials are being introduced to meet the challenge of 21st century IC technology. The increasing device count accompanied by a shrinking minimum feature size, which was expected to be smaller than 1 μm before 1990, has reached 0.1 μm at the beginning of the 21st century. Progress in the development of new materials is marching in tandem and with much the same speed as circuit density (number of devices per unit square area). The entire field of VLSI circuits depends upon circuit design, layout of elec- tronic circuitry, process development, and synthesis of new materials. As a result, traditional materials (e.g. copper) are sometimes renewed in a fashion necessary to accommodate them to modern technology. Mankind has known about copper and its processing for different uses since the prehistoric age. Now, at the beginning of the 21st century, the use of copper has opened a new era in the IC manufacturing industry. The 1990s were the decade in which copper as an interconnecting material came to the forefront and gained much attention from microelectronics engineers and sci- entists. The metallic conductivity and resistance to of bulk copper (Cu) are better than aluminum (Al). But as the feature size of the Cu-lines forming interconnects is scaled, the resistivity of the lines is seen to increase. At the same time, the electromigration and stress induced voids due to increased current den- sity become reliability issues. Innovative ideas like the use of a cobalt-tungsten cap layer and alloying of copper have worked well, but both come with an increased RC product line.

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The use of Cu-interconnect has introduced the additional burden of integration of the barrier layer in Cu-damascene architecture. The barrier layer affects the resis- tance of the Cu-lines too. The PVD-Cu/PVD-Ta interface is “magical” and the use of precursors in the ALD/CVD (/Chemical Vapor Deposi- tion) system has raised several questions, although the advantages of ALD in com- parison to the PVD system in producing perfect step coverage with very thin layers is clear. In the field of low-K, time-dependent dielectric breakdown (TDDB) and inter- layer dielectrics (ILDs), reliability is becoming more important. As the dimensions shrink, the stress gradients increase because the same amount of stress is confined within a reduced geometry. Moreover, these low-K materials are softer than SiO2 and susceptible to failure. There are many challenges and difficulties with copper interconnect but not with- out any gain. Most of the challenges are overcome partially by using advanced instrumentation and materials. Photolithography has come a long way from 365 nm exposure technology to 157 nm exposure technology. Use of advanced laser systems with lower radiation wavelengths, additional hardware, and enhancement techniques, have all contributed to these improvements. In 1997 IBM and Motorola introduced new approaches to Cu-interconnecting technology and in September 1997 IBM demonstrated their complementary metal oxide semiconductor (CMOS) device with six layers of copper lines. At the end of the decade, copper damascene processes were introduced and the century-old chemical mechanical polishing (CMP) procedure was renewed to integrate copper in deep sub-micron level circuitry. This book was developed from a series of lecture notes prepared for graduate stu- dents of different universities. The notes are based on the research and publications of countless scientists and engineers engaged in this field. I express my sincerest thanks and gratitude for their indirect help. Copper Interconnect Technology is the first book on the subject to treat materi- als, technology, and applications comprehensively, and is a product of my 25 years of research and teaching experience in different universities and research organiza- tions. It is written for professionals as well as graduate students, and belongs on the bookshelf of workers in several microelectronics disciplines. The chapters of the book are arranged sequentially following the sequence of the damascene process. In Chapter 1 basic properties of the materials used in cop- per interconnect are presented. Chapter 2 deals with the low- and high-K dielectric materials (dealing with the physical, chemical, and structural properties) that are of potential interest for scaled-down, high-speed devices. The diffusion of Cu in is well known, so Chapter 3 is devoted to the search for new barrier materi- als and metal complexes to minimize diffusion of Cu from Cu interconnects. Some of the promising barrier materials, their physical and chemical properties, and the interpretation of binary and ternary phase diagrams, are also discussed. Chapter 4 addresses different resist materials (DUV and EUV) and lithography techniques that are being used or are in the development stage. Pattern generation Preface ix technologies together with different etching systems applied in the modern IC indus- try are also considered. As the state of the art of modern integrated circuit technology has changed from the subtractive aluminum metallization process to via and trench filling additive Cu, the deposition technology has also evolved. Chapter 5 covers different deposition technologies that are frequently used in the modern Cu-damascene process. Chapter 6 deals with the damascene procedure and the chemical mechanical planarization (CMP) process. Cu-interconnect replaced Al-interconnect because of its higher bulk-conductivity and electromigration resistance. But as the feature size of the conducting lines is shrinking, the thin metal lines can no longer retain the bulk properties of the metal. In Chapter 7 the conductivity and electromigration properties of Cu-interconnecting lines are discussed. Chapter 8 deals with the routing design of the Cu-interconnects together with the reliability issues of the scaled Cu-lines forming interconnects.

Watertown, Massachusetts Tapan K. Gupta Acknowledgments

A book of such diversity would not have been possible without the indirect help of many research workers, engineers, and teachers. Virtually all of the information presented here is based on my lectures to graduate students of different universities. The notes were prepared from the research work of countless scientists and engi- neers engaged in this field. Their contributions are recognized to a small degree by citing some of their work in references at the end of the chapters. I also wish to acknowledge the work of the people who are not cited directly but who have con- tributed indirectly to the development of the book. My sincerest thanks go to them. The entire manuscript has been read by Dr. Rafael Reif, Provost, and for- mer Professor and Head, Electrical Engineering Department, MIT, Cambridge, Massachusetts and Dr. K.N. Tu, Professor of The Henry Samueli School of Engi- neering and Applied Science, and former Head of the Department of Materials Science and Engineering, University of California, Los Angeles, California (UCLA). The author is grateful to them for their help. The author also expresses his gratitude for the encouragement received from Professor Carl Thompson, Rickey/Nelson Professor, MIT, Cambridge, Massachusetts, Professor Krishna Saraswat, ECE Department and Professor Rein- hold Dauskardt, Materials Science, Stanford University, CA, and Professor P.S. Ho, Professor, University of Texas, Austin, TX. I am grateful to the anonymous review- ers for their comments and criticism that have helped in shaping the book. I have taken many illustrations and materials from different journals and maga- zines. I want to express my sincerest thanks to all the authors and the staff members for their permission to reproduce these in my book. Most of all I want to thank my wife Arundhati, my daughter Atreyee, and my son-in-law Jesse, for the love, understanding, patience, and impatience that made the preparation of this book possible.

Tapan K. Gupta

xi Contents

1 Introduction ...... 1 1.1 Trends and Challenges ...... 2 1.2 Physical Limits and Search for New Materials ...... 5 1.3 Challenges ...... 6 1.4 ChoiceofMaterials ...... 7 1.4.1 Why Copper (Cu) Interconnects? ...... 7 1.5 New Technologies...... 15 1.5.1 Multilayer Metal Architecture ...... 15 1.5.2 Substrate Engineering ...... 16 1.6 An Alternate Technology for Interconnects ...... 19 1.7 Materials Used in Modern Integrated Circuits ...... 21 1.7.1 Properties of Copper ...... 23 1.7.2 GrainSize...... 24 1.7.3 Melting Temperature ...... 25 1.8 Barrier Layer ...... 27 1.9 Low-KDielectricMaterials...... 28 1.10 Polymers...... 30 1.11 ...... 33 1.11.1 Silicon(Si)...... 33 1.12 Challenges and Accomplishments ...... 35 1.12.1 Challenges ...... 35 1.12.2 Accomplishments ...... 35 1.13 Technologies of the 21st Century, and the Plan to Meet the Challenges ...... 38 1.14 Ultra-ShallowJunction(USJ)...... 40 1.15 CircuitDesignandArchitectureImprovements ...... 41 1.16 Performance and Leakage in Low Standby Power (LSTP) Systems . . 42 1.17 Introduction of New Materials and Integration Processes ...... 43 1.17.1 Nano-Materials ...... 44 1.17.2 Superconductors ...... 45 1.17.3 IntegrationProcesses...... 47 1.18 Summary...... 53 References ...... 55

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2 Dielectric Materials ...... 67 2.1 Introduction ...... 67 2.2 Interlayer Dielectric (ILD) ...... 71 2.2.1 Introduction ...... 71 2.2.2 Mathematical Model ...... 74 2.2.3 Selection Criteria for an Ideal Low-K Material ...... 76 2.2.4 Search for an Ideal Low-K Material ...... 78 2.2.5 Achievement...... 83 2.2.6 Impact of Low-K ILD Materials on the Cu-Damascene Process ...... 92 2.2.7 Deposition Techniques ...... 95 2.3 High-KDielectricMaterials ...... 97 2.3.1 Introduction ...... 97 2.3.2 Impact on Scaling and Requirements ...... 98 2.3.3 Search for a Suitable High-K Dielectric Material ...... 99 2.3.4 Deposition Technology for High-K Materials ...... 102 2.3.5 Summary...... 102 References ...... 103

3 Diffusion and Barrier Layers ...... 111 3.1 Diffusion...... 111 3.1.1 Introduction ...... 111 3.1.2 Transitional Effects ...... 113 3.1.3 Mathematical Modeling of Diffusion in Cu-Interconnects . . . 114 3.1.4 Grain Boundary (GB) Diffusion ...... 118 3.1.5 Vacancy Diffusion...... 120 3.1.6 DriftDiffusion...... 121 3.1.7 Interdiffusion...... 122 3.1.8 Diffusion of Copper and Its Consequences ...... 122 3.1.9 Precipitation ...... 124 3.2 Barrier Layer for Cu-Interconnects ...... 125 3.2.1 Theory ...... 125 3.2.2 Ideal Barrier Layer ...... 126 3.2.3 Barrier Layer Architecture ...... 126 3.2.4 Interlayer Reactions ...... 128 3.2.5 Influence of the Barrier Layer Properties on the Reliability of Cu-Interconnects ...... 132 3.2.6 Low-K Dielectric-Barrier Layer ...... 135 3.2.7 ReactionRates ...... 135 3.2.8 Influence of the Barrier Layer on the Electrical Conductivity of Cu-Lines ...... 139 3.2.9 Influence of Barrier Layer Thermal Conductivity onCu-Line ...... 141 3.2.10 Classification of Barrier Layer ...... 144 Contents xv

3.2.11 Properties of Different Barrier Layer Materials ...... 145 3.2.12 Cap-Layer, Its Properties and Functions...... 148 3.3 Summary...... 150 References ...... 151

4 Pattern Generation ...... 161 4.1 Photolithography ...... 161 4.1.1 Introduction ...... 161 4.1.2 Resolution Limits of Optical Lithography ...... 164 4.1.3 Deep Ultraviolet (DUV) Lithography ...... 168 4.1.4 Reticles ...... 173 4.1.5 Enhancement Techniques for Resolution ...... 175 4.1.6 157 nm Lithography ...... 179 4.1.7 ChemicallyAmplifiedResist(CA)...... 183 4.1.8 Extreme Ultraviolet (EUV) Lithography ...... 185 4.1.9 e-Beam Lithography (EBL) ...... 189 4.1.10 Electron-BeamResist...... 192 4.1.11 e-BeamReticle...... 195 4.1.12 Step and Flash Imprint Lithography (SFIL) ...... 195 4.2 Etching and Cleaning of Damascene Structures ...... 197 4.2.1 Etching...... 197 4.2.2 Cleaning ...... 210 4.3 Summary...... 214 References ...... 216

5 Deposition Technologies of Materials for Cu-Interconnects ...... 223 5.1 Introduction ...... 223 5.2 Emerging Technologies ...... 224 5.2.1 Cu-Damascene Process ...... 224 5.2.2 Barrier Layer Requirements ...... 225 5.3 Deposition Requirements ...... 225 5.4 Thin Film Growth and Theory of Nucleation ...... 226 5.4.1 Nucleation Theory ...... 227 5.5 Instrumentation...... 230 5.5.1 Physical Vapor Deposition ...... 230 5.5.2 Sputtering ...... 231 5.5.3 Ionized Physical Vapor Deposition (IPVD) ...... 234 5.6 Chemical Vapor Deposition (CVD) ...... 236 5.6.1 Plasma Enhanced CVD (PECVD) System ...... 236 5.6.2 Metal-Organic Vapor Deposition (MOCVD) ...... 238 5.7 LowTemperatureThermalCVD(LTTCVD)System...... 240 5.8 Atomic Layer Deposition (ALD) ...... 241 5.9 Plating...... 243 5.9.1 History of Electroplating and Printed Circuit Boards(PCBs) ...... 243 xvi Contents

5.9.2 DCBathChemistry ...... 244 5.9.3 Electroplating of Copper Inside Damascene Architecture . . . 245 5.10 Process Chemistry for Superconformal Electrodeposition of Copper ...... 247 5.11 Electrochemical Mechanical Deposition (ECMD) ...... 248 5.12 Influence of the Seed Layer on Electroplating ...... 249 5.13 Electroless Deposition of Copper ...... 250 5.14 Stress in Cu-Interconnects ...... 251 5.15 Summary...... 253 References ...... 254

6 The Copper Damascene Process and Chemical Mechanical Polishing. . 267 6.1 The Copper Damascene Process ...... 267 6.1.1 Introduction ...... 267 6.1.2 Conventional Metallization Technology ...... 270 6.1.3 Cu-Damascene Metallization Technology ...... 271 6.1.4 General Objectives and Challenges...... 276 6.2 Chemical Mechanical Polishing (CMP) and Planarization ...... 278 6.2.1 Introduction ...... 278 6.2.2 Chemical Mechanical Polishing (CMP)Technology ...... 279 6.2.3 Copper Dishing Model ...... 285 6.2.4 SlurryChemistry...... 286 6.2.5 ParticleSizeInsidetheSlurry...... 287 6.2.6 RelativeVelocityofthePadandWafer ...... 289 6.2.7 PadPressure ...... 289 6.2.8 Pad-Elasticity ...... 289 6.2.9 PadConditioning ...... 289 6.2.10 Shallow Trench Isolation (STI) ...... 290 6.2.11 AbrasiveFreePolishing...... 291 6.2.12 End-PointDetection...... 291 6.2.13 DryInDryOut...... 292 6.2.14 Multi-Step Processing ...... 293 6.2.15 Post-CMP Cleaning ...... 293 6.2.16 CMPPatternDensityIssues ...... 295 6.3 Summary...... 296 References ...... 296

7 Conduction and Electromigration ...... 301 7.1 Conduction ...... 301 7.1.1 Introduction ...... 301 7.1.2 Conduction Mechanism and Restrictions ...... 303 7.1.3 Effect of Grain Boundary (GB) Resistance on the Conductivity of Cu-Interconnects ...... 311 7.1.4 Effect of Grain Size and Morphology of the Substrate ...... 311 Contents xvii

7.1.5 Morphology of the Cu-Film and Its Influence on the Conduction (Electrical) Mechanism of Cu-Interconnects . . . 312 7.1.6 Effect of Film Thickness on the Conductivity of Cu-Interconnects ...... 317 7.1.7 Diffusion Related Impacts on the Conductivity ofaCu-Line...... 318 7.1.8 Cu-Line Stress and Its Consequences ...... 319 7.1.9 Conduction of Heat Through Cu-Interconnects ...... 321 7.1.10 Thermal Cycling (Annealing) Related Phenomena ...... 322 7.2 Electromigration(EM)...... 324 7.2.1 Electromigration(EM)...... 324 7.2.2 Mechanism of Electromigration (EM) and Its Effects ...... 325 7.2.3 VoidFormation...... 329 7.2.4 Analytical Model on Stress Related EM ...... 330 7.2.5 Effect of Microstructure of the Film on Mass Migration . . . . 333 7.2.6 EffectofSoluteonElectromigration ...... 335 7.2.7 Melting Temperature of a Metal and Its Effect on Grain Growth...... 335 7.2.8 EffectofTemperatureonEM...... 336 7.2.9 CurrentDensityandItsEffectonEM ...... 336 7.3 Summary...... 336 References ...... 337

8 Routing and Reliability ...... 347 8.1 Routing ...... 347 8.1.1 Introduction ...... 347 8.1.2 Methods of Improving Interconnect Routings ...... 349 8.1.3 Interconnect Routing Design ...... 351 8.1.4 Challenges with High Density Routing ...... 359 8.1.5 Cascaded Driver ...... 361 8.1.6 TransmissionLineCoupling...... 361 8.1.7 Clocking of High-Speed System ...... 361 8.2 Reliability ...... 362 8.2.1 Introduction ...... 362 8.2.2 Reliability Issues Related to Cu-Interconnects ...... 365 8.2.3 Measurements...... 388 8.3 Summary...... 393 References ...... 394

Glossary (Copper Interconnects) ...... 405

Index ...... 415 Author Biography

Tapan K. Gupta received his Master of Science degree in Physics from the Indian Institute Technology, a PhD degree in Physics from Boston College, and was a Post- Doctoral Fellow in the Electrical Engineering and Communication Department at Lehigh University, Pennsylvania. A former Analog Devices Career Development Professor in the Electrical Engineering and Computer Science Department at Tufts University, an International Rotary Foundation Scholar, and recipient of a Teaching Excellency Award, Dr. Gupta is currently a Chief Materials Scientist performing research in the field of Nuclear Medicine in collaboration with different universities and industries at Radiation Monitoring Devices, Massachusetts. Dr. Gupta has 25 years of teaching and research experience at different universities and industries in the USA and 75 peer reviewed articles in the fields of physics, materials science, semiconductor physics, and nuclear medicine. Dr. Gupta is the author of the book Handbook of Thick and Thin Film Hybrid Microelectronics published by John Wiley and has authored a book chapter on solar cells and materials for Allied Publication, New Delhi.

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