AMD ™ with Direct Connect Architecture 4-Socket Server Comparison

AMD Opteron™ Processor-based Server Xeon MP Processor-based Server

HyperTransport™ HyperTransport™ Technology Buses Technology Buses Enable for Direct Connection of CPUs Maximum of Four Processors FSB Bandwidth Shared Direct Connection of CPUs Memory Capacity per Memory Controller Hub Across All Four Processors for up to 8 Sockets Scales w/ Number of Processors Intel Intel Intel Intel Maximum of Three Xeon Xeon Xeon Xeon PCI-X Bridges per AMD AMD Limited Memory Processor Processor Processor Processor DDR DDR Memory Opteron™ Opteron™ Bandwidth 144-bit 144-bit Controller Hub Processor Processor Shared by All Memory

I/O & Memory Share FSB AMD AMD Memory DDR DDR DDR Address 144-bit Opteron™ Opteron™ 144-bit 144-bit Buffer4 Processor Processor PCI-X Bridge2 PCI-X DDR Memory HyperTransport™ Address Memory Separate Memory and 144-bit Buffer PCI-X I/O Paths Eliminates Most Link Has Ample Ctlr Hub Bridge 1 PCI-X Bandwidth For Memory (MCH) I/O Devices DDR Address Buffer 144-bit PCI-X PCI-X PCI-X Bridge PCI-X PCI-X Bridge* Bridge Memory DDR Address 144-bit Buffer Bandwidth Bottlenecks: I/O Other Other IDE, USB, I/O IDE, FDC, Link Bandwidth < I/O Bridge Hub3 PCI I/O Bridge LPC, Etc. Hub** Key USB, Etc. Bandwidth Memory Tr I/O Traffic Fewer Chips Needed for a 4-Socket Server (Reduces Cost) IPC Traffic 9-Chip Chipset Needed for a 4-Socket Server

AMD Opteron Processor-based Server Intel Xeon MP Processor-based Server AMD64 with Direct Connect Architecture IA32 Architecture • Direct connection of CPUs for up to 8 sockets • High-performance 32-bit computing only •Provides simultaneous high-performance 32- and 64-bit computing • Businesses needing 64-bit benefits must switch to a new architecture • Increases memory performance, provides more balanced I/O throughput,

Architecture and allows for more linear symmetrical Integrated Memory Controller “”-style Memory Controller via Front Side Bus • Memory is directly connected to the CPU providing optimized memory performance • Passage through memory controller hub delays memory reads •Provides low-latency memory access and bandwidth that scales as processors •Processors compete for FSB bandwidth Access Memory echnology

T are added • 8-socket solutions require even more chips HyperTransport™ Technology Proprietary Hub I/O Buses • At up to 6.4GB/s bandwidth per link, designed to provide a high-speed • Bridge and hub devices can be overwhelmed by the I/O demands of attached connection between processors and core logic with sufficient bandwidth for peripherals echnology

T supporting new and existing interconnects Primary Bus

* AMD-8131™ HyperTransport™ PCI-X Tunnel 1 ServerWorks CMIC HE Memory Controller Hub (MCH) 3 ServerWorks CSB5 I/O Controller Hub ** AMD-8111™ HyperTransport I/O Hub 2 ServerWorks CIOB-X 64-bit PCI/PCI-X Controller Hub 4 ServerWorks REMC Memory Address Buffer