Annual Report Silicon Integration Initiative July 2019 - July 2020

12335 Hymeadow Drive Suite 450, Austin, TX 78750 1-512-342-2244 www.si2.org TABLE OF CONTENTS

From the Chair and President 1

Highlights 2-4

Staff 4

Board of Directors 5

Members 6

OpenAccess Coalition 7

Compact Model Coalition 8

OpenStandards Coalition 9

Special Interest Groups 10

2 From the Chair and President

Rahul Goyal, John Ellis, Si2 Board Chair President and CEO

It is my personal hope that you and your This year has tested all of us, and has shown families are doing well during these how profoundly interconnected our industry has unprecedented times. COVID-19 has proven to become. The Si2 staff and I share in the hope be a huge challenge for all of us. The board, that our members are and will continue to stay management, and staff have worked closely to safe and healthy. I’m grateful for the continued ensure Si2 is prepared for unlikely disruptive dedication of our board and our members, who events. However, few could have foreseen the contribute so much of their time to solving impact of this global pandemic. difficult interoperability problems.

On behalf of the Si2 Board of Directors, I want From the OpenAccess database API, reference to take this opportunity to thank you for the implementation and ecosystem, to the CMC’s ongoing support of Si2 and its programs. standard device models, your efforts provide the Over the past five years, Si2 has reduced its design community with crucial building blocks. costs and has increased funding to university In our report, you’ll see highlights including researchers. Even as consolidation continues, OpenAccess’ new DM6 data model and enhanced member engagement and interest remain scripting capabilities. CMC members adopted high in Si2’s programs. As a result of this two new capable, compact models, L-UTSOI and broad collaboration, I am happy to see the HICUM/L0, while our newly passed IEEE 2416 advancements made in OpenAccess, the Unified Power Model was demonstrated with an Compact Model Coalition, OpenStandards, and end-to-end tutorial on a RISC-V system design. the AI/ML Special Interest Group over the last Finally, our new AI/ML Special Interest Group 12 months. made great strides toward resolving key industry obstacles to AI/ML adoption in EDA. I am honored to serve as Si2 board chair for the next year. I look forward to continued collaboration with our innovative industry participants and Si2 staff.

1 Highlights

July 2019 February 2020

IEEE Approves Power Modeling Executive Joins Standard Built on Si2 UPM Si2 Board of Directors

The Si2 Unified Power Model, developed with major Pankaj Kukkal, vice president contributions from IBM and GLOBALFOUNDRIES, of Engineering at Qualcomm was approved as IEEE 2416-2019, a new Standard for Inc., was elected to the Si2 Power Modeling to Enable System Level Analysis, board of directors. In his current which complements UPF/IEEE 1801-2018 role, Pankaj oversees all EDA, Standard for Design and Verification of low-power, emulation and post-silicon energy-aware electronic systems. UPM/IEEE 2416- engineering functions for mobile, 2019 provides a rich set of power modeling compute, automotive and semantics enabling system designers to model artificial intelligence/machine Pankaj Kukkal entire systems with great flexibility. learning business units. Qualcomm July 2019 February 2020

Microsoft Joins New Version of oaScript Expands IC Si2 OpenAccess Coalition Capabilities into the Cloud and AI

Microsoft Corp. Design partitioning and multi-threaded parallel joined the execution are key features of the updated scripting OpenAccess interface to OpenAccess. oaScript Version 4.0, Coalition, continuing developed by programming experts in the a trend of IC design vertical integration among Si2 oaScript Working Group, leverages the powerful members. A recent Si2 industry survey showed enhancements available to OpenAccess in its most that more than 80 percent of end users develop recent Data Model 6 upgrade. The oaScript Working specialized, internal design tools. OpenAccess allows Group spent considerable time working through these home-grown tools to fit into the company’s implementation details for optimal use in each own, optimized design flow, integrating best-in- supported scripting language. oaPartitions allows an class EDA tools without sacrificing interoperability or application to rapidly load design instances, shapes, performance. or vias from a given partition without loading an entire design. An application can define partitions by any criteria the developer prefers—by geography, by November 2019 layer, or even alphabetically.

CMC Releases BSIM-CMG SPICE Model for Advanced IC Designs February 2020

The Compact Model Coalition released the Si2 Launches Special Interest Group latest version of BSIM-CMG FinFET, a standard For AI and ML in EDA compact SPICE model developed by researchers at the University of California, Berkeley, in conjunction Si2 launched a special interest group to focus on with 20 partners among the industry’s leading the growing needs and opportunities in artificial semiconductor companies. FinFET is the transistor intelligence and machine learning for electronic design that powers the industry along Moore’s Law to design automation. The group is identifying advanced leading-edge integrated circuits, including current solutions and technology gaps in AI and the latest 7nm chips used in every new smartphone, ML strategies for EDA digital design. AI and ML are tablet, server, and personal computer. redefining semiconductor design and improving performance and time to market. The SIG is open to

2 Highlights

all Si2 members and is chaired by Joydip Das, senior that semiconductor manufacturers insert between engineer, , and co-chaired by a silicon substrate and the top silicon layer. This Kerim Kalafala, senior technical staff member, EDA, layer improves power efficiency and reliability. When and master inventor, IBM. compared with conventional bulk-silicon CMOS devices, SOI designs are well-suited for low-cost, low-power applications, such as automotive and the Internet of Things.

April 2020 Jeff Brubaker of Joins Si2 OpenAccess Change Team

Jeff Brubaker, infrastructure Kerim Kalafala, IBM Joydip Das, Samsung architect for Custom Compiler at Synopsys, has been elected to the Si2 OpenAccess Change Team. Jeff began working on March 2020 custom design tools at Avanti in 2000 and joined Synopsys Samsung Executive Joins Si2 Board in 2002. In 2004, he was part of Directors of the Synopsys team which created the product that Jung Yun Choi, corporate vice presi- eventually became Custom dent of the Samsung Electronics Compiler, the Synopsys design Jeff Brubaker Design Technology team, was environment for analog, digital, Synopsys elected to the Si2 board of directors. and mixed-signal IC design. A 17-year Samsung veteran, Jung Yun leads the group responsible for developing all design tools and methodologies for Samsung April 2020 memory products: technologies Jung Yun Choi Si2 Launches Survey on Artificial and environments impacting Samsung product values, new process and Intelligence, Machine Learning in EDA package technologies, new applications and new working environments such as the Cloud. Since Si2 launched an industry-wide survey to identify joining Samsung, he has contributed to the planned usage and structural gaps for prioritizing development of low-power design methodologies and implementing artificial intelligence and machine for mobile devices, RTL-to-GDS implementation and learning in semiconductor sign-off methodologies. electronic design automation. The survey is organized by a recently formed Si2 Special Interest Group March 2020 chaired by Joydip Das, senior engineer, Samsung Electronics, CMC to Support CEA-Leti SPICE and co-chaired by Kerim Kalafala, Simulation Model senior technical staff member, EDA, and master inventor, IBM. The CMC announced the approval and financial The 18-member group is identifying how industry support of L-UTSOI, a new ultra-thin, silicon-on- collaboration will help eliminate deficiencies caused insulator transistor simulation model developed by a lack of common languages, data models, labels, by CEA-Leti, a French research institute for and access to robust and categorized training data. electronics and information technologies. Silicon- on-insulator uses a thin layer of insulating oxide

3 Highlights

June 2020

Unified Power Modeling Team Wins Si2 Power of Partnerships Award Semiconductor design experts from industry and Honorees from the UPM Working Group: academia comprised this year’s winners of the Silicon Integration Initiative’s Power of Partnerships Award, • Nagu Dhanwada, Working Group Chair, recognizing the Si2 team responsible for the most Senior Technical Staff Member, IBM significant contributions to the field of electronic • Allen Baker, Lead Software Developer, Ansys design automation. Led by Jerry Frenkil, director of • Daniel Cross, Principal Solutions Engineer, OpenStandards, members of the Unified Power Model Working Group were honored for developing Si2 • Rhett Davis, Professor of Electrical and UPM, a system-level power modeling standard which Computer Engineering, NC State University helps designers describe, analyze, and control power • David Ratchkov, CEO, Thrace Systems consumption, critical factors in reducing overall design costs and increasing chip performance.

DavidDavid Ratchkov Ratchkov Allen AllenBaker Baker NaguNagu DhanwadaDhanwada DanielDaniel Cross Cross RhettRhett Davis Davis Si2 Staff

John Ellis Marshall Tiner Jerry Frenkil Leigh Anne President and CEO Director, Production Director Clevenger Standards OpenStandards Senior Data Scientist

Terry Berke Sandy Lawrence Matt Wheaton Phillip Isenhart Manager of Office Manager Senior Programmer Computer and Member Services Information Systems Manager 4 Board of Directors

Rahul Goyal Stanley Krolikoski Keith Green Roger Carpenter Board Chair Board Treasurer Board Secretary Si2 board members are leaders from global semicon- ductor design and Jung Yun Choi David DeMaria Pankaj Kukkal manufacturing corporations. Elected annually by the Si2 membership the board of directors provides strategic direction Vic Kulkarni Juan C. Rey and oversight for Si2.

• Rahul Goyal, Board Chair, Vice President, Intel Corp., Director, R&D Strategic Enablement • Stanley Krolikoski, Board Treasurer, Fellow/Vice President, Strategic Alliances, Cadence Design Systems • Keith Green, Board Secretary, Distinguished Member of the Technical Staff, Texas Instruments • Roger Carpenter, Hardware Engineer, Leon Stok • Jung Yun Choi, Corporate Vice President, Electronics Design Technology, Samsung Electronics • David DeMaria, Corporate Vice President, Strategic Initiatives and Market Intelligence, Synopsys • Pankaj Kukkal, Vice President, EDA, Emulation and Post-Silicon Engineering, Qualcomm Technologies • Vic Kulkarni, Vice President and Chief Strategist, Ansys Richard Trihy • Juan C. Rey, Vice President of Engineering, Mentor, a Siemens Business • Leon Stok, Vice President, Electronic Design Automation Technologies, IBM • Richard Trihy, Vice President, Design Enablement, GLOBALFOUNDRIES

5 Members

OpenAccess Coalition

Adanced Micro Devices Intel Northrop Grumman Agile Analog Intento Design PDF Solutions AnaGlobe Technology Invecas Phoelex Ansys Jedat Pulsic Avatar Integrated Systems Juspertor Qualcomm Technologies Blue Cheetah Analog Design Keysight Technologies Samsung Cadence Design Systems Lattice Semiconductor Savarti Dassault Systèmes Luceda Photonics Scientific Analog Entasys Design MediaTek Silintech Fractal Technologies Mentor, a Siemens Business Silvaco Get2Spec Microsoft Synopsys Google Mythic Taiwan Semiconductor Hewlett Packard Enterprise Nanjing Industrial Innovation Manufacturing Co. Huada Empyrean Software Center of EDA Zuken Compact Model Coalition ams AG KIOXIA Corp. Sandia National Labs Analog Devices Mentor, a Siemens Business Silvaco Broadcom Micron Technology SK Hynix Cadence Design Systems NXP Semiconductors Sony Corp. GLOBALFOUNDRIES ProPlus Design Solutions STMicroelectronics Huada Empyrean Software Qualcomm Synopsys IBM Raytheon Technologies Corp. Taiwan Semiconductor Infineon Technologies Renesas Electronics Corp. Manufacturing Co. Intel Samsung Texas Instruments Keysight Technologies

OpenStandards Unified Power Model AI/ML Special Interest Coalition Working Group Group

AnaGlobe Technology Ansys Ansys Cadence Design Systems Ansys Cadence Design Systems Entasys Design Cadence Design Systems Entasys Design Google GLOBALFOUNDRIES GLOBALFOUNDRIES IBM Hewlett Packard Enterprise Google Intel IBM IBM Texas Instruments Intel Intel Corporation Thrace Systems Intento Design Marvell Semiconductor Keysight Technologies Qualcomm Technologies Mentor, a Siemens Business Savarti NC State University Texas Instruments PDF Solutions Thrace Systems Qualcomm Tool Corp. Samsung Sandia National Laboratories Silvaco SK Hynix Synopsys Texas Instruments Thrace Systems

6 OpenAccess Coalition

Backed by a group of dedicated volunteers, the OpenAccess Coalition recorded another successful year in support of the world’s most widely used, open reference database for IC design.

New Members Coalition Highlights • Microsoft oaPartitions • Northrop Grumman • Increased use of DM6 indicates • Phoelex • Scientific Analog applications are utilizing the parallel • Silicon Technologies execution enabled by oaPartitions • Silintech

oaScript 4.0 Release • oaPartitions capability Academic Members

DM5 End of Life • Auburn University • Chinese Academy of Sciences • Eindhoven University of Technology oaxPop Connectivity Work Started • Hiroshima University • Alpha testing underway • India Institute of Technology • Massachusetts Institute of oatDebug released with extension prefix Technology • NC State University • Oklahoma State University Open Access Releases • Stanford University • State University of New York, CS • Technical University Dresden DM5/22.50 • University of California, Berkeley • oa22.50p099, oa22.50p100, • University of Florida oa22.50p102 • University of South Florida • University of Waterloo DM6/22.60 • oa22.60p018, oa22.60p019, Participation oa22.60p021, oa22.60p023, oa22.60p025, oa22.60p026, • OAC Board Meetings (10) oa22.60p028, oa22.60p031, • Change Team Meetings (20) oa22.60p036 • Extension Steering Group Meetings (10) • oaScript Working Group Meetings (22) • oatDebug Working Group Meetings (10) Extension Steering Group Releases • oaxPop Working Group Meetings (9) • Open Access Live Forum • oaScript-v4.0, oatDebug-v1.0 October 2019 • Open Access Live Forum April 2020 Milestones

• New OpenAccess web page • New member portal • Migrated mailing list to a cloud-based FOR MORE INFORMATION communication service Marshall Tiner [email protected]

7 Compact Model Coalition

Simulations using models funded and qualified by CMC members power today’s advanced chip development. This year, the CMC supported eight developers and 15 funded models and active working groups. Peter Lee of Micron serves as the Peter Lee Jushan Xie Takeshi Naito CMC chair, supported by: Jushan Xie, vice chair, Cadence; Takeshi Naito, treasurer, KIOXIA; and Richard Williams, secretary, IBM.

Two New Funded Models HICUM/L0 reduces simulation time while maintaining sufficient accuracy for bias, Richard Williams Michael Schrőter Didier Celi frequency, and temperature ranges, all of which are crucial for high-frequency design. Michael Schröter developed HICUM/L0 and working group chair Didier Celi, of STMicroelectronics, promoted the model to ensure adoption by the CMC.

Harrison Lee L-UTSOI, or Leti Ultra-Thin, Silicon-On- Thierry Poiroux Olivier Rouzeau Insulator, comes from the team at CEA-Leti, including Thierry Poiroux and Olivier Rouzeau. Championed by working group chair Harrison Lee from Samsung, the model is based on more than 25 years of expertise with fully depleted silicon-on-insulator. Geoffrey Coram Shahriar Moinian Colin Shaw BSIM-CMG and BSIM-Bulk Last updated in 2017, both models received major Verilog-A Checker upgrades this year. BSIM-CMG enables leading- Developed by CMC Technology Advisor edge FinFET technology, and soon, Gate-All- Geoffrey Coram, and contributed to CMC by Around. The industry workhorse, BSIM-Bulk, his employer, Analog Devices, the Verilog-A supports high-voltage modeling. Model Pythonic Rule Enforcer (VAMPyRE) is a standalone parser and checker, written in 18-month Advance Access for CMC Members a single Python file. It aids model developers Member value was increased with the new during code development and optimization. 18-month advanced access to ever-improving model updates. Open Model Interface Working Group Under the continued leadership of the Quality Assurance working group chair, Colin Shaw of Silvaco, This ongoing effort is led by the QA Working OMI was a runner-up for the Si2 Power Group Chair, Shahriar Moinian of Broadcom. QA of Partnerships Award this year. Initially software scripts to test supplier implementation contributed to Si2 by Taiwan Semiconductor have been licensed for CMC and developer use Manufacturing Company, OMI is built around only. The wait time from bug reporting to bug-fix the TSMC Model Interface. OMI allows circuit availability has also been shortened for standard designers to simulate and analyze significant models. physical effects and perform extended design optimizations. Industry adoption was bolstered at the 2020 International Reliability FOR MORE INFORMATION Physics Symposium through an invited talk. John Ellis [email protected]

8 OpenStandards Coalition

The OpenStandards Coalition furthered industry acceptance of the Si2 Unified Power Model. UPM is a system-level power modeling standard which helps designers describe, analyze, and control power consumption, critical factors in reducing overall design costs and increasing chip performance.

Unified Power Model Milestones OpenStandards Members

• Global media coverage of IEEE approval AnaGlobe Technology of UPM as IEEE standard 2416-2019 Ansys • UPM 2.0 requirements defined Cadence Design Systems • New Si2 UPM web page and member portal published Entasys Design • BSIM-CMG support and Scenario GLOBALFOUNDRIES interface added to PowerCalc Google • Thrace Systems introduced PowerMeter, IBM the first UPM-based commercial tool Intel Corporation • The first UPM library, Nangate 15, was generated by Thrace Systems and Marvell Semiconductor tested by Si2 Qualcomm Technologies • UPM tutorial at DAC 2020 attracted more Savarti than 150 participants Texas Instruments Thrace Systems Unified Power Model Successes Tool Corp.

• UPM was used to model seven different Chiplets in the full system Unified Power Model power analysis of the “OmniChip,” Working Group Members an active interposer-based system designed and marketed by zGlue Ansys • The first RISC-V Energy per Instruction Cadence Design Systems (EPI) power model was created by the UPM Working Group, and displayed in Entasys Design the DAC 2020 power tutorial Google IBM UPM Working Group Team Wins Intel Si2 Power of Partnerships Award Texas Instruments Thrace Systems Five UPM Working Group members were honored as this year’s Si2 Power of Partnerships Award, which recognizes

the Si2 team responsible for the most FOR MORE INFORMATION significant contributions to EDA. See page 4 Jerry Frenkil [email protected]

9 Special Interest Groups

Special Interest Groups are global communities that identify and cultivate innovative, collaborative solutions to shared problems in semiconductor design. They develop targeted strategies to address the pressing needs of Si2 members and the industry. For-profit and not-for-profit organizations, including universities, are welcome to join.

Key AI/ML Survey Results

Artificial Intelligence/Machine Important Data Types Learning Special Interest Group Simulation 60% Layout 48% In February 2020, Si2 launched a Place and Route 46% special interest group to provide real benefits for EDA using artificial Timing 46% intelligence and machine learning. Power 41% Verification 34% To chart its path, the SIG conducted Design Rules 32% an industry-wide survey in early 2020 Standard Cells 30% to identify industry progress and roadblocks. EDA tool developers and chip designers comprised most of Need for Organized Training Data the 200 respondents. For key survey Chip Designers 4.55/5.0 results, see right. Tool Developers 4.55/5.0 Researchers 4.5/5.0 First Goal: Common Data Model IP Developers 4.09/5.o The survey results produced the group’s first goal: to develop a Want Common Reference Flow common data model that interfaces Researchers 100% with high-interest design data and supports data derived during design Tool Developers 84% and analysis. Chip Designers 77% IP Developers 55% First Deliverable: Industry White Paper Want Common Data Model A Collaborative Data Model for AI/ML IP Developers 4.5/5.0 in EDA, produced by a subgroup of 16 Chip Designers 3.95/5.0 authors from 11 companies, is now Tool Developers 3.88/5.0 available to Si2 members and the Researchers 3.83/5.0 wider industry.

Want On-line AI/ML Courses Tool Developers 82% Chip Designer 82% FOR MORE INFORMATION IP Developers 73% Leigh Anne Clevenger Researchers 60% [email protected]

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