DOCSLIB.ORG

Virtual Memory Process Abstraction, Part 2: Private Address Space

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Virtual Memory Process Abstraction, Part 2: Private Address Space Virtual Memory Process Abstraction, Part 2: Private Address Space Motivation: why not direct physical memory access? Address translation with pages Optimizing translation: translation lookaside buffer Extra benefits: sharing and protection Memory as a contiguous array of bytes is a lie! Why? 1 Problems with Physical Addressing Fine for small embedded systems without processes. Elevators, microwaves, radio-powered devices, … What about Main memory larger systems? 0: 1: Physical address 2: With many processes? (PA) 3: CPU 4: 4 5: 6: 7: 8: ... M-1: Data 2 Problem 1: Memory Management Main memory Process 1 Process 2 stack heap Process 3 What goes code … × where? Process n globals … Also: Context switches must swap out entire memory contents. Isn't that expensive? 3 Problem 2: Capacity 64-bit addresses can address Physical main memory offers several exabytes a few gigabytes (18,446,744,073,709,551,616 bytes) (e.g. 8,589,934,592 bytes) (Actually, it’s smaller than that ? dot compared to virtual memory.) 1 virtual address space per process, with many processes… 4 Problem 3: Protection Physical main memory Process i Process j Problem 4: Sharing Physical main memory Process i Process j 5 Solution: Virtual Memory (address indirection) Virtual memory Process 1 virtual Physical memory addresses virtual-to-physical mapping physical Virtual memory addresses Process n virtual addresses Private virtual address space Single physical address space per process. managed by OS/hardware. 6 Indirection "2" (it's everywhere!) 0 1 Direct naming "2" "2" Thing 2 3 What X currently 4 "x" maps to 5 Indirect naming "x" 2 6 "x" 7 "x" What if we move Thing? 7 Tangent: Indirection everywhere • Pointers • Constants • Procedural abstraction • Domain Name Service (DNS) • Dynamic Host Configuration Protocol (DHCP) • Phone numbers • 911 • Call centers • Snail mail forwarding • … “Any problem in computer science can be solved by adding another level of indirection.” –David Wheeler, inventor of the subroutine, or Butler Lampson Another Wheeler quote? "Compatibility means deliberately repeating other people's mistakes." Virtual Addressing and Address Translation Memory Management Unit translates virtual address to physical address Main memory 0: CPU Chip 1: Virtual address Physical address 2: (VA) (PA) 3: CPU MMU 4: 4100 4 5: 6: 7: 8: ... M-1: Data Physical addresses are invisible to programs. 9 Page-based Mapping both address spaces Virtual divided into fixed-size, aligned pages Address Space page size = power of two 0 Virtual Physical Page Address Space 0 0 Virtual Physical Page Page 0 1 Virtual Physical Page Page 2 1 Virtual Page Map virtual pages 3 … onto physical pages. Physical … Page m 2p - 1 Virtual 2 - 1 Page 2n - 1 2v - 1 Some virtual pages do not fit! Where are they stored? Some virtual pages do not fit! Where are they stored? Virtual Memory virtual address space Address Space usually much larger than 0 Virtual physical address space Physical Memory Page Address Space 0 0 Virtual Physical Page Page 0 1 Virtual Physical Page Page 2 1 Virtual Page 3 … 1. On disk (if used) Physical … Page m 2p - 1 Virtual 2 - 1 Page 2n - 1 2v - 1 2. Nowhere! (if not yet used) Not drawn to scale Virtual Memory: cache for disk? SRAM DRAM ~4 MB ~8 GB ~500 GB L1 I-cache L2 Main 32 KB unified Disk cache Memory L1 CPU Reg D-cache Throughput: 16 B/cycle 8 B/cycle 2 B/cycle 1 B/30 cycles Latency: 3 cycles 14 cycles 100 cycles millions solid-state "flash" or spinning magnetic platter. Cache miss penalty (latency): 33x Memory miss penalty (latency): 10,000x Example system 12 Design for a Slow Disk: Exploit Locality Virtual Memory Address Space Large page size 0 usually 4KB, up to 2Page size?-4MB Virtual Physical Memory Page Address Space 0 0 Virtual Physical Page Page 0 1 Fully associative Virtual • Store any virtual page in any physical pageAssociativity? Physical Page • Large mapping function Page 2 1 Virtual Page 3 … on disk Physical … Page 2m - 1 2p - 1 Virtual Sophisticated Page Replacement 2n - 1 2v - 1 replacement policypolicy? Write • Not just hardware Write-back policy? Address Translation Main memory 0: CPU Chip 1: Virtual address Physical address 2: (VA) (PA) 3: CPU MMU 4: 4100 4 5: 6: 7: 8: ... What happens in here? M-1: Data 15 Page Table Physical pages array of page table entries (PTEs) (Physical memory) mapping virtual page to where it is stored VP 1 PP 0 Physical Page Number Valid or disk address VP 2 PTE 0 0 null 1 VP 7 1 VP 4 0 PP 3 1 0 null 0 PTE 7 1 Swap space page table (Disk) VP 3 Memory resident, managed by HW (MMU), OS VP 6 How many page tables are in the system? 16 Address Translation with a Page Table Page table Virtual address (VA) base register (PTBR) Virtual page number (VPN) Virtual page offset (VPO) Base address of current process's Page table page table Valid Physical page number (PPN) Virtual page mapped to physical page? If so: Page Hit Physical page number (PPN) Physical page offset (PPO) Physical address (PA) 17 Page Hit: virtual page in memory Physical pages (Physical memory) Virtual Page Number VP 1 PP 0 Physical Page Number Valid or disk address VP 2 PTE 0 0 null 1 PP 0 VP 7 1 PP 1 VP 4 0 On disk PP 3 1 PP 3 0 null 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 VP 6 18 Page Fault: Physical pages (Physical memory) Virtual Page Number VP 1 PP 0 Physical Page Number Valid or disk address VP 2 PP 1 PTE 0 0 null 1 PP 0 VP 7 PP 2 1 PP 1 VP 4 0 On disk PP 3 1 PP 3 0 null 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 VP 6 19 Page Fault: exceptional control flow Process accessed virtual address in a page that is not in physical memory. Process User Code OS exception handler exception: page fault movl Load page return into memory Returns to faulting instruction: movl is executed again! 20 Page Fault: 1. page not in memory Physical pages (Physical memory) Virtual Page Number VP 1 PP 0 Physical Page Number Valid or disk address VP 2 PTE 0 0 null 1 PP 0 VP 7 1 PP 1 VP 4 0 On disk PP 3 1 PP 3 0 null 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 What now? VP 6 OS handles fault 21 "Page out" Page Fault: 2. OS evicts another page. Physical pages (Physical memory) Virtual Page Number VP 1 PP 0 Physical Page Number Valid or disk address VP 2 PTE 0 0 null 0 On disk VP 7 1 PP 1 VP 4 0 On disk PP 3 1 PP 3 0 null 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 VP 6 VP 1 22 "Page in" Page Fault: 3. OS loads needed page. Physical pages (Physical memory) Virtual Page Number VP 3 PP 0 Physical Page Number Valid or disk address VP 2 PTE 0 0 null 1 On disk VP 7 1 PP 1 VP 4 1 PP 0 PP 3 1 PP 3 0 null 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 Finally: Re-execute faulting instruction. VP 6 Page hit! VP 1 23 Terminology context switch Switch control between processes on the same CPU. page in Move page of virtual memory from disk to physical memory. swap page out Move page of virtual memory from physical memory to disk. thrash Total working set size of processes is larger than physical memory. Most time is spent paging in and out instead of doing useful computation. (I find all these terms useful when talking to other computer scientists about my brain…) 24 Address Translation: Page Hit 2 CPU Chip PTEA 1 PTE VA Cache/ CPU MMU 3 Memory PA 4 Data 5 1) Processor sends virtual address to MMU (memory management unit) 2-3) MMU fetches PTE from page table in cache/memory 4) MMU sends physical address to cache/memory 5) Cache/memory sends data word to processor 25 Address Translation: Page Fault Exception Page fault handler 4 2 CPU Chip PTEA Victim page 1 5 VA PTE Cache/ CPU MMU Disk 7 3 Memory New page 6 1) Processor sends virtual address to MMU 2-3) MMU fetches PTE from page table in cache/memory 4) Valid bit is zero, so MMU triggers page fault exception 5) Handler identifies victim (and, if dirty, pages it out to disk) 6) Handler pages in new page and updates PTE in memory 7) Handler returns to original process, restarting faulting instruction 26 How fast is translation? How many physical memory accesses are required to complete one virtual memory access? Translation Lookaside Buffer (TLB) Small hardware cache in MMU just for page table entries e.g., 128 or 256 entries Much faster than a page table lookup in memory. In the running for "un/classiest name of a thing in CS" 27 TLB Hit CPU Chip TLB 2 PTE VPN 3 1 VA PA CPU MMU 4 Cache/ Memory Data 5 A TLB hit eliminates a memory access 28 TLB Miss CPU Chip TLB 4 2 PTE VPN 1 3 VA PTEA CPU MMU Cache/ PA Memory 5 Data 6 A TLB miss incurs an additional memory access (the PTE) Fortunately, TLB misses are rare.
Load more

Recommended publications
  • Virtual Memory
    Chapter 4 Virtual Memory Linux processes execute in a virtual environment that makes it appear as if each process had the entire address space of the CPU available to itself. This virtual address space extends from address 0 all the way to the maximum address. On a 32-bit platform, such as IA-32, the maximum address is 232 − 1or0xffffffff. On a 64-bit platform, such as IA-64, this is 264 − 1or0xffffffffffffffff. While it is obviously convenient for a process to be able to access such a huge ad- dress space, there are really three distinct, but equally important, reasons for using virtual memory. 1. Resource virtualization. On a system with virtual memory, a process does not have to concern itself with the details of how much physical memory is available or which physical memory locations are already in use by some other process. In other words, virtual memory takes a limited physical resource (physical memory) and turns it into an infinite, or at least an abundant, resource (virtual memory). 2. Information isolation. Because each process runs in its own address space, it is not possible for one process to read data that belongs to another process. This improves security because it reduces the risk of one process being able to spy on another pro- cess and, e.g., steal a password. 3. Fault isolation. Processes with their own virtual address spaces cannot overwrite each other’s memory. This greatly reduces the risk of a failure in one process trig- gering a failure in another process. That is, when a process crashes, the problem is generally limited to that process alone and does not cause the entire machine to go down.
    [Show full text]
  • The Case for Compressed Caching in Virtual Memory Systems
    THE ADVANCED COMPUTING SYSTEMS ASSOCIATION The following paper was originally published in the Proceedings of the USENIX Annual Technical Conference Monterey, California, USA, June 6-11, 1999 The Case for Compressed Caching in Virtual Memory Systems _ Paul R. Wilson, Scott F. Kaplan, and Yannis Smaragdakis aUniversity of Texas at Austin © 1999 by The USENIX Association All Rights Reserved Rights to individual papers remain with the author or the author's employer. Permission is granted for noncommercial reproduction of the work for educational or research purposes. This copyright notice must be included in the reproduced paper. USENIX acknowledges all trademarks herein. For more information about the USENIX Association: Phone: 1 510 528 8649 FAX: 1 510 548 5738 Email: [email protected] WWW: http://www.usenix.org The Case for Compressed Caching in Virtual Memory Systems Paul R. Wilson, Scott F. Kaplan, and Yannis Smaragdakis Dept. of Computer Sciences University of Texas at Austin Austin, Texas 78751-1182 g fwilson|sfkaplan|smaragd @cs.utexas.edu http://www.cs.utexas.edu/users/oops/ Abstract In [Wil90, Wil91b] we proposed compressed caching for virtual memory—storing pages in compressed form Compressed caching uses part of the available RAM to in a main memory compression cache to reduce disk pag- hold pages in compressed form, effectively adding a new ing. Appel also promoted this idea [AL91], and it was level to the virtual memory hierarchy. This level attempts evaluated empirically by Douglis [Dou93] and by Russi- to bridge the huge performance gap between normal (un- novich and Cogswell [RC96]. Unfortunately Douglis’s compressed) RAM and disk.
    [Show full text]
  • Memory Protection at Option
    Memory Protection at Option Application-Tailored Memory Safety in Safety-Critical Embedded Systems – Speicherschutz nach Wahl Auf die Anwendung zugeschnittene Speichersicherheit in sicherheitskritischen eingebetteten Systemen Der Technischen Fakultät der Universität Erlangen-Nürnberg zur Erlangung des Grades Doktor-Ingenieur vorgelegt von Michael Stilkerich Erlangen — 2012 Als Dissertation genehmigt von der Technischen Fakultät Universität Erlangen-Nürnberg Tag der Einreichung: 09.07.2012 Tag der Promotion: 30.11.2012 Dekan: Prof. Dr.-Ing. Marion Merklein Berichterstatter: Prof. Dr.-Ing. Wolfgang Schröder-Preikschat Prof. Dr. Michael Philippsen Abstract With the increasing capabilities and resources available on microcontrollers, there is a trend in the embedded industry to integrate multiple software functions on a single system to save cost, size, weight, and power. The integration raises new requirements, thereunder the need for spatial isolation, which is commonly established by using a memory protection unit (MPU) that can constrain access to the physical address space to a fixed set of address regions. MPU-based protection is limited in terms of available hardware, flexibility, granularity and ease of use. Software-based memory protection can provide an alternative or complement MPU-based protection, but has found little attention in the embedded domain. In this thesis, I evaluate qualitative and quantitative advantages and limitations of MPU-based memory protection and software-based protection based on a multi-JVM. I developed a framework composed of the AUTOSAR OS-like operating system CiAO and KESO, a Java implementation for deeply embedded systems. The framework allows choosing from no memory protection, MPU-based protection, software-based protection, and a combination of the two.
    [Show full text]
  • Virtual Memory
    Virtual Memory Copyright ©: University of Illinois CS 241 Staff 1 Address Space Abstraction n Program address space ¡ All memory data ¡ i.e., program code, stack, data segment n Hardware interface (physical reality) ¡ Computer has one small, shared memory How can n Application interface (illusion) we close this gap? ¡ Each process wants private, large memory Copyright ©: University of Illinois CS 241 Staff 2 Address Space Illusions n Address independence ¡ Same address can be used in different address spaces yet remain logically distinct n Protection ¡ One address space cannot access data in another address space n Virtual memory ¡ Address space can be larger than the amount of physical memory on the machine Copyright ©: University of Illinois CS 241 Staff 3 Address Space Illusions: Virtual Memory Illusion Reality Giant (virtual) address space Many processes sharing Protected from others one (physical) address space (Unless you want to share it) Limited memory More whenever you want it Today: An introduction to Virtual Memory: The memory space seen by your programs! Copyright ©: University of Illinois CS 241 Staff 4 Multi-Programming n Multiple processes in memory at the same time n Goals 1. Layout processes in memory as needed 2. Protect each process’s memory from accesses by other processes 3. Minimize performance overheads 4. Maximize memory utilization Copyright ©: University of Illinois CS 241 Staff 5 OS & memory management n Main memory is normally divided into two parts: kernel memory and user memory n In a multiprogramming system, the “user” part of main memory needs to be divided to accommodate multiple processes. n The user memory is dynamically managed by the OS (known as memory management) to satisfy following requirements: ¡ Protection ¡ Relocation ¡ Sharing ¡ Memory organization (main mem.
    [Show full text]
  • Extracting Compressed Pages from the Windows 10 Virtual Store WHITE PAPER | EXTRACTING COMPRESSED PAGES from the WINDOWS 10 VIRTUAL STORE 2
    white paper Extracting Compressed Pages from the Windows 10 Virtual Store WHITE PAPER | EXTRACTING COMPRESSED PAGES FROM THE WINDOWS 10 VIRTUAL STORE 2 Abstract Windows 8.1 introduced memory compression in August 2013. By the end of 2013 Linux 3.11 and OS X Mavericks leveraged compressed memory as well. Disk I/O continues to be orders of magnitude slower than RAM, whereas reading and decompressing data in RAM is fast and highly parallelizable across the system’s CPU cores, yielding a significant performance increase. However, this came at the cost of increased complexity of process memory reconstruction and thus reduced the power of popular tools such as Volatility, Rekall, and Redline. In this document we introduce a method to retrieve compressed pages from the Windows 10 Memory Manager Virtual Store, thus providing forensics and auditing tools with a way to retrieve, examine, and reconstruct memory artifacts regardless of their storage location. Introduction Windows 10 moves pages between physical memory and the hard disk or the Store Manager’s virtual store when memory is constrained. Universal Windows Platform (UWP) applications leverage the Virtual Store any time they are suspended (as is the case when minimized). When a given page is no longer in the process’s working set, the corresponding Page Table Entry (PTE) is used by the OS to specify the storage location as well as additional data that allows it to start the retrieval process. In the case of a page file, the retrieval is straightforward because both the page file index and the location of the page within the page file can be directly retrieved.
    [Show full text]
  • HALO: Post-Link Heap-Layout Optimisation
    HALO: Post-Link Heap-Layout Optimisation Joe Savage Timothy M. Jones University of Cambridge, UK University of Cambridge, UK [email protected] [email protected] Abstract 1 Introduction Today, general-purpose memory allocators dominate the As the gap between memory and processor speeds continues landscape of dynamic memory management. While these so- to widen, efficient cache utilisation is more important than lutions can provide reasonably good behaviour across a wide ever. While compilers have long employed techniques like range of workloads, it is an unfortunate reality that their basic-block reordering, loop fission and tiling, and intelligent behaviour for any particular workload can be highly subop- register allocation to improve the cache behaviour of pro- timal. By catering primarily to average and worst-case usage grams, the layout of dynamically allocated memory remains patterns, these allocators deny programs the advantages of largely beyond the reach of static tools. domain-specific optimisations, and thus may inadvertently Today, when a C++ program calls new, or a C program place data in a manner that hinders performance, generating malloc, its request is satisfied by a general-purpose allocator unnecessary cache misses and load stalls. with no intimate knowledge of what the program does or To help alleviate these issues, we propose HALO: a post- how its data objects are used. Allocations are made through link profile-guided optimisation tool that can improve the fixed, lifeless interfaces, and fulfilled by
    [Show full text]
  • Virtual Memory - Paging
    Virtual memory - Paging Johan Montelius KTH 2020 1 / 32 The process code heap (.text) data stack kernel 0x00000000 0xC0000000 0xffffffff Memory layout for a 32-bit Linux process 2 / 32 Segments - a could be solution Processes in virtual space Address translation by MMU (base and bounds) Physical memory 3 / 32 one problem Physical memory External fragmentation: free areas of free space that is hard to utilize. Solution: allocate larger segments ... internal fragmentation. 4 / 32 another problem virtual space used code We’re reserving physical memory that is not used. physical memory not used? 5 / 32 Let’s try again It’s easier to handle fixed size memory blocks. Can we map a process virtual space to a set of equal size blocks? An address is interpreted as a virtual page number (VPN) and an offset. 6 / 32 Remember the segmented MMU MMU exception no virtual addr. offset yes // < within bounds index + physical address segment table 7 / 32 The paging MMU MMU exception virtual addr. offset // VPN available ? + physical address page table 8 / 32 the MMU exception exception virtual address within bounds page available Segmentation Paging linear address physical address 9 / 32 a note on the x86 architecture The x86-32 architecture supports both segmentation and paging. A virtual address is translated to a linear address using a segmentation table. The linear address is then translated to a physical address by paging. Linux and Windows do not use use segmentation to separate code, data nor stack. The x86-64 (the 64-bit version of the x86 architecture) has dropped many features for segmentation.
    [Show full text]
  • Chapter 4 Memory Management and Virtual Memory Asst.Prof.Dr
    Chapter 4 Memory management and Virtual Memory Asst.Prof.Dr. Supakit Nootyaskool IT-KMITL Object • To discuss the principle of memory management. • To understand the reason that memory partitions are importance for system organization. • To describe the concept of Paging and Segmentation. 4.1 Difference in main memory in the system • The uniprogramming system (example in DOS) allows only a program to be present in memory at a time. All resources are provided to a program at a time. Example in a memory has a program and an OS running 1) Operating system (on Kernel space) 2) A running program (on User space) • The multiprogramming system is difference from the mentioned above by allowing programs to be present in memory at a time. All resource must be organize and sharing to programs. Example by two programs are in the memory . 1) Operating system (on Kernel space) 2) Running programs (on User space + running) 3) Programs are waiting signals to execute in CPU (on User space). The multiprogramming system uses memory management to organize location to the programs 4.2 Memory management terms Frame Page Segment 4.2 Memory management terms Frame Page A fixed-lengthSegment block of main memory. 4.2 Memory management terms Frame Page A fixed-length block of data that resides in secondary memory. A page of data may temporarily beSegment copied into a frame of main memory. A variable-lengthMemory management block of data that residesterms in secondary memory. A segment may temporarily be copied into an available region of main memory or the segment may be divided into pages which can be individuallyFrame copied into mainPage memory.
    [Show full text]
  • X86 Memory Protection and Translation
    2/5/20 COMP 790: OS Implementation COMP 790: OS Implementation Logical Diagram Binary Memory x86 Memory Protection and Threads Formats Allocators Translation User System Calls Kernel Don Porter RCU File System Networking Sync Memory Device CPU Today’s Management Drivers Scheduler Lecture Hardware Interrupts Disk Net Consistency 1 Today’s Lecture: Focus on Hardware ABI 2 1 2 COMP 790: OS Implementation COMP 790: OS Implementation Lecture Goal Undergrad Review • Understand the hardware tools available on a • What is: modern x86 processor for manipulating and – Virtual memory? protecting memory – Segmentation? • Lab 2: You will program this hardware – Paging? • Apologies: Material can be a bit dry, but important – Plus, slides will be good reference • But, cool tech tricks: – How does thread-local storage (TLS) work? – An actual (and tough) Microsoft interview question 3 4 3 4 COMP 790: OS Implementation COMP 790: OS Implementation Memory Mapping Two System Goals 1) Provide an abstraction of contiguous, isolated virtual Process 1 Process 2 memory to a program Virtual Memory Virtual Memory 2) Prevent illegal operations // Program expects (*x) – Prevent access to other application or OS memory 0x1000 Only one physical 0x1000 address 0x1000!! // to always be at – Detect failures early (e.g., segfault on address 0) // address 0x1000 – More recently, prevent exploits that try to execute int *x = 0x1000; program data 0x1000 Physical Memory 5 6 5 6 1 2/5/20 COMP 790: OS Implementation COMP 790: OS Implementation Outline x86 Processor Modes • x86
    [Show full text]
  • Operating Systems
    UC Santa Barbara Operating Systems Christopher Kruegel Department of Computer Science UC Santa Barbara http://www.cs.ucsb.edu/~chris/ CS 170 Info UC Santa Barbara • Web page: http://www.cs.ucsb.edu/~chris/cs170/index.html • Mailing lists (one for class, one for instructors) cs170-users – used to disseminate information and ask fellow classmates cs170-admin – use to reach TA and me 2 Requirements UC Santa Barbara • The course requirements include – several projects – a midterm and a final exam • The projects (and exams) are individual efforts • The final grade will be determined according to the following weight – projects: 50% – exams: 50% • Class participation and non-graded quizzes 3 Lab Projects UC Santa Barbara ~5 programming assignments • Shell (system calls) • Threads (parallel execution, scheduling) • Synchronization (semaphores, …) • Memory (virtual memory, shared regions, …) • File systems 4 Material UC Santa Barbara • The course will adopt the following book: Andrew S. Tanenbaum and Albert S. Woodhull Operating Systems (Design and Implementation) 3rd Edition, Prentice-Hall, 2006 • The set of assignments will be updated during the course • Additional material (slides) is provided on the class Web page 5 Operating Systems UC Santa Barbara • Let us do amazing things … – allow you to run multiple programs at the same time – protect all other programs when one app crashes – allow programs to use more memory that your computer has RAM – allow you to plug in a device and just use it (well, most of the time) – protects your data from
    [Show full text]
  • Virtual Memory in X86
    Fall 2017 :: CSE 306 Virtual Memory in x86 Nima Honarmand Fall 2017 :: CSE 306 x86 Processor Modes • Real mode – walks and talks like a really old x86 chip • State at boot • 20-bit address space, direct physical memory access • 1 MB of usable memory • No paging • No user mode; processor has only one protection level • Protected mode – Standard 32-bit x86 mode • Combination of segmentation and paging • Privilege levels (separate user and kernel) • 32-bit virtual address • 32-bit physical address • 36-bit if Physical Address Extension (PAE) feature enabled Fall 2017 :: CSE 306 x86 Processor Modes • Long mode – 64-bit mode (aka amd64, x86_64, etc.) • Very similar to 32-bit mode (protected mode), but bigger address space • 48-bit virtual address space • 52-bit physical address space • Restricted segmentation use • Even more obscure modes we won’t discuss today xv6 uses protected mode w/o PAE (i.e., 32-bit virtual and physical addresses) Fall 2017 :: CSE 306 Virt. & Phys. Addr. Spaces in x86 Processor • Both RAM hand hardware devices (disk, Core NIC, etc.) connected to system bus • Mapped to different parts of the physical Virtual Addr address space by the BIOS MMU Data • You can talk to a device by performing Physical Addr read/write operations on its physical addresses Cache • Devices are free to interpret reads/writes in any way they want (driver knows) System Interconnect (Bus) : all addrs virtual DRAM Network … Disk (Memory) Card : all addrs physical Fall 2017 :: CSE 306 Virt-to-Phys Translation in x86 0xdeadbeef Segmentation 0x0eadbeef Paging 0x6eadbeef Virtual Address Linear Address Physical Address Protected/Long mode only • Segmentation cannot be disabled! • But can be made a no-op (a.k.a.
    [Show full text]
  • Operating Systems
    UC Santa Barbara Operating Systems Christopher Kruegel Department of Computer Science UC Santa Barbara http://www.cs.ucsb.edu/~chris/ Virtual Memory and Paging UC Santa Barbara • What if a program is too big to be loaded in memory • What if a higher degree of multiprogramming is desirable • Physical memory is split in page frames • Virtual memory is split in pages • OS (with help from the hardware) manages the mapping between pages and page frames 2 Mapping Pages to Page Frames UC Santa Barbara • Virtual memory: 64KB • Physical memory: 32KB • Page size: 4KB • Virtual memory pages: 16 • Physical memory pages: 8 3 Memory Management Unit UC Santa Barbara • Automatically performs the mapping from virtual addresses into physical addresses 4 Memory Management Unit UC Santa Barbara • Addresses are split into a page number and an offset • Page numbers are used to look up a table in the MMU with as many entries as the number of virtual pages • Each entry in the table contains a bit that states if the virtual page is actually mapped to a physical one • If it is so, the entry contains the number of physical page used • If not, a page fault is generated and the OS has to deal with it 5 Page Tables UC Santa Barbara • Page tables contain an entry for each virtual table • If virtual memory is big (e.g., 32 bit and 64 bit addresses) the table can become of unmanageable size • Solution: instead of keeping them in the MMU move them to main memory • Problem: page tables are used each time an access to memory is performed.
    [Show full text]