Virtual Memory Process Abstraction, Part 2: Private Address Space Motivation: why not direct physical memory access? Address translation with pages Optimizing translation: translation lookaside buffer Extra benefits: sharing and protection Memory as a contiguous array of bytes is a lie! Why? 1 Problems with Physical Addressing Fine for small embedded systems without processes. Elevators, microwaves, radio-powered devices, … What about Main memory larger systems? 0: 1: Physical address 2: With many processes? (PA) 3: CPU 4: 4 5: 6: 7: 8: ... M-1: Data 2 Problem 1: Memory Management Main memory Process 1 Process 2 stack heap Process 3 What goes code … × where? Process n globals … Also: Context switches must swap out entire memory contents. Isn't that expensive? 3 Problem 2: Capacity 64-bit addresses can address Physical main memory offers several exabytes a few gigabytes (18,446,744,073,709,551,616 bytes) (e.g. 8,589,934,592 bytes) (Actually, it’s smaller than that ? dot compared to virtual memory.) 1 virtual address space per process, with many processes… 4 Problem 3: Protection Physical main memory Process i Process j Problem 4: Sharing Physical main memory Process i Process j 5 Solution: Virtual Memory (address indirection) Virtual memory Process 1 virtual Physical memory addresses virtual-to-physical mapping physical Virtual memory addresses Process n virtual addresses Private virtual address space Single physical address space per process. managed by OS/hardware. 6 Indirection "2" (it's everywhere!) 0 1 Direct naming "2" "2" Thing 2 3 What X currently 4 "x" maps to 5 Indirect naming "x" 2 6 "x" 7 "x" What if we move Thing? 7 Tangent: Indirection everywhere • Pointers • Constants • Procedural abstraction • Domain Name Service (DNS) • Dynamic Host Configuration Protocol (DHCP) • Phone numbers • 911 • Call centers • Snail mail forwarding • … “Any problem in computer science can be solved by adding another level of indirection.” –David Wheeler, inventor of the subroutine, or Butler Lampson Another Wheeler quote? "Compatibility means deliberately repeating other people's mistakes." Virtual Addressing and Address Translation Memory Management Unit translates virtual address to physical address Main memory 0: CPU Chip 1: Virtual address Physical address 2: (VA) (PA) 3: CPU MMU 4: 4100 4 5: 6: 7: 8: ... M-1: Data Physical addresses are invisible to programs. 9 Page-based Mapping both address spaces Virtual divided into fixed-size, aligned pages Address Space page size = power of two 0 Virtual Physical Page Address Space 0 0 Virtual Physical Page Page 0 1 Virtual Physical Page Page 2 1 Virtual Page Map virtual pages 3 … onto physical pages. Physical … Page m 2p - 1 Virtual 2 - 1 Page 2n - 1 2v - 1 Some virtual pages do not fit! Where are they stored? Some virtual pages do not fit! Where are they stored? Virtual Memory virtual address space Address Space usually much larger than 0 Virtual physical address space Physical Memory Page Address Space 0 0 Virtual Physical Page Page 0 1 Virtual Physical Page Page 2 1 Virtual Page 3 … 1. On disk (if used) Physical … Page m 2p - 1 Virtual 2 - 1 Page 2n - 1 2v - 1 2. Nowhere! (if not yet used) Not drawn to scale Virtual Memory: cache for disk? SRAM DRAM ~4 MB ~8 GB ~500 GB L1 I-cache L2 Main 32 KB unified Disk cache Memory L1 CPU Reg D-cache Throughput: 16 B/cycle 8 B/cycle 2 B/cycle 1 B/30 cycles Latency: 3 cycles 14 cycles 100 cycles millions solid-state "flash" or spinning magnetic platter. Cache miss penalty (latency): 33x Memory miss penalty (latency): 10,000x Example system 12 Design for a Slow Disk: Exploit Locality Virtual Memory Address Space Large page size 0 usually 4KB, up to 2Page size?-4MB Virtual Physical Memory Page Address Space 0 0 Virtual Physical Page Page 0 1 Fully associative Virtual • Store any virtual page in any physical pageAssociativity? Physical Page • Large mapping function Page 2 1 Virtual Page 3 … on disk Physical … Page 2m - 1 2p - 1 Virtual Sophisticated Page Replacement 2n - 1 2v - 1 replacement policypolicy? Write • Not just hardware Write-back policy? Address Translation Main memory 0: CPU Chip 1: Virtual address Physical address 2: (VA) (PA) 3: CPU MMU 4: 4100 4 5: 6: 7: 8: ... What happens in here? M-1: Data 15 Page Table Physical pages array of page table entries (PTEs) (Physical memory) mapping virtual page to where it is stored VP 1 PP 0 Physical Page Number Valid or disk address VP 2 PTE 0 0 null 1 VP 7 1 VP 4 0 PP 3 1 0 null 0 PTE 7 1 Swap space page table (Disk) VP 3 Memory resident, managed by HW (MMU), OS VP 6 How many page tables are in the system? 16 Address Translation with a Page Table Page table Virtual address (VA) base register (PTBR) Virtual page number (VPN) Virtual page offset (VPO) Base address of current process's Page table page table Valid Physical page number (PPN) Virtual page mapped to physical page? If so: Page Hit Physical page number (PPN) Physical page offset (PPO) Physical address (PA) 17 Page Hit: virtual page in memory Physical pages (Physical memory) Virtual Page Number VP 1 PP 0 Physical Page Number Valid or disk address VP 2 PTE 0 0 null 1 PP 0 VP 7 1 PP 1 VP 4 0 On disk PP 3 1 PP 3 0 null 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 VP 6 18 Page Fault: Physical pages (Physical memory) Virtual Page Number VP 1 PP 0 Physical Page Number Valid or disk address VP 2 PP 1 PTE 0 0 null 1 PP 0 VP 7 PP 2 1 PP 1 VP 4 0 On disk PP 3 1 PP 3 0 null 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 VP 6 19 Page Fault: exceptional control flow Process accessed virtual address in a page that is not in physical memory. Process User Code OS exception handler exception: page fault movl Load page return into memory Returns to faulting instruction: movl is executed again! 20 Page Fault: 1. page not in memory Physical pages (Physical memory) Virtual Page Number VP 1 PP 0 Physical Page Number Valid or disk address VP 2 PTE 0 0 null 1 PP 0 VP 7 1 PP 1 VP 4 0 On disk PP 3 1 PP 3 0 null 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 What now? VP 6 OS handles fault 21 "Page out" Page Fault: 2. OS evicts another page. Physical pages (Physical memory) Virtual Page Number VP 1 PP 0 Physical Page Number Valid or disk address VP 2 PTE 0 0 null 0 On disk VP 7 1 PP 1 VP 4 0 On disk PP 3 1 PP 3 0 null 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 VP 6 VP 1 22 "Page in" Page Fault: 3. OS loads needed page. Physical pages (Physical memory) Virtual Page Number VP 3 PP 0 Physical Page Number Valid or disk address VP 2 PTE 0 0 null 1 On disk VP 7 1 PP 1 VP 4 1 PP 0 PP 3 1 PP 3 0 null 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 Finally: Re-execute faulting instruction. VP 6 Page hit! VP 1 23 Terminology context switch Switch control between processes on the same CPU. page in Move page of virtual memory from disk to physical memory. swap page out Move page of virtual memory from physical memory to disk. thrash Total working set size of processes is larger than physical memory. Most time is spent paging in and out instead of doing useful computation. (I find all these terms useful when talking to other computer scientists about my brain…) 24 Address Translation: Page Hit 2 CPU Chip PTEA 1 PTE VA Cache/ CPU MMU 3 Memory PA 4 Data 5 1) Processor sends virtual address to MMU (memory management unit) 2-3) MMU fetches PTE from page table in cache/memory 4) MMU sends physical address to cache/memory 5) Cache/memory sends data word to processor 25 Address Translation: Page Fault Exception Page fault handler 4 2 CPU Chip PTEA Victim page 1 5 VA PTE Cache/ CPU MMU Disk 7 3 Memory New page 6 1) Processor sends virtual address to MMU 2-3) MMU fetches PTE from page table in cache/memory 4) Valid bit is zero, so MMU triggers page fault exception 5) Handler identifies victim (and, if dirty, pages it out to disk) 6) Handler pages in new page and updates PTE in memory 7) Handler returns to original process, restarting faulting instruction 26 How fast is translation? How many physical memory accesses are required to complete one virtual memory access? Translation Lookaside Buffer (TLB) Small hardware cache in MMU just for page table entries e.g., 128 or 256 entries Much faster than a page table lookup in memory. In the running for "un/classiest name of a thing in CS" 27 TLB Hit CPU Chip TLB 2 PTE VPN 3 1 VA PA CPU MMU 4 Cache/ Memory Data 5 A TLB hit eliminates a memory access 28 TLB Miss CPU Chip TLB 4 2 PTE VPN 1 3 VA PTEA CPU MMU Cache/ PA Memory 5 Data 6 A TLB miss incurs an additional memory access (the PTE) Fortunately, TLB misses are rare.