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PARS-Mitteilungen 2015.Pdf GESELLSCHAFT FÜR INFORMATIK E.V. PARALLEL-ALGORITHMEN, -RECHNERSTRUKTUREN UND -SYSTEMSOFTWARE PARS INFORMATIONSTECHNISCHE GESELLSCHAFT IM VDE I n h a l t 26. PARS-Workshop Potsdam (Full Papers) ........... 3 PARS (Berichte, Aktivitäten, Satzung)................. 153 ARCS 2016 (Nürnberg, 4. – 7. April 2016) ................... 162 12. PASA-Workshop 2016 (Nürnberg, 4. – 5. April 2016) ........................................ 164 Aktuelle PARS-Aktivitäten unter: http://fg-pars.gi.de/ Computergraphik von: Georg Nees, Generative Computergraphik MITTEILUNGEN Nr. 32, September 2015 (Workshop 2015) ISSN 0177-0454 PARS-Mitteilungen Gesellschaft für Informatik e.V., Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware Offizielle bibliographische Bezeichnung bei Zitaten: Mitteilungen - Gesellschaft für Informatik e. V., Parallel-Algorithmen und Rechnerstrukturen, ISSN 0177 - 0454 PARS-Leitungsgremium: Prof. Dr. Helmar Burkhart, Univ. Basel Dr. Andreas Döring, IBM Zürich Prof. Dr. Dietmar Fey, Univ. Erlangen Prof. Dr. Wolfgang Karl, stellv. Sprecher, Univ. Karlsruhe Prof. Dr. Jörg Keller, Sprecher, FernUniversität in Hagen Prof. Dr. Christian Lengauer, Univ. Passau Prof. Dr.-Ing. Erik Maehle, Universität zu Lübeck Prof. Dr. Ernst W. Mayr, TU München Prof. Dr. Wolfgang E. Nagel, TU Dresden Dr. Karl Dieter Reinartz, Ehrenvorsitzender, Univ. Erlangen-Nürnberg Prof. Dr. Hartmut Schmeck, Univ. Karlsruhe Prof. Dr. Peter Sobe, HTW Dresden Prof. Dr. Theo Ungerer, Univ. Augsburg Prof. Dr. Rolf Wanka, Univ. Erlangen-Nürnberg Prof. Dr. Helmut Weberpals, TU Hamburg Harburg Die PARS-Mitteilungen erscheinen in der Regel einmal pro Jahr. Sie befassen sich mit allen Aspekten paralleler Algorithmen und deren Implementierung auf Rechenanlagen in Hard- und Software. Die Beiträge werden nicht redigiert, sie stellen die Meinung des Autors dar. Ihr Erscheinen in diesen Mitteilungen bedeutet keine Einschränkung anderweitiger Publikation. Die Homepage http://fg-pars.gi.de/ vermittelt aktuelle Informationen über PARS. GESELLSCHAFT FÜR INFORMATIK E.V. PARALLEL-ALGORITHMEN, -RECHNERSTRUKTUREN UND -SYSTEMSOFTWARE PARS INFORMATIONSTECHNISCHE GESELLSCHAFT IM VDE CALL FOR PAPERS 26. PARS - Workshop am 7.-8. Mai 2015 Potsdam http://fg-pars.gi.de/workshops/pars-workshop-2015/ Ziel des PARS-Workshops ist die Vorstellung wesentlicher Aktivitäten im Arbeitsbereich von PARS und ein damit verbundener Gedankenaustausch. Mögliche Themenbereiche sind: Parallele Algorithmen (Beschreibung, Komplexität, Anwendungen) Parallele Rechenmodelle und parallele Architekturen Parallele Programmiersprachen und Bibliotheken Werkzeuge der Parallelisierung (Compiler, Leistungsanalyse, Auto-Tuner) Parallele eingebettete Systeme / Cyber-Physical Systems Software Engineering für parallele und verteilte Systeme Multicore-, Manycore-, GPGPU-Computing und Heterogene Architekturen Cluster Computing, Grid Computing, Cloud Computing Verbindungsstrukturen und Hardwareaspekte (z. B. rekonfigurierbare Systeme) Zukünftige Technologien und neue Berechnungsparadigma für Architekturen (SoC, PIM, STM, Memristor, DNA-Computing, Quantencomputing) Parallelverarbeitung im Unterricht (Erfahrungen, E-Learning) Methoden des parallelen und verteilten Rechnens in den Life Sciences (z.B.Bio-, Medizininformatik) Die Sprache des Workshops ist Deutsch und Englisch. Für jeden Beitrag sind maximal 10 Seiten vorgesehen. Die Workshop-Beiträge werden als PARS-Mitteilungen (ISSN 0177-0454) publiziert. Es ist eine Workshopgebühr von ca. 100 € geplant. Termine: Beiträge im Umfang von 10 Seiten (Format: GI Lecture Notes in Informatics, nicht vor-veröffentlicht) sind bis zum 16. März 2015 in elektronischer Form unter folgendem Link einzureichen: http://www.easychair.org/conferences/?conf=pars2015 Benachrichtigung der Autoren bis 13. April 2015 Druckfertige Ausarbeitungen bis 31. August 2015 (nach dem Workshop) Programmkomitee: H. Burkhart, Basel • S. Christgau, Potsdam • A. Döring, Zürich • T. Fahringer, Innsbruck • D. Fey, Erlangen W. Heenes, Darmstadt • V. Heuveline, Heidelberg • R. Hoffmann, Darmstadt • W. Karl, Karlsruhe J. Keller, Hagen • C. Lengauer, Passau • E. Maehle, Lübeck • E. W. Mayr, München • F. Meyer auf der Heide, Paderborn • W. E. Nagel, Dresden • M. Philippsen, Erlangen • K. D. Reinartz, Höchstadt H. Schmeck, Karlsruhe • B. Schnor, Potsdam • P. Sobe, Dresden • T. Ungerer, Augsburg • R. Wanka, Erlangen • H. Weberpals, Hamburg Nachwuchspreis: Der beste Beitrag, der auf einer Diplom-/Masterarbeit oder Dissertation basiert, und von dem Autor/der Autorin selbst vorgetragen wird, wird auf dem Workshop von der Fachgruppe PARS mit einem Preis (dotiert mit 500 €) ausgezeichnet. Co-Autoren sind erlaubt, der Doktorgrad sollte zum Zeitpunkt der Einreichung noch nicht verliehen sein. Die Bewerbung um den Preis erfolgt durch E-Mail an die Organisatoren bei Einreichung des Beitrages. Veranstalter: GI/ITG-Fachgruppe PARS, http://fg-pars.gi.de Organisation: Prof. Dr. Bettina Schnor, Institut für Informatik Universität Potsdam, 14482 Potsdam, Germany Tel.: +49-331-977-3120, Fax: +49-331-977-3122, E-Mail: [email protected] Prof. Dr. Jörg Keller (PARS-Sprecher), Fakultät für Mathematik und Informatik, LG Parallelität und VLSI FernUniversität in Hagen, 58084 Hagen, Germany Tel.: +49-2331-987-376, Fax: +49-2331-987-308, E-Mail: [email protected] 3 26. PARS-Workshop (Full Papers) Seite Novel Image Processing Architecture for 3D Integrated Circuits .............................................. 5 Benjamin Pfundt, Marc Reichenbach, Dietmar Fey and Christopher Söll A run-time reconfigurable NoC Monitoring System for performance analysis and debugging Support ........................................................................................................................... 16 Erol Koser and Benno Stabernack A Proximity Scheme for Instruction Caches in Tiled CMP Architectures .............................. 26 Tareq Alawneh, Chi Chi, Ahmed Elhossini and Ben Juurlink Particle-in-Cell algorithms on DEEP: The iPiC3D case study ................................................... 38 Anna Jakobs, Anke Zitz, Norbert Eicker and Giovanni Lapenta High performance CCSDS image data compression using GPGPUs for space applications . 49 Sunil Chokkanathapuram Ramanarayanan, Kristian Manthey and Ben Juurlink Parallelization of the Particle-in-cell-Code PATRIC with GPU-Programming ...................... 59 Jutta Fitzek Real-Time Vision System for License Plate Detection and Recognition on FPGA .................. 69 Farid Rosli, Ahmed Elhossini and Ben Juurlink Extended Pattern-based Parallelization Approach for Hard Real-Time Systems and its Tool Support ........................................................................................................................ 80 Alexander Stegmeier, Martin Frieb and Theo Ungerer Parallelisierung von Embedded Real-Time Systemen — Strategien und Herausforderungen in industriellen Migrationsprojekten ........................................................ 89 Marwan Abu-Khalil Parallel Symbolic Relationship-Counting .................................................................................. 101 Andreas Doering Parallel Processing for Data Deduplication ............................................................................... 109 Peter Sobe, Denny Pazak and Martin Stiehr Energy-aware mixed precision iterative refinement for linear systems on GPU-accelerated multi-node HPC clusters ............................................................................... 119 Martin Wlotzka and Vincent Heuveline Test@Cloud — A Platform for Test Execution in the Cloud .................................................. 131 Steffen Limmer, Alexander Ditter, Dietmar Fey, Matthias Pruksch, Christopher Braun, Florian Drescher and Martin Beißer-Dresel Quantifying Performance and Scalability of the Distributed Monitoring Infrastructure SLAte ................................................................................................................... 141 Marcus Hilbrich and Ralph Müller-Pfefferkorn Automatic Sorting of Bulk Material: An Example from the Industry ................................... 152 Georg Maier 4 Novel Image Processing Architecture for 3D Integrated Circuits Benjamin Pfundt1, Marc Reichenbach1, Christopher Soll¨ 2, Dietmar Fey1 1Chair of Computer Architecture Department of Computer Science 2Institute for Electronics Engineering Department of Electrical, Electronic and Communication Engineering Friedrich-Alexander-University Erlangen-Nurnberg¨ (FAU), Germany fbenjamin.pfundt, marc.reichenbach, christopher.soell, [email protected] Abstract: Utilizing highly parallel processors for high speed embedded image pro- cessing is a well known approach. However, the question of how to provide a suf- ficiently fast data rate from image sensor to processing unit is still not solved. As Trough-Silicon-Vias (TSV), a new technology for chip stacking, become available, parallel image transmission from the image sensor to processing unit is enabled. Nev- ertheless, the usage of a new technology requires architectural changes in the pro- cessing units. With this technology at hand, we present a novel image preprocessing architecture suitable for image processing in 3D chips stacks. The architecture was de- veloped in parallel with a customized image sensor to make a real assembly possible. It is fully functionally verified and layouted for a 150 nm process. Our performance estimation shows a processing speed of 770 up to 14.400 fps (frames per second) for 5 × 5 filters.
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