INTERFACIAL REACTION BETWEEN SAC305 and SAC405 LEAD-FREE SOLDERS and ELECTROLESS NICKEL/IMMERSION SILVER (Enimag) SURFACE FINISH

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INTERFACIAL REACTION BETWEEN SAC305 AND SAC405 LEAD-FREE SOLDERS AND ELECTROLESS NICKEL/IMMERSION SILVER (ENImAg) SURFACE FINISH

RABIATUL ADAWIYAH BINTI MOHAMED ANUAR

UNIVERSITI TUN HUSSEIN ONN MALAYSIA INTERFACIAL REACTION BETWEEN SAC305 AND SAC405 LEAD-FREE SOLDERS AND ELECTROLESS NICKEL/IMMERSION SILVER (ENImAg) SURFACE FINISH

RABIATUL ADAWIYAH BINTI MOHAMED ANUAR

A thesis submitted in fulfilment of the requirement for the award of the Degree of Master of Mechanical Engineering

Faculty of Mechanical and Manufacturing Engineering Universiti Tun Hussein Onn Malaysia

MAY 2017

Dedicated to my beloved father and mother who taught me to trust in Allah, love, encouragement and prays of day and night make me able to get such success.

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ACKNOWLEDGEMENT

In the name of Allah, Most Gracious, Most Merciful Praise is to Allah, the Cherisher and Sustainer of the World and Master of the day of Judgement. My prayers for my beloved parents and family who gave countless sacrifice and did every effort in order to nurture me and provided the highest moral values. First and foremost I want to thank my advisor Dr. Saliza Azlina Binti Osman. It has been an honour to be her first Master student. I would like to express my sincere appreciation for her guidance, support, patience and encouragement throughout my research. I also appreciate all her contributions of time, ideas, and funding to make my Master experience more productive. Without her suggestions and criticisms, this thesis would not be as presented now. I am also highly appreciate the cooperation and guidance from technicians in Material and Science Laboratory for providing the technical support needed to complete this work. Lastly, I would like to thank my lab mates for supporting me to complete this study and encouragement which have kept me confident and motivated.

ABSTRACT

The different surface finish and solder size on printed circuit board strongly affect the formation of intermetallic compounds (IMCs) and solder joint reliability. Among of various surface finish in the electronic industry, electroless nickel/immersion gold is the most popular at the moment. However, because their black pad issues, electroless nickel/immersion silver (ENImAg) was developed as an alternative surface finish. Therefore, the effect on an interfacial reaction between lead-free solder and ENImAg surface finish using different solder ball size (Ø300µm, Ø500µm and Ø700µm) was investigated. All samples were subjected to an aging process with different aging times. The characterizations of IMC formation were examined by image analyzer, scanning electron microscopy and energy dispersive x-ray. The results showed that ENImAg finish was free from the black pad nickel. Subsequently, the solder ball size has a significant effect on the IMC formation and fracture surface of as-reflowed and aged solder joint. The IMC thickness of larger solder balls was found to be thicker (1.74 µm) than smaller solder balls (1.32 µm) during soldering. In contrast to aged solder joints, the smaller solder ball produced thicker (3.51 µm) IMC compared to bigger solder balls (2.47 µm). Furthermore, the fracture surface of smaller solder ball size showed ductile mode for both reflowed and aged solder joints. In addition, the solder joint on ENImAg surface finish displayed a thinner layer and smaller grain sizes compared to solder joint on bare copper.

ABSTRAK

Kemasan permukaan dan saiz bebola yang berbeza ke atas papan litar bercetak memberi kesan terhadap pembentukan sebatian antara logam (IMC) dan kebolehpercayaan penyambungan pateri. Antara pelbagai kemasan permukaan dalam industri elektronik, nikel tanpa elektrik/rendaman emas adalah yang paling popular pada masa ini. Bagaimanapun, disebabkan oleh isu pad hitam, nikel tanpa elektrik/rendaman perak (ENImAg) dihasilkan sebagai alternatif kemasaan permukaan. Oleh itu, kesan terhadap tindak balas antara muka di antara pateri bebas plumbum dan kemasan permukaan ENImAg bersama-sama dengan saiz bebola pateri yang berbeza iaitu Ø300µm, Ø500µm and Ø700µm telah dijalankan. Semua sampel melalui proses penuaan dengan masa penuaan yang berbeza. Ciri-ciri pembentukan IMC telah dianalisis dengan menggunakan penganalisis imej, mikroskop imbasan electron (SEM) dan tenaga serakan x-ray. Hasil keputusan menunjukkan bahawa, kemasan ENImAg didapati bebas daripada pad hitam nikel. Seterusnya, saiz bebola pateri mempunyai kesan yang ketara terhadap pembentukan IMC dan kekuatan ricih selepas proses pengaliran semula dan penuaan. Bola pateri yang bersaiz besar mempunyai ketebalan (1.74 µm) IMC yang lebih tebal berbanding bebola pateri bersaiz kecil (1.32 µm) ketika proses pengaliran semula. Berbeza daripada bebola pateri yang terdedah pada suhu penuaan, bebola pateri yang lebih kecil menghasilkan ketebalan (3.51 µm) IMC yang lebih tebal berbanding bebola pateri yg bersaiz besar (2.47 µm). Tambahan pula, selepas proses pengaliran semula dan penuaan, permukaan patah untuk bebola pateri yan bersaiz kecil menunjukkan mod mulur. Tambahan lagi, penyambungan pateri ke atas kemasan permukaan ENImAg menghasilkan IMC yang nipis, dan saiz bijian yang kecil berbanding penyambungan pateri ke atas tembaga.

CONTENTS

DECLARATION i DEDICATION ii ACKNOWLEDGEMENTS iii ABSTRACT iv ABSTRAK v CONTENTS vi LIST OF TABLES x LIST OF FIGURES xii LIST OF SYMBOLS AND ABBREVIATIONS xxiv LIST OF APPENDICES xxvi CHAPTER 1 INTRODUCTION 1 1.1 Introduction 1 1.2 Field of research 2 1.3 Problem statement 3 1.4 Objectives 3 1.5 Scopes of the research 4 1.6 Structure of the thesis 4 CHAPTER 2 LITERATURE REVIEW 5 2.1 Electronic packaging 5 2.1.1 Level of packaging 6 2.2 Interconnection in integrated circuit (IC) 7 2.2.1 Flip chip packaging 8

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2.3 Surface finish metallurgy 10 2.3.1 Hot-air solder levelling (HASL) 12 2.3.2 Organic solderability preservatives (OSP) 13 2.3.3 Electroless nickel/immersion gold (ENIG) 15 2.3.4 Electroless nickel/electroless palladium/ immersion gold (ENEPIG) 20 2.3.5 Immersion silver (ImAg) 23 2.3.6 Immersion tin (ImSn) 26 2.4 Soldering 29 2.4.1 Soldering technique 29 2.4.1.1 Hand soldering 29 2.4.1.2 Wave soldering 30 2.4.1.3 Reflow soldering 32 2.4.2 Lead-free solders 33 2.4.2.1 Tin-silver-copper (SAC) lead-free Solders 35 2.4.3 Solderability and wettability of solders 39 2.5 Intermetallic compound (IMC) 41 2.5.1 Effect of reflow temperature and time on interfacial intermetallic compounds (IMCs) 44 2.5.2 Effect of solder size and volume on intermetallic compounds (IMCs) 46 2.5.3 The kinetic and morphology of IMC growth 48 2.6 Fick’s law 50 2.7 Mechanical reliability testing 54 2.7.1 Effect of solder size on mechanical properties of solder joint 59 2.8 Summary 61

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CHAPTER 3 RESEARCH METHODOLOGY 62 3.1 Introduction 62 3.2 Sample preparation 64 3.3 Optimizing stable solution 64 3.3.1 Pre-treatment of substrate material 66 3.3.2 Plating equipment preparation 67 3.3.3 Electroless nickel plating 68 3.3.4 Immersion silver 68 3.4 Reflow soldering 69 3.4.1 Flux deposition 69 3.4.2 Solder ball preparation 70 3.4.3 Reflow soldering process 70 3.5 Isothermal aging 71 3.6 Characterization of the intermetallic compounds 72 3.6.1 Characterization of cross-sectional area 73 3.6.2 Characterization of top surface 74 3.7 Single-lap shear testing 75 3.8 Intermetallic compound (IMC) determination 76 3.9 Summary 78 CHAPTER 4 RESULTS AND DISCUSSION 79 4.1 Introduction 79 4.2 Optimization of electroless nickel/immersion silver solution 80 4.3 Surface morphology of intermetallic compound after reflow soldering 85 4.3.1 Effect of solder volume on bare copper 87 4.3.2 Effect of solder volume on ENImAg surface finish 94

4.4 Surface morphology of intermetallic compound after isothermal aging 103 4.4.1 Effect of solder volume of SAC305 and SAC405 on bare copper 104 4.4.2 Effect of solder volume of SAC305 and SAC405 on ENImAg surface finish 116 4.5 Mechanical testing (single-lap shear test) 130 4.5.1 Single-lap shear test of SAC305 and SAC405 on bare copper 131 4.5.2 Single-lap shear test of SAC305 and SAC405 on ENImAg surface finish 140 4.6 Summary 147 CHAPTER 5 CONCLUSION AND RECOMMENDATIONS 148 5.1 Conclusions 148 5.2 Future works and recommendations 149 REFERENCES 150 APPENDIX 170

LIST OF TABLES

2.1 The advantages and disadvantages of flip chip 10 2.2 The example of tin-silver-copper and tin copper alloys 32 2.3 Selected lead-free binary alloys 35 2.4 Liquidus and reflow temperatures SAC alloy 37 2.5 The range of contact angle (deg) with the relative wettability 40 2.6 Intermetallic compounds formation (IMC) and incompatibility between solder and common substrates 41 3.1 Different types of pre-treatment process 65 3.2 Different types of silver solution with immersion time 65 3.3 Nickel plating bath solution 68 3.4 Immersion silver plating bath solution 69 3.5 Example of weight percentages calculation 77 3.6 Atomic weight of elements 77 3.7 Weight percentage of predicted IMCs 77 3.7 Continued 78

4.1 EDX spectrum data of (Cu,Ni)6Sn5 98

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LIST OF FIGURES

2.1 Schematic diagram of the electronic packaging hierarchy 7 2.2 Schematic diagram of first level interconnect (chip pad to package leads) and their types of interconnection technologies 8 2.3 Typical flip chip Ball Grid Array (BGA) package 10 2.4 Comparison market share of surface finishes between 2003 and 2007 11 2.5 Printed circuit board with lead free HASL surface finish 12 2.6 Process flow of the hot air solder levelling (HASL) 13 2.7 Schematic diagram of the hot air solder levelling (HASL) technique 13 2.8 Printed circuit board with organic solderability preservatives (OSP) 14 2.9 Process flow of the organic solderablity preservative (OSP) 15 2.10 Printed circuit board with electroless nickel/ immersion gold (ENIG) 16

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2.11 Illustration of ENIG formation 16 2.12 Process flow of Electroless Nickel/Immersion Gold (ENIG) 18 2.13 Bad wetting of plated through hole (PTH) on printed circuit boards 19 2.14 SEM image black line pad morphology with mud crack appearance 19 2.15 Schematic diagram of the fracture 20 2.16 SEM image of N-P surface after removing gold layer (a, b) showing the black pad (black line nickel) with infirm solder joint performance and (c, d) negligible corrosion attack in Ni layer with good solder joint performance 20 2.17 Electroless nickel/electroless palladium/ immersion gold (ENEPIG) standard board 21 2.18 The schematic layer of ENEPIG surface finish 22 2.19 (a) The PdP deposition over nickel and (b) pure Pd deposition over nickel 23 2.20 Printed circuit board with immersion silver (ImAg) 24 2.21 Process flow of immersion silver (ImAg) 25 2.22 Cross section SEM images of the Sn-3.5Ag- 0.7Cu: (a) entire solder joint, (b) types of IMC layer, (c) and (d) top view at the interface. 26 2.23 Printed circuit board with immersion tin (ImSn) 27 2.24 Process flow of immersion tin (ImSn) 28

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2.25 Immersion tin whisker 28 2.26 The wave soldering process 31 2.27 Typical of solder reflow profile 33 2.28 Sn-rich corner of SAC alloys ternary phase diagram 37 2.29 Sn-Pb phase diagram 38 2.30 Sn-Ag-Cu ternary eutectic reaction 38 2.31 Schematic diagram of the solderable and protective finishes during the wetting and spreading of molten solder 40 2.32 Illustration of the interfacial reaction of SAC 305 /Cu. (a) dissolution of the copper substrate, (b) supersaturation reaction, (c) the formation

of Cu6Sn5, and (d) the formation of Cu3Sn layer

between Cu6Sn5 and Cu substrate 42 2.33 SEM images of Sn-3.9Ag-0.6Cu joint from top view 43 2.34 SEM image of SAC solder with the copper substrate (a) cross sectional IMC layers (b) top surface of IMC layers 44 2.35 The growth mechanism of IMC layer 45 2.36 The illustration of Cu-Sn IMC at several reflow

times: (a) formation of scallop Cu6Sn5, (b)

formation of Cu3Sn between Cu6Sn5 Cu substrate, and (c) increasing IMC layers with increasing reflow times 46 2.37 The interface of IMCs thickness with different sizes of solder balls: (a) 400 µm, (b) 300 µm

and (c) 200 µm 48

2.38 The position of IMC layer for both (Cu,Ni)6Sn5

and (Ni,Cu)3Sn4 (a) schematic diagram and (b) the SEM image of Sn-3.5Ag-0.7Cu/Ni interface 49 2.39 Cross section SEM images (a) Sn-3.5Ag and (b) Sn-4.0Ag-0.5Cu solder joint interface 50 2.40 Illustrated of IMC thickness measurement 53 2.41 The relationship between IMC thickness and aging time for total IMC 53 2.42 Schematic failure of BGA joint subjected to shear impact loading 55 2.43 Single-lap joint shear test (a) geometry of the single-lap solder joint, (b) optical microscope cross section view and (d) illustration of the fracture mode. 56 2.44 (a) The cross sectional view of solder joint and (b) fracture surface after shear test. 57 2.45 Types of failure mode categories. 58 2.46 Loading curve of both Sn3.5Ag0.5Cu and Sn3.5Ag solder balls after aging for 1, 16, 9 and 1 d with shear speed at 0.1mm/min 60 2.47 The shear strength of as-reflowed and aged Solder joint with different solder size 60 3.1 Flow chart of research methodology 63 3.2 (a) Plan view and (b) side view of cooper substrate with their dimension 64 3.3 The process of copper surface pre-treatment 66 3.4 Schematic of electroless plating process 67

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3.5 No-clean flux 69 3.6 The schematic diagram (a) top surface and (b) cross section of solder ball formation 70 3.7 Side view of shear testing sample 70 3.8 Carbolite HTF 1800 Furnace model 71 3.9 The temperature profile of reflow soldering 71 3.10 Memmert UN30 32L natural Conventional drying oven 72 3.11 Sample preparation of cross section characterization, (a) cutting area of the sample and, (b) side view of cross section 73 3.12 Image analyser, NIKON ECLIPSE LV150NL model 74 3.13 Hitachi SEM SU1510 74 3.14 Schematic of top surface method (a) before etching, and (b) after etching 75 3.15 Fison SEM sputter coater 75 3.16 (a) Universal material testing machine, LR30K model, and (b) direction of shear testing 76 4.1 XRD result of as-coated Cu/Ni-P layer with high phosphorous 80 4.2 Cross sectional view of Ni-P with Cu substrate 81 4.3 Top surface and cross sectional view SEM images of ENImAg surface (a,b) 8 minutes duration and (c,d) 12 minutes duration depostions 83 4.4 EDX spectrum of ENImAg finish 8 minutes deposition of ImAg 83

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4.5 XRD pattern of ENImAg surface finish for ImAg deposition (a) 8 minutes (b) 12 minutes and (c) combination of Cu/Ni-P (as-coated), 8 minutes, 12 minutes. 84 4.6 SEM images of top surface view (a) SAC/ ENImAg surface finish, (b) SAC/Cu and (c) Schematic diagram for two different location at the solder ball 86 4.7 (a) Illustration of Cu dissolved into the molten solder and (b) IMC formation after reflow at interface 87

4.8 EDX spectrum of Cu6Sn5 IMC formation 88 4.9 SEM images of top surface for SAC305/ Cu with solder size: (a, b) Ø300 µm, (c, d) Ø500 µm and (e, f) Ø700 µm 89 4.10 SEM images of top surface for SAC405/ Cu with solder size: (a, b) Ø300 µm, (c, d) Ø500 µm and (e, f) Ø700 µm 90 4.11 Intermetallic thickness of SAC305/Cu and SAC405/Cu after reflow soldering 91 4.12 Cross-sectional view of SAC305/Cu solder joint of different solder volume with solder size: (a, b) Ø300 µm (c, d) Ø500 µm and (e, f) Ø700 µm 92 4.13 Cross-sectional view of SAC405/Cu solder joint of different solder volume with solder size: (a, b) Ø300 µm (c, d) Ø500 µm and (e, f) Ø700 µm 93

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4.14 SEM images of top surface for SAC305/ ENImAg with solder size: (a, b) Ø300 µm, (c, d) Ø500 µm and (e, f) Ø700 µm 96 4.15 SEM images of top surface for SAC405/ ENImAg with solder size: (a, b) Ø300 µm, (c, d) Ø500 µm and (e, f) Ø700 µm 97

4.16 EDX spectrum of (Cu,Ni)6Sn5 IMC formation 98 4.17 Cross-sectional view of SAC305/ENImAg solder joint of different solder volume with solder size: (a, b) Ø300 µm (c, d) Ø500 µm and (e, f) Ø700 µm 99 4.18 Cross-sectional view of SAC305/ENImAg solder joint of different solder volume with solder size: (a, b) Ø300 µm (c, d) Ø500 µm and (e, f) Ø700 µm 100 4.19 Intermetallic thickness of SAC305/ENImAg and SAC405/ENImAg after reflow soldering 101 4.20 SEM images of top surface for SAC305/Cu with solder size Ø300 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 106 4.21 SEM images of top surface for SAC305/Cu with solder size Ø700 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 107 4.22 SEM images of top surface for SAC405/Cu with solder size Ø300 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h)

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2000 hours 108 4.23 SEM images of top surface for SAC405/Cu with solder size Ø700 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 109 4.24 Intermetallic thickness versus solder sizes (a) SAC305/Cu and (b) SAC405/Cu after isothermal aging 111 4.25 Cross-sectional view for SAC305/Cu with solder size Ø300 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 112 4.26 Cross-sectional view for SAC305/Cu with solder size Ø700 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 113 4.27 Cross-sectional view for SAC405/Cu with solder size Ø300 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 114 4.28 Cross-sectional view for SAC405/Cu with solder size Ø700 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 115 4.29 Interfacial Cu-Sn IMC growth kinetics on Cu substrates: (a) SAC305 solder (b) SAC405 solder 116 4.30 SEM images of top surface for SAC305/

ENImAg with solder size Ø300 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 119 4.31 SEM images of top surface for SAC305/ ENImAg with solder size Ø700 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 120 4.32 SEM images of top surface for SAC405/ ENImAg with solder size Ø300 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 121 4.33 SEM images of top surface for SAC305/ ENImAg with solder size Ø700 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 122 4.34 Cross-sectional images of SAC/ENImAg surface finish (a) before etching by using optical microscope and (b) after etching by using SEM 123 4.35 Interfacial Cu-Sn-Ni IMC on Cu/ENImAg substrates: (a) SAC305 and (b) SAC405 124 4.36 Cross-sectional view for SAC305/ENImAg with solder size Ø300 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 125 4.37 Cross-sectional view for SAC305/ENImAg with solder size Ø700 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h)

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2000 hours 126 4.38 Cross-sectional view for SAC405/ENImAg with solder size Ø300 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 127 4.39 Cross-sectional view for SAC405/ENImAg with solder size Ø700 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 128 4.40 Interfacial Cu-Sn IMC growth kinetics on ENImAg substrates: (a) SAC305 solder (b) SAC405 solder 130 4.41 Typical fracture surface after single-lap shear test 132 4.42 SEM images of fractures surface for SAC305/Cu after reflow with solder size: (a, b) Ø300 µm, (c, d) Ø500 µm and (e, f) Ø700 µm 133 4.43 SEM images of fractures surface for SAC405/Cu after reflow with solder size: (a, b) Ø300 µm, (c, d) Ø500 µm and (e, f) Ø700 µm 134 4.44 SEM images of fractures surface for SAC305/ Cu with solder size Ø300 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 136 4.45 SEM images of fractures surface for SAC305/ Cu with solder size Ø700 µm: (a, b) 250 hours

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(c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 137 4.46 SEM images of fractures surface for SAC405/ Cu with solder size Ø300 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 138 4.47 SEM images of fractures surface for SAC405/ Cu with solder size Ø700 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 139 4.48 SEM images of fractures surface for SAC305/ENImAg after reflow with solder size: (a, b) Ø300 µm, (c, d) Ø500 µm and (e, f) Ø700 µm 141 4.49 SEM images of fractures surface for SAC405/ENImAg after reflow with solder size: (a, b) Ø300 µm, (c, d) Ø500 µm and (e, f) Ø700 µm 142 4.50 SEM images of fractures surface for SAC305/ENImAg with solder size Ø300 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 143 4.51 SEM images of fractures surface for SAC305/ ENImAg with solder size Ø700 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 144 4.52 SEM images of fractures surface for SAC405/ ENImAg with solder size Ø300 µm: (a, b)

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250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 145 4.53 SEM images of fractures surface for SAC405/ ENImAg with solder size Ø700 µm: (a, b) 250 hours (c, d) 500 hours (e, f) 1000 hours and (g, h) 2000 hours 146

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LIST OF SYMBOLS AND ABBREVIATIONS

Ag - Silver Au - Gold Cu - Copper In - Indium Ni - Nickel P - Phosphorous Pb - Lead Pd - Palladium Sb - Antimony Sn - Tin Zn - Zinc BGA - Ball Grid Array CPU - Central Processing Unit DCA - Direct Chip Attach DIP - Dual in Line Package ECA - Electrical Circuit Assembly EDX - Energy Dispersive X-Ray ENEPIG - Electroless Nickel/Electroless Palladium/Immersion Gold ENIG - Electroless Nickel/Immersion Gold ENiImAg - Electroless Nickel/Immersion Silver FC - Flip Chip FESEM - Field Emission Scanning Electron Microscope

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HASL - Hot-Air Solder Levelling I/O - Input/Output IC - Integrated Circuit ImAg - Immersion Silver IMC - Intermetallic Compound ImSn - Immersion Tin JEDEC - Joint Electron Device Engineering Council JEIDA - Japan Electronic Industries Development Association MCM - Multi Chip Module NEMI - National Electronic Manufacturing Initiative OM - Optical Microscope OSP - Organic Solderability Preservative (OSP) PBB - Poly-Brominated Biphenyls PBDE - Poly-Brominated Diphenyl Ethers PCB - Printed Circuit Board PTH - Plated Through Hole PWB - Printed Wire Bond RoHS - Restriction of Hazardous Substance SAC - Tin-Silver-Cooper SEM - Scanning Electron Microscope SMD - Surface Mount Device SMT - Surface Mount Technology TAB - Tape Automated Bonding TCM - Thermal Conduction Module WEEE - Waste from Electrical and Electronic Equipment XRD - X-ray Diffraction

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LIST OF APPENDICES

APPENDIX TITLE PAGE

A SEM Images of Top Surface for SAC/Cu 170 B Cross-Sectional View for SAC/Cu 172 C SEM Images of Top Surface for SAC/ ENImAg 174 D Cross-Sectional View for SAC/ENImAg 176 E SEM Images of Fracture Surface for SAC/Cu 178 F SEM Images of Fracture Surface for SAC/ ENImAg 180 G EDX Spectrum of IMC Formation 182 H Graph of Single – Lap Shear Test 183 I Proceeding and Journal Paper 185

CHAPTER 1

INTRODUCTION

1.1 Introduction

In the current industrial world, electronic devices have connectivity with an electronic system, which is electro-mechanical structure called packaging. The electronic packaging concept has been used for more than one century in wide variety of technologies. This package is very important because without it, there would be no electronic devices produced these days. Electronic packaging technology is now widely used in the semiconductor industry. There is a rapid increase in the number of electronic packages using flip chip technology because their performance such as flip chip packages does not need peripheral space for the wire bonding with high frequency characteristics. It can also increase the number of input/output capacity and the power of connections in a smaller area. Today, electronic engineers are using the package to protect electronic devices and their interconnections. The increasing miniaturization of electronic component has challenged the researchers to investigate solder materials to meet the requirements of solder interconnects and obtain good joints between component and substrates. Driven by the current trend of smaller and thinner electronic products, the solder joint interconnection should become smaller as well. The smaller of solder joint interconnection may influences the interfacial reactions and mechanical properties such as intermetallic (IMC) thickness layer, morphology and solder joint strength. The presence of IMC layer is necessary for bonding between solder balls and substrates however, the thickness of IMC layer can affect the solder joint strength at interface. 2

1.2 Field of research

Nowadays, many users are using products based on electronic components. With the continuous development of the mobile phones, radios, televisions, computers and laptops, digital camcorders, digital cameras, and other electronic equipment based product has caused the flip chip packaging to operate in full action. Flip chip bonding technology was offers excellent performance with a shorter connection between the chip and the printed circuit board. In addition, the rating of input and output data is at the highest level and has smaller size than other methods. Solder reflow flip chip uses the solder ball as to connect between the chip and substrate. The printed circuit board will react with Sn in the solder ball to form intermetallic compound (IMC) layer during soldering process. The formation of IMC layer is desirable for necessary bonding because it is needed for the formation of solder joint. Furthermore, the brittleness of IMC layer makes it susceptible to mechanical failure even at low loads. Besides, the thickness of IMC layer can change the physical properties of material across the joint. It is because, the thicker IMC layer can cause the reliability problem of the solder joint. However, the selection of the substrate surface finish plays an important role to determine the characteristic of IMC formation. The substrate such as copper will oxidized and deteriorate if their surface unprotected. Therefore, coating deposition can act as a barrier and provide a solderable surface in the process of soldering the component to the printed circuit board (PCB). Many studies have been conducted on the joint reliability and interfacial reaction between Pb-free solders and various surface finish layers such as Cu, Au/Ni/Cu and electroless nickel-immersion gold (ENIG), during reflow and aging process. Generally, the most popular lead-free surface finishes used in electronic industries are electroless nickel/immersion gold (ENIG) and ENEPIG (electroless Pd added), immersion silver (ImAg), immersion tin (ImSn) and organic solderability preservative (OSP). Therefore, the reliability of solder joint must have solderable surface to form good solder connection between solder balls and substrates.

1.3 Problem statement

Since July 2006, the legislative of Restriction of Hazardous Substance (RoHS) was banned the use of tin-lead (Sn-Pb) and shift to lead-free solder due to human health and environmental problem. Lead usage is dangerous since it can cause lead poisoning when it enters the body through inhalation and feeding contact such as direct contact to mouth and skin contact to nose, eyes and skin lesions. Sn-Ag-Cu (SAC) is one of the lead-free solder family that can offer better alternative to the electronic industries due to reliability, good solderability and mechanical properties. The demands of surface finish have become essential for printed circuit board when the industries were shifted to lead-free compliance. Electroless nickel/ immersion gold (ENIG) has been predominant in the industries since ENIG is designed as an excellent solderable surface and highly corrosion resistant. However, ENIG surface finish possess its own weakness such as high cost of gold metal and black pad issues. The black pad can occur due to the immersion gold plating bath during assembly process, can also lead to bad wetting area and even brittle solder joints. This issue has been a concern in electronic industry as it affects the reputation of ENIG which known excellent surface finish. Thus, it is proposed that electroless nickel- immersion silver (ENImAg) will be its alternative that can replace ENIG to overcome the stated problem. Therefore, interfacial reaction between SAC305 and SAC405 lead- free solders and electroless nickel-immersion (ENImAg) surface finish need to be investigated.

1.4 Objectives

The main objectives in this research are as follows: i) To examine the effect of ENImAg surface finish on interfacial reaction (intermetallics) formed at interface during soldering and isothermal aging. ii) To evaluate the effects of solder ball volume (ball size) on interfacial reactions in terms of thickness, type and morphology. iii) To observed the solder joint reliability in term of fracture mode between surface finish and lead-free solders.

1.5 Scopes of the research

The scopes of this study consists of the following tasks: i) Deposition of ENImAg surface finish on copper substrates using electroless and immersion plating process. As comparison, bare copper will be used. ii) Formation of solder joints between two lead-free solder alloys; Sn-3.0Ag- 0.5Cu (SAC305) and Sn-4.0Ag-0.5Cu (SAC405) in three different sizes of solder ball which are Ø300, Ø500 and Ø700 µm. iii) Conduct isothermal aging at 150C for different aging duration (250, 500, 1000 and 2000 hours). iv) Conduct mechanical test through shear testing. v) Characterization of IMC formed during reflow and isothermal aging using Optical Microscope (OM), Scanning Electron Microscope (SEM) and/or Field Emission Scanning Electron Microscope (FESEM), Energy Dispersive X-ray EDX and X-ray Diffraction (XRD).

1.6 Structure of the Thesis

This thesis consists of five chapters. Chapter one is an introduction that contains field of research, problem statement, objectives and scopes of the research. Chapter two presents the basic of electronic packaging, interconnection in integrated circuit (IC), surface finish, soldering techniques, intermetallic compound formation, Fick’s law and mechanical reliability. Chapter three describes the experimental procedures and soldering techniques as well as materials characterization preparation. Chapter four contains the results and discussion obtained from experimental work. Lastly, in chapter five, the conclusion and recommendation are presented based on the research work.

CHAPTER 2

LITERATURE REVIEW

2.1 Electronic packaging

Generally, electronic devices have a connection to an electronic system with electromechanical structure called ‘packaging’. The concept of electronic devices has been used for more than a century and electronic component would not exist without packaging. Packaging is a major area of interest within the field of electronic packaging technology. Electronic packaging is a housing and interconnection of integrated circuits (IC) to design electronic systems (Szendiuch, 2011). The function of electronic packaging is to protect electronic devices from the environment. At the same time, it also acts as powering, cooling and chip packaging (Rasmussen et al., 2003 & Martens, 2013). Integrated circuit has been an object of research since the 1950s (Pecht, 1991). IC packaging is the central connection of the process that produces these systems. It must be communicated with other IC chips in a circuit through an input/output (I/O) system of interconnects (Lau et al., 1998 & Cheng et al., 2011). This package will provide circuit support and protection, power distribution, heat dissipation, signal distribution, manufacturability and serviceability (Wong & McBride, 1994 & Tummala et al., 1997). Besides that, with the performance of electronic devices, electronic components are now designed in smaller sizes (Shnawah et al., 2012) and the number of inputs/outputs has been increasing with the advance made in chip integration (Pecht, 1991; Cheng et al., 2011; Tong, 2011). The increasing numbers of chip integration production also increase production of heat flux, where it is dissipated from the chip surface area (Pecht, 1991). In the future, electronic packaging will force the researchers to design most powerful and advanced technologies of electronics. 6

2.1.1 Level of packaging

Electronic system can be divided into a simple hierarchy that consists of packaging, printed circuit boards (PCBs) and systems. These systems have several levels starting with nil until fourth level as shown in Figure 2.1. Level zero has a thin circular wafer (chip) that consists of logic gates, transistors, and gate to gate interconnections. The first packages level is a chip carrier protection, where it can range from single-chip module to multi-chip module. Some examples can be seen in the chip barrier such as dual in line package (DIP) and thermal conduction module (TCM) for both single-chip and multi-chip, respectively. Electrical circuit assembly (ECA) can be referred as the second level of packaging. Currently, this stage consists of printed wiring board (PWB) or printed circuit board (PCB). For both first level and second level, solder is usually used to joint packages to PCB (Xu et al., 2015). Whereas, third level packages is the interconnection of circuit boards and power supplies to system or physical interface. The protective structure such as cabinet is also related with this level. On the other hand, ECA interconnection and large PCB are referred as backplane. When backplane, and cable joined together, it is known as a as a single cabinet. Lastly, when a few cabinets are merged together, fourth level will be created (Pecht, 1991; Lau et al., 1998; Harper, 2005). Interconnection between cabling systems such as central processing unit (CPU) is also called fourth level of packaging (Lau et al., 1998; Harper, 2005; Tong, 2011). Nowadays, circuit and requirement system of high performance, high reliability and low cost have caused greater demands for the packaging engineer to have excellent understanding of the existing packaging technologies.

Figure 2.1: Schematic diagram of the electronic packaging hierarchy (Lau et al., 1998).

2.2 Interconnection in integrated circuit (IC)

Electronic packaging is the method by which an integrated circuit is packaged in a modular form so that it can be used in the end product such as a cell phone, a laptop computer or even a smoke detector (Harper, 2005). Packaging technologies is now being developed to another standard of chip performance. For example, the Multi Chip Module (MCM) has substantial advantages over the old PWB interconnect approaches (Neugebauer, 1990). The chip to package assembly has three different interconnections such as wire bond (WB), tape automated bonding (TAB) and flip chip (FC) (Tummala, 2001) as shown in Figure 2.2. Today, flip chip technology is widely used in electronic packaging because it offers better performance of high speed system, self-alignment during die joining, productivity enhancement over manual wire bonding and low lead inductance (Ramesham, 2014).

Figure 2.2: Schematic diagram of first level interconnect (chip pad to package leads) and their types of interconnection technologies (Tummala, 2001).

2.2.1 Flip chip packaging

In electronic packaging, wafer scale integration, assembly of discrete packages on printed wiring boards, multi-chip module, and higher packaging levels are the material requirements for the next generation of electronic packaging strategies. It is also related with the performance and cost of the future electronic system. Besides, this type of future will be strongly depending on the right choice of the packaging approach (Neugebauer, 1990). Now, electronic packaging is replacing the older technology, from wire bonding to flip chip interconnection. Flip chip interconnect technology is the direct electrical connection to approaches, where the silicon die or chip is connected face down to the substrates, circuit boards or carriers, by means of conductive bumps on the chip bond pads. According to Lau (1994) & Lau et al. (1998), flip chip also known as Controlled Collapse Chip Connection or Direct Chip Attach (DCA). Flip chip packaging is considered as the first level interconnect technology because the greatest input/output flexibility can be achieved by it. Besides that, it also offers the best performance with shorter connections between chips and circuit boards (Lau et al., 1998). Using the wire bonding connections is limited to the parameter of 9

the die. Hence, the connection can be used the whole area of the die by using flip chip. Additionally, these connections have advantages since they are using solder bump. In connection to the drop of chip voltages and increasing current requirements, flip chip has the ability to reduce voltage drop by distributing the power and grounding directly to the device’s core with area array solder bumps (Elenius & Lee, 2000). Other advantages of flip chip are better performance and reliability, cost over other packaging methods as well as its widening availability of flip chip materials, equipment and services (Riley, 1997 & Ramesham, 2014). Figure 2.3 displays the schematic of a flip chip component. Solder bump is applied to the integrated circuit (IC) to provide interconnection for the flip chip and to activate circuitry on the IC toward the substrate. For the first step processing, the flip chip assembly forms all interconnections between IC and the substrate. Then underfill or knowns as polymer material is applied between the IC and substrate to enhance package reliability, integrity and reliability of the assembly when subjected to mechanical shock or bending test (Nah et al., 2011). Solder interconnects can produce the electrical and mechanical connection between chip bond and the carrier bond pad. This technique is known as flip chip bonding technique. In the meantime, in order to ensure a reliability interconnect structure, the bump must consist of solder with various types of surface metallization. For reflow soldering, flip chip interconnects can be made simultaneously for all components in a single high speed process (Chen et al., 2010). Table 2.1 presents the summary of advantages and disadvantages of flip chip package (Elenius & Levine, 2000 & Ramesham, 2014).

Figure 2.3: Typical flip chip Ball Grid Array (BGA) package (Baldwin, 2005).

Table 2.1: The advantages and disadvantages of flip chip (Pascariu et al., 2003)

Advantages Disadvantages

1. Reduces signal inductance 1. Thermal expansion often does not match between the semiconductor chips and the 2. The contact pads are distributed over the substrate. entire chip surface from confined to the periphery. 2. Possible to increase in thermal resistance.

3. Afford to connect all the input/output in one 3. Lower design change flexibility single step. 4. Higher production process cost 4. Enhanced heat dissipated because of possibility of attachment of heat sink to backside of chip.

5. Higher signal density

2.3 Surface finish metallurgy

The consideration of surface finish on the PCB is perhaps the most essential selection material decision made for the electronic assembly. Surface finish heavily influences the cost, manufacturability, quality and reliability of the final product (Milad, 2008 & Pun et al., 2014). The function of surface finish is to protect the exposed copper circuitry and provide a solderable surface in assembling (soldering) the components to 11

the PCB (Milad et al., 2007 & Pun et al., 2014). However, surface finish as the final finish is designed to protect copper from oxidation and also acts as barrier layer to minimize growth of the IMC layer. Moreover, there are great expectations for the surface finish to meet the criteria such as solderability, contact performance, wire bondability and corrosion resistance which have to be achieved at lower cost (Milad et al., 2007). Nowadays, many surface finishes are now sharing the market and each has a characteristic that make it interesting for certain applications. The selection of a surface finish will rely on balancing different factors including performance, reliability and cost. Figure 2.4 shows the comparison market share of surface finish between 2003 and 2007 (Schueller, 2005). The vital aspect and characteristic of each surface finishes will be discussed and the figure will resembled which product that suits the characteristics of the finish and which of them not critical to the product application.

Surface Finishes Market (2003) Surface Finishes Market (2007) ENIG, 8% OSP, ENIG, 18% 14%

Immersion OSP, Tin, 2% 34%

HASL + Electrolytic, Immersion 18% Silver, 2%

HASL + Electrolytic, Immersion Immersion 70% Silver, 17% Tin, 17%

Figure 2.4: Comparison market share of surface finishes between 2003 and 2007 (Schueller, 2005).

2.3.1 Hot-air solder levelling (HASL)

Hot-Air Solder Levelling (HASL) is an under srutiny because of environmental and safety issues such as hazardous waste or lead expose, technology limitation (fine-pitch devices assembly), and equipment maintenance expenses to name a few (Parquet, 1995). HASL is widely used in North America, Europe and most of Asian countries except Japan during tin lead era (Sweatman, 2009). Since the early 1980s, this method was widely used for professional printed circuit board. Figure 2.5 shows the printed circuit board with lead free HASL surface finish. According to Choon (2003), the PCB is immersed from its edge, in a pot of molten solder, withdrawn, and then excess solder is blown off using strong blast of hot air. This process is known as solder levelling.

Figure 2.5: Printed circuit board with lead free HASL surface finish (Wright, 2015).

The flow process of HASL consists of a pre-clean cycle, preheating, flux coating, solder coating, levelling with hot air knives, cooling, and a post-clean section as shown in Figure 2.6. Meanwhile, Figure 2.7 shows a schematic diagram of the HASL process (Sweatman, 2009). Besides that, HASL gives the entire protection to copper surface of a panel and products such as solder mask over bare copper (SMOBC). It also has an excellent shelf life, shorter solder wetting times at assembly, high mechanical durability, and formation of intermetallic bond before the printed 13

wiring board assembly process. However, HASL is also popular to be known as roll tinning where a very thin layer of solder will be transferred to the panel from hot tinned rolls (Fellman, 2005).

Figure 2.6: Process flow of the hot air solder levelling (HASL) (Fellman, 2005).

Figure 2.7: Schematic diagram of the hot air solder levelling (HASL) technique (Sweatman, 2009).

2.3.2 Organic solderability preservatives (OSP)

Organic Solderability Preservatives (OSP) are getting famous as an alternative to hot air solder levelling (HASL) surface finish as shown in Figure 2.8. One of the disadvantage of HASL process is, it allows the Cu-Sn intermetallic growth where this process causes the thermal shock to degrade the printed circuit boards (PCBs) completely. Besides that, HASL also causes brittle solder joints and poor solderability. 14

Therefore, the use of OSP surface finish can helps to eliminates thermal shock and Cu- Sn intermetallic compound, and increase the solder joint reliability. The other advantages of OSP are low cost, excellent in surface co-planarity of the coated pad and excellent for fine pitch surface mount technology due to their thin thickness and even coating (Li, 1997). OSPs are normally azola based organic films. Azola is necessary in order to identify their volatility, decomposition temperature, existence of an organometallic polymer between the azola and a metal other than copper (Paw et al., 2008). There are several types of azola including benzotriazole, imidazoles, and benzimidazoles. However, benzimidazole is a one base of OSP that can cut the cost to 70% compare with HASL (Li, 1997). This type has a low temperature at 75˚C, the thickness of layer less than 10nm, can prevent copper tarnish and to allow one or two thermal reflow cycles (Tong et al., 2006).

Figure 2.8: Printed circuit board with Organic Solderability Preservatives (OSP) (Wright, 2015).

The substrate of the OSP is copper-clad using the subtractive method where the bare copper is coated with an organic sealant to prevent oxidation and exposure to the air. The thin layer of surface finish enables tight control in the z-axis and prevents opens due to co-planarity tolerances (Zarrow & Kopp, 1996). Generally, OSP surface finish is considered as a low cost option due to its simpler flow process compared to 15

HASL. It consists of four steps starting with cleaner, micro-etch, pre-dip and flood of OSP as shown in Figure 2.9.

Figure 2.9: Process flow of the organic solderablity preservative (OSP) (Wright, 2015).

2.3.3 Electroless nickel/immersion gold (ENIG)

Electroless Nickel/Immersion Immersion Gold (ENIG) was introduced in the late 1990s as final surface finish in the electronic industry as shown in Figure 2.10. ENIG is being recognised within the industry because it meets the needs for lead-free assembly. Other than that, it also offers coplanar surface for both solderable, excellent electrical contacting surface and aluminium wire bondable (Johal & Lamprecht, 2008 & Milad, 2008). ENIG is formed from the deposition of electroless - phosphorous on a catalysed copper surface, followed by a thin layer of immersion gold as shown in Figure 2.11 (Milad, 2008). Besides that, ENIG is designed to provide a highly corrosion resistant and excellent solderable surface (Long & Toscano, 2013). The other advantages of ENIG surface finish are longer shelf life, flat soldering surface for Surface Mount Technology (SMT) (Li, 2015) and its suitability for hot bar soldering and anisotropic conductive film (ACF) bonding (Johal & Lamprecht, 2008).

Figure 2.10: Printed circuit board with electroless nickel/immersion gold (ENIG) (Wright, 2015).

Figure 2.11: Illustration of ENIG formation (Slocum, 2006).

The ENIG deposition process is quite complex. A clean copper surface from solder mask residual that is also copper/tin intermetallic free is needed. Next, nickel layer is plated over copper, followed by gold plating over the nickel layer. Immersion gold entails nickel element to supply electrons that will be deposited on it. They also can lessen hydride generation and galvanic reactions (Milad, 2013). Electroless nickel process is an autocatalytic reduction process, where the aqueous metal ions are coated to a copper without path of external current (Sudagar et al., 2013 & Sapkal et al., 2015). The surface remains in contact with the electroless nickel solution as long as the reaction continued in this process. 17

Basically, the apparent element of the bath solution is nickel sulphate as the main source of nickel and sodium hypophosphite. While the source for both electrons that works for the deposition of the nickel and phosphorus is the reducing agent (Agarwala & Agarwala, 2003; Sudagar et al., 2013; Sapkal et al., 2015). Other elements of common crucial solution include complexing agent, stabilizers, chelating agents, and buffering agent (Schlesinger, 2011 & Milad, 2013). These solutions can maintain the stability of nickel solution and are responsible for the consistency of thickness layer. The important parameters during plating are the temperature and pH value to maintain a rate of deposition in particular life of the bath (Malecki & Ilnicka, 2000 & Mallory, 2009). Electroless has several advantages on the electroplating which include the quality of deposit such as physical and mechanical properties. Some of the properties are practicable on electroless such as solderability, high hardness, magnetic properties, amorphous, microcrystalline deposit, resistivity and low coefficient of friction. However, most applications of the auto-catalytic are depending on their wear and corrosion resistance (Agarwala & Agarwala, 2003). The desired properties can be vary by choosing the different temperature, pH value, and composition of the bath (Sudagar et al., 2013). Nickel layer is used to protect the copper from liquidation, perpetuate the reliability of the finish process, and protect them from cracking during test (Milad, 2013). Currently, nickel is co-deposited with phosphorous. For the circuit application, the common range of medium phosphorous used is 7 to 9 percent by weight. The content of phosphorous in electroless nickel can influence the behavior of the physical, mechanical and corrosion resistance properties of the coating. The amount of Ni-P can determine the microstructure of the coating either crystalline, amorphous, or both combination of the microstructure (Martyak, 1994). Currently, low and medium phosphorus level in electroless nickel process has a mixture of amorphous and microcrystalline nickel, while, the structure is fully amorphous when the phosphorus content is high (Guo et al., 2003; Keong et al., 2003; Sudagar et al., 2013). Based on 18

high Ni-P content, these coating have better corrosion resistant, very ductile, low porosity, low internal intrinsic stress and non-magnetic is as plated state as mentioned by Mallory (2009). Besides that, some fabricators concern about the low thickness of nickel layer because it is important to prevent nickel cracking. However, it can be seen that thin layer can cause black pad defect, whereas, thicker layer can prevent the black pad problem (Johal & Lamprecht, 2008). There are six steps of ENIG process which consist of clean/micro-etch, catalyst, electroless nickel, rinse, immersion gold and rinse/clean as shown in Figure 2.12. By comparing with other surface finish such as Organic Solderability Preservative (OSP) and Hot Air Solderability Levelling (HASL), ENIG is more expensive because the price of gold metal is higher compare to OSP and HASL. Besides, another problem which is ‘black pad’ (Lin et al., 2007) may lead to bad wetting including non-wetting and de-wetting also brittle solder joint as shown in Figure 2.13 (Bin & Yabing, 2012). Black pad defect is caused by nickel layer oxidation during immersion gold process, where it is formed between nickel and gold layer (Lin et al., 2007) as shown in Figure 2.14. The researcher found typical black pad morphology of nickel layer with ‘mud crack’ appearance on the surface solder joint with the bad wetting area and the nickel layer of bare PCB path (Li, 2015).

Figure 2.12: Process flow of electroless nickel/immersion gold (ENIG) (Johal & Lamprecht, 2008).

Figure 2.13: Bad wetting of plated through hole (PTH) on printed circuit boards (Li, 2015).

Figure 2.14: SEM image black line pad morphology with mud crack appearance (Li, 2015).

During the assembly process, a thin intermetallic with Sn atom was formed when Ni atom diffused into liquid Sn matrix. The phosphorous (P) did not take part in this reaction. P has great element concentration known as P-rich layer. The symptoms of black pad with solder joint often fractured at P-rich layer, which have brittleness property and poor wetting issues. The fracture may appear at interface between P-rich layer and Ni-Sn intermetallic layer (Yang et al., 2010). Many researchers had investigated the brittle failure mode and found a formation of Ni/Sn intermetallic compounds known as crystallographic species (Ni3Sn4). Besides, between Ni/Sn intermetallic and Ni-P layer, there are thin P-rich layer and Kirkendall void (Lee & Lee, 2006). Figure 2.15 shows the fracture location. Meanwhile, Figure 2.16 shows the SEM image of Ni-P surface after gold layer was removed.

Figure 2.15: Schematic diagram of the fracture (Yang et al., 2010).

Figure 2.16: SEM images of N-P surface after removing gold layer (a, b) showing the black pad (black line nickel) with infirm solder joint performance and (c, d) negligible corrosion attack in Ni layer with good solder joint performance (Lee & Lee, 2006).

2.3.4 Electroless nickel/electroless palladium/immersion gold (ENEPIG)

Electroless Nickel/Immersion Gold (ENIG) is popular in electronic industry. Nonetheless, due to its of disadvantages such as weak wire bonding performance and solder joint problems from black pack issues, ENEPIG is offered as an alternative to ENIG surface finish as shown in Figure 2.17. ENEPIG with high solder joint quality, 21

better performance and wire bondability was introduced in electronic industry (Ramos et al., 2011). It is expected to be inexpensive as the gold layer of lower thickness can be used (Pun et al., 2014). Using palladium (Pd) in ENEPIG surface finish, it can be developed to overcome weak wire bonding and solder joint problems (Fu et al., 2008). Pd layer between Ni and Au was introduced to be a barrier layer to prevent Ni atom liquidation during Au layer deposition (Hsiao, 2007).

Figure 2.17: Electroless nickel/electroless palladium/immersion gold (ENEPIG) standard board (Chaillot et al., 2013).

In addition, Pd layer was found to limit the corrosion of the nickel due to aggressive immersion gold process. It also allows both aluminium wire bonding and gold operation (Kao & Roberts, 2010; Ramos et al., 2011). In this surface finish, the function of Pd layer acts as a protection layer, where it can prevent from black pad problems, improve wire bonding ability and enlarge process window of bonding wire. Besides that, nickel performs as diffusion barrier layer to prevents inter-diffusion between copper and solder ball (Yoon, 2009). This way, it can prevent the gold layer from underneath layer oxidation and wetting ability when soldering (Fu et al., 2008). The thickness requirements of Ni/Pd/Au layer are Ni layer (3-6 µm), Pd layer (0.05- 0.30 µm) and Au layer (>0.030 µm), respectively. These thickness requirements do not accord to the assembly process of either tin lead or SAC. However, some of the reseachers suggested to reduce the thickness of Pd layer to 0.05 µm even if it is for 22

SnPb assembly process, with gold layer that also needs to be increased up to 0.15 µm (Chaillot et al., 2013). Figure 2.18 shows the metallic layers of ENEPIG surface finish. According to Pun et al. (2014), they was mentioned that the increasing of both Au layer and Pd layer does not improve solder joint reliability and wire bondability. Therefore, it is important to balance the Au and Pd thickness to optimize the reliability of both wire bonding and soldering. Besides the increasing Pd thickness (above 0.3 µm), this part will also result in significant reduction of shear strength with fracture mainly occurring at the Pd-Ni-Sn, and Cu-Ni-Sn intermetallic interface. ENEPIG surface finish has two types of Pd layer either using palladium phosphorous alloy (PdP), or as pure palladium. These types of layers are related to the hardness of PdP and pure Pd deposits, because the increasing of phosphorous content will increase the hardness of Pd deposits. Based on Figure 2.19, it can be seen that there is a smooth topography of electroless palladium in the individual grains, while pure Pd is showing a form of nano-roughness. Thus, the larger grains describe the known structure of the underlying nickel layer (Kao & Roberts, 2010).

Figure 2.18: The schematic layer of ENEPIG surface finish (Slocum, 2006).

(a) (b)

Figure 2.19: (a) The PdP deposition over nickel and (b) pure Pd deposition over nickel (Kao & Roberts, 2010).

2.3.5 Immersion silver (ImAg)

Immersion silver (ImAg) (Figure 2.20) has emerged as an alternative to HASL and ENIG because of its good solderability and aluminium wire bonding performance (Arra et al., 2004). It also has excellent silver solderability which maintained through the multiple reflow cycle and suitable for fine pitch electronic component (Barbetta, 2004 & Wang et al., 2009). ImAg finish can prevent the black pad problem, whisker formation, tin copper shell-life reduction and sensitivity to weak fluxes. The other benefits of the ImAg include inspectability at assembly, flatness, surface contact functionality and solder mask attack reduction (Cullen & O’Brien, 2004). Besides, immersion silver is lower in cost because of the simpler operation and it eliminates the possibility of producing the embrittling Au-Sn intermetallic compound (Yoon & Jung, 2008). The immersion plating is a process where the chemical displacement reaction will be deposited into the bare copper. During the reaction, the base metal donates the electrons that can reduce the positive charge metal ions present in the solution. During the reaction, once the metal is plated, there is no source of electrons and the reaction will automatically stop. Therefore, this reaction is considered as a self-timing process (Schlesinger, 2010). As an immersion process, it has a simple process and better result in stress testing and thermal shock (Fang & Chan, 2007). Besides, immersion process 24

needs shorter time compared with electroless plating. Choosing immersion silver as a layer, plays a role as protective finish that ensures the solderability of the underlying copper. The molten solder needs to be moistened and disseminated over the silver surface finish, then the ImAg layer will dissolve into the molten solder. This situation is similar with HASL and OSP, where it allows the formation of copper-tin intermetallic solder joint (Wang et al., 2009).

Figure 2.20: Printed circuit board with immersion silver (ImAg) (Wright, 2015).

Immersion silver deposits layer is 100 times thinner than traditional electroplated silver deposits. The range of ImAg thickness is 0.15 – 0.55 µm, which is coated with nearly pure silver. Usually, in this process a slight amount of organic material will be used to prevent tarnish, electro-migration and allow for extended shelf life (Cullen & O’Brien, 2004). These organic materials can co-deposit with silver solution and known as ‘organo - silver’ deposits. The purity of silver takes only 70 to 80 percent, and the rest 20 to 30 percent is organic addition agent or organic carbon

(Fang & Chan, 2007). Wang et al. (2009) found that in order to get the 0.5 µm Ag layer in range (Zheng, et al., 2002), the duration of plating time has to be around 1 minute to 4 minutes. The researcher reported that the thickness of immersion silver must not be too thick due to brittle solder joint in lead-free soldering, and not too thin to ensure a shelf life of this surface finish during storage (Yoon & Jung, 2008). Like an OSP finish process, ImAg has a short and simple process. The process consists of cleaning the exposed copper, micro-etching, pre-dipping, immersion silver 150

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