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Modeling of Ideal and Error Characteristics of a Multi – Stage, Interleaved Sub – Ranging Analog to Digital Converter using MATLAB.

THESIS

Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in the Graduate School of The Ohio State University

By

Dinesh Ravikumar

Graduate Program in Electrical and Computer Engineering

The Ohio State University

2016

Master's Examination Committee:

Dr. Waleed Khalil, Advisor

Dr. Ayman Fayed

Copyright by

Dinesh Ravikumar

2016

Abstract

High Speed Analog to Digital Converters (ADCs) are being widely used in digital communication, digital oscilloscopes and fast data acquisition systems since they provide the best dynamic performance in high frequency and wide bandwidth applications. The design of these high speed converters pushes the dynamic limits of the individual components beyond the basic data converters, incorporating techniques such as interleaving, averaging and dithering. This along with the requirements of low power consumption, smaller chip areas and high sampling rates which are contradictory to the high accuracy requirements, have led to the rise of complex architectures of these converters. Therefore Conceptual modeling of these converter architectures are of prime importance to gain insights on the various challenges and errors that one might come across during the actual design for a specific application.

This Master’s thesis focuses on modeling a high speed time interleaved sub-ranging ADC using MATLAB programming tool. The ADC modeled has 8 time interleaved 12 bit 3 stage pipelined architecture with one bit overlap. The INL and DNL characteristics of the modeled ADC under ideal and non-ideal conditions are investigated. The thesis studies estimation of two different types of ADC errors. The first type includes the static errors that could exist in an ADC like resistor mismatch, comparator reference offset and ii residual gain amplifier error etc. The second type includes temporal aspects of the converter like the impact of timing skew on time interleaving where several ADCs are operated in parallel.

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Dedication

Dedicated to Appa, Kavi, Vasu Athai, Kutty Athai and Athimber for their unwavering

love and support

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Acknowledgments

First and foremost, I thank Dr. Waleed Khalil, my advisor, through whose association over the last two , the foundation of my understanding and interest in analog, digital, mixed signal and RF circuits has been laid. Dr. Khalil’s courses were rigorous, though provoking and made me more inquisitive in understanding the basic and advanced concepts of circuits. I am grateful to him for having conceived the idea behind my work, his constant support, enthusiastic outlook on research and his valuable guidance throughout my graduate education.

I also thank Dr. Ayman Fayed for his detail oriented Analog IC classes with milieu replete of academic activity and for his time and suggestions in guiding me with the thesis and helping me gain extensive knowledge in analog circuits. I would like to thank Dr. Brian Dupaix for constantly reviewing this model and providing timely feedback and guiding me in the right direction.

I am totally indebted to Ramy Tantawy for being the go-to person for my entire work, for having clarified a multitude of my doubts about the underlying concepts of ADC’s and for believing in me. I also would like to thank Dr. Shane Smith, Ahmed Naguib Mohamed, Daron Disabato, Samantha McDonnell and Muhammad Swilam Ahmed for their guidance and support throughout this work.

Finally, I thank my parents, sister, aunts, uncles, cousins and grandparents whose unconditional love, support and sacrifices, helped me face any challenge that came across. I thank my friends Dr. Niveditha, Gayathri, Kruthi, Jananee, Vijay, Kiruba and Samarth who constantly stood by me and pushed me to chase my dreams.

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Vita

2012 ...... Bachelors in Engineering,

Electrical and Electronics Engineering,

Sri SaiRam Engineering College, India

2012-2014 ...... Assistant Systems Engineer,

Tata Consultancy Services Ltd, Chennai,

India

2015-2016 ...... Graduate Instructional Assistant,

The Ohio State University, Columbus, USA

Fields of Study

Major Field: Electrical and Computer Engineering

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Table of Contents

Abstract ...... ii

Dedication ...... iv

Acknowledgments...... v

Vita ...... vi

Fields of Study ...... vi

Table of Contents ...... vii

List of Tables ...... xi

List of Figures ...... xii

Chapter 1: Introduction ...... 1

1.1 Background ...... 1

1.2 Research Motivation ...... 1

1.3 Organization of the thesis ...... 4

Chapter 2: Analog to Digital Converters ...... 5

2.1 Overview ...... 5

2.2 Analog to Digital conversion process ...... 5

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2.3 ADC Specifications ...... 7

2.3.1 Sampling Rate ...... 7

2.3.2 Resolution ...... 7

2.3.3 Distortion ...... 8

2.3.4 Power ...... 8

2.3.5 Area ...... 8

2.3.6 Effective Number of Bits (ENOB) ...... 8

2.3.7 Figure of Merit (FoM) ...... 9

2.4 ADC Characteristics ...... 9

2.4.1 Static Parameters ...... 10

2.4.2 Dynamic Parameters ...... 15

2.5 ADC Architectures ...... 18

2.5.1 Flash ADC ...... 18

2.5.2 Pipelined ADC ...... 21

2.6 Sub Ranging ADCs ...... 23

2.6.1 Conventional Sub Ranging ADC architecture ...... 23

2.6.2 Overlap bits and Digital error correction ...... 24

2.7 Time interleaved ADCs ...... 28

2.7.1 Basics of Time Interleaving ...... 29

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2.7.2 Types of Time Interleaving errors ...... 30

Chapter 3: Modeling of Ideal Characteristics ...... 33

3.1 Overview ...... 33

3.2 ADC Modeling ...... 33

3.3 ADC Architecture ...... 35

3.4 Main Sample & Hold and Sub Sample & Hold ...... 37

3.5 Three stage pipelined architecture...... 41

3.5.1 Conversion Algorithm ...... 42

3.5.2 ADC Quantization ...... 44

3.5.3 Flash Function ...... 44

3.5.4 DAC Quantization ...... 45

3.5.5 Digital Error Correction ...... 45

3.5.6 Transfer function and Residue Amplification ...... 46

3.5.7 DNL & INL...... 51

3.6 8-to-1 Serializer ...... 54

Chapter 4: Error Characteristics Modeling ...... 56

4.1 Overview ...... 56

4.2 Timing Skew ...... 57

4.3 Input offset ...... 59

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4.4 Reference offset...... 61

4.5 Comparator offset with Gaussian Distribution...... 63

4.6 Resistor mismatch ...... 65

4.7 DAC & Subtractor capacitance mismatch ...... 66

4.8 Residual gain error ...... 70

Chapter 5: Conclusion...... 74

5.1 Overview ...... 74

5.2 Model Synopsis & Conclusion ...... 74

5.3 Future Scope of work ...... 76

References ...... 77

Appendix: MATLAB code for the ADC model...... 80

x

List of Tables

Table 1: Analog to Digital Conversion Architectures Classified based on Speed and

Accuracy [25]...... 18

Table 2: Tolerance Limits for Different Errors Modeled providing Comparison between

Two Architectures ...... 75

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List of Figures

Figure 2.1 Analog to Digital Conversion [6] ...... 5

Figure 2.2 Analog to Digital Conversion Process [7] ...... 6

Figure 2.3 Ideal and Non-Ideal Transfer Functions of a 3-Bit ADC [17] ...... 10

Figure 2.4 Transfer Function of a 3-Bit ADC with Quantization Error [18] ...... 11

Figure 2.5 Transfer Function of a 3-Bit ADC showing Gain Error [19] ...... 12

Figure 2.6 Transfer Function of a 3-Bit ADC showing Offset Error [20] ...... 13

Figure 2.7 Transfer Function of a 3-Bit ADC showing Differential Nonlinearity [21] ... 14

Figure 2.8 Transfer Function of a 3-Bit ADC showing Integral Nonlinearity [21] ...... 15

Figure 2.9 N-Point FFT of ADC Output [21] ...... 16

Figure 2.10 Resistance Ladder to generate Reference Levels in a Flash ADC [26] ...... 19

Figure 2.11 Flash ADC Architecture [27] ...... 20

Figure 2.12 Pipelined ADC Architecture...... 21

Figure 2.13 Conventional Sub-Ranging Architecture [35] ...... 23

Figure 2.14 Digital Error Correction in 3-Stage 12-Bit Sub-Ranging ADC With 1-Bit

Overlap using ADC Offset...... 26

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Figure 2.15 Digital Error Correction in a 2-Stage 8-Bit Sub-Ranging ADC with 1-Bit

Overlap using DAC Offset and Bit Manipulation [37] ...... 27

Figure 2.16 Digital Error Correction in 3-Stage 12-Bit Sub-Ranging ADC with 1/2-Bit

Overlap using DAC Offset but without Bit Realignment...... 28

Figure 2.17 Block Diagram of an Ideal 2x Time Interleaved ADC [32] ...... 29

Figure 2.18 Spectra of Input Signal and Timing Error Component ...... 32

Figure 3.1 Block Diagram for Modeling of an Analog to Digital Converter ...... 33

Figure 3.2 Time-Interleaved ADC Architecture ...... 36

Figure 3.3 Clocking Diagram for 8-Time Interleaved ADC...... 36

Figure 3.4 Input Sinusoidal Signal Sampled Based on a Sampling Frequency Fs...... 38

Figure 3.5 The Signal Upsampled Based on Required Number of Hits Per Bin ...... 39

Figure 3.6 Sampled and Held Input Signal ...... 39

Figure 3.7 The Signal Sampled by Sub Sample and Hold Circuit for Individual ADCs . 40

Figure 3.8 Three Stage ADC Architecture ...... 41

Figure 3.9 Three Stage ADC Modeling Algorithm ...... 42

Figure 3.10 Input Ramp Signal ...... 46

Figure 3.11 Transfer Function of 3-Stage ADC ...... 47

Figure 3.12 Output Transfer Function showing Intermediate Stage Quantization ...... 48

Figure 3.13 Output Transfer Function showing Fine Stage Quantization ...... 49

Figure 3.14 Interstage Residue Signal ...... 50

Figure 3.15 Intermediate Stage Residue Scaling ...... 50

Figure 3.16 Ideal Case Histogram ...... 51

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Figure 3.17 Actual ADC Histogram ...... 52

Figure 3.18 Ideal 3-Stage ADC DNL Characteristics ...... 53

Figure 3.19 Ideal 3-Stage ADC INL Characteristics ...... 53

Figure 3.20 Data Diagram of 8-To-1 Serializer ...... 54

Figure 3.21 Reconstructed Digital Output Vs. Sampled Analog Input ...... 55

Figure 4.1 Errors Modeled in the ADC ...... 57

Figure 4.2 Input and Output Characteristics of 8-Time Interleaved ADC with Third Lane

ADC having 100% Timing Skew...... 58

Figure 4.3 Input and Output Characteristics of 8-Time Interleaved ADC with Third Lane

ADC having 5% Timing Skew...... 59

Figure 4.4 Ramp Input with an Offset Of 10mv ...... 60

Figure 4.5 Histogram and DNL Characteristics of the ADC with Input Offset Of 33 mV.

...... 61

Figure 4.6 ADC and DAC Quantization with Ideal and Offset Reference ...... 62

Figure 4.7 Conversion Histogram & DNL Characteristics Of The ADC With 32.5 mV

Reference Offset ...... 63

Figure 4.8 Gaussian Distribution Of A 10 mV Offset In A 4-Bit Converter Based On

Pelgrom’s Law ...... 64

Figure 4.9 Dnl Characteristics Of The ADC With Fine Stage Comparator Offset Of 10mv

With Gaussian Distribution...... 64

Figure 4.10 Single Ended Version Of DAC – Subtractor Interface Circuit [42] ...... 67

Figure 4.11 Thevenin Equivalent Circuit Substitution [42]...... 68

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Figure 4.12 DNL Characteristics Of The ADC With DAC-Subtractor Interface

Capacitance Mismatch ...... 70

Figure 4.13 Residue Characteristics With 0.625 % Error In The Gain Factor Of Coarse

Stage Residue Amplification ...... 71

Figure 4.14 DNL Characteristic With 0.625 % Error In The Gain Factor Of Coarse Stage

Residue Amplification ...... 72

Figure 4.15 Residue Characteristics With 6.25 % Error In The Gain Factor Of

Intermediate Stage Residue Amplification ...... 72

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Chapter 1: Introduction

1.1 Background

Analog to Digital Converters are one of the most vital components in systems which integrate analog signals with digital domain. High speed, high performance ADCs are much in demand in fields like wireless communication, image recognition and medical instrumentation [1]. There are multiple architectural options available for implementing these high-speed high-performance ADCs and an ever growing demand for smaller, faster and low power, data converters have constantly led to the evolution of more complex ADC architectures. Among these architectures, pipelined multistage ADCs are the most commonly used in diverse applications because their op-amp gain and comparator offset errors are easily removed using digital error correction techniques [2].

Further in time interleaving, multiple ADCs are operated in parallel at lower speeds to collectively achieve faster sampling rates. [3].

1.2 Research Motivation

The design of high-speed high-performance ADCs are often tedious and time consuming.

The diverse applications of the ADCs come with their own complex architectures along with additional techniques like averaging which would improve its dynamic performance

1 at transistor level. Data converter designers are thus faced with a common dilemma: design a new product on a known architecture, making only incremental changes; or use a brand-new platform with the most advanced products and capabilities. The former may be quick and low risk, but offers a low reward. Whereas the latter offers better versatility, functionality and value though with higher risk. Also this leads to the rise various unexpected dynamic behavioral errors in the data conversion process. Thus modeling these ADCs using simulation tools, enables quick prototyping in software, minimizing development risk and providing designers with confidence that their new design will work as expected. The software offers insight into the capabilities of individual products such as analog-to-digital converters, clock ICs, and amplifiers, and makes it possible to combine devices (ADC and clock, for example) without having to design actual components [4]. The major objective of this thesis is thus to,

1. Validate functionality of a complex architecture at hand.

2. Quickly predict error tolerances of errors arising from different error sources.

There are multiple options to perform the modeling of circuits like ADCs and they are broadly classified into three categories which are described as below [5].

Conservative models

These are models that commonly use Verilog-A or Verilog-AMS. These models use an analog kernel to evaluate voltage, current and solve basic circuit equations. The models can be integrated into a full analog simulation and represent a large arena of complex circuits with hundreds of transistors within a few lines of code.

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Signal-flow models

These are models that are used in modeling abstract analog behavior of the circuits.

These models provide input/output feedback using simple equations and consider a unidirectional flow of signal.

Event-driven models

These can be used for modeling complex digital, mixed-signal and high level circuits.

They use code based models which are event driven based on the actual functioning of the circuit. The major drawback of these models is that the time complexity of the code base varies proportionally to the number of events and in turn to the circuit complexity.

MATLAB and Simulink fall into this category.

Overall, conservative models are the most complex and need maximum time and effort to model but provide the best accuracy. Whereas, event driven models provide moderate accuracy and lower time to model. Most importantly, these behavioral models are worthless if they don't accurately represent the transistor level design. Continuous model validation is necessary, because both designs and models change over time. One small change to a device model or the design could invalidate the model. Based on these facts, and the complexity of the circuit under consideration, MATLAB programming has been used in this thesis to model the characteristics of the time interleaved, multi stage ADC.

The major advantage of using MATLAB is that the model requires less effort to build, and has the least complexity to modify the model based on any design changes and a good accuracy. Also the MATLAB functions have been organized in a way to easily model many types of errors whether static or dynamic by providing easy handles and

3 variables. Further most of the existing MATLAB based models focus on the behavioral aspects of the circuit considered for modeling, efforts have been made to focus on structural, functional and the behavioral aspects of the architecture considered.

1.3 Organization of the thesis

Chapter 1 provides an introduction to the basic need for behavioral modeling of integrated circuits using the different software tools available. It also discusses in brief the various models available and the choice of the model for this particular research thesis.

Chapter 2 provides an overview of analog to digital convertors and discusses in detail the various static and dynamic characteristics of an ADC. It also gives an introduction to two most common ADC architectures viz., Flash and Pipelined. Further, it details about the sub ranging and time interleaved ADCs and its characteristics.

Chapter 3 details the modeling of the ideal characteristics of the ADC architecture considered for the research thesis. It begins with explaining the modeling algorithm along with its core components and goes on to compare the model with its circuit equivalent.

Chapter 4 explains how errors can be modeled in the algorithm. It also provides an insight of how different errors alter the behavior of the analog to digital converter.

Chapter 5 is the conclusion of the thesis. It summarizes the salient features and limitations of the project along with the suggestions to overcome these limitations and suggestions for future work.

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Chapter 2: Analog to Digital Converters

2.1 Overview

This Chapter provides a comprehensive analysis of the literature research that was carried out in order to understand the basic concepts related to ADCs. It gives a brief introduction to the ADCs, its design specifications, characteristics and architectures. It also discusses about the basics of sub ranging and time interleaved ADCs.

2.2 Analog to Digital conversion process

An analog to digital converter is defined as “A device for converting the information contained in the value or magnitude of some characteristics of an input signal, compared to a standard or reference, to information in the form of discrete states of a signal, usually with numerical values assigned to the various combinations of discrete states of the signal” [6].

Figure 2.1 Analog to Digital Conversion [6] 5

An ADC takes a continuous time signal which is usually a voltage and converts it into a binary number in the digital domain. This analog to digital conversion process usually involves the following three steps,

Figure 2.2 Analog to Digital Conversion process [7]

Sample & Hold

The sample and hold operation takes an analog sample at a particular time instant and holds the same until its amplitude is converted to a binary number. Improper setting of the Sample and Hold operation could lead to major timing errors in the converted output

[7].

Quantization

The amplitude of the analog signal is then converted to its equivalent in the digital domain. Since the analog amplitude can have infinite number of values, it has to be rounded to a specific whole number of quanta, or steps, closest to the value of the amplitude. This is called quantization [8].

Encoding

Encoding is the process where discrete amplitude values are encoded into distinct binary words of N-bit length [9]. 6

2.3 ADC Specifications

This sub-chapter discusses about the important specifications that should be considered while designing, modeling and calibrating an ADC.

2.3.1 Sampling Rate

Sampling Rate is defined as the rate at which the new sample is taken from a continuous time analog signal. Based on Shannon-Nyquist sampling theorem, the sampling rate is kept higher than twice the frequency of the signal to avoid any errors [10].

2.3.2 Resolution

Resolution is means of measuring how accurately the digital output word represents an analog input. It is defined as the smallest change in the analog input that will result in a change in the digital output. The number of bits N represents the resolution of an ADC

N and the different possible digital output states are 2 . A better resolution results in better accuracy but slows down the ADC [11]. This could be easily observed in the two basic architectures amongst ADCs. Flash ADCs offer quickest conversion but a lower resolution on the other hand; it is common to implement flash using pipelined stages to achieve a better resolution though it slows down the conversion process.

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2.3.3 Distortion

Distortion may be produced in the ADCs due to non-linearities in the transistors of the circuit or due to mismatch between identical circuit components. These are dynamic components which could be removed using techniques like offset cancellation. [12].

2.3.4 Power

Power is an important factor while designing any electronic component. The power consumption of ADCs varies with the architecture being used and the ultimate goal is usually to achieve the least power consumption possible. Power also has tradeoff with accuracy similar to conversion speed and flash ADC with a huge number of comparators is the most power hungry analog to digital converter.

2.3.5 Area

The Area occupied by an ADC again depends upon the architecture being used. Flash converters occupy maximum area as they have the maximum number of components. It is always preferred that the circuit occupies the minimum area which results in cost reduction while manufacturing the circuit for the converter [13].

2.3.6 Effective Number of Bits (ENOB)

The effective number of bits of an ADC is a measure to compare the different architectural designs. The ENOB is characterized by the equation,

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Where SINAD is the signal to noise and distortion ratio, the 6.02 term converts decibels to bits and the 1.76 term is due to the quantization error in an ideal converter [14].

2.3.7 Figure of Merit (FoM)

Figure of merit is mathematically defined as below,

The FoM takes into account the power consumption of an ADC, the ENOB and the sampling frequency. A lower FoM indicates an ADC with lower power consumption, a higher ENOB and a higher sampling frequency. All these three parameters have design tradeoffs with respect to each other. Increasing the sampling frequency will increase the bandwidth and relaxes the filtering and resolution requirements. On the other hand, it also increases the power consumption. Hence to design an ADC with optimum power consumption, sampling speed or resolution should be compromised [15].

2.4 ADC Characteristics

Performance of ADCs must be measured in the context of their application. Traditionally

ADCs used in the low speed sensors; disk drives and microcontrollers have been characterized by static or DC parameters. These include gain error, offset error, linearity etc. However, in the case of high speed applications like digital communication and medical instrumentation the dynamic specifications of an ADC play a major role [16].

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2.4.1 Static Parameters

DC or transient performance of ADCs is characterized by examining their conversion threshold voltages. The Figure 2.3 below shows two transfer functions of a 3-bit ADC.

One of the transfer functions is ideal while the other has some errors. Some of these errors are introduced in this sub-section [17].

Figure 2.3 Ideal and Non-Ideal Transfer Functions of a 3-Bit ADC [17]

Quantization Error

The analog input signal is an infinite valued quantity and the converted output is a discrete value. The quantization process in the conversion produces an error which is known as the quantization error and it could be defined as the difference between the analog input and the value of the corresponding output in voltage [18],

10

Figure 2.4 Transfer Function of a 3-Bit ADC with Quantization Error [18]

Gain and Offset Error

An important aspect to be considered while designing an ADC is the fact that the full scale voltage should match completely on to the 2N levels of the ADC. This is so, if the gain of the ADC is equal to 1. If the gain is greater than unity, the voltage range of the input should be decreased but all the output codes exist. Otherwise, if the input range is not decreased, all the codes may not exist. This deviation of characteristic from the ideal transfer function is known as gain error [19].

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Figure 2.5 Transfer Function of a 3-Bit ADC showing Gain Error [19]

From the above Figure 2.5, the gain error could be formulated using the slope of transfer function of the converter as below,

Offset error occurs, when all the digital code transitions exist, but they are all offset from the ideal design of the ADC. This means that the slope of the ADC transfer function is offset from its ideal slope by a constant value. This error can easily be calibrated through hardware or software [20].

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Figure 2.6 Transfer Function of a 3-Bit ADC showing Offset Error [20]

From the above Figure 2.6, the offset error could be formulated as below,

Where and N is the resolution of the ADC.

Differential Nonlinearity

Differential Nonlinearity (DNL) error of an ADC is the difference between the width of the ADCs transition step and the width of the transition step of an ideal behavior of the

ADC [20]. The DNL error measures how far each of the step sizes deviates from the nominal value. DNL of more than 1 LSB would mean that there exists a voltage range which has missing codes [21].

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Figure 2.7 Transfer Function of a 3-bit ADC showing Differential Nonlinearity [21]

Integral Nonlinearity

Integral Nonlinearity (INL) error occurs when the ADC transfer function deviates from the straight line. This deviation may be measured by calculating the difference between the transfer function’s slope and straight line [20]. INL of and ADC determines the accuracy of the ADC in bits. If the INL error exceeds half LSB, then the N-bit ADC might not be accurate to N-bits. This principle is utilized in over sampling and noise shaping converters [21].

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Figure 2.8 Transfer Function of a 3-bit ADC showing Integral Nonlinearity [21]

2.4.2 Dynamic Parameters

Dynamic parameters measure the performance of an ADC based on its output spectrum.

They represent a statistical averaging of the static parameters. However, obtaining a relationship between the dynamic and the static parameters of an ADC would be mathematically intensive. The Figure 2.9 below, shows a fast Fourier transform plot of the output signal of an ADC based on which the dynamic parameters of the ADC could be defined below [22][23].

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Figure 2.9 N-Point FFT of ADC Output [21]

Signal to Noise Ratio (SNR)

SNR is the ratio of signal power to noise power at the output of an ADC. Noise is generally caused due to the quantizer of the converter. Thermal and 1/F noise from the circuit analog components also degrades the SNR. SNR is expressed as below,

Where S, is the number of samples used.

The quantization noise of an ideal ADC can be considered to be spectrally white and spread over its sampling frequency. Over sampling of an ADC does spreads the quantization noise over a larger frequency, providing a higher SNR in the actual band of interests [24]. Therefore, the theoretical maximum SNR is given by, 16

Where fmax describes the maximum bandwidth of the input tone and fsample is the sampling frequency.

Spurious Free Dynamic Range (SFDR)

SFDR indicates the usable dynamic range of an ADC beyond which its dynamic distortions dominate over noise and it is measured as the difference between the RMS power of the signal and the largest in-band distortion component [21].

Total Harmonic Distortion (THD)

Whenever a periodic signal is applied as an input to an ADC, the INL and DNL errors are contributed by harmonic distortions. THD is the RMS sum of all the harmonic components (except the fundamental) of the output signal. Usually, only the first few odd harmonics are considered while calculating the THD [21].

Signal to Noise and Distortion Ratio (SINAD)

SINAD describes the ratio of maximum signal power to the total RMS noise power contributed by the harmonic distortion, quantization error and the device noise. SINAD determines the effective number of bits (ENOB) of an ADC. An ADC with N-ENOBs would produce the same noise and distortion as that of an ideal ADC with an N-bit resolution [21]. SINAD could be formulated as below,

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2.5 ADC Architectures

An analog to digital converter can be implemented in many ways. The most important and commonly used architectures include flash, pipelined, integrating, successive approximation register and sigma-delta. The choice of architecture is usually based upon the application sampling frequency, resolution, power and area requirements. These architectures could broadly be classified into three categories as shown below [25].

Low-to-Medium Speed, Medium Speed, High Speed, High Accuracy Medium Accuracy Low-to-Medium Accuracy Integrating Pipelined Flash Sigma-Delta Successive Approximation Table 1: Analog to Digital Conversion Architectures Classified based on Speed and Accuracy [25]

Though these different architectures are commonly used, based on the ADC considered only flash and pipelined architectures are discussed in this subsection.

2.5.1 Flash ADC

A resistance ladder configuration is the most common implementation of a flash ADC. A constant voltage is applied to the resistance ladder as an input and the voltage levels between the resistances are used as reference levels. If all the resistances are equal, and the input resistance to the comparator is infinite, the voltage steps between the resistances will be equal. The analog input signal or usually the sampled and held signal is then compared to these reference levels to determine the closest levels (as shown in the below

Figure 2.10 [26]).

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Figure 2.10 Resistance Ladder to generate Reference Levels in a Flash ADC [26]

This means that there would be 2N resistances for an n-bit resolution ADC. In the flash

ADC, one comparator is used for each reference level which means that the input signal of all the levels are compared simultaneously and a thermometer code is generated as shown in the Figure 2.11 below [27].

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Figure 2.11 Flash ADC Architecture [27]

Since the comparison happens simultaneously the conversion time of the converter is very less compared to the other converter architectures and also is a constant independent of the number of bits. However, the major disadvantage is that as the number of bits increases, the power consumption and the number of comparators required in the hardware increase exponentially. Flash ADCs are generally used in systems, which require very high sampling rate. Typical applications [28] of flash ADCs include digital oscilloscopes, point-to-point radio link, and direct RF downconversion.

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2.5.2 Pipelined ADC

A pipelined ADC [29] is based on a pipeline of several flash ADCs, with a resolution of few bits each. The input signal is sampled and held first and then it is quantized to a few bits using a flash ADC. The output from the first flash ADC is then converted back to an analog signal using a digital to analog converter and then subtracted from the input signal. This would result in the quantization error from the first ADC [26]. This quantization error is then quantized using another flash ADC which determines a few more bits. The number of stages the precision of each stage determines the total precision of the ADC.

Figure 2.12 Pipelined ADC Architecture [29]

Any difference between the input voltage and the voltage that results from the digital to analog converter indicates the error that results from both the ADC and DAC processes. 21

This error is then amplified by an appropriate gain factor to ensure that the voltage range is not too small and then is passed to the subsequent stages of the pipelined ADC. For an ideal linear gain, 3-staged pipelined ADC, the following equations can be derived.

( )

( )

( )

Solving the above equation we would get,

[ ] [ ]

Where the first term denotes the ideal digital output code and the second term denotes the quantization noise. The advantage of using a pipelined ADC is that multiple operations can be carried out concurrently. Although the complete conversion takes several cycles, the later stages can convert simultaneously with an earlier stage of a subsequent conversion [30].

In a pipelined ADC the amount of hardware and power consumption grows linearly with the number of bits, which is better compared to flash ADC. However, the conversion time is worse compared to the flash ADC. Pipelined ADCs are used in systems with high sampling rates and high precision [26]. The most common applications of pipelined

ADCs include digital video, cable modems, Ethernet, and radio base stations.

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2.6 Sub Ranging ADCs

A sub ranging analog to digital converter features high speed and relatively low power

[34]. The limiting factors of reduction in power consumption are only the resistor ladder and the comparators. Pipelined sub ranging ADCs dominate most of the high sampling rate applications including video, image processing, communications and a myriad of others [35]. In this section a basic pipelined sub ranging architecture is introduced and also the concept of digital error correction is explained.

2.6.1 Conventional Sub Ranging ADC architecture

Pipeline ADCs originated in 1950’s as a means to reduce the component count and power in vacuum tube flash ADCs. A block diagram of the sub ranging architecture is as shown in the below Figure 2.13.

Figure 2.13 Conventional Sub-ranging Architecture [35]

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The output of the sample and hold circuit is digitized by the first stage (course) flash converter. The course MSB conversion is then converted back into an analog signal using a DAC. The DAC output is then subtracted from the analog input, amplified and applied to the second stage ADC. The residue signal is thus digitized by the second stage ADC there by reducing the LSB bits of the digital output word. This type of ADC is generally referred to us as sub ranging because the input range is sub divided into a number of smaller ranges which are in turn further sub divided [35]. Sub ranging ADCs are usually analyzed using the residue waveform at the input to the second stage. In order for there to be no missing codes the residue waveform must exactly fill the input range of the second stage ADC. If the inter-stage alignment is not correct, missing codes will appear in the overall transfer function. If the output transfer function of an ADC sticks to a particular digital code and then jumps over a region leaving missing codes, it is termed as “Over- ranging”. The reverse condition of the residue signal is called as “Under-ranging” [35].

2.6.2 Overlap bits and Digital error correction

In order to reliably achieve higher resolution using the sub ranging architecture, overlap bits and digital error correction could be used. Addition of extra quantization levels in the over range and the under range region of sub ranging conversion is often done to solve the missing code problem. These overlap bits then are compensated by using digital error correction techniques to obtain the digital output word of the desired resolution. This achieved in three different ways as explained below.

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ADC Offset

In a standard sub ranging ADC the residue waveform must exactly fill the input range of the second stage ADC. Whenever there is over ranging the second stage ADC should return to all zeroes and start counting up again. Also, the code 001 must be added to the output of the first stage ADC to make the MSBs read the correct code. In case of under ranging the second stage ADC should generate all ones’ code and the additional over range comparators should cause the count to decrease. In this case, the code 001 must be subtracted from the MSBs to produce the corrected MSB code [36]. It is important to understand that for this correction method to work; the DAC must be more accurate than the total resolution of the ADC. The below Figure 2.14 presents the digital error correction with ADC offset for the three stage sub ranging ADC architecture considered for this model. It could be noted that the ADC quantization levels of the first two stages of the ADC are offset by half an LSB. Further, for the calculation of the digital output word, the code 001 should be added or subtracted based on the over ranging or under ranging conditions as explained earlier.

25

Figure 2.14 Digital Error Correction in 3-Stage 12-Bit Sub-ranging ADC with 1-Bit Overlap using ADC Offset.

DAC Offset

The concept explained in the previous sub section can also be implemented using a DAC offset of half LSB instead of the ADC offset. The Figure 2.15 below [37], shows a two stage sub ranging architecture with one overlapping bit. The DAC quantization levels

26 have an offset of half an LSB and the DAC output bits are manipulated to get the digital output word. In case of under ranging, the DAC output bits of the second stage start counting up from the midrange of the digital bits and the code 001 is subtracted from the first stage whereas in case of over ranging the DAC bits start counting up from 000 and the code 001 is added to the first stage.

Figure 2.15 Digital Error Correction in a 2-Stage 8-Bit Sub-ranging ADC with 1-Bit Overlap using DAC Offset and Bit Manipulation [37]

DAC Offset without bit manipulation

In 1972, Horna, suggested that the correction logic can be greatly simplified by adding an appropriate offset (usually half LSB to the DAC) so that there is no under range condition

[38]. This eliminates the need for the subtraction function and only an adder is required. 27

Considering a similar three stage architecture with half bit overlap, this could be implemented as shown in the below Figure 2.16. The output bits from the decoders are aligned and then a fixed digital word is subtracted to perform the digital error correction.

Figure 2.16 Digital Error Correction in 3-Stage 12-Bit Sub-ranging ADC with 1/2-Bit Overlap using DAC Offset but without Bit Realignment.

2.7 Time interleaved ADCs

In order to increase the bandwidth of analog to digital conversion several ADCs can be used in parallel [31]. The ADCs are interleaved in time so that the effective sampling frequency is N times higher if N ADCs are used in parallel. This result in the reduction of

28 conversion speed compared to a single ADC. But, the sample and hold circuit should now be fast enough to track the signal that should be converted.

2.7.1 Basics of Time Interleaving

In a typical time interleaved ADC if fs is the sampling frequency and if M ADCs are operated in parallel then the conversion rate of each ADC is fs/M [32]. These M interleaved ADCs operate from individual sampling phases, ∅ (where i = 1, 2, 3…M), which are phase shifted from each other by one sampling period. During these sampling phases, each individual ADC samples the input signal. At the output, data from all the

ADCs is muxed together to achieve the sampling rate fs as shown in the Figure 2.17 below.

Figure 2.17 Block Diagram of an Ideal 2x Time Interleaved ADC [32]

The above Figure 2.17 shows a 2x interleaved ADC in which the input signal is sampled by two ADCs which operate at different phases. The output of these two ADCs is then added together using a mux. The phase of the ADC 2 is time shifted by one sampling 29 period with respect to that of ADC 1 which, in frequency domain corresponds to the rotation of the phase. Thus, M interleaved ADCs generate an output identical to the single

ADC operating at fs. Unfortunately, due to device mismatch, each lane ADC has slightly different bandwidth and time instances [33]. Due to these non-idealities, often spurs might occur in the overall output spectrum.

2.7.2 Types of Time Interleaving errors

The major errors cause because of time interleaving viz., timing mismatch and bandwidth mismatch are described in detailed as below.

Timing Mismatch

Ideally, the phase difference between the adjacent lanes which are separated by one

휋 sampling period should be equal to . But, in practical implementations due to variations 𝑀 in clock buffers and sampling switches, phase or timing errors are unavoidable. In case of high input signal frequencies even a small timing mismatch can cause significant error

[33].

Sources of Timing Mismatch

The timing mismatch arises due to several factors including finite skew of clock, delay variation of clock buffers, mismatch in the sampling switches, layout mismatches etc.,

However, the implementation of sampling circuit determines the impact of timing mismatch in most of the cases. The common sources of timing mismatch for a fully differential track and hold circuit is presented in the following discussion [33].

30

One of the important timing error sources is the input distribution mismatch. This would introduce a systematic timing skew. Further, the mismatch in clock generation and distribution network also creates timing errors. These mismatches arise from different driving strength of clock buffers due to process variations, layout mismatches in the clock distribution network and hold period mismatch. In addition, mismatch in the passive sampling circuit also results in timing skew. These include mismatch in the threshold voltage of the bottom plate sampling transistor switches, variations in the ON resistance of transistor switches and mismatch in sampling capacitor due to process variation [33].

Impact of Timing Mismatch

The output spectrum of a noise free time interleaved ADCs would usually have spurs due to interleaving issues. The magnitude of these spurs which are caused only due to timing error limits the maximum achievable SNR of the ADC. In order to get an estimate of this limit, let us consider a uniformly distributed input signal which resembles a broadband signal as shown in Figure 2.18 below [33]. Also consider the spectrum of timing error signals, parabolic in nature which increases infinitely with frequency. This spectrum would represent the total timing error spectrum when multiplied with the input signal spectrum. Hence, it degrades the maximum SNR that can be achieved.

31

Figure 2.18 Spectra of Input Signal and Timing Error Component [33]

Bandwidth Mismatch

The other non-linearity that hampers the performance of time interleaved ADCs is the mismatch of the sampling front end. The magnitude and phase response of sampling circuit usually changes with the input frequency. Thus, the bandwidth error of different lane ADCs creates gain error and timing skews which changes with input frequency. The effect of the bandwidth mismatch on the gain error and timing skew is usually modeled as a simple first order RC filter [33].

32

Chapter 3: Modeling of Ideal Characteristics

3.1 Overview

This chapter would form the crux of this research thesis where the modeling principle and algorithm is introduced. The individual components which form the basic building blocks of the ADC are explained in detail. Also simulation results of the modeled blocks are presented. Further the modeling principle of the Differential Non-Linearity (DNL) and

Integral Non-Linearity (INL) is explained. It could be seen that these parameters depict the static performance of the conversion.

3.2 ADC Modeling

Analog to digital converters’ behavior modeling usually is implemented using four basic blocks as shown in the Figure 3.1 below. The four blocks include continuous time anti- aliasing filter, sampling circuit, quantizer and the codifier [39].

Figure 3.1 Block Diagram for Modeling of an Analog to Digital Converter

33

Anti-Aliasing Filter

An anti-aliasing filter is usually used to protect the information content of the signal and to maintain a higher SNR of the signal. It is in general, used in front of every quantizer to reject unwanted interferences outside the band of the interest. These are implemented by using either low pass or band-pass filters [39].

Sampling Circuit

A sampling circuit is used to transform a continuous-time signal into its sampled-data equivalent. Ideally, the output of a sampling is a sequence of delta functions whose amplitude equals the signal at the sampling times [39].

Quantizer

Amplitude quantization is the process of changing a sampled-data signal from continuous level to discrete-level. The dynamic range of the quantizer is divided into a number of equal quantization intervals, each of which is represented by a given analog amplitude.

The quantizer modifies the input amplitude into a value that represents which quantization interval it resides in. Often the value representing a quantization interval is the mid-point of the interval [39].

Codifier

Coding the quantized amplitude is the last function of an A/D converter. The codifier function varies with the architecture used for the analog to digital conversion. The simplest scheme is the one generated by the comparators of a full flash converter which uses a set of (2N − 1) logic signals whose value is 1 up to a given position and 0 beyond

[39].

34

The model presented in this research thesis also presents a similar basis of algorithm except that the anti-aliasing filter is not used since the model does not explore much of the dynamic parameters of conversion. But there is filtering function incorporated along with the sample and hold functionality. Thus the conversion process is simplified as shown in the Figure 2.1.

3.3 ADC Architecture

The model considered for modeling is as shown in the Figure 3.2 below, the main sample and hold circuit, samples the input analog signal at a given frequency. The sampled and held signal is then sampled by the sub sample & hold circuit (sub track and hold circuit is modeled as a sample and hold circuit in this work) and held by a frequency slower by the factor based on the number of time interleaved ADCs. In case of the architecture with the eight time-interleaving as shown in the Figure 3.3, we now have eight input signals which would be then passed to the eight ADCs.

35

Figure 3.2 Time-Interleaved ADC Architecture

Figure 3.3 Clocking Diagram for 8-Time Interleaved ADC 36

The above timing diagram depicts the Main Sample hold clock and the sub sample and hold circuit clocks. It could be noted that though the conversion in the time interleaved

ADCs happen in parallel, they are delayed from each other by exactly one sample sampling time period Ts. If the delay between the time-interleaved ADCs vary less than or greater than this Ts, it would lead to timing skew or timing mismatch error. The modeling of this timing skew is further discussed in Chapter 4.

3.4 Main Sample & Hold and Sub Sample & Hold

Sample and hold circuits is a vital block for an analog to digital converter as it helps in keeping the signal at a constant level while the amplitude quantization is done which is case of analog to digital converters where the conversion is distributed in time [26].

In this model, the main sample and hold circuit is simulated using MATLAB programming as explained as follows. A sinusoidal signal is constructed based on an initial input signal frequency and the number of cycles [40]. The signal is then sampled, based on the sampling frequency as shown in the below Figure 3.4.

37

Figure 3.4 Input sinusoidal signal sampled based on a sampling frequency fs.

The sampled signal is then upsampled, to obtain a certain number of hits per bin of the analog to digital conversion. In other words, each quantization level of the converter or each code of the final digital word would now be hit by the factor equivalent to the sampling factor. This upsampling is implemented in this model by increasing the sampling rate of the signal and adding zeros between the existing samples and filtering the signal with a moving FIR filter to fill in the zeros with sampled and held values. The analog sinusoidal input after sampling and upsampling would now look as shown in the below Figure 3.5,

38

Figure 3.5 The signal upsampled based on required number of hits per bin

Thus the signal after main sample and hold circuit could be represented as in Figure 3.6 below,

Figure 3.6 Sampled and Held Input Signal 39

The signal is then passed on the sub sample and hold block, for sampling the individual input signals for the individual lane time-interleaved ADCs. This is implemented in the model programmatically by sampling the sample and hold circuit’s output based on the number of cycles of the input signal, cyclically into eight different arrays and is held for eight time periods. The 8 arrays are then passed as input to the 3-stage ADC function for conversion to digital output. The signals at the input of each lane of time interleaved

ADC is as shown in the below Figure 3.7.

Figure 3.7 The signal sampled by sub sample and hold circuit for individual ADCs

40

3.5 Three stage pipelined architecture

In the sub-section the architecture of the 3-Stage sub-ranging ADC is introduced. For the modeling, the 3-Stage ADC is considered to have 4 bits in the coarse stage of conversion and 5 bits each in the intermediate and fine stages of conversion. Thus there is one bit overlap in between the stages. After each stage of conversion, a CDAC would convert the digital converted value back to analog. Then this value is subtracted from the input at the respective prior stages and further amplified by a gain value. This process is also called as residual gain amplification. Also the output code from each ADC is converted into a

12 bit digital output word using encoder and digital error correction circuits. The overall architecture of the three stage pipelined architecture is as in the Figure 3.8 below.

Figure 3.8 Three Stage ADC Architecture 41

3.5.1 Conversion Algorithm

The ADC architecture presented in the previous section is modeled using MATLAB programming, by converting the same to an equivalent algorithm as shown in the below

Figure 3.9.

Figure 3.9 Three Stage ADC Modeling Algorithm

42

The algorithm presented in the above Figure 3.9, presents the architecture in a lucid flow of steps, where the three parallel arms represent the 3-stages in the ADC. It could be noted that the coarse stage conversion should be complete before the start of the intermediate stage conversion in order to ensure complete residue scaling [40]. The algorithm steps are as below,

Algorithm Steps

1. Set the simulation parameters which include input type, number of bits in each

stage, number of bins, number of points in each bin (parameters passed from the

main function) [40].

2. Obtain the input signal corresponding to the lane ADC, generated from the sub

sample and hold circuit.

3. Set up the static and distortion characteristics of the coarse, intermediate & fine

stages of ADC and DAC without any errors to set up the quantization of each

level of the ADC.

4. For each input point, compare & obtain the coarse, intermediate and fine stage

quantization levels with residue scaling in between each stage.

5. Calculate the total output by scaling the quantization level and by doing the

digital error correction to combine to stages to form a 12-bit 3-stage ADC output

and plot the transfer function, residue levels

6. Calculate and plot the DNL, INL for the ADC.

43

3.5.2 ADC Quantization

The ADC quantization is basically done to divide the reference voltage range into n equal bins here n is the number of bits considered for that particular stage of conversion. The

ADC quantization can be mathematically modeled as follows. Consider the reference voltage levels for conversion as Vref,high and Vref,low , if the stage has n bits then, the number of quantization levels is given by 2n. Further the voltage at each quantization level is given as below,

Where is the number of quantization levels in that particular converter. Also it is this quantization that would the value of one LSB based on the formula given below.

3.5.3 Flash Function

Once the ADC quantization levels are fixed as explained in the previous sub-section, the analog input and the quantization levels are passed to the Flash conversion function which would calculate the quantization level corresponding to the input. The basic pseudo code or the algorithm for this flash conversion is as below,

Algorithm

1. Set up number of comparators needed for the flash conversion based on the

number of quantization levels or the number of bits.

44

2. Compare the input analog voltage with comparator voltage (voltage of the

quantization levels) for the n comparators iteratively.

3. Set the comparator to 1 if the input voltage is greater than the comparator voltage

else, set the comparator to zero.

4. Sum the total number of comparators that are set to 1. This would provide the

quantization level corresponding to the analog input voltage.

3.5.4 DAC Quantization

The sub-ranging ADCs require conversion of the ADC output back to analog value for the calculation of the residual input for the subsequent stages. The architecture is considered to use CDAC which would have quantization levels for n bit. Once the flash function provides the quantization level value for a particular analog input, the quantization level is passed to the DAC function and the corresponding analog value is obtained. The DAC quantization levels are determined using a procedure similar to that of the ADC quantization levels except for the fact that the DAC has half an LSB offset in order to facilitate the implementation of the digital error correction.

3.5.5 Digital Error Correction

The digital error correction technique is implemented to obtain the 12-bit digital output word from the 14 bit ADC (coarse stage ADC – 4 bits, intermediate stage ADC – 5 bits and fine stage ADC – 5 bits) with 1 bit interstage overlap. The major advantage of having the additional bits is that it provides more tolerance towards the errors that might occur in

45 the ADC. This would be discussed in more detail in Chapter 4. The digital error correction is performed using the DAC offset and the subtraction of a constant binary word from the output digital word as discussed earlier in the section 2.6.2.

3.5.6 Transfer function and Residue Amplification

This sub-section analyses the transfer function of the three stage ADC algorithm that has been modeled under ideal conditions. A ramp signal with amplitude as 1 V is passed as the input to the ADC as shown below in Figure 3.10.

Figure 3.10 Input Ramp Signal

The Transfer function for the above input is obtained as below in Figure 3.11,

46

Figure 3.11 Transfer Function of 3-Stage ADC

As one would expect, the output transfer function scales up to 4096 (212) quantization levels overall. The overall transfer function consists of three components as it could be observed from the above Figure 3.11. The first component (in blue) represents the coarse level quantization levels and it has only 16 (24) steps overall. Also as part of the digital output word, the coarse quantization levels are scaled up by 28. The second component

(in red) is the intermediate level conversion. It could be noted that each coarse stage quantization level has 16 (24) intermediate level quantization levels. The intermediate quantization levels are magnified as shown in the below Figure 3.12.

47

Figure 3.12 Output Transfer Function showing Intermediate Stage Quantization

The Figure also shows that intermediate stage conversion scaling up to a maximum of

256th quantization overall, as the intermediate conversion is scaled up by 24 for the output digital word. It could be noted that each intermediate stage quantization level has 16 (24) fine level quantization levels. The fine quantization levels are magnified as shown in the below Figure 3.13.

48

Figure 3.13 Output Transfer Function showing Fine Stage Quantization

The Figure also shows that fine stage conversion scaling up to a maximum of 16th quantization overall, as the fine stage conversion is scaled up by 20 for the output digital word.

Also, as we discussed earlier, for the conversion of the sub-ranging ADC to be appropriate the interstage residues are scaled to the entire voltage range. The scaled up residue is as shown in the Figure 3.14.

49

Figure 3.14 Interstage Residue Signal

It could be noted in the above Figure that the coarse stage has been scaled up 16 times more than the intermediate stage residue. The intermediate stage residue is focused in the below Figure 3.15.

Figure 3.15 Intermediate Stage Residue Scaling

50

3.5.7 DNL & INL

In order to analyze the static performance of the analog to digital converter, modeling of

Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) is essential. The

DNL and INL are modeled in MATLAB programming using histogram as follows.

Consider a slow ramp starting from 0 and achieving the full scale in k 212 sampling periods. The converter acquires k 212 samples producing, for an ideal response, a flat histogram with k samples per bin. Since a bin of the histogram containing less than k samples denotes a quantization interval smaller than 1 LSB and a content of more than k sample means a Δ exceeding 1 LSB, the histogram obtains the DNL and the INL plots with 1/k LSB accuracy. The slow ramp is such that k = 100 leading to an accuracy of the

DNL estimation equal to 1% LSB. The result of Figure 3.16 below shows ideal case histogram leading to systematic DNL of 0 LSB.

Figure 3.16 Ideal Case Histogram

51

The Figure contains the number of hits in each bin within the voltage range of 1 V. The histogram obtained in case of the actual 3-stage ADC conversion is as shown Figure 3.17 below,

Figure 3.17 Actual ADC Histogram

From the histogram hits, the DNL is calculated as the deviation of the step size of the actual data converter from the ideal width of the bins Δ. Assuming that Xk is the transition point between successive codes k −1 and k, then the width of the bin k is Δr(k) = (Xk+1 −

Xk); the differential non-linearity is given by [41],

The DNL is modeled using the above formula from the histogram plots and is obtained for the ideal 3-stage conversion as in Figure 3.18 below,

52

Figure 3.18 Ideal 3-Stage ADC DNL Characteristics

It could be noted that the DNL error is 0 LSB. From the DNL, the INL is further modeled using the formula below,

The modeled INL is then plotted for the ideal 3-stage conversion as in the below Figure

3.19.

Figure 3.19 Ideal 3-Stage ADC INL Characteristics 53

3.6 8-to-1 Serializer

Once the overall conversion is complete for the 3-stage ADCs in all the 8 lanes of time- interleaving, the 12-bit digital output word of each lane ADC is combined to single stream of digital word using an 8-to-1 Serializer. The data diagram of the 8-to-1 serializer is as shown in the below Figure 3.20.

Clock at 345.75 MHz

Data input 1 Data Data

Data input 2 Data Data

Data input 3 Data Data

Data input 4 Data Data

Data input 5 Data Data

Data input 6 Data Data

Data input 7 Data Data

Data input 8 Data Data

Data Data

Data Data

Data Data

8 Data bits aligned Data Data with the positive edge of the clock Data Data

Data Data

Data Data

Data Data

Data 1 Data 5 Data 1 Data output at end of first frequency division Data 3 Data 7 Data 3

Data 2 Data 6 Data 2

Data 4 Data 8 Data 4

Clock at 691 MHz

Data 1 Data 3 Data 5 Data 7 Data 1

Data output at clock/ 4 Data 2 Data 4 Data 6 Data 8 Data 2

Clock at 1.39 MHz

Data output at clock / 8 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8

Figure 3.20 Data Diagram of 8-to-1 Serializer 54

This serializer action is modeled as follows. Based on the sampling frequency and the number of cycles in the main sample and hold circuit, the frequency to serialize is set.

Then, based on the number of time interleaved ADC’s, combine the outputs of all the

ADC’s into a single digital output word. The below Figure 3.21 shows the final reconstructed digital output (in red) superimposed over the sampled input discussed in the section 3.4.

Figure 3.21 Reconstructed Digital Output vs. Sampled Analog Input

55

Chapter 4: Error Characteristics Modeling

4.1 Overview

The Major objective of this chapter is to model the prominent errors that could be present in the ADC architecture presented in Chapter 3 and also to understand how each of these errors alter the behavior of the analog to digital converter. These changes in characteristics would provide a valuable insight on how these errors could be calibrated which could be of future scope of work. Also it would provide an idea about the tolerable limits of these errors before the transistor level design of the converter.

The below Figure 4.1, enlists the various errors modeled in this research work, which are further discussed in the following sub-sections.

56

Figure 4.1 Errors Modeled in the ADC

4.2 Timing Skew

Timing skew or timing mismatch is of prime importance in the time interleaved ADC architecture. The major advantage of having Main Sample & hold (MSHA) and Sub

Track and Hold (STHA modeled as sub sample and hold in this work) present in the architecture considered, is that the tolerance of timing skew is extended to the period of the MSHA. The Timing skew within the sampling period in this model is actually modeled in MATLAB programming by zero padding the input arrays passed to the each lane ADC.

57

Output Input

Figure 4.2 Input and Output Characteristics of 8-Time Interleaved ADC with Third Lane ADC have 100% Timing skew.

The above Figure 4.2 represents the transfer function of the 8-time interleaved ADC when the third ADC had actually completely missed the corresponding sampling period and ended up sampling the input corresponding to the fourth lane ADC. This would actually result in a missing code in the conversion leading to a DNL error of greater than

1 LSB. However, missing an entire sampling period would be a rare scenario in actual circuits and might occur only if the sample and hold circuit designed does not correspond to the desired specifications. Usually in actual circuits, the sample and hold circuits tend to have up to ±5% timing errors which is considered in the below Figure 4.3 where the third lane ADC is considered to have 5% timing mismatch.

58

Output

Input

Figure 4.3 Input and Output Characteristics of 8-Time Interleaved ADC with Third Lane ADC have 5% Timing skew.

It could be observed from the above Figure 4.3, that there are actually no missing codes and the only alteration from the ideal characteristics now is that the third digital code is hit 5% fewer times and the fourth digital code is hit 5% more. This would ideally result in a DNL error which would be less than or equal to 0.05 LSB.

4.3 Input offset

In this sub-section of modeling, a ramp input as in Figure 3.10 is considered along with the 3-Stage pipelined architecture described in the section 3.5. An offset of 10 mV is initially introduced to the input as which would actually level shift the ramp signal as shown in the Figure 4.4 below.

59

Figure 4.4 Ramp Input with an Offset of 10mV

In this case, there was no deviation found in the DNL Characteristics from the ideal values. However if the offset to the input exceeds half LSB of the individual stages of the

3-stage ADC (offset 32.5 mV), the analog to digital converter start missing code as shown in the histogram and DNL in the characteristics in the Figure 4.5 below, the DNL error is up to 1 LSB.

60

Conversion Histogram DNL

Figure 4.5 Histogram and DNL Characteristics of the ADC with Input Offset of 33 mV.

4.4 Reference offset

In this sub-section, the voltage reference of all the 3-stages of the ADC and also that of the DAC is offset from the ideal value without changing any other circuitry aspect of the converter. This would alter the quantization steps of the individual stage ADCs and

DACs as shown in the Figure 4.6 below. Each step is shifted up or down with an offset Δ and thus the voltage reference for the first quantization level is 0 V and that of the last quantization level is given by (1 + Δ) V.

61

Quantization due to reference offset

Quantization due to ideal reference

Figure 4.6 ADC and DAC Quantization with Ideal and Offset Reference

The impact of the reference offset could be seen as missing quantization levels in the later stages of the conversion. A reference offset of 0.2441 mV (1 LSB of a 12-bit ADC) would lead to one missing quantization level. The below Figure 4.7 shows the histogram and DNL characteristics of the converter with reference offset of about 32.5 mV. It could be noted that the converter has a DNL error of -1 LSB due to the conversion out of range.

The histogram also shows that the bins are hit only up to 3956 quantization levels.

62

Conversion Histogram DNL

Bins hit for only up to 3956 quantization levels

Figure 4.7 Conversion Histogram & DNL Characteristics of the ADC with 32.5 mV Reference Offset

4.5 Comparator offset with Randomized Gaussian Distribution

In this sub-section the effect of the comparator offset to the conversion process is discussed briefly. The Gaussian distribution of comparator offset could be obtained from the Monte-Carlo simulation. In this work, based on the mean offset, Gaussian distribution is obtained using Gaussian curve membership function in MATLAB. Further the values are randomized using random normal distribution function in MATLAB. Based on this methodology, the distribution of the offset between various quantization levels of the converter when with randomized Gaussian mean of 10 mV could be as seen in the Figure

4.8 below.

63

Figure 4.8 Gaussian distribution of a 10 mV Offset in a 4-Bit Converter and the Random Distribution of the Error between Quantization Levels

The offset of 10 mV is introduced in the fine stage (or 3rd stage) converter of the 3-Stage conversion process and it is noted that the converter is tolerable to such an offset. The

DNL characteristics represents the ideal case as shown in the below Figure 4.9.

Figure 4.9 DNL Characteristics of the ADC with Fine Stage Comparator Offset of 10mV with Gaussian distribution

64

It is further noted that the ADC is tolerant and do not have DNL error greater than or equal to 1 LSB (1 missing code in other words) till the offset is less than or equal to one

LSB of a single stage i.e. 32.5 mV. This is mainly due to digital error correction of one bit overlap which results in a residue with half the range. Thus any offset, would now start filling the available range of the residue.

4.6 Resistor mismatch

In this sub-section, mismatches in the resistor ladder are modeled, its effect in the conversion process is studied and tolerable limits are identified. The accuracy of the resistor strings in the resistor ladder is related to matching between the resistors ultimately affecting the DNL and INL characteristics of the ADC. The resistor mismatch is formulated in the model as below,

th Suppose if the i resistor of the resistor ladder has a mismatch of then,

Considering that all the resistors in the ladder have the same mismatch,

We know that the digital output voltage of the converter is given by,

For i = 0, 1, 2 … 2N – 1.But after adding the resistor ladder mismatches the output digital voltage becomes,

65

∑ ∑

After we simplification we get,

Thus the resistor mismatch could be modeled in terms of voltage of the ADC quantization. Now this mismatch is distributed between individual resistors using a randomized Gaussian distribution as discussed in the previous section. The DNL characteristics with 1% mismatch in all the resistors of the resistor ladder was observed similar to the ideal characteristics. However the conversion process misses one code

(DNL error 1 LSB) when, the mismatch in resistance exceeds 3.25 % of the resistance in the resistor ladder.

4.7 DAC & Subtractor capacitance mismatch

In this sub-section the mismatch in capacitances of the Capacitor array Digital to Analog

Converter (CDAC) is modeled. This modeling is based on the model presented by

Behzad Razavi and Bruce A.Wooley in their work [42]. For simplicity of calculations, a single ended subtractor circuit is considered as shown in the Figure 4.10 below,

66

Figure 4.10 Single Ended Version of DAC – Subtractor Interface Circuit [42]

In the circuit, CT represents the top plate parasitics of the capacitors connected to node A and CB represents the bottom plate parasitics of the capacitors connected to node B. If n out of the N comparators produce ones in the first stage of comparison, the DAC- subtractor interface circuit could be simplified and represented using a Thevenin’s equivalent circuit as shown in the below Figure 4.11. In the Figure, the CTHEV includes the capacitance from the DAC circuit, ΔC1 represents DAC capacitance non-linearity,

ΔC3 represents input capacitance non-linearity and ΔC5 represents the subtractor capacitance non-linearity. The maximum DAC capacitance is NC, input lumped capacitance is NC and subtractor capacitance is 2C ideally.

67

Figure 4.11 Thevenin Equivalent Circuit Substitution [42]

From the circuit,

And . If Ao is the open loop gain of the operational amplifier,

then the output voltage of the circuit is given by,

( )

Where [ ]

Since typically, , and , the expression for CTHEV can be simplified as below,

( )

Now CTHEV.VTHEV can be written as below,

( ) ( )

Now the output voltage of the circuit could be formulated as below,

68

( )

[ ]

Applying Taylor expansion to the denominator of the formula above we get output voltage of the form,

Where,

[ ( ) ]

And

{ [ ( ) ] }

The above relationship when compared with the ideal output voltage expected from the

DAC-subtractor interface circuit formulated below denotes that there are both gain error and differential non-linearity. Comparing the output voltage with a straight line indicates that the gain error is given by a – b and the differential non-linearity is given by b . LSB.

Thus the capacitor mismatches in the model is implemented using the VO derived above.

Typical values considered for modeling are Ao = 1000, CB = 0.2 C, ΔC1 = ΔC3 = ΔC5 =

0.0002 C. When distributing these mean errors between the capacitors using a randomized normal distribution, the DNL characteristics could be observed as below,

69

Figure 4.12 DNL Characteristics of the ADC with DAC-Subtractor Interface Capacitance Mismatch

Thus the calculated values verify the behavior of the model. Further experiments showed that the circuit is tolerant (no missing codes) for up to 5% and 40% mismatches in the

DAC-Subtractor interface circuit’s capacitances in the coarse and fine stages of conversion for the 3-stage ADC respectively.

4.8 Residual gain error

The final error that has been modeled in this work is the error on the gain parameter used to amplify the residue. In the 3-Stage ADC considered, the residue signal is amplified 8X times between the coarse and intermediate stages of conversion and 16X times between the intermediate and fine stages of conversion. If the residue signal between the intermediate and fine stages is amplified by a factor of 7.95X instead of 8X times, then

70 the residue characteristics in the Figure 3.14 is modified as shown in the Figure 4.13 below,

Figure 4.13 Residue Characteristics with 0.625 % Error in the Gain Factor of Coarse Stage Residue Amplification

The resulting DNL characteristic is as shown in the Figure 4.14 below. It could be noted that the 3-Stage converter is tolerant (no missing code) up to an error of 0.625 % in the gain factor.

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Figure 4.14 DNL Characteristic with 0.625 % Error in the Gain Factor of Coarse Stage Residue Amplification

Figure 4.15 Residue Characteristics with 6.25 % Error in the Gain Factor of Intermediate Stage Residue Amplification

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It is further observed that the converter in tolerant (no missing code) for up to 6.25 % error in the gain factor of the residue amplification. Since the ideal gain factor is 16X, the converter would then be tolerant up to the gain factor being 15.90. The residue characteristics variation when the error in intermediate stage residue amplification is introduced could be seen in the Figure 4.16 above. The DNL characteristics observed would be similar to that shown in Figure 4.15.

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Chapter 5: Conclusion

5.1 Overview

This chapter focuses on providing an overall summary of this research thesis. It also focuses on providing a enlisting the challenges faced in modeling the ideal and error characteristics using MATLAB programming. The limitations of this model, few suggestions to overcome those limitations and also some additional features which would make the model more useful are suggested in the future scope sub-section.

5.2 Model Synopsis & Conclusion

The goal of this thesis was to model a time-interleaved sub-ranging ADC using one of the programming based modeling tool. Based on the literature study regarding the modeling tools discussed in the Chapter 1, MATLAB programming was chosen, because of its ease of use and also diverse application in the industry. Further the 12-bit 8-time interleaved

3-stage ADC was modeled along with its ideal DNL and INL characteristics. Then the model was modified to introduce some of the most important static and dynamic error parameters of the ADC including the timing skew error, input offset, reference offset, comparator offset, resistor mismatches, capacitor mismatches and the gain error. The variation in the behavior of DNL Characteristics in case of each error is differentiated.

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This would be most important in case of calibration of the various errors. Finally, the tolerance limit for each of the errors for which the ADC would start missing codes was noted and it could be noted that the digital error correction and overlapping bits adds more tolerance to the analog to digital converter. The observed tolerable limits in the model with the various errors introduced could be tabulated as shown in the table 2 below,

Table 2Tolerance limits for Different Errors Modeled providing Comparison between two Architectures

The most salient feature of this model however would be its ease of introducing any error parameter similar to the converter circuitry in few simple lines of code and the ability to observe its effect on the DNL & INL characteristics. This would save a lot of time to understand and expect these errors and limitations before starting the actual design of the circuit at transistor level. 75

5.3 Future Scope of work

The major drawback of most of the programming languages is that it is difficult to model and analyze the timing aspect of electronic circuits below 1 ms. Though attempt has been made in this research thesis to model the timing sensitivity of the converter using arrays and zero padding concepts of programming, they could not accurately model the circuit’s timing feature. Some of the suggestions for future work based on this model could be as listed below,

1. Introducing the accurate timing aspect of circuitry into the model. Though it could

be done by converting the MATLAB programming functions into Simulink

custom user defined function blocks, this would actually require modeling of the

functions compatible to Simulink. Some of the common issues one might face

while doing so might be handling continuous and discrete time signals and

handling variable sized arrays.

2. Further, based on the DNL Characteristics changes for each error modeled in the

circuit, predict algorithm could be developed to predict the error based on the

transfer function and the DNL / INL parameters. Based on the prediction, one

could also attempt to implement calibration technique and minimize these errors.

3. Finally, the different dynamic aspects of an analog to digital converter could also

be modeled with focus in concepts like harmonic distortion, spurs and the power

spectrum of the output.

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References

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[15] Imran Ahmed and David A. Johns, “DAC nonlinearity and residue gain error correction in a pipelined ADC using split-ADC architecture”, Research in Microelectronics and Electronics 2006, Ph. D. (2006). [16] D.Cline, “Noise, Speed and power tradeoffs in pipelined analog to digital converters”, Doctoral dissertation, University of California, Berkeley, 1996 [17] C.Shi, “Design and power optimization techniques of CMOS Baseband circuits for wideband wireless applications”, Doctoral dissertation, The Ohio State University 2001 [18] Dallet, Dominique and Machado Da Silva, Jose. “Dynamic Characterization of Analogue-To-Digital Converters.”, 1st ed. Netherlands: Springer, 2005. [19] Title of Page: “The ABCs of ADCs: Understanding How ADC Errors Affect Performance”, hyperlink - http://www2.itu.edu.tr/~pazarci/Maxim_The_ABCs_of_ADCsUnderstanding_How_AD C_Errors_Affect_System_Performance.pdf [20] Title of Page: “Quantization Error Image”, hyperlink - http://zone.ni.com/cms/images/devzone/tut/a/0f6e74b4501.gif> [21] Anup Salva, “Digital Calibration Algorithms for Nyquist-Rate Analog to Digital Converters”, Dissertation report submitted to the faculty of Electrical and Computer Engineering, The Ohio State University, 2001. [22] “Defining and testing of dynamic parameters in high speed ADCs”, Part 1, Maxim Corporation website, 2002. [23] “Pipelined ADCs come of ”, Maxim Corporation website, 2002. [24] J.Pirskanen, “Wideband ADCs for flexible receivers”, Receiver architectures and synchronization in digital communication, Presentation, 2001 [25] Title of Page: “Understanding Flash ADCs”, hyperlink - http://www.maxim- ic.com/appnotes.cfm/an_pk/810/ [26] Jonas Elbornsson, “Analysis, Estimation and Compensation of Mismatch Effects in A/D Converters”, Department of Electrical Engineering, Linköping’s university, Sweden, 2003. [27] Maxim. Maxim, MAX108 _5v, “1:5Gsps, 8-bit ADC with on-chip 2:2GHz track/hold amplifier.”, http://pdfserv.maxim-ic.com/arpdf/MAX108.pdf. [28] Maxim, “Understanding flash ADCs.”, hyperlink - http://www.maximic. com/appnotes.cfm/appnote number/810/ln/en/. [29] Analog Devices. AD9410 “10-bit, 210 MSPS A/D converter”, data sheet. Analog Devices, 2000. [30] Abhilash Nair, “DESIGN OF A 16BIT 10MHZ PIPELINE ADC USING THE SPLITADC ARCHITECTURE IN 0.25μ CMOS”, A Major Qualifying Project submitted to the Faculty of the WORCESTER POLYTECHNIC INSTITUTE, Electrical and Computer Engineering, on October 15, 2007. [31] W.C. Black and D.A. Hodges. “Time interleaved converter arrays”, IEEE Journal of Solid-State Circuits, SC-15(6):1022{1029, December 1980. [32] Nandish Mehta, “Sampling Time Error Calibration for Time-Interleaved ADCs”, MASTER OF SCIENCE THESIS, Delft University of Technology, 2013 [33] B. Razavi, “Design Considerations for Interleaved ADCs,” Solid-State Circuits, IEEE Journal of, vol. PP, no. 99, pp. 1–12, 2013. 78

[34] Kenichi Ohhata, Wataru Yoshimura, Daiki Tabira, Futoshi Shimozono, Masataro Iwamoto, “A 1-GHz, 7-mW, 8-Bit Sub-ranging ADC without Resistor Ladder Using Built- In Threshold Calibration”, Scientific Research Publishing Inc., March 2014 [35] R. Staffin and R. D. Lohman, "Signal Amplitude Quantizer", U.S. Patent 2,869,079, filed December 19, 1956, issued January 13, 1959. [36] H. R. Schindler, "Using the Latest Semiconductor Circuits in a UHF Digital Converter," Electronics, August 1963, pp. 37-40. [37] O.A.Horna, “A 150 Mbps A/D and D/A conversion system”, COMSAT Technical Review, Volume 2, Number 1, spring 1972. [38] G. G. Gorbatenko, "High-Performance Parallel-Serial Analog to Digital Converter with Error Correction," IEEE National Convention Record, New York, March 1966. [39] Page Titled: “Data Converters Glossary”, hyperlink - https: //www.maximintegrated.com/en/app-notes/index.mvp/id/641 [40] Page Titled – “Errors in ADC”, hyperlink - http: //www.ti.com/lit/an/slaa013/slaa013.pdf [41] MATLAB example titled “Simulate a sample and hold system”, hyperlink - http://www.mathworks.com/help/signal/ug/simulate-a-sample-and-hold-system.html [42] Behzad Razavi, Bruce A.Wooley, “A 12-b 5-MSample/s Two-Step CMOS A/D Converter”, IEEE, IEEE journal of solid state circuits, December 1992. [43] D. J. Kinniment, D. Aspinall, and D.B.G. Edwards, "High-Speed Analogue-Digital Converter," IEE Proceedings, Vol. 113, pp. 2061-2069, Dec. 1966. [44] O. A. Horna, "A 150Mbps A/D and D/A Conversion System," Comsat Technical Review, Vol. 2, No. 1, pp. 52-57, 1972. [45] J. L. Fraschilla, R. D. Caveney, and R. M. Harrison, "High Speed Analog-to-Digital Converter," U.S. Patent 3,597,761, filed Nov. 14, 1969, issued Aug. 13, 1971. [46] Walt Kester, “ADC Architectures V: Pipelined Sub-ranging ADCs”, Analog Devices, MT 034 Tutorial. [47] Franco Maloberti, “Data Converters”, Springer 2007. [48] Sanjiv.P, Github MATLAB repository for Data Conversion and digital signal processing Matlab program models, solutions for Franco Maloberti textbook on Data Converters [49] J-E. Eklund, “A/D Conversion for Sensor Systems”, PhD thesis 491, Department of Physics and Measurement Technology, Linköping University, Sweden, May 1997. [50] Fraunhofer Institut. “Fast and high resolution A/D converters”, hyperlink - http://www.iis.faunhofer.de/asic/analog/msr/msr adc.html. [51] MATLAB examples offered by Course EE 451 since fall 1996, New Mexico Institute of Mining and Technology, hyperlink - http://www.ee.nmt.edu/~rison/ee451_fall96/matlab/sample.html [52] Texas Instruments, “High Speed ADC Basics”, Application Report, January 2011, hyperlink - http://www.ti.com/lit/an/slaa510/slaa510.pdf [53] Texas Instruments, “AN-1721 High Speed ADCs with Interfacing, Driving and Clocking Schemes”, Application Report, January 2013, hyperlink - http://www.ti.com/lit/an/snaa049a/snaa049a.pdf

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Appendix: MATLAB code for the ADC model.

%% Main Program to run the model with 12-bit 8-time interleaved 3-stage conversion%% clear all; fsampling = 2e9; %sampling frequency finput = 1e8; % input frequncy noCycles=2; % no of cycles in sine wave flag_ramp=0; ti =8; ups=100; n=(fs/fin)*nCyl; n_bin=(n+1)*ups; adc1=[]; adc2=[]; adc3=[]; adc4=[]; adc5=[]; adc6=[]; adc7=[]; adc8=[]; z=[]; out1=[]; out2=[]; out3=[]; out4=[]; out5=[]; out6=[]; out7=[]; out8=[]; adc2(1:ups)=0.5; adc3(1:2*ups)=0.5; adc4(1:2*ups)=0.5; adc5(1:4*ups)=0.5; adc6(1:5*ups)=0.5; adc7(1:6*ups)=0.5; adc8(1:7*ups)=0.5; [z]=sample_and_hold(fin,noCyles,flag_ramp,fs,ups); % sub sample and hold for interleaving% for i=0:n 80

a=(i*ups)+1; b=(i+1)*ups; if mod(a,(ti*ups)) <= ups && mod(b,(ti*ups)) <= ups adc1=[adc1,z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b)]; elseif mod(a,(ti*ups)) <= (2*ups) && mod(b,(ti*ups)) <= (2*ups) adc2=[adc2,z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b)]; % adc3=[adc3,z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b)]; elseif mod(a,(ti*ups)) <= (3*ups) && mod(b,(ti*ups)) <= (3*ups) adc3=[adc3,z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b)]; elseif mod(a,(ti*ups)) <= (4*ups) && mod(b,(ti*ups)) <= (4*ups) adc4=[adc4,z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b)]; elseif mod(a,(ti*ups)) <= (5*ups) && mod(b,(ti*ups)) <= (5*ups) adc5=[adc5,z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b)]; elseif mod(a,(ti*ups)) <= (6*ups) && mod(b,(ti*ups)) <= (6*ups) adc6=[adc6,z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b)]; elseif mod(a,(ti*ups)) <= (7*ups) && mod(b,(ti*ups)) <= (7*ups) adc7=[adc7,z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b)]; elseif mod(a,(ti*ups)) > (7*ups) adc8=[adc8,z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b),z(a:b)]; end end % 8 ADCs operated in parallel for time interleaving% [out1]=three_stage_one_bit_overlap_solution1(adc1); [out2]=three_stage_one_bit_overlap_solution1(adc2); [out3]=three_stage_one_bit_overlap_solution1(adc3); [out4]=three_stage_one_bit_overlap_solution1(adc4); [out5]=three_stage_one_bit_overlap_solution1(adc5); [out6]=three_stage_one_bit_overlap_solution1(adc6); [out7]=three_stage_one_bit_overlap_solution1(adc7); [out8]=three_stage_one_bit_overlap_solution1(adc8); output=[]; outputword=[]; % 8:1 Serializer % for j=0:n c=(j*ups)+1; d=(j+1)*ups; if mod(j,ti) == 0 output=[output,out1(c:d)]; elseif mod(j,ti) == 1 output=[output,out2(c:d)]; elseif mod(j,ti) == 2 output=[output,out3(c:d)]; %output=[output,out4((c+95):d)]; elseif mod(j,ti) == 3 output=[output,out4(c:d)]; elseif mod(j,ti) == 4 output=[output,out5(c:d)]; elseif mod(j,ti) == 5 81

output=[output,out6(c:d)]; elseif mod(j,ti) == 6 output=[output,out7(c:d)]; elseif mod(j,ti) == 7 output=[output,out8(c:d)]; end end figure('Name','ADC o/p vs i/p') outputword=output/4096; plot(outputword,'r*') hold on plot(z,'k'); % INL DNL Calculation [DNL,INL,ideal,real,in,co,edges] = INL_DNL(z,output,n_bin); figure ('Name','DNL'); plot(DNL); xlim([0 n_bin]); title('DNL with 100 samples per bin'); grid; figure ('Name','INL') plot(INL) xlim([0 n_bin]); title('INL with'); grid; % Main sample and Hold % function [z]=sample_and_hold(fin,nCyl,flag_ramp,fs,ups) %Very high sampling rate fs %Frequency of sinusoid fin %generate five cycles of sinusoid nCyl t=0:1/fs:nCyl*1/fin; %time index if flag_ramp==1 x = 1*t; else x=0.5*(1+sin(2*pi*fin*t)); end y = upsample(x,ups); h = ones(ups,1); z = filter(h,1,y); figure('Name','sample and hold') plot(t,x); hold on; stem(z); hold on stairs(z,'r') % INL, DN function function [DNL,INL,ideal,real,in,co,edges]=INL_DNL(in_source,in_conv,n_bin) size_c=size(in_conv); if size_c(1)==1 82

in_conv=in_conv'; end size_s=size(in_source); if size_s(1)==1 in_source=in_source'; end size_c=size(in_conv); size_s=size(in_source); points_c=size_c(1); points_s=size_s(1); points=min([points_c points_s]); in=in_source([1:points]); co=in_conv([1:points]); % offset and gain = 1 in1=in(1); inp=in(points); in=((in-in1)/(inp-in1)); co1=co(1); cop=co(points); co=((co-co1)/(cop-co1)); edges=[0, 1:n_bin]; edges=((edges)/n_bin); ideal=histc(in,edges); figure('Name','ideal histogram'); plot(ideal) real=histc(co,edges); figure('Name','actual histogram'); plot(real) mismatch=real-ideal; figure('Name','Actual - Ideal'); plot(mismatch) SxLSB=points/n_bin; DNL=mismatch/SxLSB; DNL(1)=DNL(2); DNL(n_bin)=DNL(n_bin-1); DNL(n_bin+1)=DNL(n_bin); INL=cumsum(DNL); INL=INL-edges'*INL(n_bin+1); % Three Stage 12 bit Flash ADC % clear all; flag_flash=1; % 0 for full flash & 1 for three step flash flag_ramp=1; % 0 for sine input 1 for ramp input % Simulation parameters % nbit_coarse=4; % First Coarse Conversion nbit_intermediate=5; % Second step conversion nbit_fine=5; % Fine Conversion nbit=12; % total no of bits nbinc=(2^nbit_coarse); 83 nbini=(2^nbit_intermediate); nbinf=(2^nbit_fine); n_bin=(2^nbit); points = n_bin*100; t=[1:points]; Res_gain=2^nbit_coarse; % Residue Gain scaling after coarse conversion Res_gain2=2^nbit_intermediate; % Residue gain scaling after intermediate conversion % ADC & DAC Variables % firstbin=Vref_low; lastbin=Vref; coarseadc_off=0; coarse_random_DNL_error=0; flag_lsb=0; coarse_Stat_mismatch= 0.006; Rmismatch=0.0; flag_capmismatch_coarsedac=0; intadc_off=0; int_random_DNL_error=0; int_Stat_mismatch= 0.0; flag_capmismatch_intdac=0; fineadc_off=0; fine_random_DNL_error=0/2^nbit_coarse; fine_Stat_mismatch= 0.0; % Coarse ADC Characteristics % yc=statchar_gaussian(nbinc+1,coarseadc_off,coarse_random_DNL_error,firstbin,lastbin, flag_lsb,coarse_Stat_mismatch,Rmismatch); % DAC characteristics % yd=statcharDAC(nbinc+1,coarseadc_off,coarse_random_DNL_error,firstbin,lastbin,flag_l sb,flag_capmismatch_coarsedac); % Intermediate ADC Characteristics % yi=statchar(nbini+1,intadc_off,int_random_DNL_error,firstbin,lastbin,flag_lsb,int_Stat_mi smatch,Rmismatch); % DAC 2 characteristics % yd2=statcharDAC(nbini+1,intadc_off,int_random_DNL_error,firstbin,lastbin,flag_lsb,flag_ capmismatch_intdac); % Fine ADC Characteristics % yf=statchar(nbinf+1,fineadc_off,fine_random_DNL_error,firstbin,lastbin,flag_lsb,fine_Stat _mismatch,Rmismatch); % CONVERSION % for i=1:points % coarse conversion % [out_coarse(i),comp]=Flash(x(i),ycoarse); if out_coarse(i)<=1 out_coarse(i)=1; end if out_coarse(i)>=nbinc; out_coarse(i)=nbinc; end 84

%------Residual ------% yout(i)=yDAC(out_coarse(i)); res(i)=(x(i)-yout(i)+(lastbin/32))*(8.0); % Intermediate conversion % [out_intermediate(i),comp]=Flash(res(i),yintermediate); if out_intermediate(i)<=1 out_intermediate(i)=1; end if out_intermediate(i)>=nbini; out_intermediate(i)=nbini; end %------Residual ------% youtb(i)=yDAC2(out_intermediate(i)); res2(i)=(res(i)-youtb(i)+(lastbin/64))*(16); % fine conversion % [out_fine(i),comp]=Flash(res2(i),yfine); if out_fine(i)<=1 out_fine(i)=1; end if out_fine(i)>=nbinf; out_fine(i)=nbinf; end if out_fine(i) >= 9 && out_fine(i) <= 25 out_fi(i) = out_fine(i) - 8; elseif out_fine(i) < 9 out_fi(i) = out_fine(i) + 8; out_intermediate(i) = out_intermediate(i)-1; if out_intermediate(i) <= 1 out_intermediate(i) = 1; end else out_fi(i) = out_fine(i) - 24; out_intermediate(i) = out_intermediate(i)+1; end if out_intermediate(i) >= 9 && out_intermediate(i) <= 25 out_inter(i) = out_intermediate(i) - 8; elseif out_intermediate(i) < 9 out_inter(i) = out_intermediate(i) + 8; out_coarse(i) = out_coarse(i)-1; if out_coarse(i) <= 1 out_coarse(i) = 1; end else out_inter(i) = out_intermediate(i) - 24; out_coarse(i) = out_coarse(i)+1; end out_c(i)=(out_coarse(i)-1)*(2^8); % coarse stage output scaled up 85 out_i(i)=(out_inter(i)-1)*(2^4)*flag_flash; % intermediate stage output scaled up out_f(i)=(out_fi(i)-1)*flag_flash; % fine stage output out(i)= out_c(i)+out_i(i)+out_f(i); end %------Graphics------% % figure 1 --> ADC Transfer Function % % figure 2 --> Residual % % figure 3 --> SNDR with ENOB % %------% figure ('Name', 'ADC transfer function') no=[1:points]; plot(no,out_c,no,out_i,no,out_f) xlim([0 points]) grid; figure ('Name','Residue levels') plot(res,'r') hold on plot(res2,'k') xlim([0 points]) grid; figure ('Name','Ramp input') xmag=x*4096; plot(xmag,'r') xlim([0 points]) hold on plot(out,'k') grid; function y=statchar(nbin,offset,step,firstbin,lastbin,flag_lsb,dV,dR) % Static Characteristics Function % function x=statchar(nbin,offset,dnl,firstbin,lastbin,half) % nbin % offset, absolute value % step in LSB % firstbin value of the first bin % lastbin value of the last bin bin=(1:nbin); %ideal response if flag_lsb==1 err=(nbin)*step*(lastbin-firstbin)/(nbin-1); %one LSB error else err=(rand(1,nbin))*step*(lastbin-firstbin)/(nbin-1); %random error end staterr= (dV./((2).^((bin-1)/2))); Rmismatch = (dR/nbin); y=offset+err+firstbin+staterr+Rmismatch+(bin-1)*(lastbin-firstbin)/(nbin-1); y(1)=firstbin; function y=statcharDAC(nbin,offset,step,firstbin,lastbin,flag_lsb,capmismatch_flag) bin=[1:nbin]; %ideal response if flag_lsb==1 86

err=(nbin)*step*(lastbin-firstbin)/(nbin-1); %random error else err=(rand(1,nbin))*step*(lastbin-firstbin)/(nbin-1); %random error end if capmismatch_flag ==1 y=offset+err+firstbin*(1+0.005)+(bin-1)*(lastbin+0.005-firstbin)/(nbin-1); else y=offset+err+firstbin+(bin-1)*(lastbin-firstbin)/(nbin-1); end y(1)=firstbin; function [out,comp]=Flash(xin,x) % Function that implements Flash ADC conversion % Basic Pseudocode: % Set the quantisation levels (no of comparators)based on size of input array % Compare input voltage with comparator voltage for n comparators iteratively % set comparator =1 if Input voltage greater than comparator voltage. % Else set comparator = 0 % Sum all comparator values to represent quantisation level of a particular input value ncomp=max(size(x)); for i=1:ncomp if x(i) <= xin; comp(i)=1; else comp(i)=0; end end out=sum(comp);

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