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Stage, Time Interleaved Sub – Ranging Analog to Digital Converter Using MATLAB

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Stage, Time Interleaved Sub – Ranging Analog to Digital Converter Using MATLAB Modeling of Ideal and Error Characteristics of a Multi – Stage, Time Interleaved Sub – Ranging Analog to Digital Converter using MATLAB. THESIS Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in the Graduate School of The Ohio State University By Dinesh Ravikumar Graduate Program in Electrical and Computer Engineering The Ohio State University 2016 Master's Examination Committee: Dr. Waleed Khalil, Advisor Dr. Ayman Fayed Copyright by Dinesh Ravikumar 2016 Abstract High Speed Analog to Digital Converters (ADCs) are being widely used in digital communication, digital oscilloscopes and fast data acquisition systems since they provide the best dynamic performance in high frequency and wide bandwidth applications. The design of these high speed converters pushes the dynamic limits of the individual components beyond the basic data converters, incorporating techniques such as interleaving, averaging and dithering. This along with the requirements of low power consumption, smaller chip areas and high sampling rates which are contradictory to the high accuracy requirements, have led to the rise of complex architectures of these converters. Therefore Conceptual modeling of these converter architectures are of prime importance to gain insights on the various challenges and errors that one might come across during the actual design for a specific application. This Master’s thesis focuses on modeling a high speed time interleaved sub-ranging ADC using MATLAB programming tool. The ADC modeled has 8 time interleaved 12 bit 3 stage pipelined architecture with one bit overlap. The INL and DNL characteristics of the modeled ADC under ideal and non-ideal conditions are investigated. The thesis studies estimation of two different types of ADC errors. The first type includes the static errors that could exist in an ADC like resistor mismatch, comparator reference offset and ii residual gain amplifier error etc. The second type includes temporal aspects of the converter like the impact of timing skew on time interleaving where several ADCs are operated in parallel. iii Dedication Dedicated to Appa, Kavi, Vasu Athai, Kutty Athai and Athimber for their unwavering love and support iv Acknowledgments First and foremost, I thank Dr. Waleed Khalil, my advisor, through whose association over the last two years, the foundation of my understanding and interest in analog, digital, mixed signal and RF circuits has been laid. Dr. Khalil’s courses were rigorous, though provoking and made me more inquisitive in understanding the basic and advanced concepts of circuits. I am grateful to him for having conceived the idea behind my work, his constant support, enthusiastic outlook on research and his valuable guidance throughout my graduate education. I also thank Dr. Ayman Fayed for his detail oriented Analog IC classes with milieu replete of academic activity and for his time and suggestions in guiding me with the thesis and helping me gain extensive knowledge in analog circuits. I would like to thank Dr. Brian Dupaix for constantly reviewing this model and providing timely feedback and guiding me in the right direction. I am totally indebted to Ramy Tantawy for being the go-to person for my entire work, for having clarified a multitude of my doubts about the underlying concepts of ADC’s and for believing in me. I also would like to thank Dr. Shane Smith, Ahmed Naguib Mohamed, Daron Disabato, Samantha McDonnell and Muhammad Swilam Ahmed for their guidance and support throughout this work. Finally, I thank my parents, sister, aunts, uncles, cousins and grandparents whose unconditional love, support and sacrifices, helped me face any challenge that came across. I thank my friends Dr. Niveditha, Gayathri, Kruthi, Jananee, Vijay, Kiruba and Samarth who constantly stood by me and pushed me to chase my dreams. v Vita 2012 ...............................................................Bachelors in Engineering, Electrical and Electronics Engineering, Sri SaiRam Engineering College, India 2012-2014 .....................................................Assistant Systems Engineer, Tata Consultancy Services Ltd, Chennai, India 2015-2016 .....................................................Graduate Instructional Assistant, The Ohio State University, Columbus, USA Fields of Study Major Field: Electrical and Computer Engineering vi Table of Contents Abstract ............................................................................................................................... ii Dedication .......................................................................................................................... iv Acknowledgments............................................................................................................... v Vita ..................................................................................................................................... vi Fields of Study ................................................................................................................... vi Table of Contents .............................................................................................................. vii List of Tables ..................................................................................................................... xi List of Figures ................................................................................................................... xii Chapter 1: Introduction ...................................................................................................... 1 1.1 Background .......................................................................................................... 1 1.2 Research Motivation ............................................................................................ 1 1.3 Organization of the thesis ..................................................................................... 4 Chapter 2: Analog to Digital Converters ........................................................................... 5 2.1 Overview .............................................................................................................. 5 2.2 Analog to Digital conversion process .................................................................. 5 vii 2.3 ADC Specifications .............................................................................................. 7 2.3.1 Sampling Rate ............................................................................................... 7 2.3.2 Resolution ..................................................................................................... 7 2.3.3 Distortion ...................................................................................................... 8 2.3.4 Power ............................................................................................................ 8 2.3.5 Area ............................................................................................................... 8 2.3.6 Effective Number of Bits (ENOB) ............................................................... 8 2.3.7 Figure of Merit (FoM) .................................................................................. 9 2.4 ADC Characteristics ............................................................................................. 9 2.4.1 Static Parameters ......................................................................................... 10 2.4.2 Dynamic Parameters ................................................................................... 15 2.5 ADC Architectures ............................................................................................. 18 2.5.1 Flash ADC .................................................................................................. 18 2.5.2 Pipelined ADC ............................................................................................ 21 2.6 Sub Ranging ADCs ............................................................................................ 23 2.6.1 Conventional Sub Ranging ADC architecture ............................................ 23 2.6.2 Overlap bits and Digital error correction .................................................... 24 2.7 Time interleaved ADCs ...................................................................................... 28 2.7.1 Basics of Time Interleaving ........................................................................ 29 viii 2.7.2 Types of Time Interleaving errors ............................................................... 30 Chapter 3: Modeling of Ideal Characteristics .................................................................. 33 3.1 Overview ............................................................................................................ 33 3.2 ADC Modeling ................................................................................................... 33 3.3 ADC Architecture .............................................................................................. 35 3.4 Main Sample & Hold and Sub Sample & Hold ................................................. 37 3.5 Three stage pipelined architecture...................................................................... 41 3.5.1 Conversion Algorithm ................................................................................ 42 3.5.2 ADC Quantization ...................................................................................... 44 3.5.3 Flash Function ............................................................................................
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