High Performance GAA SNWT with a Triangular Cross Section: Simulation and Experiments

applied sciences

Article High Performance GAA SNWT with a Triangular Cross Section: Simulation and Experiments

Ming Li *, Gong Chen and Ru Huang

Key Laboratory of Microelectronic Devices and Circuits (MOE), Institute of Microelectronics, Peking University, Beijing 100871, China; [email protected] (G.C.); [email protected] (R.H.) * Correspondence: [email protected]

Received: 30 June 2018; Accepted: 31 August 2018; Published: 4 September 2018

Abstract: In this paper, we present a gate-all-around silicon nanowire transistor (GAA SNWT) with a triangular cross section by simulation and experiments. Through the TCAD simulation, it was found that with the same nanowire width, the triangular cross-sectional SNWT was superior to the circular or quadrate one in terms of the subthreshold swing, on/off ratio, and SCE immunity, which resulted from the smallest equivalent distance from the nanowire center to the surface in triangular SNWTs. Following this, we fabricated triangular cross-sectional GAA SNWTs with a nanowire width down to 20 nm by TMAH wet etching. This process featured its self-stopped etching behavior on a silicon (1 1 1) crystal plane, which made the triangular cross section smooth and controllable. The fabricated triangular SNWT showed an excellent performance with a large Ion/Ioff ratio (~107), low SS (85 mV/dec), and preferable DIBL (63 mV/V). Finally, the surface roughness mobility of the fabricated device at a low temperature was also extracted to conﬁrm the beneﬁt of a stable cross section.

Keywords: silicon nanowire; triangular cross section; simulation; experiment; TMAH; low temperature; mobility

1. Introduction The semiconductor industry is driven by the continuous device scaling of the metal-oxide- semiconductor ﬁeld-effect transistor (MOSFET) according to Moore’s Law. However, with the feature size stepping into the nano-scaled regime, the traditional planar device is confronted with great challenges, such as a weaker electrostatic controllability and larger body leakage. Recently, enormous attention has been paid to gate-all-around silicon nanowire transistors (GAA SNWT) due to their extraordinary electrostatic controllability, and they are considered as one of the most promising candidates in the sub-10nm technology node. However, GAA SNWT still has some issues relating to its performance and process which need to be addressed before it is used in commercial applications. Firstly, the short channel effect (SCE) is a critical factor affecting the device’s static power consumption and driving performance. In principle, it can be effectively suppressed by continuously reducing the line width of nanowires. Many research institutions have already done a lot of work in this area [1–5]. However, some issues still emerge, such as the limitation of the lithography patterning and the geometry variation from process instability [6]. Therefore, it is necessary to suppress SCE by optimizing the structure besides the line width, such as the cross-sectional shape, thereby improving the device performance. The second challenge comes from the lack of a feasible method for fabricating three-dimension suspended silicon nanowire with an accurately controlled size and cross-sectional shape [7], which is beneﬁcial to the device variability suppression and mobility enhancement. Meanwhile, this silicon

Appl. Sci. 2018, 8, 1553; doi:10.3390/app8091553 www.mdpi.com/journal/applsci Appl. Sci. 2018, 8, 1553 2 of 11 nanowire process flow should be highly compatible with the traditional CMOS technology considering its manufacturability.Appl. Sci. 2018, 8, x FOR PEER REVIEW 2 of 11 For the first challenge, we proposed a triangular shape to be the optimized cross section for the nanowire process flow should be highly compatible with the traditional CMOS technology nanowireconsidering and to its confirm manufacturability. its advantages in scalability and performance by TCAD simulation. For the second issue,For the we first adopted challenge, the we anisotropic proposed TMAH a triangular wet etchingshape to processbe the optimized to form thecross suspended section fornanowire the channelnanowire with and a stable, to confirm smooth, its advantages and precisely-size-controlled in scalability and performance inverted by triangular TCAD simulation. cross section For the shape. Thesecond low-temperature issue, we adopted mobility the characterization anisotropic TMAH was wet then etching carried process out to to evaluate form the the suspended benefitto the suppressionnanowire ofchannel surface with roughness a stable, scattering smooth, and by theprecisely-size-controlled self-limited structure. inverted triangular cross section shape. The low-temperature mobility characterization was then carried out to evaluate the 2. Simulationbenefit to the suppression of surface roughness scattering by the self-limited structure.

2.1. Device2. Simulation Parameters

2.1.GAA Device SNWTs Parameters with three typical cross-sectional shapes, including triangles, squares, and circles, were simulated by TCAD tool Synopsys Sentaurus. The schematic structure of the device with three GAA SNWTs with three typical cross-sectional shapes, including triangles, squares, and circles, different cross-sectional shapes is shown in Figure1. Considering the consistency in fabrication, the were simulated by TCAD tool Synopsys Sentaurus. The schematic structure of the device with three threedifferent nanowires cross-sectional were set asshapes the same is shown line in width Figure D. 1. Some Considering key process the consistency parameters in fabrication, were based the on the requirementsthree nanowires for a 5were nm set technology as the same node line inwidth IRDS D. 2017 Some [ 8key]. process parameters were based on the requirementsOwing to the for excellent a 5 nm technology controllability node in of IRDS the 2017 channel [8]. potential in GAA SNWTs, the silicon ﬁlm thicknessOwing or line to width the excellent of nanowire controllability can be relaxed of the channel to Lg [9 potential]. Therefore, in GAA the SNWTs, nanowire the width silicon of film the GAA SNWTsthickness was set or toline 16 width nm according of nanowire to IRDS can be 2017, relaxed and to the Lg gate [9]. lengthTherefore, was the set nanowire to the range width of 12of the to 28 nm. TheGAA other SNWTs device was parameters set to 16 nm are according listed in to Table IRDS1 2017,. The and models the gate we length used was in Sentaurusset to the range tools of include12 Mobilityto 28 nm. (PhuMob The other &high device ﬁeld parameters saturation are listed & Enormal), in Table 1. Effective The models Intrinsic we used Density, in Sentaurus Recombination tools include Mobility (PhuMob &high field saturation & Enormal), Effective Intrinsic Density, (SRH(DopingDep)), and Quantum Potential model. Recombination (SRH(DopingDep)), and Quantum Potential model.

FigureFigure 1. Schematic 1. Schematic structure structure of GAA of GAA SNWTs SNWTs with threewith th cross-sectionalree cross-sectional shapes shapes used inused the in simulation. the simulation.

Table 1. Table 1.Device Device parameters used used in in the the simulation. simulation.

DeviceDevice Parameter Parameter Value Value Gate length (nm) 12~28 Gate length (nm) 12~28 Gate overlap length (nm) 0 Gate overlap length (nm) 0 NanowireNanowire width width (nm) (nm) 16 16 EOTEOT (nm) (nm) 0.67 0.67 ChannelChannel doping doping concentration concentration (cm− (cm3)−3) 1 1 ×× 101016 16 Source/DrainSource/Drain extension extension doping doping concentration concentration (cm− (cm3) −3) 55 ×× 101019 19 Source/DrainSource/Drain doping doping concentration concentration (cm− (cm3)−3) 1 1 ×× 101020 20 DopingDoping gradient gradient (nm/dec) (nm/dec) 1 1 Appl. Sci. 2018, 8, 1553 3 of 11 Appl. Sci. 2018, 8, x FOR PEER REVIEW 3 of 11

2.2.2.2. SimulationSimulation ResultsResults

Figure 2a–c shows the trends of Vth, SS, and DIBL as a function of gate length in different cross- Figure2a–c shows the trends of V th, SS, and DIBL as a function of gate length in different cross-sectionalsectional GAA GAASNWTs. SNWTs. From FromFigure Figure 2a, it 2cana, it be can no beticed noticed that the that triangular the triangular devices devices have the have lowest the Vth roll-off, whether in the linear region or the saturation region. Here, the Vth values of long channel lowest Vth roll-off, whether in the linear region or the saturation region. Here, the Vth values of long channeldevices deviceswith three with cross-sectional three cross-sectional shapes differ shapes from differ each from other, each whic other,h is whichmainly is due mainly to the due different to the differentwork functions work functions of the gate of thematerial. gate material. For the triangul For thear, triangular, circular, circular,and square and devices, square devices, they are they 4.37 areeV, 4.374.53 eV,eV, 4.53 and eV, 4.60 and eV, 4.60 respectively. eV, respectively. This is This to maintain is to maintain the same the sameoff-state off-state current current of 100 of nA/ 100μ nA/m whenµm whencomparing comparing the on-state the on-state current current of short of shortchannel channel device devices.s. In addition, In addition, it can also it can be also found be foundfrom Figure from Figure2b,c that2b,c the that triangular the triangular devices devices also have also smaller have smallerDIBL and DIBL SS under and SS the under same the gate same length gate condition. length condition.Even for GAA Even SNWTs for GAA with SNWTs the same with linewidth the same of linewidth 16 nm, only of 16 the nm, triangular only the devices triangular can devicessuccessfully can successfullyreduce the reducegate length the gate to 16 length nm tounder 16 nm the under requirement the requirement of SS < of 67mV/dec, SS < 67mV/dec, which which met IRDS met IRDS 2017 2017requirements requirements on the on 5 the nm 5 technology nm technology node node [8], [as8], shown as shown in Figure in Figure 2d.2 Additionally,d. Additionally, compared compared to tothe theworst worst quadrate quadrate GAA GAA SNWTs, SNWTs, the the gate gate length length of oftriangular triangular one one is isreduced reduced by by approximately approximately 8 8nm. nm.

0.5 D=16nm 400 Square 0.4 Circle Triangle 0.3 300 D=16nm

(V) 0.2

th 200 V 0.1 Vtlin/Vtsat Square DIBL (mV/V) DIBL V /V Circle 100 0.0 tlin tsat V /V Triangle tlin tsat -0.1 0 12 16 20 24 28 12 16 20 24 28 (a)Lg (nm) (b) Lg(nm)

180 26 Square 160 Circle 24 Triangle 140 22

120 D=16nm 20 SS<67mV/dec (nm) D=16nm 100 g

L D=16nm 18 SS<70mV/dec

SS (mV/dec) DIBL<50mV/dec 80 16 60 5nm7/8nm target target by IRDS by ITRS 2017 14 12 16 20 24 28 SCT (c)L (nm) (d) Cross-sectional Shape g

FigureFigure 2. 2.( a(a––cc)) The The trend trend of of V Vthth,, SS, SS, and and DIBL DIBL for for different different cross-sectional cross-sectional shapes shapes of of GAA GAA SNWTs SNWTs as as a functiona function of gateof gate length; length; (d )(d The) The ability ability to scaleto scale down down GAA GAA FETs FE withTs with different different cross-sections. cross-sections.

TheThe electrostatic electrostatic controllability controllability and shortand channelshort ch effectsannel affecteffects not affect only static not poweronly consumption,static power butconsumption, also driving but capability. also driving Given thecapability. ﬁxed off-state Given current, the fixed SCE off-state determines current, the threshold SCE determines voltage level, the threshold voltage level, which will impact the device’s overdrive voltage—Vgs-Vth, and hence on-state which will impact the device’s overdrive voltage—Vgs-Vth, and hence on-state current. Figure3 shows thecurrent. relationship Figure 3 between shows the relationship off-state current between and thethe on-stateoff-state currentcurrent forand GAA the on-state SNWTs withcurrent three for cross-sectionsGAA SNWTs underwith three different cross-sections gate length under conditions. different From gate Figure length3, itconditions. is noticed thatFrom the Figure triangular 3, it is devicesnoticed havethat the the triangular best on/off devices ratio. have Under the the best same on/off off-state ratio. Under current the of same 100 nA/off-stateµm, duecurrent to betterof 100 electrostaticnA/μm, due control to better capability electrostatic and SCE control immunity, capability the triangularand SCE immunity, devices have the a triangular higher on-state devices current, have reachinga higher 940on-stateµA/ µcurrent,m, which reaching is nearly 940 10% μA/ higherμm, which than is that nearly of the 10% circular higher devices, than that and of nearlythe circular 36% higherdevices, than and quadrate nearly 36% ones. higher than quadrate ones. Appl. Sci. 2018, 8, x FOR PEER REVIEW 4 of 11 Appl. Sci. 2018, 8, 1553 4 of 11 Appl. Sci. 2018, 8, x FOR PEER REVIEW 4 of 11

100000 100000 Square 10000 CircleSquare 10000 1000 TriangleCircle 1000 100 Triangle m)  100 m) 10 

(nA/ 10 1 off (nA/ I 1 D=16nm 0.1 off I LD=16nm=12~28nm 0.1 g 0.01 Step=4nmLg=12~28nm 0.01 1E-3 Step=4nm 500 600 700 800 900 1000 1100 1E-3 500 600 700I ( 800A/mm) 900 1000 1100 on Ion (A/mm) Figure 3. The relationship between the off-state and the on-state current of different cross-sectional GAAFigure SNWTs 3. The withrelationship varying betweengate length. the off-state and the on-state current of different cross-sectional GAA SNWTs with varying gate length. 2.3. Equivalent Model 2.3. Equivalent Model 2.3. EquivalentIn order to Model further investigate the advantages of triangular devices, we compared the trends of

th In orderon to further investigate the advantages of triangular devices, we compared the trends ofth V andIn orderI with to furthera cross-sectional investigate area the advantagesof different of GA triangularA SNWTs. devices, From weFigure compared 4, we thecan trends see that of VVth Vth andon Ion with a cross-sectional area of different GAA SNWTs. From Figure 4, we can see that Vth and Ion havewith a cross-sectionallinear correlation area with of different the cross-sectional GAA SNWTs. area, From and Figure are almost4, we can independent see that V thofand cross- Ion sectionalandhave Ion a linearhave shape, a correlation linear so the correlation cross-sectio with the with cross-sectionalnal areathe cross-sectional is the root area, factor and area, areaffect almostanding are the independent almost short channelindependent ofcross-sectional effect of of cross-GAA SNWTs.sectionalshape, so shape, the cross-sectional so the cross-sectio area isnal the area root is factor the root affecting factor theaffect shorting the channel short effect channel of GAA effect SNWTs. of GAA SNWTs. 35 0.5 35 square 0.5 square 30 circular 0.4 30 triangularcircular 0.4 25 triangular

25 0.3 V th A)

20 0.3 V  (V) th A) ( 20 

0.2 (V) on ( I 15 0.2 on

I 15 10 0.1 0.1 10 Lg=14nm 5 Lg=14nm 0.0 0 40 80 120 160 200 5 2 0.0 0 40Area 80 (nm 120) 160 200 2 Area (nm )

FigureFigure 4.4. TheThe trendstrends ofof VVthth and I on withwith cross-sectional cross-sectional area area in in GAA GAA SNWTs SNWTs. Figure 4. The trends of Vth and Ion with cross-sectional area√ in GAA SNWTs π 3 = 2 2 = π 2 2 =√3 2 2 SsquareSsquareD =D,Scircle, Scircle= DD,S, triangleStriangle= D D (1)(1) 2 4π4 2 √43 4 2 Ssquare=D , Scircle= D , Striangle= D (1) For quadrate, circular, circular, and triangular nanowire 4 de devices,vices, the relationship 4 between line width and and cross-sectionalFor quadrate, area circular, is shown and in Equationtriangular (1). nanowire The The triangular triangular devices, devices devicesthe relationship have have the the betweensmallest smallest cross-sectionalline cross-sectional width and areacross-sectional under the samearea is line shown width width in condition,Equation condition, (1). and and The thus thus triangular have have the the devices strongest strongest have electros electrostatic the smallesttatic control control cross-sectional capability capability andarea can under obtain the samethe best line device width performance. condition, and thus have the strongest electrostatic control capability and can obtain the best device performance. 3. Experiments Experiments 3. Experiments According to the simulation results, triangular cross-sectional GAA GAA SNWTs SNWTs have superior SCE controllabilityAccording compared compared to the simulation to to circular circular results, or quadrate triangular ones, cross-sectional which makes GAA them SNWTs promising have in insuperior a sub-5 SCE nm node.controllability However,However, compared another another concern toconcern circular comes comes or fromquadrate from the lack ones,the oflack awhich feasible of amakes feasible method them formethod promising forming for such informing a suspended sub-5 such nm suspendednode.silicon However, nanowire silicon withanother nanowire an accurately concern with an controlledcomes accurately from size cothe andntrolled lack cross-sectional of size a andfeasible cross-sectional shape, method which for is shape, quiteforming criticalwhich such tois suspended silicon nanowire with an accurately controlled size and cross-sectional shape, which is Appl. Sci. 2018, 8, 1553 5 of 11 Appl. Sci. 2018, 8, x FOR PEER REVIEW 5 of 11 thequite device critical variability to the device suppression variability and suppression mobility behavior. and mobility The existing behavior. works The didexisting not achieveworks did either not processachieve variationeither process suppression variation [10 suppression] or a precisely-controlled [10] or a precisely-controlled equilateral triangle equilateral [7,11], triangle and also [7,11], did notand give also thedid mobilitynot give characterizationthe mobility characterization at a low temperature, at a low temperature, which reﬂects which the surfacereflects roughnessthe surface scatteringroughness [ 12scattering]. [12]. TMAHTMAH isis the the abbreviation abbreviation for Tetramethylammoniumfor Tetramethylammonium Hydroxide, Hydroxide, a kind ofa photoresistkind of photoresist developer whichdeveloper was provenwhich was to be proven an excellent to be anisotropic an excellent si-etching anisotropic solution. si-etching Therefore, solution. we intended Therefore, to thewe adoptintended TMAH to the wet adopt etching TMAH technique wet toetching get the techniqu triangulare to nanowires, get the triangular which can nanowires, accurately controlwhich thecan sizeaccurately of nanowires control and the produce size of ananowires nearly-equilateral and prod triangleuce a nearly-equilateral thanks to the extremely triangle high thanks anisotropic to the corrosionextremely rate high of anisotropic (1 0 0) and (1corrosion 1 0) to (1 rate 1 1) of crystal (1 0 0) plane and (1 by 1 TMAH 0) to (1 wet 1 1) etching. crystal plane Meanwhile, by TMAH the wetwet etchingetching. technique Meanwhile, can the avoid wet surface etching damage technique induced can avoid by dry surface etching damage so that induced the channel by dry mobility etching can so bethat enhanced. the channel mobility can be enhanced.

3.1.3.1. KeyKey ProcessProcess ofof TriangularTriangular Nanowire Nanowire Formation Formation OwingOwing to to different different atomic atomic densities densities of crystalof crystal planes, planes, the etchingthe etching rate of rate TMAH of TMAH on (1 1 on 1) is(1 usually 1 1) is muchusually smaller much thansmaller that than on that (1 0 on 0) and(1 0 0) (1 and 1 0), (1 so 1 0), the so etching the etching of TMAH of TMAH can becan self-stopped be self-stopped [13– [13–15]. A15]. schematic A schematic diagram diagram of suspended of suspended triangular triangular nanowires nanowires by TMAH by wetTMAH etching wet isetching shown is in shown Figure 5in. ThisFigure process 5. This can process accurately can controlaccurately the sizecontrol and the shape size of and the shape silicon of nanowires, the silicon which nanowires, are formed which from are differentformed from initial different line widths initial of the line silicon widths Fin. of The the specific silicon processFin. The flow specific is listed process as follows: flow is listed as follows: 1. Thermal oxidation to produce a silicon oxide buffer layer; 2.1. ChemicalThermal oxidation vapor deposition to produce to producea silicon siliconoxide buffer nitride layer; as a hard mask layer; 3.2. ElectronChemical beam vapor lithography deposition andto produce anisotropic silicon dry nitride etching as toa hard form mask a silicon layer; nitride hard mask and 3. siliconElectron Fins; beam lithography and anisotropic dry etching to form a silicon nitride hard mask and 4. Removesilicon Fins; the native oxide on the silicon surface with a dilute hydrofluoric acid solution at 4. roomRemove temperature; the native oxide on the silicon surface with a dilute hydrofluoric acid solution at room 5. Anisotropictemperature; wet etching silicon Fins at 35 ◦C and in 25% TMAH solution, so triangular silicon 5. nanowiresAnisotropic are wet formed etching under silicon the siliconFins at nitride35 °C and hard in mask, 25% whileTMAH the solution, silicon substrate so triangular will alsosilicon be etchednanowires to form are formed a triangle; under the silicon nitride hard mask, while the silicon substrate will also be etched to form a triangle; 6. Remove silicon nitride hard mask by 170 ◦C phosphoric acid; 6. Remove silicon nitride hard mask by 170 °C phosphoric acid; 7. Remove the silicon oxide buffer layer by diluted hydrofluoric acid at room temperature, and the 7. Remove the silicon oxide buffer layer by diluted hydrofluoric acid at room temperature, and the triangular suspended silicon nanowires are achieved. triangular suspended silicon nanowires are achieved.

FigureFigure 5.5. TheThe diagramdiagram ofof triangulartriangular suspendedsuspended nanowirenanowireby byTMAH. TMAH.

WhenWhen thethe TMAHTMAH solutionsolution etchesetches thethe sideside ofof thethe siliconsilicon Fin,Fin, thethe etchingetching windowwindow isis determineddetermined byby thethe toptop siliconsilicon nitridenitride hardhard maskmask andand thethe bottombottom cornerscorners ofof siliconsilicon Fin.Fin. IfIf thethe siliconsilicon FinsFins havehave aa sufﬁcientsufficient height height and and long long enough enough etching etching time, time, both both sides sides of of thethe siliconsilicon FinsFins willwill bebe completelycompletely etchedetched andand leadlead toto punch-through,punch-through, anan invertedinverted triangulartriangular siliconsilicon nanowirenanowire willwill bebe formedformed underunder thethe siliconsilicon nitridenitride hardhard mask,mask, andand aa triangletriangle bumpbump onon thethe siliconsilicon substratesubstrate willwill bebe simultaneouslysimultaneously formed,formed, asas shownshown inin FigureFigure5 .5. At At this this time, time, the the side side surfaces surfaces formed formed by by the the wet wet etching etching are are all all (1 (1 1 1 1) 1) crystal crystal planes,planes, presentingpresenting anan angleangle of of 54.7 54.7°◦ with with thethe (1(1 00 0)0) crystalcrystal planeplane of of thethe surface. surface. Figure 6 illustrates the SEM images of different TMAH etching times of the triangular device, and it is noted that even if the over-etching time has exceeded 10 s (over-etching time exceeds 50%) Appl. Sci. 2018, 8, 1553 6 of 11

Figure6 illustrates the SEM images of different TMAH etching times of the triangular device, Appl. Sci. 2018, 8, x FOR PEER REVIEW 6 of 11 and it is noted that even if the over-etching time has exceeded 10 s (over-etching time exceeds 50%) in Figure6c, the width and cross section of the silicon nanowires remain basically the same, and only in Figure 6c, the width and cross section of the silicon nanowires remain basically the same, and only the sharp corners are slightly etched, indicating that the TMAH etching technology has the strong the sharp corners are slightly etched, indicating that the TMAH etching technology has the strong capability to suppress cross section ﬂuctuations. capability to suppress cross section fluctuations.

Figure 6. 35 °C, 25% TMAH solution is used to etch a silicon Fin with a 50 nm width. The SEM images Figure 6. 35 ◦C, 25% TMAH solution is used to etch a silicon Fin with a 50 nm width. The SEM images obtained after different etching times (a–c): 0 s/20 s/30 s. obtained after different etching times (a–c): 0 s/20 s/30 s.

3.2. Fabrication of GAA SNWT with Triangular Cross Section 3.2. Fabrication of GAA SNWT with Triangular Cross Section Based on the above analysis, we adopted the TMAH wet etching technique to fabricate a P-type Based on the above analysis, we adopted the TMAH wet etching technique to fabricate a P-type inverted triangular cross-sectional GAA FET on a bulk-si substrate, as shown in Figure 7. The process inverted triangular cross-sectional GAA FET on a bulk-si substrate, as shown in Figure7. The process flow is given as follows: ﬂow is given as follows: 1. Channel Engineering 1. Channel Engineering  thermal oxidation on a bulk silicon substrate to produce a silicon oxide buffer layer; • chemicalthermal oxidationvapor deposition on a bulk to silicon produce substrate a silicon to nitride produce hard a silicon mask oxidelayer; buffer layer; • opticalchemical lithography, vapor deposition anisotropic to produce dry etching, a silicon and nitride oxidation hard maskto produce layer; LOCOS isolation, • andoptical active lithography, regions are anisotropic achieved; dry etching, and oxidation to produce LOCOS isolation, and  chemicalactive regions vapor are deposition achieved; to produce a polysilicon hard mask layer; • electronchemical beam vapor lithography deposition and to produce anisotropic a polysilicon dry etching hard to maskproduce layer; a polysilicon hard mask; • electronelectron beam beam lithography and anisotropic dry etchingetching toto produceform a silicon a polysilicon nitride hard mask;mask • andelectron Si Fins; beam lithography and anisotropic dry etching to form a silicon nitride hard mask

 removeand Si Fins; the native oxide on the silicon surface by the diluted hydrofluoric acid solution at room temperature; • remove the native oxide on the silicon surface by the diluted hydrofluoric acid solution at  Si Fin anisotropic wet etching by TMAH solution to form inverted triangular nanowires room temperature; under the silicon nitride hard mask; • Si Fin anisotropic wet etching by TMAH solution to form inverted triangular nanowires  high-energy ion implantation is performed on the active region to generate N− doping as under the silicon nitride hard mask; an N− well of PMOS; • high-energy ion implantation is performed on the active region to generate N− doping as  low-energy ion implantation is performed on the active region, and only the exposed area an N− well of PMOS; in the trench can generate N+ doping, preventing the bottom parasitic transistor from • turninglow-energy on; ion implantation is performed on the active region, and only the exposed area  removein the trench the silicon can generatenitride hard N+ mask doping, and preventingthe silicon oxide the bottom buffer parasiticlayer by phosphoric transistor fromacid andturning diluted on; hydrofluoric acid, and suspended silicon nanowires are obtained; • sacrificialremove the oxidation silicon nitride to round hard the mask corner and of thetriangular silicon oxidenanowires; buffer layer by phosphoric acid  removeand diluted sacrificial hydrofluoric oxide by acid, diluted and hydrofluoric suspended silicon at room nanowires temperature; are obtained; • sacrificial oxidation to round the corner of triangular nanowires; 2. Gate Engineering • remove sacrificial oxide by diluted hydrofluoric at room temperature;  thermal oxidation to produce gate oxide; 2. Gate Engineering  chemical vapor deposition to generate a polysilicon gate material layer; • polysiliconthermal oxidation gate ion to implantation produce gate and oxide; rapid thermal annealing;

• electronchemical beam vapor lithography deposition and to generate anisotropic a polysilicon dry etching gate to materialproduce layer;the polysilicon gate; 3. Source and drain Engineering  high-dose implantation is performed on large fan-out regions of source and drain, followed by rapid thermal annealing;  chemical vapor deposition to produce the isolation layer; Appl. Sci. 2018, 8, 1553 7 of 11

• polysilicon gate ion implantation and rapid thermal annealing; • electron beam lithography and anisotropic dry etching to produce the polysilicon gate;

3. Source and drain Engineering

• high-dose implantation is performed on large fan-out regions of source and drain, followed by rapid thermal annealing; Appl. Sci.• 2018chemical, 8, x FORvapor PEER REVIEW deposition to produce the isolation layer; 7 of 11 • optical lithography and dry etching to form the contact holes;  optical lithography and dry etching to form the contact holes; • metal contacts and interconnections formation.  metal contacts and interconnections formation.

FigureFigure 7.7. ProcessProcess forfor fabricatingfabricating P-typeP-type GAAGAA SNWTSNWT byby thethe TMAHTMAH wetwet etchingetching techniquetechnique onon aa bulkbulk siliconsilicon substrate.substrate.

There is a bottom parasitic transistor below the silicon nanowire device, and we need to There is a bottom parasitic transistor below the silicon nanowire device, and we need to effectively effectively suppress it. A common practice is to insert an isolation layer between the gate material suppress it. A common practice is to insert an isolation layer between the gate material and the parasitic and the parasitic transistor, but chemical planar polishing (CMP) equipment is required to complete transistor, but chemical planar polishing (CMP) equipment is required to complete the planarization the planarization treatment. Due to the lack of CMP, high-dose implantation in the trench is used treatment. Due to the lack of CMP, high-dose implantation in the trench is used here, which can here, which can greatly increase the channel doping concentration and the threshold voltage of the greatly increase the channel doping concentration and the threshold voltage of the parasitic transistor, parasitic transistor, thereby preventing it from turning on. The silicon nanowire channel can still thereby preventing it from turning on. The silicon nanowire channel can still maintain a low doping maintain a low doping concentration due to the protection of the silicon nitride hard mask. After the concentration due to the protection of the silicon nitride hard mask. After the suspended silicon suspended silicon nanowires are formed, the triangular silicon nanowires are sacrificially oxidized nanowires are formed, the triangular silicon nanowires are sacriﬁcially oxidized slightly to make their slightly to make their sharp corners round, avoiding the reliability issues of the device. sharp corners round, avoiding the reliability issues of the device.

4.4. DeviceDevice CharacteristicsCharacteristics FigureFigure8 8aa is is an an SEM SEM image image of of multiple multiple suspended suspended silicon silicon nanowires nanowires formed formed by by the the TMAH TMAH wet wet etchingetching technique.technique. Each Each silicon silicon nanowire nanowire has has good good uniformity. uniformity. Figure Figure8b is 8b a TEM is a cross-sectionalTEM cross-sectional view ofview the siliconof the silicon nanowire nanowire after the after gate the oxidation gate oxid processation and process gate materialand gate deposition, material deposition, which turned which out toturned be an out inverted to be triangle,an inverted and triangle, the angle and between the angl thee self-stoppedbetween the (1self-stopped 1 1) and the (1 surface 1 1) and crystal the surface plane iscrystal close plane to the is theoretical close to the 54.7 theoretical◦, almost reaching54.7°, almost an equilateral reaching an triangle equilateral apex. triangle apex.

Figure 8. (a) SEM image of multiple suspended silicon nanowires formed by TMAH etching; (b) TEM image of silicon nanowires after gate oxidation and polysilicon gate deposition. Appl. Sci. 2018, 8, x FOR PEER REVIEW 7 of 11

 optical lithography and dry etching to form the contact holes;  metal contacts and interconnections formation.

Figure 7. Process for fabricating P-type GAA SNWT by the TMAH wet etching technique on a bulk silicon substrate.

There is a bottom parasitic transistor below the silicon nanowire device, and we need to effectively suppress it. A common practice is to insert an isolation layer between the gate material and the parasitic transistor, but chemical planar polishing (CMP) equipment is required to complete the planarization treatment. Due to the lack of CMP, high-dose implantation in the trench is used here, which can greatly increase the channel doping concentration and the threshold voltage of the parasitic transistor, thereby preventing it from turning on. The silicon nanowire channel can still maintain a low doping concentration due to the protection of the silicon nitride hard mask. After the suspended silicon nanowires are formed, the triangular silicon nanowires are sacrificially oxidized slightly to make their sharp corners round, avoiding the reliability issues of the device.

4. Device Characteristics Figure 8a is an SEM image of multiple suspended silicon nanowires formed by the TMAH wet etching technique. Each silicon nanowire has good uniformity. Figure 8b is a TEM cross-sectional view of the silicon nanowire after the gate oxidation process and gate material deposition, which turnedAppl. Sci. out2018 to, 8 ,be 1553 an inverted triangle, and the angle between the self-stopped (1 1 1) and the surface8 of 11 crystal plane is close to the theoretical 54.7°, almost reaching an equilateral triangle apex.

Figure 8. (a) SEM image of multiple suspended silicon nanowires formed by TMAH etching; (b) TEM Figure 8. (a) SEM image of multiple suspended silicon nanowires formed by TMAH etching; (b) TEM image of silicon nanowires after gate oxidation and polysilicon gate deposition. Appl. imageSci. 2018 of, 8 silicon, x FOR nanowiresPEER REVIEW after gate oxidation and polysilicon gate deposition. 8 of 11

FigureFigure9 a,b9a,b shows shows the the transfer transfer and outputand output characteristics characteristics of a P-type of a GAAP-type SNWT GAA with SNWT a triangular with a crosstriangular section. cross The section. nanowire The nanowire had a line had width a line of wi 20dth nm of and 20 anm gate and length a gate of length 140 nm. of 140 Under nm. Under a bias voltagea bias voltage of 1.0 V, of the 1.0 on-state V, the on-state current normalizedcurrent normalized by the line by widththe line reached width 1402reachedµA/ 1402µm, μ theA/ leakageμm, the currentleakagewas current limited was to limited 0.4 nA/ toµ 0.4m, nA/ andμ them, and on/off the ratioon/off exceeded ratio exceeded 106. Furthermore, 106. Furthermore, the device the device had a lowhad subthresholda low subthreshold slope ofslope 85 mV/dec of 85 mV/dec and DIBL and ofDIBL 63mV/V. of 63 mV/V. FigureFigure 1010 illustratesillustrates thethe trendstrends ofof subthresholdsubthreshold slope,slope, DIBL,DIBL, andand thresholdthreshold voltagevoltage withwith differentdifferent gategate lengthslengths forfor thethe triangulartriangular GAAGAA SNWTs.SNWTs. FromFrom FigureFigure 1010a,a, itit cancan bebe foundfound thatthat thethe subthresholdsubthreshold slopeslope remained almost almost constant constant as as the the gate gate length length decreased, decreased, while while the theDIBL DIBL increased increased slightly. slightly. The Thereason reason why why DIBL DIBL degraded degraded with with the gate the gatelength length scaling scaling more more obviously obviously is that is thatthe polysilicon the polysilicon gate gateoverlapped overlapped the trench, the trench, resulting resulting in the in the device’s device’s source source and and drain drain extension extension regions regions not not being aa nanowirenanowire structure,structure, but but the the traditional traditional planar planar structure. structure. Hence, Hence, the high the levelhigh drainlevel voltagedrain voltage can impose can aimpose greater a inﬂuence greater oninfluence the channel on the potential. channel In potential. Figure 10 b,In the Figure threshold 10b, voltagethe threshold of the triangular voltage of GAA the SNWTstriangular in theGAA linear SNWTs and saturatedin the linear region and is saturated almost constant region asis almost the gate constant length is as varying, the gate indicating length is thatvarying, it had indicating an excellent that SCE it had suppressing an excellent capability. SCE suppressing capability.

1600 3 10 V =0.05V

m) 2 ds m)

 10  1 V =1.0V A/ 10 ds A/ 1200   ( 100 ( ds -1 ds 10 800

10-2 Vgs=0.0~-1.0V 10-3 Step=-0.2V 400 10-4 10-5 Drain Current I Current Drain I Current Drain 10-6 0 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 (a) Vgs (V) (b) Vgs (V)

FigureFigure 9.9. (a) Transfer characteristic; ( (bb)) output output characteristic characteristic of of P-ty P-typepe triangular triangular GAA GAA SNWT SNWT with with D D= 20 = 20nm nm and and Lg L=g 140= 140 nm. nm.

100 100 -0.3 Vtlin

80 80 (V) Vtsat th -0.2 DIBL(mV/V) 60 60 -0.1

40 40 SS DIBL 0.0 20 20 D=20nm D=20nm

0 0 voltage V Threshold 0.1 120 140 160 180 200 220 240 260 120 140 160 180 200 220 240 260 Subthreshold Swing(mV/dec) (a) Lg(nm) (b) Lg(nm)

Figure 10. The trends of SS, DIBL, and Vth with Lg for triangular cross-sectional GAA SNWTs.

5. Mobility Model In this section, we plan to characterize the carrier mobility in the fabricated GAA SNWTs by Bias-Temperature experiments so that surface roughness mobility can be obtained at a low temperature, which can verify the benefit to mobility resulting from the stable and smooth triangular cross-sectional shape. The Y-function method can be used to extract the mobility of the fabricated triangular cross- sectional GAA SNWTs [16]. The Y function can be calculated as follows: Appl. Sci. 2018, 8, x FOR PEER REVIEW 8 of 11

Figure 9a,b shows the transfer and output characteristics of a P-type GAA SNWT with a triangular cross section. The nanowire had a line width of 20 nm and a gate length of 140 nm. Under a bias voltage of 1.0 V, the on-state current normalized by the line width reached 1402 μA/μm, the leakage current was limited to 0.4 nA/μm, and the on/off ratio exceeded 106. Furthermore, the device had a low subthreshold slope of 85 mV/dec and DIBL of 63 mV/V. Figure 10 illustrates the trends of subthreshold slope, DIBL, and threshold voltage with different gate lengths for the triangular GAA SNWTs. From Figure 10a, it can be found that the subthreshold slope remained almost constant as the gate length decreased, while the DIBL increased slightly. The reason why DIBL degraded with the gate length scaling more obviously is that the polysilicon gate overlapped the trench, resulting in the device’s source and drain extension regions not being a nanowire structure, but the traditional planar structure. Hence, the high level drain voltage can impose a greater influence on the channel potential. In Figure 10b, the threshold voltage of the triangular GAA SNWTs in the linear and saturated region is almost constant as the gate length is varying, indicating that it had an excellent SCE suppressing capability.

1600 3 10 V =0.05V

m) 2 ds m)

 10  1 V =1.0V A/ 10 ds A/ 1200   ( 100 ( ds -1 ds 10 800

10-2 Vgs=0.0~-1.0V 10-3 Step=-0.2V 400 10-4 10-5 Drain Current I Current Drain I Current Drain 10-6 0 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 (a) Vgs (V) (b) Vgs (V)

Appl. Sci.Figure2018 ,9.8 ,( 1553a) Transfer characteristic; (b) output characteristic of P-type triangular GAA SNWT with D9 of 11 = 20 nm and Lg = 140 nm.

100 100 -0.3 Vtlin

80 80 (V) Vtsat th -0.2 DIBL(mV/V) 60 60 -0.1

40 40 SS DIBL 0.0 20 20 D=20nm D=20nm

0 0 voltage V Threshold 0.1 120 140 160 180 200 220 240 260 120 140 160 180 200 220 240 260 Subthreshold Swing(mV/dec) (a) Lg(nm) (b) Lg(nm)

FigureFigure 10.10. The trends ofof SS,SS, DIBL,DIBL, andand VVthth with L g forfor triangular triangular cross-sectional cross-sectional GAA GAA SNWTs. SNWTs.

5. Mobility Model In this section, section, we we plan plan to to characterize characterize the the carrier carrier mobility mobility in inthe the fabricated fabricated GAA GAA SNWTs SNWTs by byBias-Temperature Bias-Temperature experiments experiments so sothat that surfac surfacee roughness roughness mobility mobility can can be be obtained obtained at at a a low temperature, whichwhich cancan verify the beneﬁtbenefit to mobility resulting from the stable and smooth triangular cross-sectional shape.shape. Appl. Sci.The 2018 Y-function Y-function, 8, x FOR PEER method method REVIEW cancan be be used used to extract to extract the themobility mobility of the of fabricated the fabricated triangular triangular 9cross- of 11 cross-sectionalsectional GAA GAASNWTs SNWTs [16]. The [16]. Y The functi Y functionon can be can calculated be calculated as follows: as follows: Ids Y≡ =k0VdsVgs − Vth, (2) Idsgm p Y ≡ √ = k0Vds Vgs − Vth , (2) gm Here, k0 is given by W μC Here, k0 is given by k = eff ox, 0 L (3) WeffµeffCox k0 = , (3) Firstly, the driving current Ids and the transconductanceLeff gm of the GAA SNWTs in the linear regionFirstly, were measured the driving to currentobtain the Ids andY function, the transconductance and then the intercept gm of the of GAAthis straight SNWTs line in theat the linear x- axisregion was were the measuredthreshold voltage to obtain V theth and Y function, the mobility and of then the the device intercept was ofextracted this straight by the line slope at the k0. x-axis This methodwas the can threshold be adopted voltage to Vextractth and the the trends mobility of mobi of thelity device varying was with extracted temperature, by the slope as shown k0. This in methodFigure 11a.can be adopted to extract the trends of mobility varying with temperature, as shown in Figure 11a.

800 12 700  700 sr ph Exp. T=4.3K 600 10 This work A) Exp. T=300K

 600

( Model T=4.3K 500 8

ds Model T=300K /Vs) 2 400 500

6 /Vs) 2 Exp. V =0.05V 300 4 ds Model 400 (cm D=20nm Ref.[18] w/o H2 anneal

2 eff D=20nm L =160nm Ref.[18] w/ H2 anneal 

Mobility (cm Mobility 200 g 300 Lg=160nm Drain Current I 0 200 10 100 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 100 101 102 103 (a)Temp.(K) (b) V (V) (c) gs T(K)

FigureFigure 11. 11. (a(a) )The The trend trend of of mobility mobility with with temperature temperature in in GAA GAA SNWTs; SNWTs; ( (bb)) comparison comparison of of current current simulationsimulation results results with with experimental experimental results results of ofGAA GAA SNWT SNWT at atT = T 4.3 = 4.3K and K and 300 300K, respectively; K, respectively; (c) effective(c) effective electron electron mobility mobility as a function as a function of temperature of temperature for triangular for triangular GAA SNWT GAA achieved SNWT achieved by TMAH by wet etching and quadrate SNWT with/without H2 annealing. TMAH wet etching and quadrate SNWT with/without H2 annealing.

It is noticed that the mobility is mainly determined by phonon scattering at room temperature, It is noticed that the mobility is mainly determined by phonon scattering at room temperature, and and the surface roughness scattering dominantly contributed to mobility when the temperature the surface roughness scattering dominantly contributed to mobility when the temperature dropped dropped below 70 K. Additionally, the Coulomb scattering had little effect on the mobility over the below 70 K. Additionally, the Coulomb scattering had little effect on the mobility over the entire entire temperature range because of the lower channel doping of the GAA SNWTs. Here, three kinds of mobility can be obtained by the following equations:

1 1 1 1 = + + , (4) μ μsr μph μcoulomb

-α, μph=AT (5)

α, μCoulomb=BT (6)

Here, μsr, μph, and μCoulomb denote the surface roughness mobility, the phonon scattering mobility, and the Coulomb scattering mobility, respectively. A and B are fitting coefficients, and α is the temperature coefficient. According to the scattering theory [17], α is set to 1.5. From Figure 11a, it can be seen that the modelling results can fit the experimental data quite well. The three fitting coefficients are μsr = 629 cm2/Vs, A = 2.38 × 106 cm2K1.5/Vs, and B = 2.42 × 106 cm2/K1.5Vs. As shown in Figure 11b, the device current in the linear region at two different temperatures was calculated using the mobility obtained by this model, and the modelling results are also in good agreement with the experimental results. It is worth mentioning that the mobility in our work is higher than that in GAA SNWTs with or without H2 annealing [18] in Figure 11c, indicating that the inverted triangle cross section achieved by TMAH wet etching can effectively reduce the influence of surface roughness scattering.

6. Conclusions We demonstrated a gate-all-around silicon nanowire transistor (GAA SNWT) with a triangular cross section by simulation and experiments. Through three-dimensional simulation tool Sentaurus, Appl. Sci. 2018, 8, 1553 10 of 11 temperature range because of the lower channel doping of the GAA SNWTs. Here, three kinds of mobility can be obtained by the following equations:

1 1 1 1 = + + , (4) µ µsr µph µcoulomb

−α µph = AT , (5) α µCoulomb = BT , (6)

Here, µsr, µph, and µCoulomb denote the surface roughness mobility, the phonon scattering mobility, and the Coulomb scattering mobility, respectively. A and B are fitting coefficients, and α is the temperature coefficient. According to the scattering theory [17], α is set to 1.5. From Figure 11a, it can be seen that the modelling results can fit the experimental data quite well. The three fitting 2 6 2 1.5 6 2 1.5 coefficients are µsr = 629 cm /Vs, A = 2.38 × 10 cm K /Vs, and B = 2.42 × 10 cm /K Vs. As shown in Figure 11b, the device current in the linear region at two different temperatures was calculated using the mobility obtained by this model, and the modelling results are also in good agreement with the experimental results. It is worth mentioning that the mobility in our work is higher than that in GAA SNWTs with or without H2 annealing [18] in Figure 11c, indicating that the inverted triangle cross section achieved by TMAH wet etching can effectively reduce the influence of surface roughness scattering.

6. Conclusions We demonstrated a gate-all-around silicon nanowire transistor (GAA SNWT) with a triangular cross section by simulation and experiments. Through three-dimensional simulation tool Sentaurus, it was found that with the same nanowire width, the triangular cross-sectional SNWT exhibited the lowest subthreshold swing, the highest on/off ratio, and the most excellent SCE immunity compared with the circular and quadrate ones, which may be attributed to the smallest equivalent distance from the nanowire center to the surface in triangular SNWTs. Then, P-type triangular GAA SNWTs with Lg = 140 nm and D = 20 nm were fabricated by the TMAH wet etching technique. Thanks to the anisotropic etching rate of the TMAH solution, a self-stopped etching behavior on a (1 1 1) crystal plane can be achieved, ensuring the accurately controlled size and cross-sectional shape of the channel. Finally, we measured and modelled the carrier mobility of fabricated devices with varying temperatures so as to extract the surface roughness mobility of 629 cm2/Vs, conﬁrming the beneﬁt of a stable and smooth cross section obtained by TMAH treatment.

Author Contributions: Conceptualization, M.L.; Methodology, M.L.; Software, G.C.; Formal Analysis, M.L. and G.C.; Data Curation, G.C.; Writing—Original Draft Preparation, G.C.; Writing—Review & Editing, M.L.; Project Administration, M.L. and R.H. Funding: This research received no external funding. Acknowledgments: This work was supported in part by the National Key Research and Development Plan (No. 2016YFA0200504), Program of National Natural Science Foundation of China (No. 61474004 & No. 61421005). The authors would like to thank the staff of National Key Laboratory of Micro/Nano Fabrication for the assistance in device fabrication. Conﬂicts of Interest: The authors declare no conﬂict of interest.

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