Effects of Testing Parameters in Capacitance-Voltage Profiling of MOS Capacitors
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6.152 SPRING 2009 1 Effects of Testing Parameters in Capacitance-Voltage Profiling of MOS Capacitors Tony Hyun Kim Abstract—Small-signal CV curves of MOS capacitors were about 35A=s˚ . The oxide layer on the backside of the wafer was observed as a function of various test parameters, such as etched by SF6 gas, in order to open up an electrical contact sweep direction and stepping rate of the bias voltage, lighting to the substrate-end of the MOS capacitor. conditions, and N2 flow over the device under test. Qualitative differences are found as the bias voltage behavior was changed; The capacitors were lithographed as follows: the aluminum- in particular, the phenomenon of deep-depletion was observed deposited wafer was first treated with hexamethyldisilazane at faster sweep rates. Furthermore, it is observed that improper (HMDS) in order to promote photoresist adhesion. Positive lighting conditions and unsintered devices yield CV curves that photoresist was applied and pre-baked at 95◦C for 30 seconds. differ from the direct measurements of the structural properties In the i-Stepper Projection Aligner Wafer Stepper, the wafers of the wafer, such as the doping level. were exposed through a mask containing square capacitors of various sizes. The post-exposure bake was at 110◦C for 30 I. INTRODUCTION seconds. The exposed photoresist regions were dissolved in the MALL-SIGNAL capacitance-voltage (CV ) measurement development process using TMAH. A gaseous mixture of Cl2 S is a standard technique for the characterization of semi- and BCl3 was then applied for 30 seconds to the wafers in the conductor devices. In this investigation, several square MOS reactive ion etching (R.I.E.) metal dry etch system to remove capacitors were fabricated and analyzed under various testing the unprotected aluminum, thereby defining the aluminum gate conditions. In particular, the sweep direction and stepping rate of the devices. In order to observe the electrical consequences of sintering, of the bias voltage source, lighting conditions, and N2 flow three out of the six wafers were then sintered for 15 minutes over the device under test were investigated for their effect on ◦ the CV curve of the capacitors. at 425 C degrees in 75% flow of forming gas; the other three Based on independent measurements of structural parame- remained unsintered as controls. ters, in particular the doping level of the substrate, the optimal CV testing settings can be discovered. B. CV Measurement 2 The experiment was conducted with square (100µm) and Small-signal capacitance of the MOS capacitor was mea- 2 (500µm) MOS capacitors. This investigation also evaluates sured at various bias voltages. The measured capacitances electrical consequences of sintering, in which the completed were normalized by the device area to yield capacitance device is annealed in hydrogen gas, neutralizing unbound per area, denoted by C∗. At different bias levels, the MOS silicon atoms (i.e. charged impurities) at the oxide interface. capacitor behaves in qualitatively different modes (inversion, It is shown that (lack of) sintering causes a horizontal shift in depletion, accumulation) which have measurable characteristic the CV curve corresponding to a shifted flatband voltage. capacitances, Cinv and Cacc = Cox. The different capaci- tances can be ascribed to the different charge distributions II. EXPERIMENT that arise within the structure at different DC biases. The bias A. Device Fabrication voltage level at which the capacitor transitions between modes V MOS capacitors were fabricated on ρ = 4:3 ± 1:5Ω · cm is given by the flatband voltage FB. 15 −3 These measurements can be utilized to deduce various n-type Si wafers, corresponding to ND ≈ 10 cm [1]. The resistivity was obtained by a four-point probe measurement of structural quantities of interest, such as the oxide thickness t N the sheet resistance, along with the manufacturer’s stated wafer ( ox), substrate doping level ( D), and interface impurity Q thickness of 675 ± 25µm. Following standard cleans used charges ( f ). They are related by the following formulas: to remove organic (10 minute, SC-1) and inorganic/metal-ion ox tox = ∗ (1) contaminants (15 minute, SC-2), and HF etch of native oxide, Cox ∗2 new oxide was grown by a one-hour atmospheric pressure 4 jΦF j CS ◦ ND = (2) dry oxidation at 1000 C. The thickness of the grown oxide qs was measured to be t = 483 ± 43A˚ by ellipsometry. These ∗ ox QF = −Cox (VFB − φMS) (3) reported values are averages over the set of six wafers that were developed for this experiment, hence the relatively large where are the permittivities and q is the fundamental standard deviations. charge; CS is the “semiconductor capacitance” which can be deduced from the measured capacitances according to the Subsequently, 2500A˚ of aluminum was deposited over the ∗ ∗ ∗ CoxCS kT ND oxide by physical vapor deposition. The deposition rate was formula Cinv = ∗ ∗ ; and finally ΦF = log is Cox+CS q ni 6.152 SPRING 2009 2 Fig. 1. The CV curves that result from sweeping the bias voltage from −5 Fig. 2. Variation in CV curves as the bias voltage sweeping rate is varied to 5 (blue) and from 5 to −5 (red). All other parameters are held constant. between a delay of 3 (blue) and 500 ms (red). In other words, blue represents (A) (100µm)2 capacitor at 3 ms delay; (B) (100µm)2 capacitor at 500 ms a faster sweep rate than red. All other parameters, including direction of delay; (C) (500µm)2 capacitor at 3 ms delay; (D) (500µm)2 non-sintered sweep, are held constant. (A) (100µm)2 capacitor, −5 to 5; (B) (100µm)2 capacitor at 3 ms delay. capacitor, 5 to −5; (C) (100µm)2 non-sintered capacitor, −5 to 5; (D) (500µm)2 capacitor, −5 to 5. the workfunction of the doped wafer with respect to intrinsic silicon. A good theoretical discussion of these relationships minority carrier generation time. In such a case, the charge can be found in [1, p. 29]. continues to accumulate in the depletion region rather than The HP-4061A CV measurement system offered several in the inversion layer. Such a charge configuration leads to adjustable electrical settings, such as the direction of the bias a lower than expected overall capacitance, which is clearly voltage sweep (i.e. −5V to 5V vs. 5V to −5V ) and also the exhibited in Figure 1C in the inversion side of the 5 to −5 stepping rate of the sweep (3 ms vs. 500 ms delay between sweep. steps). These settings were varied to study their effects on the One may expect deep-depletion with the 5 to −5 sweep, resulting CV curves. since it is in this sweep direction that the device transitions The measurement system isolated the wafer under test into the inversion mode. In other words, the transient dynamics associated with inversion layer formation plays an important from room lighting, and offered a feature in which N2 gas was streamed on the wafer. Both of these parameters were role in the resulting CV curves. This hypothesis is consistent investigated for their effects on the CV measurement. with the measured data: the 5 to −5 sweeps consistently yield a lower inversion capacitance, indicating deep-depletion. III. RESULTS AND DISCUSSION B. Bias Voltage Sweep Rate A. Bias Voltage Sweep Direction The effect of the sweep rate was also considered. Figure The effect on the CV curve due to the bias sweep direction 2 shows the resulting CV curves when the delay between is shown in Figure 1. It was generally found that the accumu- each bias step is set to 3 ms and 500 ms. As with the lation portion of the CV curve (right side of graph) is robust previous case, only the portion of the curve corresponding against various parameter changes. However, the inversion to the inversion regime is susceptible to testing parameters. regime (left side of graph) shows dependence on the sweep Hence, these comparisons (in particular, Figure 2D) again direction, with the 5 to −5 sweep consistently yielding a lower suggest deep-depletion. inversion-mode capacitance C . The lower capacitance is a inv As noted earlier, deep-depletion occurs when the capacitor characteristic signature of the “deep-depletion” phenomenon, is subject to conditions that are too rapidly-changing for the explained below. generation of minority carriers needed for inversion-mode The inversion mode of pMOS capacitor operation arises equilibrium. It is then natural to suspect deep-depletion for when, at significantly negative voltage at the aluminum gate, faster bias sweeps. This prediction is confirmed by Figure the MOS capacitor structure accumulates minority carriers 2, which shows the faster sweep to consistently yield a low at the substrate side of the oxide layer (the “inversion”). capacitance. It appears then that a step deplay of 3 ms is too Simultaneously, the depletion region ceases to expand since fast for inversion-mode equilibrium in these devices. the excess charge at the gate is matched at the inversion layer by the minority carriers. However, since minority carriers are generally not abundant in the bulk, the device may not C. Lighting conditions and N2 flow arrive at the theoretical inversion-state equilibrium, when the The HP-4061A system provides a metallic casing which applied bias voltage is varied too rapidly with respect to the shields the device from external light sources. Additionally, 6.152 SPRING 2009 3 nitrogen gas can be flowed over the the wafer throughout the measurement. In the presence of external light, it was found that the inversion capacitance was smaller by an order of magnitude; and the calculated results for ND were on the order of 1016cm−3, which is clearly incorrect. However, there was no appreciable effect of N2 flow over the substrate.