USOO8729739B2

(12) United States Patent (10) Patent No.: US 8,729,739 B2 Lubomirsky et al. (45) Date of Patent: May 20, 2014

(54) B-DIRECTIONAL 257/328,329,334, 266: 307/271.3, 307/300, 43–46,592,404, 55, 77,272.3, 32 (75) Inventors: Vadim Lubomirsky, Bet Shemesh (IL); See application file for complete search history. Damian Urciuoli, Bowie, MD (US) (56) References Cited (73) Assignee: The United States of America as U.S. PATENT DOCUMENTS represented by the Secretary of the 4,571,606 A * 2/1986 Benjamin et al...... 257,339 Navy, Washington, DC (US) 4,611,123 A 9, 1986 McDonald 5,057,791 A * 10/1991 Thompson et al...... 330,277 (*) Notice: Subject to any disclaimer, the term of this 5,066,869 A * 1 1/1991 Neidorff ...... 327,143 patent is extended or adjusted under 35 5,216.352 A 6/1993 Studtmann U.S.C. 154(b) by 469 days. (Continued) OTHER PUBLICATIONS (21) Appl. No.: 13/017,227 Krishnaswami. S., et al., “Gate oxide reliability of 4H-SiC MOS (22) Filed: Jan. 31, 2011 devices.” Intl. Reliability Physics Symp., 2005, pp. 592-593. (Continued) (65) Prior Publication Data Primary Examiner — Fritz M. Fleming US 2011 FO267132A1 Nov. 3, 2011 Assistant Examiner — Jagdeep Dhillon (74) Attorney, Agent, or Firm — Eric B. Compton Related U.S. Application Data (57) ABSTRACT A circuit breaker comprising first and second , each (63) Continuation-in-part of application No. 12/768,898, comprising a gate, drain and Source connection, the JFETs filed on Apr. 28, 2010. Sources being operatively connected to each other to form a common-source connection and adapted to be connected to (51) Int. C. and operating to open an external circuit when the current HO2B I/24 (2006.01) flowing through the JFETs exceeds a predetermined thresh (52) U.S. C. old, the JFETs' gates, and common-source connection being USPC ...... 307/112: 307/77; 307/55; 307/32; operatively connected to a circuit which causes the 330/277; 330/51: 330/107; 330/306: 361/88; JFETs to turn off when the predetermined threshold is 361/58; 361/111: 361/18: 361/54; 327/430; exceeded; whereupon the current flows through the common 327A431 Source connection into the second gate and into the gate driver (58) Field of Classification Search circuit which causes the gate driver circuit to turn off the first CPC ...... H02B 1/24; H01L 27/098: H01L 24/00; and second JFETs and open the circuit breaker. Also claimed H01L 2029/00, H02M 3/28 is a method of sensing an overloaded circuit comprising lead USPC ...... 357/23.4, 23.8, 23.14, 43, 55, 59, 86, ing and trailing JFETs in a circuit that open the circuit and 357/23, 44, 46; 330/277, 51, 107,300, 302, prevent current flow when a predetermined threshold is 330/305,306; 455/78, 84; 361/88, 58,54, exceeded. 361/56, 57,91, 111, 18; 327/430, 431; 20 Claims, 15 Drawing Sheets

JFET FE 2

------US 8,729,739 B2 Page 2

(56) References Cited Veliadis, V. et al., “Exploring the design space of rugged seven lithographic level silicon carbide vertical JFETs for the development U.S. PATENT DOCUMENTS of 1200-V, 50-A devices.” 2007 Int. Device Research Symp., 2007, pp. 1-2. 5,463,252 A 10, 1995 Jones et al. 5,583,384 A 12/1996 Henry Veliadis, V., et al., “A2055-V (at 0.7 mA/cm2), 24-A (at 706 W/cm2) 5,606,482 A 2, 1997 Witmer normally-ON4H-SiC JFET with 0.068-cm2 active area and blocking 5,714,777 A 2f1998 Ismail et al. voltage capability of 94% of the SiC material limit.” IEEE Electron 5,726,848 A 3/1998 Boenig Device Lett., vol. 29, No. 12, pp. 1325-1327, Dec. 2008. 5,742,463 A * 4, 1998 Harris ...... 361/88 Veliadis, V., et al., “A 1680 V (at 1 mA/cm2), 54 A (at 780 W/cm2) 6,034,385 A 3/2000 Stephani et al. normally-ON 4H-SiC JFET with 0.143 cm2 active area.” IEEE Elec 6,178,077 B1 1/2001 Kaluza et al. tron Device Lett, vol. 29, No. 10, pp. 1132-1134 Oct. 2008. 6,876,245 B2 4/2005 de Buda 7,072,162 B2 7/2006 D'Amato Uriciuoli, D.P., “Evaluation of SiC VJFET Devices for Scalable 7,199.491 B2 4/2007 Novinsky et al. Solid-State Circuit Breakers.” ARL-MR-0693, Army Research Labo 7,436,642 B2 10/2008 Grisoni ratory, May 2008. 7,745,273 B2 6, 2010 Treu et al. Veliadis, V., A 9-kV Normally-On Vertical Channel SiC JFET for 7,768,758 B2 8, 2010 Maier et al. Unipolar Operation, IEEE Electron Device Letters, vol. 31, No. 5, 8, 130,023 B2 * 3/2012 Veliadis ...... 327,430 May 2010. 2006, O1981.73 A1 9, 2006 ROZman et al. Stephani. D., et al., “Silicon carbide junction field effect .” 2008/0204958 A1* 8, 2008 Shearon et al...... 361 (93.9 Int. J. of High Speed Electronics and Syst., vol. 16, No. 3, pp. 2009 OO33293 A1 2/2009 Xing et al. 825-854, Sep. 2006. 2010/0277006 A1* 11/2010 Urciuoli...... 307 130 Magnus Willander et al., “Silicon carbide and diamond for high OTHER PUBLICATIONS temperature device applications,” Journal of Materials Science: Urciuoli, D.P. et al., "Bi-directional Scalable Solid-State Circuit Materials in Electronics 17 (2006) 1-25. Breakers for Hybrid-electric Vehicles.” International Journal of High Speed Electronics and Systems, vol. 19, No. 1 (2009) pp. 183-192. * cited by examiner U.S. Patent May 20, 2014 Sheet 1 of 15 US 8,729,739 B2

U.S. Patent May 20, 2014 Sheet 2 of 15 US 8,729,739 B2

{{0|.JOV70|| {{}{} U.S. Patent US 8,729,739 B2

U.S. Patent May 20, 2014 Sheet 4 of 15 US 8,729,739 B2

|uejodlgpueºuse?q 09 |queunoeneº| |?oneuro)|

ty"91: «$2»--~--~------U.S. Patent May 20, 2014 Sheet 5 Of 15 US 8,729,739 B2

U.S. Patent May 20, 2014 Sheet 6 of 15 US 8,729,739 B2

U.S. Patent May 20, 2014 Sheet 7 Of 15 US 8,729,739 B2

uois?apuedoesrioli

U.S. Patent May 20, 2014 Sheet 8 of 15 US 8,729,739 B2

U.S. Patent May 20, 2014 Sheet 9 Of 15 US 8,729,739 B2

U.S. Patent May 20, 2014 Sheet 10 of 15 US 8,729,739 B2

U.S. Patent May 20, 2014 Sheet 11 of 15 US 8,729,739 B2

-i-rl•-1 IIeZLEHTIIq?LEHT U.S. Patent May 20, 2014 Sheet 12 of 15 US 8,729,739 B2

U.S. Patent May 20, 2014 Sheet 13 of 15 US 8,729,739 B2

99 -8 J??uÐAu| U.S. Patent May 20, 2014 Sheet 14 of 15 US 8,729,739 B2

t C .9 U O isS a r

g U.S. Patent US 8,729,739 B2

O CY)

O CY) US 8,729,739 B2 1. 2 B-DIRECTIONAL CIRCUIT BREAKER common-source configuration, and to provide proper gate control to transition the JFETs to the non-conducting (off) CROSS-REFERENCE TO RELATED State. APPLICATIONS A preferred embodiment circuit breaker comprises first and second JFETs; the first JFET comprising a first gate, first This application is a continuation-in-part of and claims drain and first source connection, the second JFET compris priority to U.S. application Ser. No. 12/768,898 entitled ing a second gate, second drain and second source connec “Solid State Circuit Breaker listing as inventor Damian tion; the first and second sources being operatively connected Urciuoli, filed Apr. 28, 2010, hereby incorporated by refer to each other to form a common-source connection, the first 10 CCC. and second drains adapted to be connected to an external circuit having a current flowing therein, the circuit breaker STATEMENT OF GOVERNMENT INTEREST operating to open the external circuit when the current flow ing through the JFETs exceeds a predetermined threshold, the The invention described herein may be manufactured, first and second gates, and common-source connection being used, and licensed by or for the United States Government. 15 operatively connected to a gate driver circuit which causes the JFETs to turn-off when the predetermined threshold is FIELD OF INVENTION exceeded; whereby when a predetermined threshold is exceeded, the current flows through the common-source con This invention relates broadly to circuit breakers and in nection, through the gate driver circuit and into the second particular to circuit breakers comprising integrated circuits. gate which causes the gate driver circuit to turn-off the first and second JFETs and thereby open the circuit breaker. BACKGROUND OF THE INVENTION The preferred embodiment may optionally provide two control lines for external independent or synchronized JFET The present invention is directed to, interalia, bidirectional gate control. These lines can be used for manual control or for current flow applications. In addition to AC systems, many 25 actuation from the output of other sensors or devices. For DC power electronic systems have bidirectional current flow example, optical couplers may be utilized which may be through a single power distribution bus. Commonly, these activated by light emitting responsive to manual systems Supply energy to and from electrical storage ele operation or a sensed condition, such as a predetermined ments. Other AC and DC systems operate between active current level. power sources and/or potential power sources. In these cases, 30 a fault can result in an over-current condition in either direc BRIEF DESCRIPTION OF THE DRAWINGS tion in the system. Some examples of these systems include hybrid electric vehicle drives, grid-tie photovoltaic inverter A more complete appreciation of the invention will be systems, and bidirectional DC-DC converters. Such systems readily obtained by reference to the following Description of cover a wide range of power levels, generally require fault 35 the Preferred Embodiments and the accompanying drawings protection, and benefit further from bidirectional fault pro in which like numerals in different figures represent the same tection. structures or elements. The representations in each of the For distributed and off-grid power systems and hybrid figures are diagrammatic and no attempt is made to indicate electric ground vehicle power systems, power electronic con actual scales or precise ratios. Proportional relationships are Verters and power distribution equipment operating at up to 40 shown as approximates. several hundred volts and up to hundreds of kilowatts are FIG. 1 schematically illustrates a complementary pair of being developed. To prevent damage to converters or other PNP and NPN BJTs connected to provide a similar function system components during fault conditions, fault current to a unijunction (UJT). interrupt speeds in tens to hundreds of microseconds are FIG. 2 schematically illustrates a test circuit designed to necessary. In many of these systems, AC and DC power 45 evaluate device triggering and effective anode-to-cathode components operate between two Voltage busses having inde conduction current of the complementary pair of PNP and pendent Sourcing capability, and require bidirectional fault NPN BJTs connected to provide a similar function to a UJT. isolation. Such conditions can require fault protection sys FIG. 3 is a schematic illustration of series common-source tems having symmetric ratings for bidirectional Voltage connected JFETs with additional parallel sets of common blocking in the off-state and bidirectional current conduction 50 source connected JFETs indicated by dotted outlines. in the on-state. FIG. 4 schematically illustrates an example common In many applications, bidirectional fault isolation is pro Source biasing condition resulting in bipolar gate current vided by mechanical contactors or relays. However, mechani flow. The bias levels shown are representative and should not cal fault protection devices often do not have adequate actua be construed to be the only bias levels for which bipolar gate tion speeds for protection of Solid-state system components. 55 current flows in the bidirectionally conducting common Furthermore, these mechanical devices can Suffer severe deg source JFET structure described herein. radation, dramatically reducing operating life, or resulting in FIG.5 is a schematic illustration of bipolar current actuated catastrophic system failure. JFET gate driver circuit with two auxiliary optically isolated control channels. BRIEF SUMMARY OF THE INVENTION 60 FIG. 6 is a schematic illustration of a BDSSCB Test Circuit used to evaluate bipolar gate current actuated JFET gate A preferred embodiment comprises a gate driver designed driver. to enable an inherent hardware over-current protection fea FIG. 7 is a graphical illustration of turn-offtransition wave ture usable, for example, for high speed scalable bidirectional forms from Synchronized actuation of both gate driver opto solid-state circuit breakers (BDSSCBs). The gate driver oper 65 coupler control channels shown at 10 usec per division cap ates to sense bipolar gate current in reverse conducting junc tured for a 10-A conduction from D1 to D2 (specifically JFET tion field effect transistors (JFETs) connected in a series device number 1 forward conduction prior to turn-off). US 8,729,739 B2 3 4 FIG. 8 is a graphical illustration of turn-off transition wave It will be understood that when an element such as an forms from Synchronized actuation of both gate driver opto object, layer, region or substrate is referred to as being “on” or coupler control channels shown at 10 usec per division cap extending “onto' another element, it can be directly on or tured for 10-A conduction from D2 to D1 (specifically JFET extend directly onto the other element or intervening ele device number 2 forward conduction prior to turn-off). ments may also be present. In contrast, when an element is FIG.9 is a graphical illustration of turn-off transition wave referred to as being “directly on' or extending “directly onto' forms from bipolar gate current actuation shown at 10 usec another element, there are no intervening elements present. It per division captured for conduction from D2 to D1 (specifi will also be understood that when an element is referred to as cally JFET device number 2 forward conduction prior to being “connected' or “coupled to another element, it can be 10 directly connected or coupled to the other element or inter turn-off). vening elements may be present. In contrast, when an element FIG. 10 is a graphical illustration of turn-off transition is referred to as being “directly connected' or “directly waveforms from bipolar gate current actuation shown at 10 coupled to another element, there are no intervening ele usec per division captured for conduction from D1 to D2 ments present. (specifically JFET device number 1 forward conduction prior 15 It will be understood that, although the terms first, second, to turn-off). etc. may be used herein to describe various elements, com FIG. 11 schematically illustrates a preferred embodiment ponents, regions, layers and/or sections, these elements, com BDSSCB design with parallel pairs of common-source con ponents, regions, layers and/or sections should not be limited nected JFETs, and a bidirectional RCD snubber connected by these terms. For example, when referring first and second across opposite JFET drain terminals to mitigate Voltage JFETs in a pair, these terms are only used to distinguish one overshoot from series inductance. JFET from another JFET. Thus, a first JFET, element, com FIG. 12 illustrates a preferred embodiment packaged 30 ponent, region, layer or section discussed below could be ampere Bidirectional Solid-State Circuit Breaker JFET mod termed a second JFET, element, component, region, layer or ule along side of a dime (approx. 17.91 mm (0.705 in)) section without departing from the teachings of the present mathematically revealing a module portion (shown in grey) 25 invention. having both a length and width of approximately 0.95 inches. Furthermore, relative terms, such as “lower” or “bottom’ FIG. 13 illustrates application of the Bidirectional Solid and “upper” or “top” may be used herein to describe one State Circuit Breaker JFET module. element's relationship to other elements as illustrated in the FIG. 14 illustrates application of the Bidirectional Solid Figures. It will be understood that relative terms are intended State Circuit Breaker JFET module used in conjunction with 30 to encompass different orientations of the device in addition connection of a photovoltaic source to a utility. to the orientation depicted in the Figures. For example, if the FIG. 15 illustrates application of the Bidirectional Solid device in the Figures is turned over, elements described as State Circuit Breaker JFET module used in conjunction with being on the “lower side of other elements would then be connection of a battery source to bidirectional DC-DC oriented on “upper sides of the other elements. The exem device. 35 plary term “lower, can therefore, encompass both an orien FIG. 16 illustrates multiple fault detection scenarios using tation of “lower” and “upper.” depending of the particular at least one preferred embodiment of the present invention. orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below' or DETAILED DESCRIPTION OF PREFERRED “beneath other elements would then be oriented “above' the EMBODIMENT 40 other elements. The exemplary terms “below' or “beneath’ can, therefore, encompass both an orientation of above and The embodiments of the invention and the various features below. Furthermore, the term “outer may be used to refer to and advantageous details thereof are explained more fully a Surface and/or layer that is farthest away from a Substrate. with reference to the non-limiting embodiments that are illus Embodiments of the present invention are described herein trated in the accompanying drawings and detailed in the fol 45 with reference to cross-section illustrations that are schematic lowing description. It should be noted that the features illus illustrations of idealized embodiments of the present inven trated in the drawings are not necessarily drawn to scale. tion. As such, variations from the shapes of the illustrations as Descriptions of well-known components and processing a result, for example, of manufacturing techniques and/or techniques are omitted so as to not unnecessarily obscure the tolerances, are to be expected. Thus, embodiments of the embodiments of the invention. The examples used herein are 50 present invention should not be construed as limited to the intended merely to facilitate an understanding of ways in particular shapes of regions illustrated herein but are to which the embodiments of the invention may be practiced and include deviations in shapes that result, for example, from to further enable those skilled in the art to practice the manufacturing. For example, a region or object illustrated as embodiments of the invention. Accordingly, the examples a rectangular will, typically, have tapered, rounded or curved should not be construed as limiting the scope of the embodi 55 features. Thus, the regions illustrated in the figures are sche ments of the invention. matic in nature and their shapes are not intended to illustrate The terminology used herein is for the purpose of describ the precise shape of a region of a device and are not intended ing particular embodiments only and is not intended to limit to limit the scope of the present invention. the full scope of the invention. As used herein, the singular Unless otherwise defined, all terms (including technical forms “a”, “an and “the are intended to include the plural 60 and Scientific terms) used herein have the same meaning as forms as well, unless the context clearly indicates otherwise. commonly understood by one of ordinary skill in the art to It will be further understood that the terms “comprises” and/ which this invention belongs. It will be further understood or “comprising, when used in this specification, specify the that terms, such as those defined in commonly used dictio presence of stated features, integers, steps, operations, ele naries, should be interpreted as having a meaning that is ments, and/or components, but do not preclude the presence 65 consistent with their meaning in the context of the relevant art or addition of one or more other features, integers, steps, and will not be interpreted in an idealized or overly formal operations, elements, components, and/or groups thereof. sense unless expressly so defined herein. US 8,729,739 B2 5 6 It will also be appreciated by those of skill in the art that The BJT implementation can Support more negative references to a structure or feature that is disposed “adjacent BDSSCB drive voltages while offering a greater selection of another feature may have portions that overlap or underlie the components. adjacent feature. JFETs in the Series Common-Source Configuration Because mechanical contactors do not provide adequate The series common-source configuration of JFETs for the actuation speeds in many applications, and Suffer severe deg Bidirectional Solid State Circuit Breaker (BDSSCB) imple radation during repeated fault isolation, a Solid-state circuit mentation necessitates that a JFET or set of parallel JFETs breaker (SSCB) is required. A set of normally-on junction reverse conduct during BDSSCB conduction in either direc gate field effect transistor (JFET) devices fabricated from tion. FIG.3 shows a schematic of JFETs in a common-source 10 configuration with additional parallel sets of common-source wide band gap semiconductor material having a collectively connected JFETs indicated by dotted outlines. For simplicity, low conduction loss to provide large current handling capa a bidirectional solid-state circuit breaker (BDSSCB) struc bility and fast transition speed for current interruption can be ture having only two JFETs connected in a common-source applied. Advanced gate drivers are being developed for Sili configuration is discussed through the following sections. con Carbide (SiC) vertical JFET (VJFET) devices. These 15 However, similar effects are applicable to a plurality of com JFET devices have voltage blocking ratings at or above 1200 mon-source connected JFETs with those entities connected in V and low drain-to-source resistances for scalable bidirec parallel. Reverse conduction occurs when positive current is tional solid-state circuit breaker (BDSSCB) applications. passed through the JFET from source-to-drain. For a reverse In contrast to mechanical devices, bidirectional Solid-state conducting JFET, a negative Vs is established. If a positive circuit breakers (BDSSCBs), even coupled with transient gate-to-source bias is applied to the reverse conducting JFET Voltage Suppression components, can be actuated three orders this voltage will add with the source-to-drain conduction drop of magnitude faster. Although practical BDSSCBs have to increase the gate-to-drain bias (V-Vis-Vs). If the higher conduction Voltage drops than their mechanical coun V, bias exceeds the gate-to-drain junction built-in potential terparts, current Scalable designs can dramatically reduce of approximately 2.7V, a bipolar gate current will form as a on-state losses, and semiconductor packaging techniques can 25 result of forward conduction of the parasitic that exists enable adequate cooling. BDSSCBs facilitate dramatic at that junction. This effect is shown Schematically using improvements in reliability and operating life, resulting in example Voltages in FIG. 4. The bipolar gate current can be Superior system protection and reduced system maintenance continuous, and is fed by a portion of drain-to-source current and repair. that flows through a path formed by the gate driver circuit and As JFET designs have been modified for more normally-on 30 gate-to-drain junction of the reverse conducting JFET. The operation, the magnitude of negative gate biases required to bipolar gate current path is also illustrated in FIG. 4. Bipolar block the rated 1200-V drain voltage have increased. There gate current is generally undesirable for both gate driver and fore, gate drivers operating at more negative drive Voltages device operation. may be needed for more normally-on devices. Additionally, Reducing or eliminating the positive gate-to-source bias gate driver components having ratings Supporting more nega 35 applied to the reverse conducting JFET can increase its tive gate biases will provide more Voltage margin in the Source-to-drain current for which no bipolar gate current BDSSCB gate driver implementation. The 1200-Vrated 0.1- exists. This occurs because a reduction in Visallows a larger cm SiC JFETs, used in a scaled experimental test, were Vs, resulting in a V, less than 2.7V. However, for JFETs biased in the off-state using a gate-to-source Voltage of-33V. designed to have a significant reduction in conduction loss by The bias level was the minimum magnitude for meeting the 40 the application of a positive Vs bias, a reduced Vs bias will full blocking rating of the JFETs, and was selected to provide lead to higher on-state Voltage drops for a given device cur an operating margin for the 40-V maximum blocking rating rent. Instead, JFETs having a more normally-on or very nor of the (UJT). Because UJT device mally-on (VNON) characteristic show less on-state resis applications are limited, very few UJT devices are available tance reduction from positive gate bias, and can be commercially, thereby limiting UJT device parameters. This 45 implemented in this bidirectional solid-state circuit breaker combination of factors has necessitated an alternate Solution (BDSSCB) application. Using a zero-volt gate bias, reverse to replace the discrete UJT device. conducting VNONJFETs can be operated over a wider drain A complementary pair of PNP and NPN BJTs can be current range without the formation of bipolar gate current. connected as shown in FIG. 1 to provide a similar function to The Zero-volt gate bias also reduces the complexity of gate the UJT. PNP and NPN BJTs of a 60-V rated dual comple 50 driver circuitry. However, the negative Vs bias required for mentary pair were evaluated in place of the UJT device, in the voltage blocking up to 1200V may belowerfor VNONJFETs test circuit shown in FIG. 2. The test circuit was designed to than that for other JFETs. evaluate device triggering and effective anode-to-cathode BDSSCB Bipolar Gate Current Actuated Gate Driver conduction current. The BJT configuration triggered at a Bidirectional Solid-State Circuit Breaker (BDSSCB) similar level to that of the UJT and conducted an effective 55 applications have various electrical and thermal operating anode-to-cathode continuous current in excess of 100 mA. conditions. At higher device temperatures, JFET on-state Both results indicate that the complementary BJT configura resistance increases causing a higher conduction Voltage drop tion can be used to replace the UJT device and to provide and higher device power dissipation. Under Such operating higher effective anode-to-cathode voltage blocking. The conditions, JFET current ratings are reduced and bipolar gate maximum effective anode-to-gate blocking Voltage of the 60 current forms at lower reverse conduction currents. Also, any complementary BJT configuration is typically 5 V, compared currents including short duration pulses in excess of the rated to the 40-V rating for that of the UJT. However, because a JFET reverse current can cause undesired bipolar gate cur large resistance is connected in series with the gate of either rent. Because the Vs values that cause bipolar gate current device in the BDSSCB gate driver application, a low voltage can be slightly greater than or equal to the maximum Vs. can be placed across the anode-to-gate connec 65 values of device power dissipation limits, the presence of tions, as shown in FIG. 1, without incurring significant power bipolar gate current can be used to determine if the BDSSCB dissipation in either the Zener diode or the series gate . should be transitioned to the off-state. A gate driver circuit US 8,729,739 B2 7 8 was designed and built to sense bipolar gate current in reverse gate of the UJTs and by the connected in series with conducting VNONJFETs and to provide proper gate control the UJT gates. By gating the forward conducting JFET to the to transition the JFETs to the off-state. The driver circuit off-state before gating the reverse conducting JFET to the maintains (latches) the JFETs in the off-state after bipolar off-state, the reverse conducting JFET is protected from a gate current is detected to avoid a possible oscillatory condi Source-to-drain Voltage in excess of its reverse blocking capa tion or a possible drain current regulation condition caused by bility. operation in the linear region rather than operation in the Two auxiliary optically isolated control channels allow saturation or cutoff regions. The driver also provides two external gate driver actuation. The open collector BJT output isolated input control lines for external independent or Syn ofan optocoupler U1, U2} is connected in parallel with each chronized JFET gate control. These lines can be used for 10 UJT with the BJT collector and emitter connected to the UJT manual control or for actuation from the output of other anode and cathode, respectively. The optocouplers can be sensors or devices. turned-on individually to select the order in which the JFETs FIG. 5 schematically illustrates a preferred embodiment are turned-off, or the optocouplers can be turned-on simulta bipolar gate current actuated driver (BCAD) circuit wherein neously to provide synchronized JFET turn-off transitions. when a bipolar gate current flows into the gate of either JFET 15 External actuation can be achieved by either holding one or (Q1, Q2) while reverse conducting, the bipolar gate current both optocouplers in the on-state, or by momentarily turning will flow into the gate driver circuit through the common on one or both optocouplers. In either the bipolar gate current source connection. The BDSSCB bipolar gate current actu actuated or externally actuated modes of JFET turn-off, the ated gate driver circuit of FIG. 5 includes two optional aux gate driver output maintains (latches) the JFET off-state bias iliary optically isolated control channels. The BDSSCB is until the Voltage of the gate bias Supply is brought to Zero or represented by two JFETs connected in a series common nearly Zero Volts. If still in the on-state, the optocouplers can Source configuration shown in a dotted outline. The negative be turned-off, and the gate bias Supply Voltage can be restored gate voltage bias is provided by a DC power supply with the to resume conduction through the BDSSCB. positive terminal connected to the common-sources of the Scaled Experimental Testing JFETs. A circuit connected to each JFET gate provides actua 25 A gate driver configuration was designed in accordance tion from bipolar gate current and from an external input. In with the principles of the present invention, built, and suc the following discussion, labels in braces { } refer to compo cessfully evaluated to enable an inherent hardware over-cur nents shown in FIG. 5. When a bipolar gate current enters the rent protection feature for high speed scalable bidirectional gate of either JFET {Q1, Q2} while reverse conducting solid-state circuit breakers (BDSSCBs). The gate driver con (source-to-drain current), the bipolar gate current will flow 30 figuration was also evaluated under manual actuation using into the gate driver circuit through the common-source con the input control lines for external synchronized JFET gate nection. A resettable or other device that opens at a set control. The gate driver configuration of FIG.5 was built and current level T1, T2} conducts the bipolar gate current, and tested with two 1200-V rated 0.1-cm VNON SiC VJFETs a resistive Voltage drop forms across that resettable device. connected in the common-source configuration. An isolated When the Voltage reaches the anode-to-gate trigger Voltage or 35 DC-DC converter with adjustable output voltage regulation offset voltage of the unijunction transistor (UJT) {Q3, Q5} was built to provide JFET gate bias voltages of -3.3 V, result connected across the resettable device, the UJT will turn-on ing in JFET drain-to-source blocking voltages of 1200V. FIG. and conduct current from anode-to-cathode sourced by the 6 shows the schematic of the BDSSCB test circuit. An iso gate bias DC power supply. A high speed diode {D1, D3} is lated DC power Supply was used as a source, and a resistive used with its cathode and anode connected to the gate and 40 load of 53.6 ohms was connected in series with the JFETs. A cathode, respectively, of the UJT to prevent a gate-to-cathode bidirectional snubber was connected in parallel with the reverse Voltage in excess of the rated value. A {C1, BDSSCB at the two JFET drain terminals. The Section C2} is connected between the anode and gate of the UJT to labeled DUT (device under test) represents the BDSSCB, prevent undesired triggering of the UJT from circuit tran which incorporates the bidirectional snubber. The setup sients, and a resistor R1, R4} is connected in series with the 45 allowed the connections of the DC power supply to be easily UJT gate to limit gate current. Together, the capacitor {C1, interchanged for bidirectional testing. The gate driver was C2} and resistor R1, R4} act as a low-pass filter. A resistor demonstrated with two 1200-V. 10-A rated 0.1 cm VNON {R2, R5 and Zener diode {D2, D4 connected in series with SiC VJFETs in the BDSSCB test circuit, and performed well the UJT provide a fixed gate voltage for the MOSFET {Q4, in both external and bipolar gate current actuated modes. Q6} that has its drain connected to the gate of the forward 50 Synchronized actuation of both optocoupler control chan conducting JFET (in this example), and its source connected nels of the gate driver was tested first. Each test was begun by to the negative terminal of the JFET gate bias supply. After the increasing the test circuit power Supply Voltage until the UJT begins to conduct, the MOSFET is gated-on, connecting desired JFET drain current was measured. Both optocoupler the negative terminal of the DC power supply to the forward inputs were then driven in parallel by a manually triggered conducting JFET gate. The resettable device in parallel with 55 function generator with a pulse having an amplitude of 5 V the gate-to-source junction of the forward conducting JFET is and a duration of 5 us. BDSSCB currents from 2A to 10A in forced to conduct current until it reaches its non-conducting 1-A increments were tested. In each test, the JFET turn-off state, and the JFET negative gate bias is applied to turn-off the delay (the time between the start of the optocoupler input forward conducting JFET. Before its transition to a non pulse and the start of JFET turn-off) was consistently 2.7 us. conducting state, the current through the resettable device 60 No delay was observed between the JFETs at turn-off. FIG.7 triggered a similar sequence of events on the set of devices shows the waveforms acquired from the 10A test with current controlling the gate potential of the reverse conducting JFET flow from D1 to D2 (referring to those labels in FIG. 6). thereby biasing it to the off-state an interval of time after the Channels 1 through 4 correspond to the following wave turn-off of the JFET that was previously forward conducting. forms: channel 1: Synchronized optocoupler input signal The time interval between forward and reverse conducting 65 active high; channel 2: JFET 1 I, 10 A/div; channel 3: JFET JFET device transitions to the off-state is determined in part 1 V, 500 V/div; channel 4: JFET 2 V, 50 V/div. FIG. 8 by the values of the connected across the anode and shows the waveforms acquired from the 10A test with current US 8,729,739 B2 10 flow from D2 to D1 (referring to those labels in FIG. 6). Physics Symp., 2005, pp. 592-593 and D. Stephani and P. Channels 1 through 4 correspond to the following wave Friedrichs, “Silicon carbide junction field effect transistors, forms: channel 1: Synchronized optocoupler input signal Int. J. of High Speed Electronics and Syst., Vol. 16, no. 3, pp. active high; channel 2: JFET 2 I, 10 A/div; channel 3: JFET 825-854, September, 2006, both of which are hereby incor 1V, 50V/div; channel 4:JFET2V, 500V/div. In all tests porated by reference. Also, the low JFET gate-charge results of this operating mode, the gate driver performed as expected. in fast transition speed and can aid in device current sharing Although individual JFET turn-off transitions occur on the during Switching transitions. nanosecond time scale, the parallel bidirectional snubber Silicon carbide (SiC) 1200-V. 10-A, normally-on, vertical slowed the total BDSSCB transition time to approximately 20 JFETs were developed for a BDSSCB evaluation. Unlike LS. 10 Next, the gate driver was tested forbidirectional actuation other normally-on SiC JFET devices, that are designed for based on the formation of bipolar gate current in the reverse maximum conduction with a positive gate bias, the BDSSCB conducting JFET. From JFET thermal characterization data, JFETs were designed to have a more normally-on character fluid circulated through the JFET baseplate was heated to 80° istic for rated conduction at Zero gate bias, as described fur C. to increase JFET conduction Voltage drops, resulting in 15 ther in V. Veliadis et al., “Exploring the design space of rugged bipolar gate current formation for currents near 10 A. The seven lithographic level silicon carbide vertical JFETs for the Supply current of the test circuit was increased until a development of 1200-V, 50-A devices,” in 2007 Int. Semi BDSSCB turn-off transition was observed at 11.5A. With the conductor Device Research Symp., 2007, pp. 1-2, hereby drain connections of the BDSSCB reversed, the test was incorporated by reference. Additionally, the JFETs exhibit repeated with BDSSCB current in the opposite direction and extremely low leakage currents and sharp onsets of break a BDSSCB turn-off transition was observed at 11 A. The down at both the drain-to-gate and Source-to-gate junctions, small difference in SSCB currents for driver actuation was not resulting instable and efficient operation, as described further unexpected and can be attributed to differences in device in V. Veliadis et al., “A 2055-V (at 0.7 mA/cm2), 24-A (at 706 parameters. FIGS.9 and 10 show waveforms acquired during W/cm2) normally-ON4H SiC JFET with 0.068-cm2 active the bipolar gate current actuated gate driver tests for 25 area and blocking voltage capability of 94% of the SiC mate BDSSCB current in both directions. In FIG. 9, BDSSCB rial limit.” IEEE Electron Device Lett., Vol. 29, no. 12, pp. current flow was initially from D2 to D1 (referring to those 1325-1327, December, 2008 and V. Veliadis, et al., “A 1680 V labels in FIG. 6). Channels 1 through 4 correspond to the (at 1 mA/cm2), 54A (at 780 W/cm2) normally-ON 4H SiC following waveforms: channel 1: no optocoupler input signal; JFET with 0.143 cm2 active area. IEEE Electron Device channel 2: JFET 2 I, 10 A/div; channel 3: JFET 1 V, 50 30 Lett., vol. 29, no. 10, pp. 1132-1134 October, 2008, both of V/div; channel 4: JFET 2 V, 500 V/div. In FIG. 10, which are hereby incorporated by reference. BDSSCB current flow was initially from D1 to D2 (referring A preferred embodiment comprises a scalable bidirec to those labels in FIG. 6). Channels 1 through 4 correspond to tional solid-state circuit breaker (BDSSCB) for fast fault pro the following waveforms: channel 1: no optocoupler input tection, in power electronic systems having bidirectional cur signal; channel 2: JFET 1 I, 10 A/div; channel 3: JFET 1 35 rent flow. The BDSSCBs exhibit near symmetric V, 500V/div; channel 4: JFET2V, 50V/div. For current bidirectional current-conduction and Voltage-blocking capa in either direction, a 2 microsecond delay was observed bility using silicon carbide (SiC) junction field effect transis between the turn-off of the forward conducting JFET (JFET tors (JFETs) and are controlled by an efficient self triggering with current flow into its drain) and the reverse conducting gate driver. In addition to AC systems, DC power electronic JFET (JFET with current flow into its source). This result is 40 systems such as those of hybrid electric vehicle drives stand to based in part on the resistor R1, R4} and capacitor C1, C2} benefit from this technology. BDSSCBs provide important values selected during gate driver fabrication. The perfor advantages over their conventional mechanical counterparts mance results of the hardware implementation confirm the BDSSCBs can provide fault protection with dramatic functionality of the bipolar gate current actuated JFET driver. improvements in reliability and operating life, resulting in In many power Switching applications, normally-off 45 Superior system protection and reduced maintenance and devices are preferred over normally-on devices for their abil actuation that is faster than mechanical fault protection ity to block voltage in the absence of control power. However, devices. Many AC and bidirectional DC systems, especially in many applications, a normally-on fault protection device those having power electronic components, stand to benefit may be preferred. This can be based on the percentage of significantly from these advantages. SiC normally-on JFETs system operating time that the protection device spends in the 50 are well suited to the BDSSCB application due to their: nor on-state, and on the system reliability impact of damage to the mally-on state, ability to bidirectionally conduct with low fault protection sub-system, or its malfunction. With the nor resistance (relative to other structures) mal bidirectional solid-state circuit breaker (BDSSCB) state in both the forward and reverse direction, positive tempera being the on-state, System reliability is increased by not need ture coefficient, and high operating temperature capability. ing to provide an active bias to maintain rated conduction. A 55 SiC 0.1-cm JFETs may be utilized to have a more nor Voltage-controlled, majority-carrier device, having a positive mally-on characteristic specifically for a common-source of on-state resistance, is preferred. BDSSCB design, which allows higher bidirectional conduc These features simplify device control, and promote balanced tion currents at a zero-volt JFET gate bias, and enables bipolar currents among parallel devices, facilitating current-scalable gate current to be used as a means of detecting JFET over bidirectional solid-state circuit breakers (BDSSCBs). Junc 60 current conditions, while inherently compensating for device tion field effect transistors (JFETs) meet these criteria and can temperature. A novel BDSSCB gate driver was designed for provide additional advantages over metal oxide semiconduc bipolar gate current actuated, or externally actuated turn-off. tor field effect transistors (). Without gate oxides, The BCAD driver was evaluated successfully on a small JFETs can operate at higher temperatures than MOSFETs, scale 10-A BDSSCB, with current flow in both directions, and can be more tolerant of high transient Voltages as 65 having two common-source connected 0.1-cm SiC JFETs. described further in S. Krishnaswami, et al., “Gate oxide As depicted in FIGS. 13-16, a preferred embodiment of the reliability of 4H SiC MOS devices.” in Intl. Reliability present invention may be used in: US 8,729,739 B2 11 12 Hybrid electric vehicle systems effect transistors (JFETs) controlled by an efficient self trig Grid-tie renewable energy inverter systems gering gate driver. Bidirectional Solid-state circuit breakers Bidirectional DC-DC converters (BDSSCBs) provide important advantages over their conven Charge and discharge of energy storage systems tional mechanical counterparts. Even coupled with transient Regenerative power (brakes, elevators, etc.) 5 Voltage Suppression components, preferred embodiment FIG. 13 schematically depicts an application of the bidirectional BDSSCBs may achieve actuation times three BDSSCB gate driver circuitry 30 connected between a DC orders of magnitude lower. BDSSCBs may also offer dra bus 31 and a 3-phase inverter 33. matic improvements in reliability and operating life, resulting FIG. 14 illustrates an application of the Bidirectional in Superior system protection and reduced maintenance. Solid-State Circuit Breaker JFET module 30 used in conjunc- 10 As used herein the terminology latch includes the elements tion with connection of a photovoltaic source 35 to a utility disclosed in FIG. 1, such as a UJT, which is normally-off 37. (open) but is turned-on (closed) when activated and remains FIG. 15 illustrates an application of the Bidirectional in the on-state until reset. Solid-State Circuit Breaker JFET module 30 used in conjunc As used herein the terminology includes a transistor tion with the connection of a battery source 38 to a bidirec- 15 such as a MOSFET, but is not limited to a MOSFET and may tional DC-DC converter 39. be a switch element. FIG. 16 illustrates an application of the Bidirectional As used herein the terminology resettable fuse or fuse Solid-State Circuit Breaker JFET module 30 used in conjunc refers to a self triggered or internally triggered device that tion with the connection of a battery source 38 to a bidirec opens when triggered and includes a transient blocking unit, tional DC-DC converter 39. The bidirectional DC-DC con- 20 and the terminology “open' or “activated refers to when the verter 39 is operatively connected to a 3-phase inverter 41 and fuse is blown or when current is blocked. engine 43. The modules 30 afford protection against both As used herein, the terminology MOSFET means metal single point failures (SPF) and two point failures (TPF) in oxide semiconductor field effect transistor. multiple fault detection scenarios. The possible SPF and TPF As used herein, the terminology “predetermined thresh locations of shorts in the circuitry of FIG. 16 include: 25 old’ correlates to an overflow or overload situation (in which (A) Short: DC-DC battery side (SPF, some iso/non-iso the circuit breaker is designed to open) when a bipolar gate DC-DC) current flows through the common-source connection, enters (B) Short: DC-DC bus side (SPF, non-iso DC-DC) the gate driver and passes through the gate/drain junction of (C) Short: DC bus (SPF, non-iso DC-DC) the reverse conducting JFET. (D) Short: inverter bridge (TPF/SPF snubber) 30 As used herein the terminology JFETs is the plural of JFET (E) Short: DC-DC bus side (SPF, non-iso DC-DC)(F) which means junction field effect transistor. Short: DC bus (SPF) As used herein, the terminology BJT correlates to bipolar (G) Over-voltage: P.M. over-speed junction transistor. The Bidirectional Solid-State Circuit Breaker JFET mod As used herein, bipolar gate current, as referred to herein, ule applications for the present invention include, for 35 shall be the current flowing through the gate-to-drainjunction example, distributed and off-grid power systems and hybrid of a reverse conducting JFET with that current flowing into electric ground vehicle power systems, power electronic con the gate connection and flowing out of the drain connection of Verters and power distribution equipment operating at up to the JFET. several hundred volts and up to hundreds of kilowatts. To The foregoing description of the specific embodiments are prevent damage to converters or other system components 40 intended to reveal the general nature of the embodiments during fault conditions, fault current interrupt speeds in tens herein that others can, by applying current knowledge, readily to hundreds of microseconds can be necessary. In many of modify and/or adapt for various applications such specific these systems, AC and DC power components operate embodiments without departing from the generic concept, between two Voltage busses having independent sourcing and, therefore, such adaptations and modifications should and capability, and require bidirectional fault isolation. Such con- 45 are intended to be comprehended within the meaning and ditions can require fault protection systems having symmetric range of equivalents of the disclosed embodiments. It is to be ratings forbidirectional Voltage blocking in the off-state and understood that the phraseology or terminology employed bidirectional current conduction in the on-state. Mechanical herein is for the purpose of description and not of limitation. contactors do not provide adequate actuation speeds in many Therefore, while the embodiments herein have been applications, and Suffer severe degradation during repeated 50 described in terms of preferred embodiments, those skilled in fault isolation. A BDSSCB, as described in the foregoing, the art will recognize that the embodiments herein can be overcomes these deficiencies. A preferred embodiment may practiced with modification within the spirit and scope of the comprise a set of normally-onjunction field effect transistors appended claims. (JFETs) fabricated from wide band gap semiconductor mate The invention claimed is: rial having a collectively low conduction loss to provide large 55 1. A circuit breaker comprising current handling capability and fast transition speed for cur first and second JFETs the first JFET comprising a first rent interruption. Advanced gate drivers are being developed gate, first drain and first source connection, the second for SiC vertical JFET (VJFET) devices. A preferred embodi JFET comprising a second gate, second drain and Sec ment may be used in conjunction with JFETs that have volt ond source connection; the first and second sources age blocking ratings at or above 1200 V, and low drain-to- 60 being operatively connected to each other to form a source resistances for scalable BDSS CB applications. common-source connection, the first and second drains A preferred embodiment comprises a scalable bidirec adapted to be connected to an external circuit having a tional solid-state circuit breaker (BDSSCB) capable of fast current flowing therein, the circuit breaker operating to fault protection, in power electronic systems having bidirec open the external circuit when the current flowing tional current flow. A preferred embodiment exhibits sym- 65 through the JFETs exceeds a predetermined threshold, metric bidirectional current-conduction and Voltage-block the first and second gates, and common-source connec ing capability using novel Silicon Carbide (SiC) junction field tion being operatively connected to a gate driver circuit US 8,729,739 B2 13 14 which causes the JFETs to turn off when the predeter transistor being operatively connected to the gate of the PNP mined threshold is exceeded; transistor at a first junction, and the diode having a diode whereby when a predetermined threshold is exceeded, cur anode and a diode cathode, the diode anode being connected rent flows through the common-source connection, into to the first junction and the diode cathode being connected to the gate driver circuit, and into the second gate which the emitter of the PNP transistor at the anode of each latch, causes the gate driver circuit to turn off the first and and the emitter of the NPN transistor forming the cathode of second JFETs and open the circuit breaker. each latch. 2. The circuit breaker of claim 1 wherein the gate driver 6. The circuit breaker of claim 2 wherein the first and circuit comprises: second Switch elements are each selected from the group a Voltage source comprising positive and negative termi 10 consisting of a MOSFET, another type of transistor, a switch nals; the Voltage source operating to Supply a negative element, or a . Voltage to the first and second gates when the predeter 7. The circuit breaker of claim 2 wherein the voltage source mined threshold is exceeded; the common-source con is one of a battery or Switching converter. nection being operatively connected to the positive ter 8. The circuit breaker of claim 2 wherein the JFETs are minal; 15 normally turned-on with approximately a Zero-volt gate bias first and second resettable fuses, each resettable fuse hav and wherein the gate driver latches its output in the JFET ing first and second fuse terminals, the first fuse termi off-state when the predetermined threshold is met, until the nals being operatively connected to the positive terminal driver output is reset. and second fuse terminals each being connected to the 9. The circuit breaker of claim 2 further comprising first first and second gates; and second optical couplers which bypass the first and second first and second latches operatively connected to the first latches, respectively, the first and second optical couplers and second resettable fuses, the first and second latches being activated by light responsive to manual operation or a being normally in an off mode and operating to activate sensed condition, such as a level of predetermined current when there is a sufficient voltage differential across one passing through the circuit breaker, such that when at least of the first or second resettable fuses; each of the first and 25 one optical coupler is manually activated or activated by a second resettable fuses being operatively connected to sensor, at least one of the first and second Switch elements is one of the first and second latches such that when a latch activated causing the circuit breaker to activate and open the is activated, a fuse is activated; external circuit. first and second Switch elements operatively connected to 10. The circuit breaker of claim 1 wherein the predeter the first and second latches, the first and second gates 30 mined threshold is based upon a maximum Vs value based and the negative terminal, the first switch element allow upon the JFET device power dissipation limit and wherein the ing current when the first latch is activated and the sec predetermined threshold is exceeded, the current flowing ond Switch element allowing current when the second through the common-source connection, into the gate driver latch is activated; the activation of the first switch ele circuit and into the second gate is a bipolar gate current ment operating to connect the negative terminal to the 35 created when the voltage differential between the common first gate to turn off the first JFET; the activation of the Source connection and the second drain exceed the maximum second Switch element operating to operatively connect rated Vs value. the negative terminal to the second gate; 11. A circuit breaker comprising whereby when a predetermined threshold is exceeded, the leading and trailing JFETs; the leading JFET comprising a current flows through the common-source connection 40 first gate, first drain and first Source connection, the into the gate of at least one of the JFETs causing a trailing JFET comprising a second gate, second drain sufficient voltage differential across the second fuse, and second source connection; the first and second causing the first latch to activate which (a) activates the Sources being operatively connected to each other to first Switch element causing the first gate to become form a common-source connection, the first and second negative and turn off the first JFET and (b) opens the first 45 drains adapted to be connected to an external circuit resettable fuse and activates the second latch which acti having a current flowing therein, the circuit breaker Vates the second Switch element thereby causing the operating to open when the current flows through the second gate to become negative and turn off the second JFETs exceeds a predetermined threshold, the first and JFET, and causing the second fuse to open. second gates, and common-source connection being 3. The circuitbreaker of claim 2 wherein the circuit breaker 50 operatively connected to a gate driver circuit which will detect the predetermined threshold and open the external causes the JFETs to turn off when the predetermined circuit for a current flowing through the JFETs from either threshold is exceeded; direction. the gate driver circuit comprising: 4. The circuit breaker of claim 3 wherein the JFET where a Voltage source comprising positive and negative termi the current enters the drain corresponds to the leading JFET 55 nals; the Voltage source operating to Supply a negative and the JFET where the current exits the drain corresponds to Voltage to the first and second gates when the predeter the trailing JFET, and wherein the second gate corresponds to mined threshold is exceeded; the common-source con the gate of the trailing JFET and the first gate corresponds to nection being operatively connected to the positive ter the gate of the leading JFET, and when the current exceeds the minal; predetermined threshold, an overflow current flows through 60 first and second resettable fuses, each resettable fuse hav the common-source connection into the second gate causing ing first and second fuse terminals, the first fuse termi a sufficient Voltage differential across the second fuse, caus nals being operatively connected to the positive terminal ing the first latch to activate. and second fuse terminals each being connected to one 5. The circuit breaker of claim 2 wherein at least one of the of the first and second gates; first and second latches comprises a PNP transistor, an NPN 65 first and second latches operatively connected to the first transistor and a diode, each of the PNP and NPN transistors and second resettable fuses, the first and second latches having an emitter, gate and collector, the collector of the NPN being normally in an off-mode and operating to activate US 8,729,739 B2 15 16 when there is a sufficient voltage differential across one the NPN transistor being operatively connected to the gate of of the first or second resettable fuses; each of the first and the PNP transistor at a first junction, and the diode having a Second resettable fuses being operatively connected to diode anode and a diode cathode, the diode anode being one the first and second latches such that when a latch is connected to the first junction and the diode cathode being activated, a fuse is activated: connected to the emitter of the PNP transistor at the anode of first and second switch elements operatively connected to each latch, and the emitter of the NPN transistor forming the the first and second latches, the first and second gates cathode of each latch. and the negative terminal, the first switch element turn 15. The circuit breaker of claim 11 wherein the first and ing-on when the first latch is activated and the second Second switch elements each comprise a transistor or switch Switch element turning-on when the second latch is acti 10 element including a thyristor. vated; the activation of the first switchelement operating 16. The circuit breaker of claim 11 wherein the voltage to connect the negative terminal to the first gate to turn source is one of a battery or switching converter. off the leading JFET; the activation of the second switch 17. The circuit breaker of claim 11 wherein the JFETs are element operating to operatively connect the negative normally turned on with approximately a zero-voltgate bias. terminal to the second gate; 15 18. The circuit breaker of claim 11 further comprising first whereby when a predetermined threshold is exceeded, the and second optical couplers which bypass the first and second current flows through the common-source connection latches, respectively, the first and second optical couplers into the gate of the trailing JFET causing a sufficient being activated by light responsive to manual operation or a Voltage differential across the second fuse, causing the sensed condition, such as a level of predetermined current first latch to activate which (a) activates the first switch passing through the circuit breaker, such that when at least element causing the first gate to become negative and one optical coupler is manually activated or activated by a turn off the leading JFET and (b) opens the first reset sensor, at least one of the first and second switch elements is table fuse and activates the second latch which activates activated, causing the circuit breaker to activate and open the the second Switch element thereby causing the second external circuit. gate to become negative and turn off the trailing JFET, 25 and causing the second fuse to open. 19. The circuit breaker of claim 11 wherein the voltage 12. The circuit breaker of claim 11 wherein the circuit Source provides a negative voltage to the first and second gates upon activation of the first and second switch elements. breaker will detect the predetermined threshold and open the 20. A method of sensing an overload in a circuit breaker external circuit for a current flowing through the JFETs from comprising: either direction, and when the current is reversed, the leading 30 JFET becomes the trailing JFET and the trailing JFET operatively connecting leading and trailing JFETs in a becomes the leading JFET. circuit to open the circuit and prevent current flow when 13. The circuit breaker of claim 12 wherein the second gate a predetermined threshold is exceeded; the leading and corresponds to the gate of the trailing JFET and the first gate trailing JFETs being connected to each other through a corresponds to the gate of the leading JFET, and when the 35 common source connection; and current exceeds the predetermined threshold, a bipolar gate operatively connecting a gate driver circuit to the common current flows through the common-source connection into the Source connection and the gates of each of the leading Second gate causing a sufficient voltage differential across the and trailing JFETs, such that when a bipolar gate current second fuse, causing the first latch to activate. passes through the common source connection through 14. The circuit breaker of claim 11 wherein at least one of 40 the gate driver circuitry and into the gate of the trailing the first and second latches comprises a PNP transistor, an JFET and out of the drain of the trailing JFET, the gate NPN transistor and a diode, each of the PNP and NPN tran driver circuitry turns off the leading and trailing JFETs. sistors having an emitter, gate and collector, the collector of ck k k k k