IP CORE OVERVIEW

OpenRISC 1200 RISC/DSP Core

· 250 MIPS performance @ 250MHz worst- Introduction case conditions · Predictable execution rate for hard real-time The OpenRISC 1000 architecture is the latest in applications the development of modern open architectures · Fast and deterministic internal interrupt and the base for a family of 32- and 64-bit response RISC/DSP processors. Open architecture allows · Thirty-two, 32-bit general-purpose registers a spectrum of chip and system implementations · DSP MAC 32x32 at a variety of price/performance points for a · Custom user instructions range of applications. Designed with emphasis on performance, simplicity, low power L1 Caches consumption, scalability, and versatility, it · Harvard model with split instruction and targets medium and high performance data cache networking, portable, embedded, and automotive · Instruction/data cache size scalable from applications. 1KB to 64KB · Physically tagged and addressed · Cache management special-purpose registers Features The OpenRISC 1200 RISC/DSP Core consists of · Harvard model with split instruction and several modular units. data MMU

System I/F · Instruction/data TLB size scalable from 16 OpenRISC 1200 to 256 entries PM POWERM IMMU · Direct-mapped hash-based TLB I/F WB · Linear address space with 32-bit virtual I DB ICache address and physical address from 24 to 32 DEBUG I/F 8KB bits · Page size 8KB with per-page attributes DCache TICK TIMER CPU/DSP 8KB WB I Sophisticated Unit INT PIC DMMU · Power reduction from 2x to 100x I/F · Software controlled clock frequency in slow and idle modes High Performance 32-Bit CPU/DSP · Interrupt wake-up in doze and sleep modes · Dynamic for individual units · 32-bit architecture implementing ORBIS32 instruction set Advanced Debug Unit · Scalar, single-issue 5-stage pipeline · Conventional target-debug agent with a delivering sustained throughput debug exception handler · Single-cycle instruction execution on most · Non-intrusive debug/trace for both RISC instructions and system

OpenRISC 1200 · Real-time trace of RISC and system · Access and control of debug unit from RISC or via development interface System Interface · Complex chained watchpoint and breakpoint · System interface optimized for system-on- conditions chip applications · Low-latency, open-standard dual Integrated Tick Timer WISHBONE interface · Task scheduling and precise time measuring · Dual interface – simultaneous flow of · Maximum timer range of 2^32 clock cycles instructions and data · Maskable tick-timer interrupt · Variety of peripheral cores optimized for · Single-run, restartable or continuous mode transparent interconnection with the OpenRISC 1200 Programmable Interrupt Controller · 2 non-maskable interrupt sources · 30 maskable interrupt sources General Description · two interrupt priorities The OpenRISC 1200 Core is ideally Custom and Optional Units suited for applications that require 32-bit · Additional units such as a floating-point unit performance compared to performance of 16-bit can be added as standard units processors and need low cost and low power · 8 custom units can be added and controlled consumption advantage compared to 64-bit through special-purpose registers or processors. customer instructions

Development Tools Support · 250 MIPS Dhrystone 2.1 @ 250MHz wc · GNU ANSI , C++, Java and Fortran · 250 MMAC operations @ 250MHz wc compilers · <1W @ 250MHz, 0.18u, full throttle (est) · GNU debugger, linker, assembler and · <500mW @ 250MHz, 0.18u, half throttle utilities (est) · Architectural simulator · Area <0.5 sqmm @ 0.18u 6LM (cache memories not included) Operating System Support · Target Applications · uClinux · Internet, networking and telecom · OAR RTEMS real-time OS applications · Embedded applications Leading 3rd party products such as Windows CE · Portable and wireless applications and VxWorks are planned to be available. · Home entertainment consumer electronics · Automotive applications Specifications · 250 MHz in worst-case 0.18u 6LM

Utilization

The table in this section lists the intended applications of the different cores.

Core FPGA Size Silicon Area Speed Power Consumption

Authors reserve the right to make changes in specifications at any time and without notice. The information in this publication is believed to be accurate and reliable. No responsibility, however, is assumed by the Authors for its use, nor for any infringements of patents or other rights of third parties resulting from its use.

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OpenRISC 1200