Douglas Wong America Electronic Components

Jan. 7th 2011, CES Las Vegas Flash Forward:Forward @ Flash CES Memory2011 Storage Solutions Agenda

• A Short History on • What is NAND Flash Memory? • The Need for Speed

Flash Forward @ CES 2011 Flash Memory Timeline ’84 ’85 ’86 ’87 ------’91 ’92 ’93 --- 2000s

JitVJoint Vent ure SANDISK-type Development (SanDisk)

NAND-type NANDNAND--typetype (Toshiba) (Toshiba, FileFile-- Samsung) Storage

FLASH ACEE-type X MEMORY (TI) AND-type ThibToshiba AND-type (Hitachi) (Hitachi)

NOR-type NORNOR--typetype (Excel / (,AMD) Il)Intel) CodeCode-- Split-gate-type X Storage (SEEQ) SST-type SST-type (SST) (SST, Sanyo)

DiNOR-type DiNOR-type (Mitsubishi) (Mitsubishi)

Flash Forward @ CES 2011 Flash Memory Primer

• All Flash requires Erase before Programming –Erase

–Program

Flash Forward @ CES 2011 NAND AGAG--ANDAND NROM NOR

Bit line(metal)

Contact

Source line Word line(poly) (Diff. Layer) Word line(poly) Word line(poly) Word line(poly) Cell Circuit Unit Cell Unit Cell Unit Cell Unit Cell

Source line Bit / Source line Source line (Diff. Layer) (Diff. Layer) (Diff. Layer) 2F 2F 3F 2F Layout 2F 2F 2F 5F Cross- section

Cell Size 4F2 6F2 4F2 10F2

Simple structure High productivity Minimum cell size High reliability Scalability advantage

Flash Forward @ CES 2011 17 Years of NAND Flash Memory Progress 16M LOCOS 0.7~0.4um SASA--STISTI 0.25um～0.13um New Structures 90nm～

32M WSi 1 64M Control Gate ONO Control Gate

Tunnel Floating Floating Gate Control GateFloating Gate Gate ONO WSi Oxide STI Tunnel Oxide Tunnel Oxide LOCOS 256M Floating GateControl Gate 512M STI )

2 Floating GateControl Gate 0.1 MLC um

(( 1G LOCOS 1G Floating Gate 2G 2G Control Gate STI Cell Size 4G 4G 8G 8G 0.01 16G STI 16G Multi Level Cell 32G

Fine Lithography 250250nmnm 160160nmnm 130130nmnm 9090nmnm 7070nmnm 5555nmnm 43nm

0.001 Flash Forward @ CES 2011 NAND Flash Memory • NAND Flash was intended for file storage applications • NAND Flash is page-based for Read & Program operations

– The internal data register holds one page of date

– A “page” is the unit of transfer between the data register and the memory array. All program and read operations transfer a page of data between the data register and a page in the memory array.

Flash Forward @ CES 2011 Growing Need for Higher NAND I/F Speed • Performance demand with the growth of storage interface •With continuing innovations in the NAND architecture and enhanced I/O speed, increased performance can be achieved.

Flash Forward @ CES 2011 Advantages of Larger Page Size Read & Program Performance increased by long page size since tR and tPROG does not depend on page size. Faster I/O needed to fill/empty page buffer.

Page size: 2kB Serial Data in Serial Data out Page Buffer tR: Random Access Time

tPROG: tPROG: Program Time tR: NAND Page tRC/tWC:Read Cycle/Write Cycle Time

Page size: 8kB

Serial Data in Page Buffer Serial Data out

tPROG: tR: NAND Page

Flash Forward @ CES 2011 9 NAND Flash Page Read Operation

CE

ALE Register Data-Out tR CLE

WE Page Address

RE Command Command I/O1~8 00h 30h D0 D2111

Wait(tR) R/B Column Page Addr. Addr.

Flash Forward @ CES 2011 Calculated Legacy NAND Page Read Time*

300

250

200

150 tR tRC*Page Size

100

50

0 2 kB 4 kB 8 kB *SLC NAND, legacy NAND interface. Time represents calculated theoretical read time based on typical specifications for legacy NAND and Toggle Mode cycle times. Actual read time may vary depending on host performance and other factors.

Flash Forward @ CES 2011 Calculated DDR (Toggle) NAND I/F Page Read Time*

300

250

200

150 tR tRC*Page Size

100

50

0 2 kB 4 kB 8 kB *SLC NAND, 133 MT/s, toggle mode NAND interface. Time represents calculated theoretical read time based on typical specifications for legacy NAND and Toggle Mode cycle times. Actual read time may vary depending on host performance and other factors.

Flash Forward @ CES 2011 NAND Interface Evolution •As ppqerformance requirements increase ,gy(, the legacy NAND interface(SDR– single data rate) becomes bottleneck, esp. for read performance. • JEDEC NAND Flash I/F specification is scheduled to be ratified in early 2011 Legacy SDR Toggle-mode DDR Synchronous DDR (50Mbps)(~50 Mbps)

WE# CK WE# RE# W/R# Pinout RE# DQ DQ DQ DQS DQS

WE# WE# CK W/R# Writes DQS DQS Din Din Din

CK RE# W/R# Reads RE# DQS DQS DtDout Dout Dout

Supported interface is identified by Read ID

Flash Forward @ CES 2011 High-Speed NAND Flash Interface

• New features to enable up to 400 Mbps – Complementary DQS and RE signals – Vref (SSTL) – On Die Termination –DQS ldlatency adjustment

Note: Features are under discussion and subject to change without notice.

Flash Forward @ CES 2011 High-Speed NAND Flash Interface

DDR High- Legacy Speed Type Description SDR (Toggle/ Sync) DDR 15 16 20 ALE ALE ALE I Address Latch Enable Toggle CE# CE# Toggle DDR 400 DDR CLE CLE NAND CLE CLE CLE I Command Latch Enable NAND ALE ALE /CE /CE /CE I Chip Enable RE# RE# WE# WE# /RE /RE or W/R# /RE I Read Enable or W/R# WP# WP# DQS# /WE /WE or CK /WE I Write Enable or CK R/B# R/B# RE DQS DQS Vref /WP /WP /WP I Write Protect DQ[0:7] DQ[0:7] Vpp R/B R/B R/B O Ready/Busy DQ DQ DQ I/O Data Input/Output DQS DQS I/O Data Strobe /DQS I/O Data Strobe Complement RE I Read Enable Complement Vpp I External High Voltage Vref I Voltage Reference

Flash Forward @ CES 2011 Backward Compatibility

• High-Speed NAND Flash supports backward compatibility • New signals and functions are user-selective • Set feature command is used for changing interface

• ONFi-JEDEC Joint Task Grouppgpgy collaborating to provide a single, industry standard, high-speed NAND interface with backward compatibility.

• For an early and close look at the spec or contributions to the standard, please join JEDEC.

Flash Forward @ CES 2011