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Download Technical Paper TECHNICAL INFORMATION IMPROVED NOISE SUPPRESSION VIA MULTILAYER CERAMIC CAPACITORS (MLCs) IN POWER-ENTRY DECOUPLING Arch G. Martin AVX Corporation Myrtle Beach, S.C. R. Kenneth Keenan TKC Pinellas Park, FL Abstract: A new decoupling technique is proposed for surface mounted designs that recommends using 0.1 µF MLCs as the circuit-level decoupling capacitors and 1.0 µF to 10 µF MLCs in place of the tantalum as the board-level power-entry capacitor. This combination of MLCs on each PCB coupled with a single system level tantalum or aluminum is probably an optimum arrangement; performance is enhanced, and cost is not increased. IMPROVED NOISE SUPPRESSION VIA MULTILAYER CERAMIC CAPACITORS (MLCs) IN POWER-ENTRY DECOUPLING Arch G. Martin and R. Kenneth Keenan Introduction In a typical power distribution system (Figure ESL C ESR 1-a), the power-entry capacitor Cb , is a relatively large-valued capacitor near the power-entry point on the PCB. The purposes of power-supply decoupling ______1 shown in Figure 1-b are to: XC = • Prevent transmission of PCB-generated noise to 2pfCC the backplane/motherboard and power supply. ZC = Î (ESR)2 + (XC - XESL)2 • Supply charge to the power entry capacitor so XESL = 2pfESLC that the voltage at the PCB power entry point is maintained at Vcc (usually 5 VDC). Figure 2. Total capacitor impedance • Suppress power supply backplane ringing result- ing from inductance of power supply (Lw) and backplane (Lm). These factors, coupled with higher speeds, greater In the past, these board level decoupling applica- density, the need for improved emissions perfor- tions or power-entry capacitors have been dominated mance, increased reliability, and the trend toward dis- by aluminum electrolytic and tantalum capacitors, tributed power supplies, have all served to focus upon but the push into surface mount configurations pre- the need for better and more efficient decoupling sents major problems in the use of these electrolytic techniques, including capacitive decoupling at the capacitors. Exposure of aluminum to Floroinert power entry point, Cb. vapors used in vapor phase soldering (VPS) is detri- Recent advances in ceramic technology have mental to aluminum. In addition, aluminum elec- increased MLC volumetric and cost efficiencies such trolyte boils at VPS temperatures and also at IR that high value, small physical size capacitors are (infrared) reflow temperatures (207-215 degrees C). now practical and able to compete with electrolytics. Solid tantalum capacitors on the other hand have rad- MLCs are compatible with surface mount processing ically different coefficients of expansion between the and do not have the limitations of electrolytic capaci- tantalum slug, lead frame and epoxy resin body. This, tors. In addition, they are non-polar, which elimi- coupled with the non-metallurgical bond of the cath- nates a major source of surface mount assembly ode electrode, limits tantalum capacitor soldering defects stemming from polarity of electrolytics dur- temperatures to well below the normal temperatures ing assembly. used in surface mount assembly. Both aluminum and Power-entry filtering performance of MLCs is tantalum electrolytic capacitors must receive special far superior to that of electrolytic capacitors, as handling at lower temperatures than the rest of the MLCs are characterized by much lower values of surface mount assembly for optimum electrolytic ESL and ESR. These characteristics, plus newer capacitor reliability. high capacitance values, make MLCs ideal power- entry capacitors. FIVE ADDITIONAL CHAINS Lm DECOUPLING CAPACITOR Lw PCB PCB Lb Ld ESLd POWER FEED jj Cb Cd TRACES FERRITE BEAD POWER SUPPLY BACKPLANE/ POWER ENTRY DECOUPLING CHAIN OF K DIPS POWER ENTRY CAPACITOR C MOTHERBOARD CAPACITOR, Cb CAPACITOR, Cd b 1b. Printed circuit board (PCB) 1a. Power supply to printed circuit board (PCB) Figure 1: Power distribution system for typical digital equipment Additionally, some of the power-entry capacitance Care is taken not to use an overly-large power- is shifted to a single system tantalum (see systems entry capacitor, which is likely to exhibit excessive considerations below for suppression of backplane ESL and result in undesirable emissions. ringing). For the example in Figure 1b with six six-DIP This new approach requires revision of conven- chains: tional decoupling thinking, but results in significant Cb $ 10 x 36 x 0.01 µF = 3.6 µF, improvement in design, emissions, and reliability. (Next highest standard value = 4.7 µF) Conventional Approach A ferrite bead is used at the power entry point to The conventional approach to PCB-level decou- prevent low-frequency ringing and to minimize trou- pling is to choose one decoupling capacitor per semi- blesome high-frequency clock-harmonic voltage at conductor package and one power-entry capacitor per the power entry point. The relatively high-speed gate PCB. Except on extremely large PCBs, capacitors at currents required during a clock transition are large- points intermediate to the power entry and decou- ly supplied by the decoupling capacitors, Cd, located pling capacitors are not required or recommended close to the gates to which the current is supplied. (References 1 and 2). One aim of the conventional approach has been to minimize the value of the circuit level (Cd) decoupling capacitors. A lower bound on decoupling capacitance is set by charge drawdown (droop) considerations LC CC RC (Reference 1): ______1 XC = 21fCC Cd $ 9 x Sum of switched capacitance, 2 2 ZC = Î RC + (XC - XL) where the switched capacitance is the sum of the out- XL = 21fLC put gate plus load capacitance associated with the semiconductor package. Typically, only half the out- put gates in a given semiconductor package (NAND, NOR, etc.) are being switched at a clock pulse transi- Figure 2: Total capacitor impedance tion; then, the switched capacitance is only one-half that of the total gate plus load capacitance. For the layout of Figure 1b with 5 output gates per DIP Ideally, the equivalent series inductances (ESLs) being switched and with each output gate fanned out and resistance (ESRs) of both the power entry and to two input gates, the assumption of LSTTL technol- decoupling capacitors (Figure 2) would be zero, as the ogy (Cout = 20 pf, cin = 5 pf) leads to: impedances of those capacitors would be minimum. This provides maximum reduction in the transfer of Cd $ 9 x 5 x (20 + (2 x 5)) = 1,350 pf = 0.00135 µF, switched-gate noise back to the power-entry point. (Next highest standard value = .01 µF) Excess ESL, together with excess trace inductance and/or trying to load a single decoupler with too The value of the power entry capacitor is chosen many semi-conductor packages, causes high-fre- large enough to handle the relatively low-frequency quency ringing. Those clock-harmonic currents which task of recharging the decoupling capacitors between are nearest the ringing frequency are transmitted to each transition of the clock pulse: the power bus with little attenuation, causing emis- sions problems. Cb $ 10 x Sum of decoupling capacitors (Cd) on PCB. New Decoupling Techniques EFFECTIVE INDUCTANCE (CAPACITOR RESPONSE TO PULSE EDGE OF 200ma/10ns) The conventional approach has been to chose the 10 decoupling capacitor as the lowest standard value in order to minimize both ESL, ESR, and cost. 8 Improvements in multilayer ceramic capacitor (MLC) technology over the past few years has greatly 6 1.2mF changed designers’ dependency upon these factors. 0.5mF With improved MCL technology has also come .07mF 0.24mF 4 0.71mF reduced cost for higher values (Figure 3). Today, .01mF 0.37mF MLCs are less dependent upon high-cost metals due to less expensive electrodes materials. 2 EFF. INDUCTANCE, nh (L = Vxdt/di) 0 0.05 0.20 0.35 0.50 0.65 0.80 0.95 1.10 1.25 EFF. CAPACITANCE, mF (C = Ixdt/dv) PRICE VS. CAPACITANCE Figure 4: Effective inductance (ESL) of AVX MLC RELATIVE (Volume price for 106 pieces.) COST dipped radials (Lead length > 0.1000) 1.5 replenishment purposes, the decoupling capacitors are in series with the power-entry capacitor (no 0.33mF reliance on the power supply between clock pulses). 1.0 In terms of the preceding example: If we decrease 0.1mF the size of the 4.7 µF power entry capacitor to 1.0 µF .01mF (MLC), how much would the values of the decouplers 0.5 have to be increased in order to maintain an effective total decoupling capacitance of 0.01 µF/DIP x 36 DIPs = 0.36 µF? 0 0.1 0.2 0.3 (Total Cd)(1.0) = 0.36, Total Cd =0.563 µF CAPACITANCE VALUE, mF 1.0 + (Total Cd) If decouplers had been chosen at the 0.00135 µF Figure 3: Cost of MLCs (volume purchased = lower limit, they would have to be increased to 1,000,000 pieces) 0.563/36 = 0.0156 µF. In practice, a decoupling value of 0.1 µF can and is generally used anyway. The smaller size of today’s MLCs has greatly This design approach allows the power entry reduced inductance variation with increasing capaci- capacitor value to be reduced to take advantage of tance value. The effective inductance can be mea- the lower ESL and ESR of MLC capacitors. This sured via MLC response to pulse-edge rate of 200 will result in maximum reduction of transmitted ma/10 ns. Figure 4 shows that there is less than 1 nH switched-gate noise back to the power-entry point difference between a 0.068 µF and a 1.0 µF. This low and the back panel of the total system. As shown in inductance for higher values allows the capacitance Figure 5, this reduction is, relative to that provided value to be chosen by the current requirements, not by the conventional approach (4.7 µF power-entry the capacitor’s inductance.
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