Time-Code Reception Time-Code Reception

Home , Atomic clock, Leap second, Time signal

Table of Contents

General Information ...... 5 Introduction ...... 5 Time-Code Transmitters ...... 5 Time-Code Signals and their Reception...... 6 Time-Code Receivers ...... 7 TEMIC Devices for Time-Code Reception...... 8 U4223B ...... 8 U4226B ...... 10 T4225B ...... 10  INCOR - the TEMIC Software...... 11 Microcontrollers ...... 11 M43C505 ...... 11 M44C588 ...... 11 Design of a Time-Code Receiver with U422xB...... 14 U4223B Circuit Technology...... 14 Board Layout ...... 16 Antenna Circuit ...... 16 Application ...... 16 Decoding Algorithm ...... 17 The Use of the TCO Signal ...... 18 Layout Example ...... 19 Data Sheets ...... 21 U4223B: Time-Code Receiver with A/D Converter...... 21 U4224B: Time-Code Receiver with Digitized Serial Output...... 39 U4226B: Time-Code Receiver with TC Output...... 55 T4225B: Low-Cost Time-Code Receiver...... 71 M43C505 Low-Current 3- and 5-V Solution for Consumer Applications...... 87 M44C588 Versatile High-End Controller for General Purposes...... 89

TELEFUNKEN Semiconductors 3 07.97 General Information Introduction Time-Code Transmitters From time to time, time deviations or power fails occur For precise time synchronization, there are four trans- to clocks and watches which must be corrected. For cor- mitters worldwide. One transmitter is located in the USA, rect time setting, an atomic clock can be used as a its reception area is more or less the entire area of North reference clock. Several transmission stations situated America. Another transmitter, located near London, worldwide send coded signals based on the atomic refer- covers UK, and a transmitter in Germany is delivering the ence clock with information on the precise time via long time information for Europe. Additionally, there is one waves. To receive and decode these signals, a special transmitter in Japan. receiver is necessary. Amplitude-modulated time-code transmitters deliver the The most convenient and exact method of time data to decode the present time (based on an atomic time synchronization for the customer is the receiver being in- normal), the day, the month and the year. They provide tegrated into the watch, automatically monitoring the also information about summer- and winter time if rele- time. An essential requirement for such a time-code vant. The information is transmitted via a long-wave receiver is a small design and low current consumption at transmitter in the frequency range of 40 to 80 kHz. This minimum voltage supply. frequency range is the best solution to construct receivers with low power consumption and high sensitivity. TEMIC was one of the industry’s first suppliers of time- code receivers and manufactured as soon as 1986 receiver circuits for general time-code applications in high- volume production.

Time-code transmitter Present time Day Atomic-based time Month Year Daylight saving hour

Long-wave transmitter

Figure 1. Time-code transmission

Table 1. The most important time-code transmitters worldwide

Type Location Frequency Power Modulation

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁDCF77 Mainflingen/ 77.5 kHz 50 kW Carrier reduced by 12 dB for 100 or 200 ms

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á

Á Frankf. a.M. (FRG)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁJG2AS Sanwa (J) 40 kHz 10 kW Carrier switched off for 200, 500 or 800 ms

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁMSF Teddington (GB) 60 kHz 50 kW Carrier switched off for 10, 200 or 300 ms

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁWWVB Fort Collins (USA) 60 kHz 50 kW Carrier reduced by 10 dB for 200, 500 or

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á

Á (unconfirmed) 800 ms

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TELEFUNKEN Semiconductors 5 07.97 Time-Code Signals and their of a deletion takes seconds or a fraction of a second, in long waves, this can take several minutes up to half an Reception hour. Time-code transmitters on long waves are best suited for A well-constructed radio-controlled clock with a ferrite clocks with radio-controlled synchronization because antenna has high sensitivity and can pick up signals of they have good propagation characteristics and their up to some 30 dBmV/m. By using the U4223B with ADU, receivers can be dimensioned with low power consump- values of about 20 dBmV/m can be achieved. Even wrist tion. The four most important transmitters worldwide watches with their complex antenna construction (with regard to commercial clocks) are summarized in can be designed so to operate at up to approximately table 1. 40 dBmV/m. In low-cost products only 50 dBmV/m were measured. Therefore, radio-controlled clocks which Figure 2 shows the propagation distances of DCF77, receive the DCF77 signal can operate without any figure 3 the information distributed by the transmitter. problems in Germany up to a distance of 600 km from the The field strength measured in the reception area consists transmitter’s location (Mainflingen/ Frankfurt am Main). of two components: the ground wave and the space wave Within this area, the field strength is more than 1 mV/m which arises from reflections in the ionosphere. The most which is sufficient enough to guarantee good reception. predominant reception possibility exists up to a distance At a distance of more than 600 km and less than 2000 km of 2000 km from the transmitter. from the transmitter (see figure 4), radio-controlled From figure 2, it can be seen that the ground wave is still clocks can only operate with several restrictions because dominant up to a distance of almost 600 km from the ground waves and space waves become entangled. This transmitter and the field strength is at least 60 dBmV/m may cause interferences and therefore deletion of the (1 mV/m). Ground waves and space waves become signal. Radio-controlled reception is nevertheless pos- entangled at distances between 600 and 2000 km. Recep- sible in this area by using highly efficient antennas and tion is then less stable due to interferences. In long receivers as well as intelligent decoding software. Best distances, longest stable field strengths can be expected reception time is the night time as a lot of interference at night time. While in short waves, the transmission time sources are then switched off.

110

100

90 Ground wave

m 70 Night 60

50 Winter day Space waves Field strentgh ( dB V ) V Field strentgh ( dB 40

30 Summer day 20

0 100 1000 10000

13323 Distance ( km )

Figure 2. Propagation distances of the time-code transmitter DCF77

6 TELEFUNKEN Semiconductors 07.97 Time frame 1 minute Time frame ( index count 1 second ) 0 5 10 15 20 25 30 3540 45 50 55 0 5 10

Coding Minutes Hours Calendar Day Month Year when day of required the week Example: 19.35 h s 1 24810 20 40 P1 1 2 4 81020P2

Sec. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Minutes Hours Start bit Parity bit P1 Parity bit P2

93 7527 e

Figure 3. The German transmitter DCF77: a typical time-code example

2000 km

600 km

Figure 4. The propagation area of the time-code transmitter DCF77

Time-Code Receivers The first approach is a straight-through receiver which obtains the signal from a ferrite antenna (tuned to the desired frequency) and amplifies it. The selectivity is Radio-controlled clocks receive time-code signals from achieved by using one or two crystal filters. The AM regional time-code transmitters around the world in the modulation is toggling the decoder stage. At the output of VLF area. The signal is received and decoded by the the decoder stage (TCO), a rectangular signal, following radio-controlled system. the amplitude modulation, is present. The second solution is using the U4223B which delivers TEMIC offers two different solutions to receive time- a 4-bit digitized signal to the microcontroller. By means  code transmissions. Both solutions have the same of TEMIC’s software INCOR , an improved overall sensi- receiving concept. tivity of more than 6 dB can be achieved.

TELEFUNKEN Semiconductors 7 07.97 TEMIC Devices for Time-Code Reception

U4223B summer- to winter time is also carried out in each individual country if the information from the transmitter TEMIC launched a new era in precise and user-friendly is available. radio-controlled clocks when the first TEMIC ICs for The U4223B family offers high sensitivity and low power radio-controlled consumer clocks were introduced in consumption. The circuit can be used for universal appli- 1986 and has remained a leader in this field since then. cations due to its supply voltage of 1.2 V to 5.25 V. With µ µ The U4223B family was developed to achieve constant its typical power consumption of 13 A to 20 A, it is high sensitivity rates with low voltage and power con- particularly suitable for long-life battery applications. sumption. Therefore, radio-controlled clocks as well as Features all other clocks and wrist watches can be used with D standard batteries and have very long operating times. Very low power consumption D m Radio-controlled clocks consist of an antenna, a receiver Very high sensitivity (1 V typical) circuit, a microcontroller as well as various display and D Choice of selectivity by use of one or two input elements. The U4223B is a very efficient receiver crystal filters circuit which can be universally applied for receiving the D time-code signals in the VLF area. Furthermore, the Power-down mode available TEMIC MARC4 microcontroller family can be used in D Few external components necessary applications with the U4223B and U4226B for radio- D controlled systems. 4-bit parallel output D AGC hold mode for bridging over known inter- The radio-controlled clock is constantly set precisely. ferences (e.g., stepper motor) Therefore, the internal crystal clock is then set precisely to the second by the received signal. Switching from D SSO20 package

Time-code receiver

U4223B U4224B U4226B T4225B

Figure 5. Time-code reception

8 TELEFUNKEN Semiconductors 07.97 PON CLK D3 D2 D1 D0 93 7726 e 12 17 18 19 20 16 11 VCC 1 FLB Power supply ADC Decoder 10 GND FLA 3 9 DEC Impulse circuit AGC Rectifier & 13 SL 2 amplifier IN integrator 4561415 78 SB Q1A Q1B Q2A Q2B REC INT

Figure 6. U4223B block diagram

Control lines +VCC

D0 Ferrite 1 20 Antenna 10 nF D1 2 19 f = 77.5 kHz 10 nF res D2 3 18 10 nF D3 4 17 10 nF PON 3) 5 16 77.5 kHz 2) U4223B 77.5 kHz Microcomputer 6 15

7 14 C 4) Keyboard 1 1) CLK 6.8 nF SL 8 13 Display C2 33 nF 9 12 1) If SL is not used, SL is connected to VCC 2) 10 11 77.5-kHz crystal can be replaced by 10 pF C3 3) If IC is activated, PON is connected to GND 10 nF 4) 94 8968 Voltage swing 100 mVpp at Pin 12

Figure 7. Application circuit U4223B for 77.5 kHz

TELEFUNKEN Semiconductors 9 07.97 U4226B D Digitized serial output signal D SSO20 package D AGC hold mode for bridging over known interferences (e.g., stepper motor) D Selectivity choice by use of one or two crystal filters D Extremely low power consumption T4225B D Very high sensitivity D Same specifications as U4226B but only available as D Power-down mode die (wafer form, die-on-foil and die-in-trays)

PON TCO 93 7727 e 15 16 GND 3 11 FLB Power Supply Decoder VCC 1 10 FLA

9 DEC

AGC Rectifier & 12 SL Amplifier Integrator IN 2 4561314 7 8 SB Q1A Q1B Q2A Q2B REC INT

Figure 8. U4226B block diagram

+ VCC Control lines

Ferrite Antenna 1 20 NC fres = 77.5 kHz

2 19 NC TCO

NC PON 3) 3 18 Microcomputer SL 1) 4 17 NC Keyboard

5 16 77.5 kHz 2) U4226B Display 6 15

C1 7 14 6.8 nF C 8 13 2 77.5 kHz 33 nF 9 12

C3 10 11 1) If SL is not used, SL is connected to VCC 10 nF 2) 77.5 kHz crystal can be replaced by 10 pF 95 10469 3) If IC is activated, PON is connected to GND

Figure 9. Application circuit U4226B for 77.5 kHz

10 TELEFUNKEN Semiconductors 07.97  D INCOR - the TEMIC Software 32-kHz crystal oscillator D Low-power consumption (2.5 mA sleep)  INCOR is a special software program for microcontroller- D based time signal decoders. In combination with a special Voltage range of 2.4 V to 5.5 V ADC hardware interface on the U4223B chip, it is This microcontroller can be programmed in a high-level possible to improve the time-code readability at weak language (qFORTH) with an optimizing compiler. A  input signals of more than 6 dB. INCOR is written in C power-saving and a sleep mode is a standard in the  language and fits into the M44C588. INCOR can only be MARC4 family. The M43C505 has also a separate watch used together with the U4223B. It reduces time-code crystal oscillator for the time-keeping function. The reception problems in areas with difficult receiving built-in LCD voltage generation with temperature com- conditions * especially in areas with very weak field pensation completes the features for this solution. strength conditions or noisy environments (e.g., USA, Japan, Spain, Italy, Scandinavia). M44C588 Microcontrollers 4-Bit, High-End, Low-Power Microcontroller D CPU with programmable system clock TEMIC offers a complete family of cost-effective, single- chip CMOS microcontrollers, based on a 4-bit CPU core D 9-KByte ROM designed for the voltage range of 1.8 up to 6.2 V appli- D 256 4 bit internal and 256 4 bit external RAM cations. The modular MARC4 architecture is HARVARD-like, high-level language oriented and best D 20 fixed I/ O lines + 16 optional designed for analog, digital watch and clock applications D Liquid crystal display driver with up to with time-code receiver functions. The MARC4 control- 32 4 segment outputs ler’s low-voltage and low-power consumption suits the requirements of watches and clocks. D 2 to 3 watch-motor drivers M43C505 D 2 buzzer output drivers D 32-kHz crystal oscillator 4-Bit, Low-End, Low-Power Microcontroller D Low-power consumption (3 mA sleep) D CPU with 2-MHz RC clock generator D Large voltage range from 1.8 V to 6.2 V D 4-KByte ROM The M44C588 as any member of the MARC4 family can D 256 4-bit RAM be programmed in a high-level language (qFORTH) with an optimizing compiler. It has a compact, RISC-like D 12 I/ O lines + 4 inputs instruction set with a ROM look-up table. A unique D AUTOSLEEP function is available. The MARC4 has a Liquid-crystal display driver with 20 4 segment drives built-in self-check routine in a separate 1 k 8-bit ROM area. An economical, PC-based development system is D Buzzer output driver available.

TELEFUNKEN Semiconductors 11 07.97 VEE2 VEE1 C2 C1 OSCIN OSCOUT AVDD VSS VDD NRST TE SCLIN SCLOUT

VREG Real time Low voltage Master Test System clock detect reset clock S17...S32 LCD Sleep (bidir. I/O) 32 x 4 Timer/ and ROM RAM Prescaler counter PRAM S1...S16 9K x 8 bit 256 x 4 bit Watch– dog Timer 1 16 I/O Interval I/O Port 4 256 x 4 bit MARC4 Timer COM0.. Timer 0 (high drive) COM3 4–bit CPU core

I/O bus

I/O I/O Interrupt Interrupt I/O I/O & reset I/O serial Buzzer

Port 0 Port 1 Port B Port 6 96 11556

 Figure 10. M44C588 (for INCOR software)

TST1 TST2 TCL NRST VDD VSS

System-clock generation Sleep Power-on reset

RAM address registers ROM X 4096 x 8 bit Y RAM SP 253 x 4 bit Program counter RP Memory bus Instruction bus CCR Instruction Interrupt decoder TOS ALU controller

I/O bus I/O I/O + strobe C1 C2 32 kHz LCD VEE2 driver VEE1 4 4 Inputs I/O External Oscillator key int. interrupts Prescaler VREG 4 4

PORT 1 PORT 0 PORT 5PORT 4 INT7 AV DD AV SS COM0...3 OD INT2, S01...20 BUZZER 32 kHz 96 12020

Figure 11. M43C505

12 TELEFUNKEN Semiconductors 07.97 Table 2. TEMIC products for time-code receivers

Product Function Key Features Benefits Package Availa–

bility

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁU4223B Time-code receiver • Extremely low-power Sensitivity increased SSO20 Now



ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á with A/D converter consumption by INCOR software

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á • Very high sensitivity

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á • Very high selectivity by using

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á two crystals

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á • 4-bit ADC output

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁT4225B Time-code receiver • Die version Low-cost solution Die form Now

with TCO

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á • Extremely low-power

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á consumption

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁ • Á Á Á Á Á

Á Very high sensitivity

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á • Very high selectivity by using

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á Á two crystals

U4226B Time-code receiver • Extremely low-power Flexible to different SSO20 Now

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ with TCO consumption applications

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á Á

• Very high sensitivity

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á Á

• Very high selectivity by using

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á two crystals

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁU4224B Time-code receiver • Extremely low-power Flexible to different SO16L Now

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á with TCO consumption applications

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á • Very high sensitivity

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á • Very high selectivity by using

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á Á two crystals



ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ • ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁM44C588 4-bit low-power Up to 128 segments LCD drive For INCOR software Die form Q3/97

microcontroller

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á • 512 4–bit RAM

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á • 9-KByte ROM

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á • Mask-programmable

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁM43C505 4-bit low-power • Up to 80 segments LCD drive Low-cost solution Die form Now

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á Á microcontroller

• 256 4-bit RAM

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á

Á • 4-KByte ROM

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á Á Á

• Mask-programmable

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TELEFUNKEN Semiconductors 13 07.97 Design of a Time-Code Receiver with U422xB U4223B Circuit Technology The radio-controlled receiver chip U4223B and its modi- fications combine high sensitivity and low power con- R1 sumption with a broad range of applications. The supply T3 T4 voltage range of 1.2 V to 5.25 V enables various applications such as battery supply or supply of standard Vo logic circuits. The IC’s power consumption of typically T1 13 µA to 20 µA fits for long life-battery applications, Vi e.g., wrist watches. The sensitivity in this case, however, T VS is near to the physical limit. The signal-to-noise ratio and 2 T T6 T7 thus the overall sensitivity can be improved by means of 5 an internal A/D converter and special software for signal analysis. Several innovations were needed in circuit tech- R2 I1 I2 nology to achieve these improvements. 1 mA 0.1 mA The operating resistances of amplification stages become larger, the lower the supply currents. For this reason, integration limits, preventing further decrease of the Figure 12b. Differential stage with electronic load supply current, show up very soon. This difficulty is over- come by using active, electronic resistances (figures 12a Figure 12. and 12b). Figure 13a shows the principle diagram of a crystal filter. Figure 12a shows a conventional differential stage. In An undesired signal is generated at high frequencies due to the parallel capacitance (load capacitance) Cb. figure 12b, the circuit with T3 – T7 replaces the operating resistances R1 and R2. The values of the operating resistances are determined by the differential resistance C b of the transistor diodes T5 and T6. The transistor current sources T3 and T4 are controlled via the control loop (T7).

The amplification of this circuit is approximately: I1/I2. C a L R The non-linearity of the diodes T5 and T6 is completely compensated by the non-linearity of a similar subsequent stage, thus resulting in very low-distorted amplifiers. As a disadvantage, additional noise is generated due to the Figure 13a. Principle of a crystal-filter circuit current sources T3 and T4. The bandwidth of 100 kHz at an amplification factor of 10 is identical to a conventional II1 differential stage. 2

R1 R2 200 k 200 k

Ve Vo Vi T 1 Q Cp V T2 S 1.2 p

VS I1

2.5 mA

Figure 13b. Crystal filter with capacitance compensation Figure 12a. Conventional differential stage Figure 13.

14 TELEFUNKEN Semiconductors 07.97 A new crystal-filter circuit was developed (figure 13b) The resistance of the pinch resistors P1 and P2 increases which enables the compensation of parallel capacitance according to the voltage control used. Depending on the of the crystal and additionally easy adjustability of the technology applied, a factor of about 3 in the range of 0 V bandwidth. Selectivity was improved by using two filters. to 5 V is normal. In the circuit as shown in figure 15, the The circuit consists of two differential stages connected pinch resistances serve as controllable emitter resis- crosswise at the outputs. The first stage has a crystal filter tances. By means of the transistors T1 – T3, the output between the emitters. The second differential stage with voltage Vout tracks the input voltage Vin and the pinch re- Cp produces an equal capacitive current which compen- sistances are made equal to one another. The input sates the undesired output current. electrode In acts as a diode in reverse direction, i.e., it hardly picks up any current flow.

I 1 I2 I3

0.5 mA 0.25 mA T 5 4 times Out T T 6 3 T T 8 1 T2 T1 4 times T 7 PP T In 1 2 T 4 Ve 2 T 500 k 3 Iout 4 times Figure 15. Decoupling amplifier based on controlled pinch resistances I 0.5 1 0.5 T T The decoding by means of a normal Schmitt trigger is m m 9 10 A I2 A somewhat disadvantageous, because only logic 0 or 1 are available as output signal. The U4223B’s integrated A/D converter, however, provides the processor with a 4-bit signal. A special software achieves a signal-to-noise ratio Figure 14. Rectifier circuit with asymmetrical which is approximately 6 dB better than that when using differential stages a Schmitt-trigger (TCO) signal, and thus also a gain in sensitivity of up to 6 dB. The converter especially developed for TCO handling requires only a current supply of m Improved bandwidth-to-current-consumption ratio is approximately 1.7 A. The input signal generates a µ m achieved by using a new type of rectifier circuit (see current of 0 A to 100 A. A/D conversion is triggered figure 14). Two asymmetrical differential stages are built off by an external clock signal. After a downward slope into this new rectifier stage. By means of this circuitry, a of the clock signal, a value appears at the 4-bit output bandwidth of more than 100 kHz at only 1.5 µA current which corresponds to the variation in the mean value of consumption can be achieved. the antenna voltage. The time-code signal can be decoded by means of a series of such sampling values in a time To design with small capacitances in the external sequence of approximately 10 ms. After the upward slope circuitry, largest possible modulation and smallest of the clock signal, a value appears which approximately possible creepage currents have to be gained. This is corresponds to the level of the antenna voltage (field- achieved by using controlled pinch resistances instead of strength signal). By means of this value, an indication of field-effect transistors (figure 15). receiving conditions can be derived.

TELEFUNKEN Semiconductors 15 07.97 Board Layout effect of an interference on the antenna circuit causes an interference voltage which is proportional to the resonant When designing a board layout, certain guidelines have resistance, while the signal voltage generated by the to be maintained to achieve high sensitivity and minimum transmitter field is proportional to the root of the resonant parasitic effects. The wires connected to the antenna have resistance. This means that when the resonant resistance to be shielded or twisted and should be very short in size is decreased, sensitivity is also decreased somewhat. It is on the board. The filter crystals have to be placed very more important in most cases, however, that the efficien- close to the IC pins in order to avoid additional cy-to-noise ratio is improved than taking care of the input capacitances. Even circuit capacitances of a few tenths pF voltage only. 100 kW is recommended as a standard diminish the “far-off selectivity” and thus the sensitivity value. of the system. Pulsing currents, for example for a stepper The resonant Q factor of the ferrite antenna should be as motor, can activate the antenna by means of the magnetic high as possible as sensitivity increases proportionally to field. Electro-magnetic fields can also be generated by the root of the resonant Q factor and the suppression of the circuit. It should be therefore as small, as narrow as interferences generated near the antenna is improved. possible. Ground loops as well as metal covers near the ferrite antenna can mute the antenna due to induced eddy Higher resonant Q factors can nevertheless be influenced currents. This can be avoided if the axes of the antenna in a negative way by temperature and environmental rod are on level with the circuit path. conditions. Therefore, resonant Q factor values of more than 100 are critical. To avoid serial resistances which At lower frequencies, the radio-controlled clock IC has reduce the Q factor, the antenna-circuit capacitor should very good interference suppression so that the supply be placed as close as possible to the antenna coil. voltage interference can be easily avoided by sieving via an RC filter. Television sets interfere above all in the fifth Measuring the resonant resistance is complicated as the harmonic of the line frequency. If the clock is on top of resonant circuit should neither be muted nor detuned by a television set it only receives if the television set is the measuring instrument. The resonant circuit can be switched off. Gas discharge lamps (fluorescent tubes) activated without interference by a wire loop which is operating at 50 Hz inductively are weak interference near the antenna rod. By using an indicator which has suf- factors as long as the discharge is stable and the inter- ficiently high impedance and low capacitance (the test ference suppression is effective. Energy-saving lamps probe 1:10 of a typical oscillograph usually has 1 M and operating at high frequencies have (in contrast to the approximately 8 pF which is not sufficient), the resonant interference factors mentioned above) a stronger inter- resistance Rres can be determined by the resonant circuit ference spectrum which is, however, according to capacitance, C, and a measurement of the bandwidth, b, measurements carried out by TEMIC, below 77.5 kHz. to Rres = 1/ (2 pbC). Another method of defining the resonant resistance value is to halve the resonant voltage by In case the moment of the beginning of an interference parallel switching a resistor (the value has to be tested). impulse is known, the SL function can be used. If there is The resistance is then equal to the resonant resistance. a logic “0” at the SL input, the operating stage of the The resonant Q factor (Q = f / ) can be determined by receiver is memorized. After interference decreases and res b the bandwidth, b, and the resonant frequency, f . after the reset of the SL input (logic “0”), the receiver res carries on operation. Application A main application is the suppression of self distortion Figure 16 shows the dimensioning of the external compo- that may occur due to the impulse of the stepper motor. nents for European receiving conditions, i.e., for Antenna Circuit receiving the time-code signal DCF77 from Mainflingen/ Frankfurt a.M. The receiver input is dimensioned for the normal use of Other transmitters, for example the American WWVB a tuned ferrite antenna. An aerial or ferrite antenna can be (60 kHz) in Fort Collins, the English MSF (60 kHz) in used. However, a tuned input circuit has to be available Teddington or the Japanese JG2AS (40 kHz) in Sanwa where the throw antenna can be coupled onto it, either need different component layouts because their modula- inductively or by means of a tap. Optimum signal-to- tion differs from each other (see table 2), and different noise ratio is achieved for a resonant resistance of the crystals because their transmission frequency differs antenna circuit of 200 to 400 kW. However, using a from each other. resonant resistance of more than 200 kW is disadvantageous due to internal and external interference sources. The crystal bandwidth can be influenced by the resis- This is because the capacitive or inductive influential tance Rsb for different types of time-code frequencies.

16 TELEFUNKEN Semiconductors 07.97 The crystal Q1 can be replaced by a capacitance of 10 pF with regard to circuitry between TCO decoding or 4-bit (respectively 22 pF for 40 kHz). This causes a loss in decoding. In order to avoid negative effects of the output selectivity and somewhat sensitivity. pulses on the antenna circuit, the digital outputs are smoothed by 10 nF each. Highest sensitivity is achieved Figure 16 shows a block diagram of the U4223B with by using an antenna which operates symmetrically. This external circuitry for 4-bit decoding. Apart from the means that a central tap of the antenna coil is connected connections to the microprocessor, there is no difference with VCC instead of the connection shown in figure 16.

Table 3. *

Transmitter Frequency C1 C2 C3 C4 Rsb

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DCF 77.5 kHz 6.8 nF 33 nF 10 nF 220 pF o

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

WWVB MSF 60 kHz 15 nF 47 nF 10 nF 220 pF 10 k

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

JG2AS 40 kHz 680 pF 220 nF 10 nF 220 pF

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

* = C4 improves the sensitivity in some designs to a certain extent

10 nF Microprocessor 10 nF 77.5 kHz

10 nF 2) Q2 D D PON Q2A 10 nF 1 2 D3 TCO Q2B

D 0 Analog-digital SL +V converter CC Clock VCC U4223B control CLK Stabilization 2) De- IN1 FLB C Recti- co- 3 Amplifier 10 nF fier der IN FLA Ferrite antenna GND SB Q1A Q1B RECINT DEC 1)

Rsb C C Q C4 1 2 1) C sometimes 1 220 p 6.8 n 33 n 4 77.5 kHz helpful REC INT DEC 2) TCO und IN1 for JG2AS R C 1 only accessible in 1 1 M T4223B 680 p C2 220 n

Figure 16. U4223B with external circuitry for 4–bit decoding

Decoding Algorithm the integrating capacitor C2 which is picked up by the input DEC of the decoder (figure 16). If the RF amplitude The T4223B (T means chip form) offers two possibilities changes, the voltage at the capacitor C2 also changes be- for decoding: The TCO (Time-Code Output) output and cause the variable gain amplifier is continuously the 4-bit output. In the packaged IC U4223B, only the self-regulating (see figure 17). During charging and 4-bit output is possible due to the pin number. The devices decharging of the integrating capacitor C2, positive and U4224B to U4226B only have a TCO output. The signals negative currents occur. of both outputs are basically generated by the current via

TELEFUNKEN Semiconductors 17 07.97 These currents are transferred into a voltage which trig- The Use of the TCO Signal gers the TCO via a comparator with hysteresis (Schmitt trigger). The Schmitt-trigger’s output reflects the trans- In the following explanation it is assumed that the proc- mitter’s modulation. essor uses the TCO signal for decoding the time-code signal DCF77. The TCO output has to be checked The time constants of the system are adjusted so that the regularly in order to recognize any changes. A sampling output voltage (which adjusts the amplification of the rate of 50 Hz – 100 Hz is adequate enough to be able to control amplifier) of the integrator at Pin INT follows the differentiate clearly between the incoming pulse lengths input signal within approximately 100 ms. Figure 17 of 100 ms and 200 ms. When using the existing clock shows the reactions (modulation) on two pulses of crystal of 32768 Hz, a sampling rate of 64 Hz is recom- approximately 100 and 200 ms. mended. First of all, a software meter * which counts from 0 – 63 every second * is synchronized with the After the input voltage decreases, the output voltage of rising slope of the TCO signal. Then, the rising slope is the integrator increases rapidly and sets the control acknowledged by the internal clock and does not have to amplifier to a higher level of amplification until the be observed any longer. Errors at the beginning of the previous signal level at the rectifier is reached once again. slope are suppressed by this procedure. Before being able Then the process is repeated, but in the opposite direction. to begin with single-bit recognition, the beginning of a The current through the integration capacitor corresponds new minute has to be obtained from the input data. The to the differential quote of the voltage and shows a modulation of DCF therefore ignores the 59th second positive and negative wave. The current is picked up from pulse which is indicated by the absence of a TCO the decoder and fed to a Schmitt trigger. At the TCO, the decrease. To verify this, the 20th pulse which should be Schmitt trigger generates high potential after a positive 200 ms long can then be checked. When the wave and low potential after a negative wave. minute-synchronization has been completed, single-bit recognition starts. At the 4-bit output, the integration converter splits up the Due to the internal 1/ 64-s clocking, the program current into 16 stages by means of an A/D converter. This recognizes a slope of approximately 6.4 clocks as being enables better recognition of the modulation when logic “0” and a slope of approximately 12.8 clocks as interference or noise is present. A sequence of 4-bit being logic “1”. The data sheet provides recommenda- values is fed to the microprocessor and analyzed with a tions for the time windows to be used. Slopes outside the special program. In this case, the decoding requires a very time window are caused by interferences and can be effective procedure and a powerful microcontroller with ignored. If there is no slope present then the time code can at least 3 k 8 ROM and about 128 byte RAM. By using not be decoded and there has to be a pause to wait for the  TEMIC’s software INCOR , the signal-to-noise ratio is next minute to begin. After the end of a minute, the data improved by more than 6 dB. of a complete time-code telegram has come in and the bit pattern generated can be converted into commands for controlling the display or the clock hand. In order to avoid a false display, the parity bits in the time-code telegram should also be checked. Best reception (as expected from a time-controlled watch) is guaranteed if the following time-code telegram is also decoded and compared with the one which has been decoded previously. Only if both time-code telegrams differ by exactly a minute, will the result be accepted. If there are no correct results even from a longer receiving time of, for example, 10 minutes, the receiver will be switched off and another attempt will be started after one or two hours. In current-critical applications, the decoding can only be started after a day has elapsed. The Use of the 4-Bit Output The use of a 4-bit output is more difficult than the use of the TCO signal. The microprocessor has to provide a 4-bit wide input port and an output lead for the clock signal. To suppress interferences caused by steep impulse slopes, Figure 17. Principle of dynamic procedures the four signal leads should be blocked by capacitors.

18 TELEFUNKEN Semiconductors 07.97 Every high-low transition of the clock signal starts a con- filter for the power supply of the receiver is applied with version of the ADU (64 conversions per second). The Rv = 1 kW and CS = 4.7 mF. The antenna supply is as conversion is completed and the result can be read from short as possible and surrounded by shielding conductors the processor after 4 ms at the very latest. With regard to (see figure 19). The connections of the filter crystals are the decoding process, there is no difference between also kept as short as possible. 4-bit-and TCO-signal decoding. However, if 4-bit decoding is carried out, a 16-value sampling rate (instead of The output TCO and input INI are not available in this simple modulation changes) has to be analyzed. Then, layout. according to the result, a decision has to be made whether the sequence corresponds to a short pulse, a long pulse or In figures 18 and 19, only a few important circuit no pulse at all. TEMIC provides the customer with an elements are shown, the rest can be found by means of  figure 16. The microcontroller M38207E8HP is used for effective decoding program, the INCOR software. controlling and signal evaluation. The clock signal CLK Layout Example is fed to the receiver via a small capacitor of 1 pF. This ensures that the slope’s deviation at the receiver IC is only Figures 18 and 19 show the design of a piggyback board 100 mV which is sufficient for proper operation. At (front side and reverse side). The layout contains the re- higher voltages, a distortion of the antenna circuit due to ceiver IC U4223B in an SO20L package for 4-bit the bond wires can not be avoided. With a ferrite antenna decoding and a TEMIC MARC4 microcontroller. of 120 mm, placed 2 cm near to the board and with  Depending on the programming, the processor can TEMIC’s INCOR software, improved field sensitivity of control an LCD display, the stepper motor of the clock more than 10 mV/ m is gained. This can be proven under hands etc. The connection for each application as well as laboratory conditions in the Faraday cage. In normal for a keyboard is achieved by using the numerous pins. cases, a sensitivity value as mentioned above is not The supply voltage is 3 to 5 V (due to the microprocessor) necessary, but the advantage of improved interference and is fed to the reverse side. On the front side, a lowpass suppression is obvious.

Rv 1k

4.7

10n 10n 10n 10n

sb R Q1

4 C 1p 1 C 2 C

Figure 18. The front side of a board layout Figure 19. The reverse side of a board layout

TELEFUNKEN Semiconductors 19 07.97 U4223B Time-Code Receiver with A/D Converter

Description

The U4223B is a bipolar integrated straight-through receiver circuit in the frequency range of 40 to 80 kHz. The device is designed for radio-controlled clock applications.

Features D Very low power consumption D Only a few external components necessary D Very high sensitivity D 4-bit digital output D D High selectivity by using two crystal filters AGC hold mode D Power-down mode available

Block Diagram

PON CLK D3 D2 D1 D0 93 7726 e 12 17 18 19 20 16 11 VCC 1 FLB Power supply ADC Decoder 10 GND FLA 3 9 DEC Impulse circuit AGC Rectifier & 13 SL 2 amplifier IN integrator 4561415 78 SB Q1A Q1B Q2A Q2B REC INT

Figure 1.

TELEFUNKEN Semiconductors 21 Rev. A3, 20-Jun-97 U4223B

Pin Description Pin Symbol Function 1 D0 (LSB) VCC 20 1 VCC Supply voltage 2 IN Amplifier – Input IN 2 19 D1 3 GND Ground 4 SB Bandwidth control GND 3 18 D2 5 Q1A Crystal filter 1 6 Q1B Crystal filter 1 SB 4 17 D3 (MSB) 7 REC Rectifier output 8 INT Integrator output Q1A 5 16 PON U4223B 9 DEC Decoder input 10 FLA Lowpass filter Q1B 6 15 Q2B 11 FLB Lowpass filter

REC 7 14 Q2A 12 CLK Clock input for ADC 13 SL AGC hold mode

INT 8 13 SL 14 Q2A Crystal filter 2 15 Q2B Crystal filter 2 DEC 9 12 CLK 16 PON Power ON/OFF control 17 D3 Data out MSB FLA 10 11 FLB 18 D2 Data out 19 D1 Data out 93 7728 e 20 D0 Data out LSB

Figure 2. Pinning

IN SB A ferrite antenna is connected between IN and VCC. For A resistor RSB is connected between SB and GND. It high sensitivity, the Q factor of the antenna circuit should controls the bandwidth of the crystal filters. It is recom- be as high as possible. Please note that a high Q factor mended: RSB = 0 W for DCF 77.5 kHz, RSB = 10 kW for requires temperature compensation of the resonant 60 kHz WWVB and RSB = open for JG2AS 40 kHz. frequency in most cases. Specifications are valid for Q>30. An optimal signal-to-noise ratio will be achieved by a resonant resistance of 50 to 200 kW. VCC 94 8381

IN SB

GND 94 8379

Figure 3. Figure 4.

22 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4223B

Q1A, Q1B SL

In order to achieve a high selectivity, a crystal is con- AGC hold mode: SL high (VSL = VCC) sets normal func- nected between the pins Q1A and Q1B. It is used with the tion, SL low (VSL = 0) disconnects the rectifier and holds serial resonant frequency of the time-code transmitter the voltage VINT at the integrator output and also the AGC (e.g., 60 kHz WWVB, 77.5 kHz DCF or 40 kHz JG2AS). amplifier gain. The equivalent parallel capacitor of the filter crystal is internally compensated. The compensated value is about 0.7 pF. If full sensitivity and selectivity are not needed, VCC the crystal filter can be substituted by a capacitor of 82 pF.

Q1A Q1B 94 8378 Figure 8. GND 94 8382 Figure 5. INT

Integrator output: The voltage VINT is the control voltage REC for the AGC. The capacitor C2 between INT and DEC defines the time constant of the integrator. The current Rectifier output and integrator input: The capacitor C1 through the capacitor is the input signal of the decoder. between REC and INT is the lowpass filter of the rectifier and at the same time a damping element of the gain control. 94 8375

94 8374

INT REC GND GND Figure 9. Figure 6.

FLA, FLB DEC Lowpass filter: A capacitor C3 connected between FLA Decoder input: Senses the current through the integration and FLB suppresses higher frequencies at the trigger capacitor C2. The dynamic input resistance has a value of circuit of the decoder. about 420 kW and is low compared to the impedance of C2.

DEC FLB FLB

GND 94 8376 94 8377

Figure 7. Figure 10.

TELEFUNKEN Semiconductors 23 Rev. A3, 20-Jun-97 U4223B

Q2A, Q2B A sequence of the digitalized time-code signal can be analyzed by a special noise-suppressing algorithm in According to Q1A/Q1B, a crystal is connected between order to increase the sensitivity and the signal-to-noise the Pins Q2A and Q2B. It is used with the serial resonant ratio (more than 10 dB compared to conventional frequency of the time-code transmitter (e.g., 60 kHz decoding). Details about the time-code format are WWVB, 77.5 kHz DCF or 40 kHz JG2AS). The equiva- described separately. lent parallel capacitor of the filter crystal is internally compensated. The value of the compensation is about 0.7 pF. Decimal Gray 0 0000 1 0001 2 0011 3 0010 Q2A Q2B 4 0110 5 0111 6 0101 94 8383 GND 7 0100 Figure 11. 8 1100 9 1101 10 1111 11 1110 PON 12 1010 If PON is connected to GND, the receiver will be 13 1011 activated. The set-up time is typically 0.5 s after applying 14 1001 GND at this pin. If PON is connected to VCC, the receiver will switch to power-down mode. 15 1000

VCC VCC PON

D0 ... D3 PON

94 8373 94 9221 GND

Figure 12. Figure 13.

CLK D0, D1, D2, D3 The input of the ADC is switched to the AGC voltage by the rising slope of the clock. When conversion time has The outputs of the ADC consist of PNP-NPN push-pull passed (about 1.8 ms at 25°C), the digitalized field- stages and can be directly connected to a microcomputer. strength signal is stored in the output registers D0 to D3 In order to avoid any interference of the output into the as long as the clock is high and can be read by a micro- antenna circuit, we recommend terminating each digital computer. The falling slope of the clock switches the output with a capacitor of 10 nF. The digitalized signal of input of the ADC to the time-code signal. In the mean- the ADC is Gray coded (see table). It should be taken into time, the digitalized time-code signal is stored in the account that in power-down mode (PON = high), D0, D1, output registers D0 to D3 as long as the clock is low (see D2 and D3 will be high. figure 14).

24 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4223B

Vclk Thus, the first step in designing the antenna circuit is to mV measure the bandwidth. Figure 17 shows an example for 100 the test circuit. The RF signal is coupled into the bar antenna by inductive means, e.g., a wire loop. It can be 50 measured by a simple oscilloscope using the 10:1 probe. The input capacitance of the probe, typically about 10 pF, should be taken into consideration. By varying the fre- 0 47 811 12 t/ms quency of the signal generator, the resonant frequency Now, the time-code can be determined. signal can be read Falling edge initiates time-code conversion Now, the AGC value can be read RF signal Scope generator Rising edge initiates 77.5 kHz AGC signal conversion 93 9188

Figure 14. Probe 10 : 1 w10 MW C wire loop res In order to minimize interferences, we recommend a 94 7907 e voltage swing of about 100 mV. A full supply-voltage Figure 16. swing is possible but reduces the sensitivity. At the point where the voltage of the RF signal at the probe drops by 3 dB, the two frequencies can then be VCC measured. The difference between these two frequencies is called the bandwidth BWA of the antenna circuit. As the value of the capacitor Cres in the antenna circuit is known, CLK it is easy to compute the resonant resistance according to the following formula: + 1 Rres p GND 94 9231 2 BWA Cres where Figure 15. Rres is the resonant resistance, BWA is the measured bandwidth (in Hz) Cres is the value of the capacitor in the antenna circuit Please note: (in Farad). The signals and voltages at the Pins REC, INT, FLA, If high inductance values and low capacitor values are FLB, Q1A, Q1B, Q2A and Q2B cannot be measured by used, the additional parasitic capacitances of the coil standard measurement equipment due to very high inter- (v20 pF) must be considered. The Q value of the capa- nal impedances. For the same reason, the PCB should be citor should be no problem if a high Q type is used. The protected against surface humidity. Q value of the coil differs more or less from the DC resistance of the wire. Skin effects can be observed but do not dominate. Design Hints for the Ferrite Antenna Therefore, it should not be a problem to achieve the The bar antenna is a very critical device of the complete recommended values of the resonant resistance. The use clock receiver. Observing some basic RF design rules of thicker wire increases the Q value and accordingly helps to avoid possible problems. The IC requires a reso- reduces bandwidth. This is advantageous in order to nant resistance of 50 kW to 200 kW. This can be achieved improve reception in noisy areas. On the other hand, by a variation of the L/C-relation in the antenna circuit. temperature compensation of the resonant frequency It is not easy to measure such high resistances in the RF might become a problem if the bandwidth of the antenna region. A more convenient way is to distinguish between circuit is low compared to the temperature variation of the the different bandwidths of the antenna circuit and to cal- resonant frequency. Of course, the Q value can also be re- culate the resonant resistance afterwards. duced by a parallel resistor.

TELEFUNKEN Semiconductors 25 Rev. A3, 20-Jun-97 U4223B

Temperature compensation of the resonant frequency is or to use a twisted wire for the antenna-coil connection. a must if the clock is used at different temperatures. This twisted line is also necessary to reduce feedback of Please ask your supplier of bar antenna material and of noise from the microprocessor to the IC input. Long con- capacitors for specified values of the temperature nection lines must be shielded. coefficient. Furthermore, some critical parasitics have to be consid- A final adjustment of the time-code receiver can be ered. These are shortened loops (e.g., in the ground line carried out by pushing the coil along the bar antenna. The of the PCB board) close to the antenna and undesired maximum of the integrator output voltage VINT at loops in the antenna circuit. Shortened loops decrease the Pin INT indicates the resonant point. But attention: The Q value of the circuit. They have the same effect like con- load current should not exceed 1 nA, that means an input ducting plates close to the antenna. To avoid undesired resistance w 1 GW of the measuring device is required. loops in the antenna circuit, it is recommended to mount Therefore, a special DVM or an isolation amplifier is the capacitor Cres as close as possible to the antenna coil necessary.

Absolute Maximum Ratings

Parameters Symbol Value Unit

Supply voltage VCC 5.25 V Ambient temperature range Tamb –25 to +75 _C Storage temperature range Rstg –40 to +85 _C Junction temperature Tj 125 _C Electrostatic handling ± VESD 2000 V (MIL Standard 883 D), except Pins 5, 6, 14 and 15

Thermal Resistance

Parameters Symbol Maximum Unit

Thermal resistance RthJA 70 K/W

Electrical Characteristics

VCC = 3 V, reference point Pin 3, input signal frequency 80 kHz, Tamb = 25_C, unless otherwise specified Parameters Test Conditions / Pin Symbol Min Typ Max Unit

Supply voltage range Pin 1 VCC 1.2 5.25 V Supply current Pin 1 ICC Without reception signal 30 mA with reception signal = 200 mV 15 25 mA OFF mode 0.1 mA Set-up time after VCC = 1.5 V t 2 s VCC ON AGC amplifier input; IN Pin 2 Reception frequency range fin 40 80 kHz Minimum input voltage Rres = 100 kW, Qres > 30 Vin 1 1.5 mV Maximum input voltage Vin 40 80 mV Input capacitance to GND Cin 1.5 pF

26 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4223B

Parameters Test Conditions / Pin Symbol Min Typ Max Unit ADC; D0, D1, D2, D3 Pins 17, 18, 19 and 20 Output voltage HIGH RLOAD = 870 kW to GND VOH VCC-0.4 V LOW RLOAD = 650 kW to VCC VOL 0.4 V Output current HIGH VTCO = VCC/2 ISOURCE 3 10 mA LOW VTCO = VCC/2 ISINK 4 12 mA Input current into DEC Falling slope of CLK Idecs –32 –25 –18 nA (first bit) Input current into DEC Falling slope of CLK Idece 28 35 42 nA (last bit) Input current into DEC Falling slope of CLK Idecst 1.75 4 7 nA (step range) Input voltage at IN RF generator at IN, without (first bit) modulation rising slope of CLK Vmin –10 dBmV Input voltage at IN RF generator at IN, without (last bit) modulation rising slope of CLK Vmax 60 dBmV Input voltage at IN RF generator at IN, without (step range) modulation rising slope of CLK Vstep 4.7 dBmV Clock input; CLK Pin 12 Input voltage swing Vswing 50 100 VCC mV Clock frequency fclk 100 125 Hz Dynamical input resistance Rdyn. 100 kW Power-ON/OFF control; PON Pin 16 Input voltage HIGH Required IIN y 0.5 mA VCC-0.2 V LOW VCC-1.2 V Input current VCC = 3 V IIN 1.4 1.7 2 mA VCC = 1.5 V 0.7 mA VCC = 5 V 3 mA Set-up time after PON t 0.5 2 s AGC hold mode; SL Pin 13 Input voltage HIGH Required IIN y 0.5 mA VCC-0.2 V LOW VCC-1.2 V Input current Vin = VCC 0.1 mA Vin = GND 2.5 mA Rejection of interference ȧfd – fudȧ = 625 Hz signals Vd = 3 mV, f d = 77.5 kHz using 2 crystal filters af 43 dB using 1 crystal filter af 22 dB

TELEFUNKEN Semiconductors 27 Rev. A3, 20-Jun-97 U4223B

Test Circuit (for Fundamental Function)

Test point: DVM with high and Ipon low input line for measuring a Vd voltage Vxx or a current Ixx 300k 300k 300k 300k by conversion into a voltage 1.657V

Sd0 Sd1 Sd2 Sd3 Spon 1M 82p 1M Vd0 Vd1 Vd2 Vd3 Isl

D2 D3 PON Q2B Q2A Ssl

D1 SL ANALOG ÎÎÎÎU4223B 1M Iclk DIGITAL ÎÎÎÎ TIME CONVERTER D0 CONTROL CLK Ivcc 100k Vclk VCC STABILISATION FLB DECODING

Sdec Iin FLA 10M AGC– AMPLIFIER RECTIFIER 100M IN DEC 1M Idec

GND SB Q1A Q1B REC INT Vcc 3V 82p 680p 3.3n 420k Vdec Vrec ~ Srec Vin Ssb Sint

Vsb 10M 10M 1M Vint

Vrec Isb Vint Irec Iint 94 9189

Figure 17.

28 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4223B

10 Field strength

4 Time-code signal

0 80 0 20 40 60 80 0 20 40 60

Gating (100/s) 94 9190

Figure 18. Example of a normal DCF signal

12 Field strength 10

6 Time-code signal 4

0 80 0 20 40 60 80 0 20 40 60

Gating (100/s) 94 9219

Figure 19. Example of a disturbed DCF signal

TELEFUNKEN Semiconductors 29 Rev. A3, 20-Jun-97 U4223B

Application Circuit for DCF 77.5 kHz Control lines +VCC

D0 Ferrite 1 20 Antenna 10 nF D1 2 19 f = 77.5 kHz 10 nF res D2 3 18 10 nF D3 4 17 10 nF PON 3) 5 16 77.5 kHz 2) U4223B 77.5 kHz Microcomputer 6 15

Figure 20. Application Circuit for WWVB 60 kHz Control lines +VCC

D0 Ferrite 1 20 Antenna 10 nF D1 2 19 f = 60 kHz 10 nF res D2 3 18 10 nF RSB D3 4 17 W 10 nF 10 k PON 3) 5 16 60 kHz 2) U4223B 60 kHz Microcomputer 6 15

7 14 C 4) Keyboard 1 1) CLK 15 nF SL 8 13 Display C2 47 nF 9 12 1) If SL is not used, SL is connected to VCC 10 11 2) 60-kHz crystal can be replaced by 10 pF C3 3) If IC is activated, PON is connected to GND 94 8969 10 nF 4) Voltage swing 100 mVpp at Pin 12 Figure 21.

30 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4223B

Application Circuit for JG2AS 40 kHz +V CC Control lines

D0 Ferrite 1 20 Antenna 10 nF D1 2 19 10 nF fres = 40 kHz D2 3 18 10 nF D3 4 17 10 nF PON 3) 5 16 40 kHz 2) U4223B 40 kHz Microcomputer 6 15

14 7 4) C1 CLK Keyboard 1 MW SL 1) 680 pF 8 13 Display 220 nF R C 2 9 12 1) If SL is not used, SL is connected to VCC 10 11 2) 40-kHz crystal can be replaced by 22 pF C 3 3) If IC is activated, PON is connected to GND 94 8970 10 nF 4) Voltage swing 100 mVpp at Pin 12

Figure 22.

TELEFUNKEN Semiconductors 31 Rev. A3, 20-Jun-97 U4223B

PAD Coordinates The T4223B is also available as die for “chip-on-board” mounting. DIE size: 2.26 x 2.09 mm PAD size: 100 x 100 mm (contact window 88 x 88 mm) Thickness: 300 mm " 20 mm SYMBOL X-Axis/mm Y-Axis/mm SYMBOL X-Axis/mm Y-Axis/mm IN1 128 758 CLK 2044 1372 IN 128 310 SL 2044 1624 GND 354 124 Q2A 1980 1876 SB 698 128 Q2B 1634 1876 Q1A 1040 128 PON 1322 1876 Q1B 1290 128 TCO 1008 1876 REC 1528 128 D3 696 1876 INT 1766 128 D2 384 1876 DEC 2044 268 D1 128 1682 FLA 2044 676 D0 128 1368 FLB 2044 1012 VCC 128 1098

The PAD coordinates are referred to the left bottom point of the contact window.

PAD Layout

D2 D3 TCO PON Q2B Q2A D1 SL

D0 CLK

VCC T4223B FLB

IN1 FLA

IN DEC Y Axis GND SB Q1A Q1B REC INT

X Axis 94 8892 Reference point (%) Figure 23.

32 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4223B

Information on the German Transmitter Station: DCF 77, Location: Mainflingen/Germany, Frequency 77.5 kHz, Geographical coordinates: 50__ 0.1’N, 09__ 00’E Transmitting power 50 kW Time of transmission: permanent

Time frame 1 minute ( index count 1 second ) Time frame 0 5 10 15 20 25 30 3540 45 50 55 0 5 10 8 4 8 1 8 2 4 1 2 4 8 1 2 4 1 2 4 8 2 4 1 1 2 A1 Z1 A2 S Z2 R 10 P1 20 10 10 20 40 80 P3 20 10 P2 20 10 40

coding minutes hourscalendar day month year when day of required the week 93 7527 Example:19.35 h s 124810 20 40 P1 1 2 4 81020P2

seconds 20 21 22 23 24 25 26 27 2829 30 31 32 33 34 35 minutes hours Start Bit Parity Bit P1 Parity Bit P2

Figure 24.

Modulation time frame. A time frame contains BCD-coded information of minutes, hours, calendar day, day of the week, The carrier amplitude is reduced to 25% at the beginning month and year between the 20th second and 58th second of each second for a period of 100 ms (binary zero) or of the time frame, including the start bit S (200 ms) and 200 ms (binary one), except the 59th second. parity bits P1, P2 and P3. Furthermore, there are 5 addi- Time-Code Format (based on tional bits R (transmission by reserve antenna), A1 (announcement of change-over to summer time), Z1 (dur- Information of Deutsche Bundespost) ing summer time 200 ms, otherwise 100 ms), Z2 (during The time-code format consists of 1-minute time frames. standard time 200 ms, otherwise 100 ms) and A2 There is no modulation at the beginning of the 59th (announcement of leap second) transmitted between the second to indicate the switch over to the next 1-minute 15th second and 19th second of the time frame.

TELEFUNKEN Semiconductors 33 Rev. A3, 20-Jun-97 U4223B

Information on the British Transmitter Station: MSF Geographical coordinates: 52__ 22’N, 01_ 11’W Frequency 60 kHz Time of transmission: permanent, except the first Transmitting power 50 kW Tuesday of each month from 10.00 h to 14.00 h. Location: Teddington, Middlesex

Time frame 1 minute Time frame ( index count 1 second) 0510 15 20 25 3035 40 45 50 55 0510 4 1 4 2 2 8 2 8 4 2 1 8 4 2 1 8 4 2 8 4 1 0 0 1 1 40 20 80 20 10 10 20 10 10 40 20 10

year month day of hour minute minute month day Switch over to of identifier the next time frame week Parity BST hour + minute check day of week bits day + month year 1 BST 7 GMT change 0 impending

500 ms 500 ms

93 7528 Example: 80 40 20 10 8 42110 8 4 2 1 March 1993

seconds 17 18 19 20 21 22 23 24 25 26 27 28 29 30 year month

Figure 25.

Modulation Time-Code Format The carrier amplitude is switched off at the beginning of The time-code format consists of 1-minute time frames. each second for a period of 100 ms (binary zero) or A time frame contains BCD–coded information of year, 200 ms (binary one). month, calendar day, day of the week, hours and minutes. At the switch-over to the next time frame, the carrier amplitude is reduced for a period of 500 ms. The prescence of the fast code during the first 500 ms at the beginning of the minute in not guaranteed. The transmission rate is 100 bits/s and the code contains information of hour, minute, day and month.

34 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4223B

Information on the US Transmitter Station: WWVB Location: Fort Collins Frequency 60 kHz Geographical coordinates: 40__ 40’N, 105__ 03’W Transmitting power 10 kW Time of transmission: permanent

Time frame 1 minute Time frame ( index count 1 second) 0 51015 202530 35 4045 50 55 0 510 M D B D 8 4 2 1 1 8 4 2 4 2 1 8 2 1 4 8 D D 80 40 10 00 00 40 20 80 20 10 P3 20 P2 FR 40 20 10 P1 10 P0 P0 SU A A P4 800 400 200 100 P5 2 1

daylight savings time bits leap second warning bit minutes hours days UTI UTI year sign correction leap year indicator bit “0” = non leap year “1” = leap year

93 7529 e Example: UTC 18.42 h Time frame

P0 40 20 10 8421P1 20 10 8 4 2 1 P2

seconds 012354678910 11 12 13 14 15 16 17 18 19 20 minutes hours Frame-reference marker

Figure 26.

Modulation Time-Code Format

The carrier amplitude is reduced by 10 dB at the begin- The time-code format consists of 1-minute time frames. ning of each second and is restored within 500 ms (binary A time frame contains BCD-coded information of one) or within 200 ms (binary zero). minutes, hours, days and year. In addition, there are 6 position-identifier markers (P0 thru P5) and 1 frame- reference marker with reduced carrier amplitude of 800 ms duration.

TELEFUNKEN Semiconductors 35 Rev. A3, 20-Jun-97 U4223B

Information on the Japanese Transmitter Station: JG2AS Location: Sanwa, Ibaraki Frequency 40 kHz Geographical coordinates: 36_11’ N, 139_51’ E Transmitting power 10 kW Time of transmission: permanent

Time frame 1 minute (index count 1 second) Time frame 0 5 1015 2025 3035 40 45 50 55 0 5 10 4 1 2 1 2 8 4 8 4 4 2 1 8 2 1 8 10 40 20 P1 20 10 P2 80 40 20 10 P3 P4 P5 P0 PO SUB FRM ADD ADD 10 0 200

minutes hours days code dut1 Example: 18.42 h Time frame P0 40 20 10 8 4 2 1P1 20 10 8 4 21P2

seconds 59 0 1234 5 6 7 8 9 1011121314151617181920 minutes hours Frame-reference marker (FRM) Position-identifier marker P0 Position identifier marker P1

0.5 second: Binary one 0.8 second: Binary zero 0.2 second: Identifier markers P0...P5 0.8 s 0.2 s 0.5 s 93 7508 e “1” “0” “P”

Figure 27.

Modulation Time-Code Format The carrier amplitude is 100% at the beginning of each The time-code format consists of 1-minute time frames. second and is switched off after 500 ms (binary one) or A time frame contains BCD-coded information of after 800 ms (binary zero). minutes, hours and days. In addition, there are 6 position- identifier markers (P0 thru P5) and 1 frame-reference markers (FRM) with reduced carrier amplitude of 800 ms duration. Ordering and Package Information Extended Type Number Package Remarks U4223B-CFS SSO20 plastic U4223B-CFSG3 SSO20 plastic Taping according to IEC-286-3 T4223B-CF No Die on foil T4223B-CC No Die on carrier

36 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4223B

Package Information

Package SSO20 5.7 Dimensions in mm 5.3 6.75 4.5 6.50 4.3

1.30 0.15 0.25 0.15 0.05 6.6 0.65 6.3 5.85

20 11

technical drawings according to DIN specifications 13007

110

TELEFUNKEN Semiconductors 37 Rev. A3, 20-Jun-97 U4224B Time-Code Receiver with Digitized Serial Output

Description

The U4224B is a bipolar integrated straight-through receiver circuit in the frequency range of 40 to 80 kHz. The device is designed for radio-controlled clock applications.

Features D Very low power consumption D Only a few external components necessary

D Very high sensitivity D Digitalized serial output signal D High selectivity by using two crystal filters D AGC hold mode D Power-down mode available

Block Diagram

PON TCO 93 7727 e 15 16 GND 3 11 FLB Power supply Decoder VCC 1 10 FLA

9 DEC

AGC Rectifier & 12 SL amplifier integrator IN 2 4561314 7 8 SB Q1A Q1B Q2A Q2B REC INT

Figure 1.

TELEFUNKEN Semiconductors 39 Rev. A3, 20-Jun-97 U4224B

Pin Description Pin Symbol Function VCC 1 16 TCO 1 VCC Supply voltage

IN 2 15 PON 2 IN Amplifier – Input 3 GND Ground GND 3 14 Q2B 4 SB Bandwidth control 5 Q1A Crystal filter 1 4 SB 13 Q2A 6 Q1B Crystal filter 1 U4224B 7 REC Rectifier output Q1A 5 12 SL 8 INT Integrator output

Q1B 6 11 FLB 9 DEC Decoder input 10 FLA Lowpass filter REC 7 10 FLA 11 FLB Lowpass filter 12 SL AGC hold mode INT 8 9 DEC 13 Q2A Crystal filter 2

93 7729 e 14 Q2B Crystal filter 2 15 PON Power ON/OFF control

Figure 2. Pinning 16 TCO Time-code output

IN SB A ferrite antenna is connected between IN and VCC. For A resistor RSB is connected between SB and GND. It con- high sensitivity, the Q factor of the antenna circuit should trols the bandwidth of the crystal filters. It is be as high as possible. Please note that a high Q factor recommended: RSB = 0 W for DCF 77.5 kHz, RSB = requires temperature compensation of the resonant 10 kW for 60 kHz WWVB and RSB = open for JG2AS frequency in most cases. Specifications are valid for 40 kHz. Q > 30. An optimal signal-to-noise ratio will be achieved by a resonant resistance of 50 to 200 kW.

VCC 94 8381

IN SB

GND 94 8379

Figure 3. Figure 4.

40 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4224B

Q1A, Q1B SL

In order to achieve a high selectivity, a crystal is con- AGC hold mode: SL high (VSL = VCC) sets normal nected between the Pins Q1A and Q1B. It is used with the function, SL low (VSL = 0) disconnects the rectifier and serial resonant frequency of the time-code transmitter holds the voltage VINT at the integrator output and also (e.g., 60 kHz WWVB, 77.5 kHz DCF or 40 kHz JG2AS). the AGC amplifier gain. The equivalent parallel capacitor of the filter crystal is internally compensated. The compensated value is about VCC 0.7 pF. If full sensitivity and selectivity are not needed, the crystal filter can be substituted by a capacitor of 10 pF for DCF and WWVB and 22 pF for JG2AS. SL

94 8378

Q1A Q1B Figure 8.

GND 94 8382

Figure 5. INT Integrator output: The voltage VINT is the control voltage for the AGC. The capacitor C2 between INT and DEC REC defines the time constant of the integrator. The current Rectifier output and integrator input: The capacitor C1 through the capacitor is the input signal of the decoder. between REC and INT is the lowpass filter of the rectifier and at the same time a damping element of the gain 94 8375 control.

94 8374 INT

REC GND

GND Figure 9.

Figure 6. FLA, FLB DEC Lowpass filter: A capacitor C3 connected between FLA Decoder input: Senses the current through the integration and FLB suppresses higher frequencies at the trigger capacitor C2. The dynamic input resistance has a value of circuit of the decoder. about 420 kW and is low compared to the impedance of C2.

FLB FLB DEC

94 8377

GND 94 8376 Figure 10.

Figure 7.

TELEFUNKEN Semiconductors 41 Rev. A3, 20-Jun-97 U4224B

Q2A, Q2B An additional improvement of the driving capability may be achieved by using a CMOS driver circuit or an NPN According to Q1A/Q1B, a crystal is connected between transistor with pull-up resistor connected to the collector the Pins Q2A and Q2B. It is used with the serial resonant (see figure 14). When using a CMOS driver, this circuit frequency of the time-code transmitter (e.g., 60 kHz must be connected to VCC. WWVB, 77.5 kHz DCF or 40 kHz JG2AS). The equi- VCC valent parallel capacitor of the filter crystal is internally compensated. The value of the compensation is about 10 kW 0.7 pF. 100 kW TCO Pin16 TCO Q2A Q2B 94 8395 e Figure 14.

94 8383 GND

Figure 11. Please note: The signals and voltages at the Pins REC, INT, FLA, PON FLB, Q1A, Q1B, Q2A and Q2B cannot be measured by standard measurement equipment due to very high inter- If PON is connected to GND, the receiver will be nal impedances. For the same reason, the PCB should be activated. The set-up time is typically 0.5 s after applying protected against surface humidity. GND at this pin. If PON is connected to VCC, the receiver Design Hints for the Ferrite Antenna will switch to power-down mode. The bar antenna is a very critical device of the complete VCC clock receiver. Observing some basic RF design rules helps to avoid possible problems. The IC requires a resonant resistance of 50 kW to 200 kW. This can be achieved by a variation of the L/C-relation in the antenna circuit. PON It is not easy to measure such high resistances in the RF region. A more convenient way is to distinguish between 94 8373 the different bandwidths of the antenna circuit and to calculate the resonant resistance afterwards. Figure 12. Thus, the first step in designing the antenna circuit is to TCO measure the bandwidth. Figure 16 shows an example for the test circuit. The RF signal is coupled into the bar The digitized serial signal of the time-code transmitter antenna by inductive means, e.g., a wire loop. It can be can be directly decoded by a microcomputer. Details measured by a simple oscilloscope using the 10:1 probe. about the time-code format of several transmitters are The input capacitance of the probe, typically about 10 pF, described separately. should be taken into consideration. By varying the frequency of the signal generator, the resonant frequency The output consists of a PNP-NPN push-pull-stage. It can be determined. should be taken into account that in power-down mode (PON = high), TCO will be high.

VCC RF signal Scope generator 77.5 kHz PON

TCO Probe 10 : 1 w10 MW C 94 8380 GND wire loop res 94 7907 e

Figure 13. Figure 15.

42 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4224B

At the point where the voltage of the RF signal at the circuit is low compared to the temperature variation of the probe drops by 3 dB, the two frequencies can then be resonant frequency. Of course, the Q value can also be re- measured. The difference between these two frequencies duced by a parallel resistor. is called the bandwidth BWA of the antenna circuit. As the value of the capacitor Cres in the antenna circuit is known, Temperature compensation of the resonant frequency is it is easy to compute the resonant resistance according to a must if the clock is used at different temperatures. the following formula: Please ask your supplier of bar antenna material and of capacitors for specified values of the temperature + 1 coefficient. Rres p 2 BWA Cres Furthermore, some critical parasitics have to be consid- where ered. These are shortened loops (e.g., in the ground line Rres is the resonant resistance, of the PCB board) close to the antenna and undesired BWA is the measured bandwidth (in Hz) loops in the antenna circuit. Shortened loops decrease the Cres is the value of the capacitor in the antenna circuit Q value of the circuit. They have the same effect like con- (in Farad). ducting plates close to the antenna. To avoid undesired If high inductance values and low capacitor values are loops in the antenna circuit, it is recommended to mount used, the additional parasitic capacitances of the coil the capacitor Cres as close as possible to the antenna coil (v20 pF) must be considered. The Q value of the or to use a twisted wire for the antenna-coil connection. capacitor should be no problem if a high Q type is used. This twisted line is also necessary to reduce feedback of The Q value of the coil differs more or less from the DC noise from the microprocessor to the IC input. Long resistance of the wire. Skin effects can be observed but do connection lines must be shielded. not dominate. A final adjustment of the time-code receiver can be Therefore, it should not be a problem to achieve the carried out by pushing the coil along the bar antenna. The recommended values of the resonant resistance. The use maximum of the integrator output voltage VINT at of thicker wire increases the Q value and accordingly Pin INT indicates the resonant point. But attention: The reduces bandwidth. This is advantageous in order to load current should not exceed 1 nA, that means an input improve reception in noisy areas. On the other hand, resistance w 1 GW of the measuring device is required. temperature compensation of the resonant frequency Therefore, a special DVM or an isolation amplifier is might become a problem if the bandwidth of the antenna necessary.

Absolute Maximum Ratings

Parameters Symbol Value Unit Supply voltage VCC 5.25 V Ambient temperature range Tamb –25 to +75 _C Storage temperature range Rstg –40 to +85 _C Junction temperature Tj 125 _C Electrostatic handling ± VESD 2000 V (MIL Standard 883 D), except Pins 5, 6, 13 and 14

Thermal Resistance

Parameters Symbol Value Unit Thermal resistance RthJA 70 K/W

TELEFUNKEN Semiconductors 43 Rev. A3, 20-Jun-97 U4224B

Electrical Characteristics

VCC = 3 V, reference point Pin 3, input signal frequency 80 kHz, Tamb = 25_C, unless otherwise specified Parameters Test Conditions / Pin Symbol Min. Typ. Max. Unit Supply voltage range Pin 1 VCC 1.2 5.25 V Supply current Pin 1 ICC Without reception signal 30 mA with reception signal = 200 mV 15 25 mA OFF mode 0.1 mA Set-up time after VCC ON VCC = 1.5 V t 2 s AGC amplifier input; IN Pin 2 Reception frequency range fin 40 80 kHz Minimum input voltage Rres = 100 kW, Qres > 30 Vin 1 1.5 mV Maximum input voltage Vin 40 80 mV Input capacitance to ground Cin 1.5 pF Timing code output; TCO Pin 16 Output voltage HIGH RLOAD = 870 kW to GND VOH VCC-0.4 V LOW RLOAD = 650 kW to VCC VOL 0.4 V Output current HIGH VTCO = VCC/2 ISOURCE 3 10 mA LOW VTCO = VCC/2 ISINK 4 12 mA Decoding characteristics DCF77 based on the values of the application circuit fig. 17 TCO pulse width 100 ms t100 60 90 130 ms TCO pulse width 200 ms t200 160 190 230 ms

Delay compared with the transient of the RF signal:

drop down (start transition) ts 30 60 ms rise for 100 ms pulse te1 25 55 ms (end transition) rise for 200 ms pulse te2 10 30 ms (end transition) Decoding characteristics WWVB based on the values of the application circuit fig. 18 TCO pulse width 200 ms t200 140 200 ms TCO pulse width 500 ms t500 440 500 ms TCO pulse width 800 ms t800 740 800 ms

Delay compared with the transient of the RF signal:

drop down (start transition) ts 45 80 ms rise (end transition) te 20 45 ms

44 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4224B

Parameters Test Conditions / Pin Symbol Min. Typ. Max. Unit Decoding characteristics JG2AS based on the values of the application circuit fig. 19: TCO pulse width 200 ms t200 240 410 ms TCO pulse width 500 ms t500 420 490 ms TCO pulse width 800 ms t800 720 790 ms

Delay compared with the transient of the RF signal:

start transition (RF on) ts 10 110 ms end transition (RF off) te 30 220 ms Power-ON/OFF control; PON Pin 15 Input voltage Required IIN y 0.5 mA HIGH VCC-0.2 V LOW VCC-1.2 V Input current VCC = 3V IIN 1.4 1.7 2 mA VCC = 1.5 V 0.7 mA VCC = 5 V 3 mA Set-up time after PON t 0.5 2 s AGC hold mode; SL Pin 12 Input voltage Required IIN y 0.5 mA HIGH VCC-0.2 V LOW VCC-1.2 V Input current Vin = VCC 0.1 mA Vin = GND 2.5 mA Rejection of interference ȧfd – fudȧ = 625 Hz signals Vd = 3 mV, f d = 77.5 kHz using 2 crystal filters af 43 dB using 1 crystal filter af 22 dB

TELEFUNKEN Semiconductors 45 Rev. A3, 20-Jun-97 U4224B

Test Circuit (for Fundamental Function)

Test point: DVM with high and low input Vd Ipon line for measuring of a voltage Vxx or a current lxx by conversion into a voltage. 1.657V 300k

Stco Spon 1M 82p 1M Vtco Isl

TCO PON Q2B Q2A Ssl

U4224B SL 10M Ivcc 100k Sdec

VCC STABILISATION DECODING FLB Iin Idec FLA AGC- 100M 1M AMPLIFIER RECTIFIER IN DEC Vdec

GND SB Q1A Q1B REC INT V CC ~ 3 V 82p 680p 3.3 n 420k Vin Vrec Srec Ssb Sint

Vsb 10M 10M 1M Vint

Vrec Vint Isb Irec Iint 94 8384 e

Figure 16.

46 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4224B

Application Circuit for DCF 77.5 kHz Control lines + VCC

Ferrite Antenna 1 16 f = 77.5 kHz res TCO 2 15 PON 3) Microcomputer 3 14 77.5 kHz SL 1) 4 13 Keyboard U4224B 5 12 77.5 kHz 2) Display 6 11 C3 10 10 nF C 7 1 1) If SL is not used, SL is connected to VCC 2) 77.5-kHz crystal can be replaced by 10 pF 6.8 nF 8 9 C 2 3) If IC is activated, PON is connected to GND 33 nF

94 8279 e Figure 17.

Application Circuit for WWVB 60 kHz Control lines + VCC

Ferrite Antenna 1 16 f = 60 kHz res TCO 2 15 PON 3) Microcomputer 3 14 RSB 60 kHz SL 1) 4 13 Keyboard 10 kW U4224B 5 12 60 kHz 2) Display 6 11 C3 10 10 nF C 7 1 1) If SL is not used, SL is connected to VCC 2) 15 nF 8 9 60-kHz crystal can be replaced by 10 pF C2 3) If IC is activated, PON is connected to GND 47 nF

94 8278 e Figure 18.

TELEFUNKEN Semiconductors 47 Rev. A3, 20-Jun-97 U4224B

Application Circuit for JG2AS 40 kHz Control lines + VCC

Ferrite Antenna 1 16 f = 40 kHz res TCO 2 15 PON 3) Microcomputer 3 14 40 kHz SL 1) 4 13 Keyboard U4224B 5 12 40 kHz 2) Display 6 11 C3 10 nF C1 7 10 1) C If SL is not used, SL is connected to VCC 680 pF 2 1 MW 2) 8 9 40-kHz crystal can be replaced by 22 pF R 3) If IC is activated, PON is connected to GND 220 nF

94 7724 e

Figure 19.

48 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4224B

Information on the German Transmitter

Station: DCF 77, Location: Mainflingen/Germany, Frequency 77.5 kHz, Geographical coordinates: 50__ 0.1’N, 09__ 00’E Transmitting power 50 kW Time of transmission: permanent

coding minutes hourscalendar day month year when day of required the week 93 7527 Example:19.35 h s 124810 20 40 P1 1 2 4 81020P2

seconds 20 21 22 23 24 25 26 27 2829 30 31 32 33 34 35 minutes hours Start Bit Parity Bit P1 Parity Bit P2

Figure 20.

Modulation second to indicate the switch over to the next 1-minute time frame. A time frame contains BCD-coded The carrier amplitude is reduced to 25% at the beginning information of minutes, hours, calendar day, day of the of each second for a period of 100 ms (binary zero) or week, month and year between the 20th second and 58th 200 ms (binary one), except the 59th second. second of the time frame, including the start bit S (200 ms) and parity bits P1, P2 and P3. Furthermore, there are 5 additional bits R (transmission by reserve antenna), Time-Code Format (based on A1 (announcement of change-over to summer time), Z1 (during summer time 200 ms, otherwise 100 ms), Z2 Information of Deutsche Bundespost) (during standard time 200 ms, otherwise 100 ms) and A2 The time-code format consists of 1-minute time frames. (announcement of leap second) transmitted between the There is no modulation at the beginning of the 59th 15th second and 19th second of the time frame.

TELEFUNKEN Semiconductors 49 Rev. A3, 20-Jun-97 U4224B

Information on the British Transmitter

Station: MSF Geographical coordinates: 52__ 22’N, 01_ 11’W Frequency 60 kHz Time of transmission: permanent, except the first Transmitting power 50 kW Tuesday of each month from 10.00 h to 14.00 h. Location: Teddington, Middlesex

Time frame 1 minute Time frame ( index count 1 second) 0510 15 20 25 3035 40 45 50 55 0510 4 1 4 2 2 8 2 8 4 2 1 8 4 2 1 8 4 2 8 4 1 0 0 1 1 40 20 80 20 10 10 20 10 10 40 20 10

year month day of hour minute minute month day Switch over to of identifier the next time frame week Parity BST hour + minute check day of week bits day + month year 1 BST 7 GMT change 0 impending

500 ms 500 ms

93 7528 Example: 80 40 20 10 8 42110 8 4 2 1 March 1993

seconds 17 18 19 20 21 22 23 24 25 26 27 28 29 30 year month

Figure 21.

Modulation Time-Code Format The carrier amplitude is switched off at the beginning of The time-code format consists of 1-minute time frames. each second for a period of 100 ms (binary zero) or A time frame contains BCD-coded information of year, 200 ms (binary one). month, calendar day, day of the week, hours and minutes. At the switch-over to the next time frame, the carrier amplitude is reduced for a period of 500 ms. The prescence of the fast code during the first 500 ms at the beginning of the minute in not guaranteed. The transmission rate is 100 bits/s and the code contains information of hour, minute, day and month.

50 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4224B

Information on the US Transmitter

Station: WWVB Location: Fort Collins Frequency 60 kHz Geographical coordinates: 40__ 40’N, 105__ 03’W Transmitting power 10 kW Time of transmission: permanent

daylight savings time bits leap second warning bit minutes hours days UTI UTI year sign correction leap year indicator bit “0” = non leap year “1” = leap year

93 7529 e Example: UTC 18.42 h Time frame

P0 40 20 10 8421P1 20 10 8 4 2 1 P2

seconds 012354678910 11 12 13 14 15 16 17 18 19 20 minutes hours Frame-reference marker

Figure 22.

Modulation Time-Code Format The time-code format consists of 1-minute time frames. The carrier amplitude is reduced by 10 dB at the A time frame contains BCD1–coded information of beginning of each second and is restored within 500 ms minutes, hours, days and year. In addition, there are (binary one) or within 200 ms (binary zero). 6 position-identifier markers (P0 thru P5) and 1 frame-reference marker with reduced carrier amplitude of 800 ms duration.

TELEFUNKEN Semiconductors 51 Rev. A3, 20-Jun-97 U4224B

Time frame 1 minute (index count 1 second) Time frame 0 5 1015 2025 3035 40 45 50 55 0 5 10 4 1 2 1 2 8 4 8 4 4 2 1 8 2 1 8 10 40 20 P1 20 10 P2 80 40 20 10 P3 P4 P5 P0 PO SUB FRM ADD ADD 10 0 200

minutes hours days code dut1 Example: 18.42 h Time frame P0 40 20 10 8 4 2 1P1 20 10 8 4 21P2

seconds 59 0 1234 5 6 7 8 9 1011121314151617181920 minutes hours Frame-reference marker (FRM) Position-identifier marker P0 Position identifier marker P1

0.5 second: Binary one 0.8 second: Binary zero 0.2 second: Identifier markers P0...P5 0.8 s 0.2 s 0.5 s 93 7508 e “1” “0” “P”

Figure 23.

Modulation Time-Code Format The time-code format consists of 1-minute time frames. The carrier amplitude is 100% at the beginning of each A time frame contains BCD-coded information of second and is switched off after 500 ms (binary one) or minutes, hours and days. In addition, there are after 800 ms (binary zero). 6 position-identifier markers (P0 thru P5) and 1 frame- reference marker (FRM) with reduced carrier amplitude of 800 ms duration.

Ordering and Package Information Extended Type Number Package Remarks U4224B-CFL SO16L plastic U4224B-CFLG3 SO16L plastic Taping according to IEC–286–3

52 TELEFUNKEN Semiconductors Rev. A3, 20-Jun-97 U4224B

Package Information Package SO16L Dimensions in mm 10.5 9.25 10.1 8.75

2.45 2.70 2.25 0.3 2.45 0.2

0.25 0.49 0.10 7.5 7.3 0.35 1.27 10.56 8.89 10.15

technical drawings according to DIN specifications

1 95 11493

TELEFUNKEN Semiconductors 53 Rev. A3, 20-Jun-97 U4226B Time-Code Receiver with TC Output

Description

The U4226B is a bipolar integrated straight-through receiver circuit in the frequency range of 40 to 80 kHz. The device is designed for radio-controlled clock applications.

Features D Very low power consumption D Only a few external components necessary

D Very high sensitivity D Digitalized serial output signal D High selectivity by using two crystal filters D AGC hold mode D Power-down mode available

Block Diagram

PON TCO 93 7727 e 15 16 GND 3 11 FLB Power supply Decoder VCC 1 10 FLA

9 DEC

AGC Rectifier & 12 SL amplifier integrator IN 2 4561314 7 8 SB Q1A Q1B Q2A Q2B REC INT

Figure 1.

TELEFUNKEN Semiconductors 55 Rev. A2, 20-Jun-97 U4226B

Pin Description Pin Symbol Function 1 VCC Supply voltage 2 IN Amplifier – Input VCC 1 20 NC 3 GND Ground IN 2 19 NC 4 SB Bandwidth control

GND 3 18 NC 5 Q1A Crystal filter 1 6 Q1B Crystal filter 1 SB 4 17 NC 7 REC Rectifier output Q1A 5 16 TCO 8 INT Integrator output U4226B 9 DEC Decoder input Q1B 6 15 PON 10 FLA Lowpass filter REC 7 14 Q2B 11 FLB Lowpass filter 12 SL AGC hold mode INT 8 13 Q2A 13 Q2A Crystal filter 2 DEC 9 12 SL 14 Q2B Crystal filter 2 FLA 10 11 FLB 15 PON Power ON/OFF control 16 TCO Time code output 94 10467 17 NC Not connected 18 NC Not connected Figure 2. Pinning 19 NC Not connected 20 NC Not connected

IN SB A ferrite antenna is connected between IN and VCC. For A resistor R is connected between SB and GND. It con- high sensitivity, the Q factor of the antenna circuit should SB trols the bandwidth of the crystal filters. It is be as high as possible. Please note that a high Q factor recommended: R = 0 W for DCF 77.5 kHz, R = requires temperature compensation of the resonant SB SB 10 kW for 60 kHz WWVB and R = open for JG2AS frequency in most cases. We recommend a Q factor SB 40 kHz. between 50 and 100. Specifications are valid for Q > 30. An optimal signal-to-noise ratio will be achieved by a resonant resistance of 50 to 200 kW. 94 8381 VCC

SB IN

GND

94 8379

Figure 3. Figure 4.

56 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-97 U4226B

Q1A, Q1B SL

In order to achieve a high selectivity, a crystal is con- AGC hold mode: SL high (VSL = VCC) sets normal func- nected between the Pins Q1A and Q1B. It is used with the tion, SL low (VSL = 0) disconnects the rectifier and holds serial resonant frequency of the time-code transmitter the voltage VINT at the integrator output and also the AGC (e.g., 60 kHz WWVB, 77.5 kHz DCF or 40 kHz JG2AS). amplifier gain. The equivalent parallel capacitor of the filter crystal is internally compensated. The compensated value is about VCC 0.7 pF. If full sensitivity and selectivity are not needed, the crystal filter can be substituted by a capacitor of 10 pF for DCF and WWVB and 22 pF for JG2AS. SL

94 8378

Q1A Q1B Figure 8.

GND 94 8382 INT Figure 5. Integrator output: The voltage VINT is the control voltage for the AGC. The capacitor C2 between INT and DEC REC defines the time constant of the integrator. The current through the capacitor is the input signal of the decoder. Rectifier output and integrator input: The capacitor C1 between REC and INT is the lowpass filter of the rectifier and at the same time a damping element of the gain 94 8375 control.

94 8374 INT

REC GND

GND Figure 9.

Figure 6. DEC FLA, FLB Lowpass filter: A capacitor C connected between FLA Decoder input: Senses the current through the integration 3 and FLB suppresses higher frequencies at the trigger capacitor C . The dynamic input resistance has a value of 2 circuit of the decoder. about 420 kW and is low compared to the impedance of C2.

DEC FLB FLB

GND 94 8376 94 8377

Figure 7. Figure 10.

TELEFUNKEN Semiconductors 57 Rev. A2, 20-Jun-97 U4226B

Q2A, Q2B An additional improvement of the driving capability may be achieved by using a CMOS driver circuit or an NPN According to Q1A/Q1B, a crystal is connected between transistor with pull-up resistor connected to the collector the Pins Q2A and Q2B. It is used with the serial resonant (see figure 14). When using a CMOS driver, this circuit frequency of the time-code transmitter (e.g., 60 kHz must be connected to VCC. WWVB, 77.5 kHz DCF or 40 kHz JG2AS). The equivalent parallel capacitor of the filter crystal is internally VCC compensated. The value of the compensation is about 0.7 pF. 10 kW 100 kW TCO Pin16 Q2A Q2B TCO 94 8395 e

Figure 14. 94 8383 GND Please note: Figure 11. The signals and voltages at the Pins REC, INT, FLA, FLB, Q1A, Q1B, Q2A and Q2B cannot be measured by PON standard measurement equipment due to very high inter- If PON is connected to GND, the receiver will be nal impedances. For the same reason, the PCB should be activated. The set-up time is typically 0.5 s after applying protected against surface humidity. GND at this pin. If PON is connected to VCC, the receiver Design Hints for the Ferrite Antenna will switch to power-down mode. The bar antenna is a very critical device of the complete VCC clock receiver. Observing some basic RF design rules helps to avoid possible problems. The IC requires a resonant resistance of 50 kW to 200 kW. This can be achieved by a variation of the L/C-relation in the antenna circuit. PON It is not easy to measure such high resistances in the RF region. A more convenient way is to distinguish between 94 8373 the different bandwidths of the antenna circuit and to Figure 12. calculate the resonant resistance afterwards. Thus, the first step in designing the antenna circuit is to TCO measure the bandwidth. Figure 16 shows an example for The digitized serial signal of the time-code transmitter the test circuit. The RF signal is coupled into the bar can be directly decoded by a microcomputer. Details antenna by inductive means, e.g., a wire loop. It can be about the time-code format of several transmitters are measured by a simple oscilloscope using the 10:1 probe. described separately. The input capacitance of the probe, typically about 10 pF, should be taken into consideration. By varying the The output consists of a PNP-NPN push-pull-stage. It frequency of the signal generator, the resonant frequency should be taken into account that in power-down mode can be determined. (PON = high), TCO will be high. RF signal Scope VCC generator 77.5 kHz PON

Probe TCO 10 : 1 w10 MW C wire loop res 94 8380 GND 94 7907 e

Figure 13. Figure 15.

58 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-97 U4226B

At the point where the voltage of the RF signal at the circuit is low compared to the temperature variation of the probe drops by 3 dB, the two frequencies can then be resonant frequency. Of course, the Q value can also be re- measured. The difference between these two frequencies duced by a parallel resistor. is called the bandwidth BWA of the antenna circuit. As the value of the capacitor Cres in the antenna circuit is known, Temperature compensation of the resonant frequency is it is easy to compute the resonant resistance according to a must if the clock is used at different temperatures. the following formula: Please ask your supplier of bar antenna material and of capacitors for specified values of the temperature + 1 coefficient. Rres p 2 BWA Cres Furthermore, some critical parasitics have to be consid- where ered. These are shortened loops (e.g., in the ground line Rres is the resonant resistance, of the PCB board) close to the antenna and undesired BWA is the measured bandwidth (in Hz) loops in the antenna circuit. Shortened loops decrease the Cres is the value of the capacitor in the antenna circuit Q value of the circuit. They have the same effect like (in Farad). conducting plates close to the antenna. To avoid If high inductance values and low capacitor values are undesired loops in the antenna circuit, it is recommended used, the additional parasitic capacitances of the coil to mount the capacitor Cres as close as possible to the (v20 pF) must be considered. The Q value of the capaci- antenna coil or to use a twisted wire for the antenna-coil tor should be no problem if a high Q type is used. The connection. This twisted line is also necessary to reduce Q value of the coil differs more or less from the DC feedback of noise from the microprocessor to the IC resistance of the wire. Skin effects can be observed but do input. Long connection lines must be shielded. not dominate. A final adjustment of the time-code receiver can be Therefore, it should not be a problem to achieve the carried out by pushing the coil along the bar antenna. The recommended values of the resonant resistance. The use maximum of the integrator output voltage VINT at Pin of thicker wire increases the Q value and accordingly INT indicates the resonant point. But attention: The load reduces bandwidth. This is advantageous in order to current should not exceed 1 nA, that means an input improve reception in noisy areas. On the other hand, resistance w 1 GW of the measuring device is required. temperature compensation of the resonant frequency Therefore, a special DVM or an isolation amplifier is might become a problem if the bandwidth of the antenna necessary.

Absolute Maximum Ratings

Thermal Resistance

Parameters Symbol Value Unit Thermal resistance RthJA 70 K/W

TELEFUNKEN Semiconductors 59 Rev. A2, 20-Jun-97 U4226B

Electrical Characteristics

VCC = 3 V, reference point Pin 3, input signal frequency 80 kHz, Tamb = 25_C, unless otherwise specified Parameters Test Conditions / Pin Symbol Min. Typ. Max. Unit Supply voltage range Pin 1 VCC 1.2 5.25 V Supply current Without reception signal ICC 25 mA with reception signal = 200 mV 15 20 mA OFF mode pin 1 0.1 mA Set-up time after VCC ON VCC = 1.5 V t 2 s AGC amplifier input; IN Pin 2 Reception frequency range fin 40 80 kHz Minimum input voltage Rres = 100 kW, Qres > 30 Vin 1 1.5 mV Maximum input voltage Vin 40 80 mV Input capacitance to ground Cin 1.5 pF Timing code output; TCO Pin 16 Output voltage HIGH RLOAD = 870 kW to GND VOH VCC-0.4 V LOW RLOAD = 650 kW to VCC VOL 0.4 V Output current HIGH VTCO = VCC/2 ISOURCE 3 10 mA LOW VTCO = VCC/2 ISINK 4 12 mA Decoding characteristics DCF77 based on the values of the application circuit fig. 20: TCO pulse width 100 ms t100 60 90 130 ms TCO pulse width 200 ms t200 160 190 230 ms

Delay compared with the transient of the RF signal:

drop down (start transition) ts 30 60 ms rise for 100 ms pulse te1 25 55 ms (end transition) rise for 200 ms pulse te2 10 30 ms (end transition) Decoding characteristics WWVB based on the values of the application circuit fig. 21: TCO pulse width 200 ms t200 140 200 ms TCO pulse width 500 ms t500 440 500 ms TCO pulse width 800 ms t800 740 800 ms

Delay compared with the transient of the RF signal:

drop down (start transition) ts 45 80 ms rise (end transition) te 20 45 ms Decoding characteristics JG2AS based on the values of the application circuit fig. 22: TCO pulse width 200 ms TCO pulse width 500 ms t200 240 410 ms TCO pulse width 800 ms t500 420 490 ms t800 720 790 ms Delay compared with the transient of the RF signal:

start transition (RF on) end transition (RF off) ts 10 110 ms te 30 220 ms

60 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-97 U4226B

Parameters Test Conditions / Pin Symbol Min. Typ. Max. Unit Power-ON/OFF control; PON Pin 15 Input voltage HIGH Required IIN y 0.5 mA VCC-0.2 V LOW VCC-1.2 V Input current VCC = 3V IIN 1.4 1.7 2 mA VCC = 1.5 V 0.7 mA VCC = 5 V 3 mA Set-up time after PON t 0.5 2 s AGC hold mode; SL Pin 12 Input voltage HIGH Required IIN y 0.5 mA VCC-0.2 V LOW VCC-1.2 V Input current Vin = VCC 0.1 mA Vin = GND 2.5 mA Rejection of interference ȧfd – fudȧ = 625 Hz signals Vd = 3 mV, f d = 77.5 kHz using 2 crystal filters af 43 dB using 1 crystal filter af 22 dB Test Circuit (for Fundamental Function) Test point: DVM with high and low input Vd Ipon line for measuring of a voltage Vxx or a current lxx by conversion into a voltage. 1.657V 300k

Stco Spon 1M 82p 1M Vtco Isl

TCO PON Q2B Q2A Ssl

U4226B SL 10M Ivcc 100k Sdec

VCC STABILISATION DECODING FLB Iin Idec FLA AGC- 100M 1M AMPLIFIER RECTIFIER IN DEC Vdec

GND SB Q1A Q1B REC INT VCC 3 V ~ 82p 680p 3.3 n 420k Vin Vrec Srec Ssb Sint

Vsb 10M 10M 1M Vint

Vrec Vint Isb Irec Iint 94 8384 e

Figure 16.

TELEFUNKEN Semiconductors 61 Rev. A2, 20-Jun-97 U4226B

Figure 17 shows a typical diagram to control sensitivity 1.0 by measuring the voltage at INT vs. Vin. The input signal (e.g., generator frequency 77.5 KHz) is coupled to the in- 0.9 put of the circuit via a transformer with a 50–W termination. In order to avoid a load at the INT Pin, the voltage should be measured with a meter input resistance 0.8 > 1 GW! INT (1) normal curve ) V ( V 0.7 (2) no optimal layout conditions 2 0.6 1 0.5 –200 20406080100

95 11210 Vin ( dBmV ) Figure 17.

INT 50 –10 dB Generator VCC Rg Ra La signal Lb V Rb U4226B INT (e.g., 77.5 kHz) (Ri > GW)

IN 95 11209

Ra = Rb = 50W La = Lb = 88 m H

Figure 18.

Layout

95 10214 95 10214

Figure 19.

62 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-97 U4226B

Application Circuit for DCF 77.5 kHz

+ VCC Control lines

Ferrite Antenna 1 20 NC fres = 77.5 kHz

2 19 NC TCO

NC PON 3) 3 18 Microcomputer SL 1) 4 17 NC Keyboard

5 16 77.5 kHz 2) U4226B Display 6 15

C1 7 14 6.8 nF C 8 13 2 77.5 kHz 33 nF 9 12

1) C3 10 11 If SL is not used, SL is connected to VCC 10 nF 2) 77.5-kHz crystal can be replaced by 10 pF 3) 95 10469 If IC is activated, PON is connected to GND

Figure 20.

TELEFUNKEN Semiconductors 63 Rev. A2, 20-Jun-97 U4226B

Application Circuit for WWVB 60 kHz

+ VCC Control lines

Ferrite Antenna 1 20 NC fres = 60 kHz 2 19 NC TCO

NC PON 3) 3 18 Microcomputer SL 1) 4 17 NC 10 kW Keyboard 5 16 60 kHz 2) U4226B Display 6 15

C1 7 14 15 nF C 8 13 2 60 kHz 47 nF 9 12

1) C3 10 11 If SL is not used, SL is connected to VCC 10 nF 2) 60-kHz crystal can be replaced by 10 pF 3) 95 10470 If IC is activated, PON is connected to GND

Figure 21.

64 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-97 U4226B

Application Circuit for JG2AS 40 kHz

+ VCC Control lines

Ferrite Antenna 1 20 NC fres = 40 kHz 2 19 NC TCO

3 18 NC PON 3) Microcomputer SL 1) 4 17 NC Keyboard

5 16 40 kHz 2) U4226B Display 6 15 680 pF 7 14 C1 C2 1 MW 8 13 220 nF 40 kHz 9 12

1) C3 10 11 If SL is not used, SL is connected to VCC 2) 40-kHz crystal can be replaced by 22 pF 3) 95 10471 10 nF If IC is activated, PON is connected to GND

Figure 22.

TELEFUNKEN Semiconductors 65 Rev. A2, 20-Jun-97 U4226B

Information on the German Transmitter

Station: DCF 77, Location: Mainflingen/Germany, Frequency 77.5 kHz, Geographical coordinates: 50__ 0.1’N, 09__ 00’E Transmitting power 50 kW Time of transmission: permanent

coding minutes hourscalendar day month year when day of required the week 93 7527 Example:19.35 h s 124810 20 40 P1 1 2 4 81020P2 seconds 20 21 22 23 24 25 26 27 2829 30 31 32 33 34 35 minutes hours Start Bit Parity Bit P1 Parity Bit P2

Figure 23.

Modulation second to indicate the switch over to the next 1-minute time frame. A time frame contains BCD-coded The carrier amplitude is reduced to 25% at the beginning information of minutes, hours, calendar day, day of the of each second for a period of 100 ms (binary zero) or week, month and year between the 20th second and 58th 200 ms (binary one), except the 59th second. second of the time frame, including the start bit S (200 ms) and parity bits P1, P2 and P3. Furthermore, there are 5 additional bits R (transmission by reserve antenna), A1 Time-Code Format: (based on (announcement of change–over to summer time), Z1 (during summer time 200 ms, otherwise 100 ms), Z2 Information of Deutsche Bundespost) (during standard time 200 ms, otherwise 100 ms) and A2 The time-code format consists of 1-minute time frames. (announcement of leap second) transmitted between the There is no modulation at the beginning of the 59th 15th second and 19th second of the time frame.

66 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-97 U4226B

Information on the British Transmitter

Time frame 1 minute Time frame ( index count 1 second) 0510 15 20 25 3035 40 45 50 55 0510 4 1 4 2 2 8 2 8 4 2 1 8 4 2 1 8 4 2 8 4 1 0 0 1 1 40 20 80 20 10 10 20 10 10 40 20 10

year month day of hour minute minute month day Switch over to of identifier the next time frame week Parity BST hour + minute check day of week bits day + month year 1 BST 7 GMT change 0 impending

500 ms 500 ms

93 7528 Example: 80 40 20 10 8 42110 8 4 2 1 March 1993

seconds 17 18 19 20 21 22 23 24 25 26 27 28 29 30 year month

Figure 24.

Modulation Time-Code Format The carrier amplitude is switched off at the beginning of The time-code format consists of 1-minute time frames. each second for a period of 100 ms (binary zero) or A time frame contains BCD-coded information of year, 200 ms (binary one). month, calendar day, day of the week, hours and minutes. At the switch-over to the next time frame, the carrier amplitude is reduced for a period of 500 ms. The prescence of the fast code during the first 500 ms at the beginning of the minute in not guaranteed. The transmission rate is 100 bits/s and the code contains information of hour, minute, day and month.

TELEFUNKEN Semiconductors 67 Rev. A2, 20-Jun-97 U4226B

Information on the US Transmitter

Station: WWVB Location: Fort Collins Frequency 60 kHz Geographical coordinates: 40__ 40’N, 105__ 03’W Transmitting power 10 kW Time of transmission: permanent

daylight savings time bits leap second warning bit minutes hours days UTI UTI year sign correction leap year indicator bit “0” = non leap year “1” = leap year

93 7529 e Example: UTC 18.42 h Time frame

P0 40 20 10 8421P1 20 10 8 4 2 1 P2 seconds 012354678910 11 12 13 14 15 16 17 18 19 20 minutes hours Frame-reference marker

Figure 25.

Modulation Time-Code Format The time-code format consists of 1-minute time frames. The carrier amplitude is reduced by 10 dB at the begin- A time frame contains BCD-coded information of ning of each second and is restored within 500 ms (binary minutes, hours, days and year. In addition, there are one) or within 200 ms (binary zero). 6 position-identifier markers (P0 thru P5) and 1 frame-reference marker with reduced carrier amplitude of 800 ms duration.

68 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-97 U4226B

Time frame 1 minute (index count 1 second) Time frame 0 5 1015 2025 3035 40 45 50 55 0 5 10 4 1 2 1 2 8 4 8 4 4 2 1 8 2 1 8 10 40 20 P1 20 10 P2 80 40 20 10 P3 P4 P5 P0 PO SUB FRM ADD ADD 10 0 200

minutes hours days code dut1 Example: 18.42 h Time frame P0 40 20 10 8 4 2 1P1 20 10 8 4 21P2

seconds 59 0 1234 5 6 7 8 9 1011121314151617181920 minutes hours Frame-reference marker (FRM) Position-identifier marker P0 Position identifier marker P1

0.5 second: Binary one 0.8 second: Binary zero 0.2 second: Identifier markers P0...P5 0.8 s 0.2 s 0.5 s 93 7508 e “1” “0” “P”

Figure 26.

Modulation Time-Code Format The time-code format consists of 1-minute time frames. The carrier amplitude is 100% at the beginning of each A time frame contains BCD-coded information of second and is switched off after 500 ms (binary one) or minutes, hours and days. In addition, there are 6 position- after 800 ms (binary zero). identifier markers (P0 thru P5) and 1 frame-reference marker (FRM) with reduced carrier amplitude of 800 ms duration.

TELEFUNKEN Semiconductors 69 Rev. A2, 20-Jun-97 U4226B

Ordering and Package Information Extended Type Number Package Remarks U4226B-MFS SSO20 plastic U4226B-MFSG3 SSO20 plastic Taping according to IEC-286-3

Package Information

Package SSO20 5.7 Dimensions in mm 5.3 6.75 4.5 6.50 4.3

1.30 0.15 0.25 0.15 0.05 6.6 0.65 6.3 5.85

20 11

technical drawings according to DIN specifications 13007

110

70 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-97 T4225B Low-Cost Time-Code Receiver

Description

The T4225B is a bipolar integrated straight-through receiver circuit in the frequency range of 40 to 80 kHz. The device is designed for radio-controlled clock applications.

Features D Very low power consumption D Only a few external components necessary

D Very high sensitivity D Digitalized serial output signal D High selectivity by using two crystal filters D AGC hold mode D Power-down mode available

Block Diagram

PON TCO 95 10481

GND FLB Power supply Decoder VCC FLA

DEC

IN1 AGC Rectifier & SL amplifier integrator IN

SB Q1A Q1B Q2A Q2B REC INT

Figure 1.

TELEFUNKEN Semiconductors 71 Rev. A2, 20-Jun-96 T4225B

PAD Coordinates The T4225B is only available as die for “chip-on-board” mounting. DIE size: 2.26 x 1.54 mm PAD size: 100 x 100 mm (contact window 88 x 88 mm) Thickness: 300 mm " 20 mm Symbol Function x-axis/mm y-axis/mm IN1 Amplifier input (inverted) 128 846 IN Amplifier input (non inverted) 128 310 GND Ground 354 124 SB Bandwidth control 696 128 Q1A Crystal filter 1 1040 128 Q1B Crystal filter 1 1290 128 REC Rectifier output 1528 128 INT Integrator output 1766 128 DEC Decoder input 2044 268 FLA Lowpass filter 2044 676 FLB Lowpass filter 2044 1072 SL AGC hold mode 2044 1310 Q2A Crystal filter 2 1724 1324 Q2B Crystal filter 2 1402 1324 PON Power-ON/OFF control 918 1324 TCO Time-code output 460 1324 VCC Supply voltage 128 1246

The PAD coordinates are referred to the left bottom point of the contact window.

PAD Layout

TCO PON Q2B Q2A SL VCC

FLB

IN1 FLA T4225B

IN DEC

GND SB Q1A Q1B REC INT y – axis

x – axis 95 10386 Reference point (%)

Figure 2.

72 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-96 T4225B

IN REC A ferrite antenna is connected between IN and VCC. For Rectifier output and integrator input: The capacitor C1 high sensitivity, the Q factor of the antenna circuit should between REC and INT is the lowpass filter of the rectifier be as high as possible. Please note that a high Q factor and at the same time a damping element of the gain requires temperature compensation of the resonant control. frequency in most cases. We recommend a Q factor between 50 and 100. Specifications are valid for Q > 30. 94 8374 An optimal signal-to-noise ratio will be achieved by a resonant resistance of 50 to 200 kW. VCC REC

IN GND

Figure 6.

94 8379 Figure 3. DEC

SB Decoder input: Senses the current through the integration A resistor RSB is connected between SB and GND. It con- capacitor C2. The dynamic input resistance has a value of trols the bandwidth of the crystal filters. It is recom- about 420 kW and is low compared to the impedance of mended: R = 0 W for DCF 77.5 kHz, R = 10 kW for SB SB C2. 60 kHz WWVB and RSB = open for JG2AS 40 kHz. 94 8381

DEC SB

GND GND 94 8376

Figure 4. Figure 7. Q1A, Q1B In order to achieve a high selectivity, a crystal is connected between the Pins Q1A and Q1B. It is used with the SL serial resonant frequency of the time-code transmitter (e.g., 60 kHz WWVB, 77.5 kHz DCF or 40 kHz JG2AS). AGC hold mode: SL high (VSL = VCC) sets normal The equivalent parallel capacitor of the filter crystal is function, SL low (VSL = 0) disconnects the rectifier and internally compensated. The compensated value is about holds the voltage VINT at the integrator output and also 0.7 pF. If full sensitivity and selectivity are not needed, the AGC amplifier gain. the crystal filter can be substituted by a capacitor of 10 pF for DCF and WWVB and 22 pF for JG2AS. VCC

SL Q1A Q1B 94 8378

GND Figure 8. 94 8382

Figure 5.

TELEFUNKEN Semiconductors 73 Rev. A2, 20-Jun-96 T4225B

INT PON

Integrator output: The voltage VINT is the control voltage If PON is connected to GND, the receiver will be for the AGC. The capacitor C2 between INT and DEC activated. The set-up time is typically 0.5 s after applying defines the time constant of the integrator. The current GND at this pin. If PON is connected to VCC, the receiver through the capacitor is the input signal of the decoder. will switch to power-down mode. 94 8375 VCC

INT PON

GND 94 8373 Figure 12. Figure 9.

TCO FLA, FLB The digitized serial signal of the time-code transmitter Lowpass filter: A capacitor C3 connected between FLA can be directly decoded by a microcomputer. Details and FLB suppresses higher frequencies at the trigger about the time-code format of several transmitters are circuit of the decoder. described separately. The output consists of a PNP-NPN push-pull-stage. It should be taken into account that in power-down mode (PON = high), TCO will be high. FLB FLB VCC

PON

94 8377 TCO Figure 10.

94 8380 GND Q2A, Q2B Figure 13. According to Q1A/Q1B, a crystal is connected between the Pins Q2A and Q2B. It is used with the serial resonant An additional improvement of the driving capability may frequency of the time-code transmitter (e.g., 60 kHz be achieved by using a CMOS driver circuit or an NPN WWVB, 77.5 kHz DCF or 40 kHz JG2AS). The equi- transistor with pull-up resistor connected to the collector valent parallel capacitor of the filter crystal is internally (see figure 14). When using a CMOS driver, this circuit compensated. The value of the compensation is about must be connected to VCC. 0.7 pF. VCC

10 kW 100 kW Q2A Q2B TCO Pin16 TCO 94 8383 GND 94 8395 e

Figure 11. Figure 14.

74 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-96 T4225B

Please note: If high inductance values and low capacitor values are The signals and voltages at the Pins REC, INT, FLA, used, the additional parasitic capacitances of the coil FLB, Q1A, Q1B, Q2A and Q2B cannot be measured by (v20 pF) must be considered. The Q value of the capaci- standard measurement equipment due to very high inter- tor should be no problem if a high Q type is used. The nal impedances. For the same reason, the PCB should be Q value of the coil differs more or less from the DC protected against surface humidity. resistance of the wire. Skin effects can be observed but do Design Hints for the Ferrite Antenna not dominate. The bar antenna is a very critical device of the complete Therefore, it should not be a problem to achieve the clock receiver. Observing some basic RF design rules recommended values of the resonant resistance. The use helps to avoid possible problems. The IC requires a reso- of thicker wire increases the Q value and accordingly nant resistance of 50 kW to 200 kW. This can be achieved reduces bandwidth. This is advantageous in order to by a variation of the L/C-relation in the antenna circuit. improve reception in noisy areas. On the other hand, It is not easy to measure such high resistances in the RF temperature compensation of the resonant frequency region. A more convenient way is to distinguish between might become a problem if the bandwidth of the antenna the different bandwidths of the antenna circuit and to cal- circuit is low compared to the temperature variation of the culate the resonant resistance afterwards. resonant frequency. Of course, the Q value can also be reduced by a parallel resistor. Thus, the first step in designing the antenna circuit is to measure the bandwidth. Figure 16 shows an example for Temperature compensation of the resonant frequency is the test circuit. The RF signal is coupled into the bar a must if the clock is used at different temperatures. antenna by inductive means, e.g., a wire loop. It can be Please ask your supplier of bar antenna material and of measured by a simple oscilloscope using the 10:1 probe. capacitors for specified values of the temperature The input capacitance of the probe, typically about 10 pF, coefficient. should be taken into consideration. By varying the Furthermore, some critical parasitics have to be frequency of the signal generator, the resonant frequency considered. These are shortened loops (e.g., in the ground can be determined. line of the PCB board) close to the antenna and undesired loops in the antenna circuit. Shortened loops decrease the RF signal Scope generator Q value of the circuit. They have the same effect like 77.5 kHz conducting plates close to the antenna. To avoid undesired loops in the antenna circuit, it is recommended Probe to mount the capacitor Cres as close as possible to the 10 : 1 antenna coil or to use a twisted wire for the antenna-coil w W 10 M connection. This twisted line is also necessary to reduce C wire loop res feedback of noise from the microprocessor to the IC 94 7907 e input. Long connection lines must be shielded. Figure 15. A final adjustment of the time-code receiver can be At the point where the voltage of the RF signal at the carried out by pushing the coil along the bar antenna. The probe drops by 3 dB, the two frequencies can then be maximum of the integrator output voltage VINT at Pin measured. The difference between these two frequencies INT indicates the resonant point. But attention: The load is called the bandwidth BWA of the antenna circuit. As the current should not exceed 1 nA, that means an input value of the capacitor Cres in the antenna circuit is known, resistance w 1 GW of the measuring device is required. it is easy to compute the resonant resistance according to Therefore, a special DVM or an isolation amplifier is the following formula: necessary. + 1 Rres p 2 BWA Cres where Rres is the resonant resistance, BWA is the measured bandwidth (in Hz) Cres is the value of the capacitor in the antenna circuit (in Farad).

TELEFUNKEN Semiconductors 75 Rev. A2, 20-Jun-96 T4225B

Absolute Maximum Ratings

Parameters Symbol Value Unit Supply voltage VCC 5.25 V Ambient temperature range Tamb –25 to +75 _C Storage temperature range Rstg –40 to +85 _C Junction temperature Tj 125 _C Electrostatic handling (MIL Standard 883 D), ± VESD 2000 V except Pad Q1A, Q1B, Q2A, Q2B

Electrical Characteristics

VCC = 3 V, reference point Pin 3, input signal frequency 80 kHz, Tamb = 25_C, unless otherwise specified Parameters Test Conditions / Pin Symbol Min. Typ. Max. Unit Supply voltage range Pad VCC VCC 1.2 5.25 V Supply current Pad VCC ICC Without reception signal 25 mA with reception signal = 200 mV 15 20 mA OFF mode 0.1 mA Set-up time after VCC ON VCC = 1.5 V t 2 s AGC amplifier input; IN Pad IN Reception frequency range fin 40 80 kHz Minimum input voltage Rres = 100 kW, Qres > 30 Vin 1 1.5 mV Maximum input voltage Vin 40 80 mV Input capacitance to ground Cin 1.5 pF Timing code output; TCO Pad TCO Output voltage HIGH RLOAD = 870 kW to GND VOH VCC-0.4 V LOW RLOAD = 650 kW to VCC VOL 0.4 V Output current HIGH VTCO = VCC/2 ISOURCE 3 10 mA LOW VTCO = VCC/2 ISINK 4 12 mA Decoding characteristics DCF77 based on the values of the application circuit fig. 20:

TCO pulse width 100 ms t100 60 90 130 ms TCO pulse width 200 ms t200 160 190 230 ms

Delay compared with the transient of the RF signal:

drop down (start transition) ts 30 60 ms rise for 100 ms pulse te1 25 55 ms (end transition) rise for 200 ms pulse te2 10 30 ms (end transition)

76 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-96 T4225B

Parameters Test Conditions / Pin Symbol Min. Typ. Max. Unit Decoding characteristics WWVBbased on the values of the application circuit fig. 21:

TCO pulse width 200 ms t200 140 200 ms TCO pulse width 500 ms t500 440 500 ms TCO pulse width 800 ms t800 740 800 ms

Delay compared with the transient of the RF signal:

drop down (start transition) ts 45 80 ms rise (end transition) te 20 45 ms JG2AS based on the values of the application circuit fig. 22:

TCO pulse width 200 ms t200 240 410 ms TCO pulse width 500 ms t500 420 490 ms TCO pulse width 800 ms t800 720 790 ms

Delay compared with the transient of the RF signal:

start transition (RF on) ts 10 110 ms end transition (RF off) te 30 220 ms Power- ON/OFF control; PON Pad PON Input voltage Required IIN y 0.5 mA HIGH VCC-0.2 V LOW VCC-1.2 V Input current VCC = 3 V IIN 1.4 1.7 2 mA VCC = 1.5 V 0.7 mA VCC = 5 V 3 mA Set-up time after PON t 0.5 2 s AGC hold mode; SL Pad SL Input voltage Required IIN y 0.5 mA HIGH VCC-0.2 V LOW VCC-1.2 V Input current Vin = VCC 0.1 mA Vin = GND 2.5 mA Rejection of interference ȧfd – fudȧ = 625 Hz signals Vd = 3 mV, f d = 77.5 kHz using 2 crystal filters af 43 dB using 1 crystal filter af 22 dB

TELEFUNKEN Semiconductors 77 Rev. A2, 20-Jun-96 T4225B

Test Circuit (for Fundamental Function)

Test point: DVM with high and low input Vd Ipon line for measuring of a voltage Vxx or a current lxx by conversion into a voltage. 1.657V 300k

Stco Spon 1M 82p 1M Vtco Isl

TCO PON Q2B Q2A Ssl

T4225B SL 10M Ivcc 100k Sdec

VCC STABILISATION DECODING FLB Iin Idec IN1 FLA AGC- 100M 1M AMPLIFIER RECTIFIER IN DEC Vdec

GND SB Q1A Q1B REC INT V CC ~ 3 V 82p 680p 3.3 n 420k Vin Vrec Srec Ssb Sint

Vsb 10M 10M 1M Vint

Vrec Vint Isb Irec Iint 95 10549

Figure 16.

78 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-96 T4225B

Figure 17 shows a typical diagram to control sensitivity 1.0 by measuring the voltage at INT vs. Vin. The input signal (e.g., generator frequency 77.5 kHz) is coupled to the input of the circuit via a transformer with a 50-W 0.9 termination. In order to avoid a load at the INT Pin, the voltage should be measured with a meter input resistance 0.8 > 1 GW! INT

(1) normal curve ) V ( V 0.7 (2) no optimal layout conditions 2 0.6 1 0.5 –200 20406080100

95 11210 Vin ( dBmV ) Figure 17.

VCC INT 50 –10 dB Generator Rg Ra La signal Lb Rb VINT IN1 T4225B (e.g., 77.5 kHz) (Ri > GW)

IN 95 11208 Ra = Rb = 50W La = Lb = 88 m H

Figure 18.

Layout

95 10212 95 11213

Figure 19.

TELEFUNKEN Semiconductors 79 Rev. A2, 20-Jun-96 T4225B

Application Circuit for DCF 77.5 kHz Control lines

+VCC

TCO PON 3) Microcomputer 1) 77.5 kHz SL

95 10385 Keyboard

VCC Display TCO PON Q2B Q2A SL C 3 IN1 FLB Ferrite Antenna T4225B 10 nF fres = 77.5 kHz FLA

IN DEC GND SB Q1A Q1B REC INT 1) If SL is not used, SL is connected to VCC 2) 77.5-kHz crystal can be replaced by 10 pF C C 1 2 3) If IC is activated, PON is connected to GND

77.5 kHz 2) 6.8 nF 33 nF Figure 20. Application Circuit for WWVB 60 kHz Control lines

+VCC

TCO PON 3) Microcomputer 1) 60 kHz SL

95 10384 Keyboard

VCC Display TCO PON Q2B Q2A SL C 3 IN1 FLB Ferrite Antenna T4225B 10 nF f res = 60 kHz FLA 1) If SL is not used, SL is IN DEC connected to VCC GND SB Q1A Q1B REC INT 2) 60-kHz crystal can be replaced by 10 pF 3) If IC is activated, PON is connected to GND C C 1 2 10 k

60 kHz 2) 15 nF 47 nF Figure 21.

80 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-96 T4225B

Application Circuit for JG2AS 40 kHz

Control lines

TCO PON 3) Microcomputer 1) 40 kHz SL

95 10383 Keyboard

VCC Display TCO PON Q2B Q2A SL C 3 IN1 FLB Ferrite 10 nF Antenna T4225B fres = 40 kHz FLA

IN DEC 1) If SL is not used, SL is GND SB Q1A Q1B REC INT connected to VCC 2) 40-kHz crystal can be replaced by 22 pF 3) If IC is activated, PON is connected to GND 1 M W C2

R 220 nF 40 kHz 2) C1 0.68 nF

Figure 22.

TELEFUNKEN Semiconductors 81 Rev. A2, 20-Jun-96 T4225B

Information on the German Transmitter

Station: DCF 77, Location: Mainflingen/Germany, Frequency 77.5 kHz, Geographical coordinates: 50__ 0.1’N, 09__ 00’E Transmitting power 50 kW Time of transmission: permanent

Figure 23.

Modulation second to indicate the switch over to the next 1-minute time frame. A time frame contains BCD-coded The carrier amplitude is reduced to 25% at the beginning information of minutes, hours, calendar day, day of the of each second for a period of 100 ms (binary zero) or week, month and year between the 20th second and 58th 200 ms (binary one), except the 59th second. second of the time frame, including the start bit S (200 ms) and parity bits P1, P2 and P3. Furthermore, there are 5 additional bits R (transmission by reserve antenna), A1 Time-Code Format: (based on (announcement of change-over to summer time), Z1 (during summer time 200 ms, otherwise 100 ms), Z2 Information of Deutsche Bundespost) (during standard time 200 ms, otherwise 100 ms) and A2 The time-code format consists of 1-minute time frames. (announcement of leap second) transmitted between the There is no modulation at the beginning of the 59th 15th second and 19th second of the time frame.

82 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-96 T4225B

Information on the British Transmitter

Time frame 1 minute Time frame ( index count 1 second) 0510 15 20 25 3035 40 45 50 55 0510 4 1 4 2 2 8 2 8 4 2 1 8 4 2 1 8 4 2 8 4 1 0 0 1 1 40 20 80 20 10 10 20 10 10 40 20 10

year month day of hour minute minute month day Switch over to of identifier the next time frame week Parity BST hour + minute check day of week bits day + month year 1 BST 7 GMT change 0 impending

500 ms 500 ms

93 7528 Example: 80 40 20 10 8 42110 8 4 2 1 March 1993

seconds 17 18 19 20 21 22 23 24 25 26 27 28 29 30 year month

Figure 24.

Modulation Time-Code Format The carrier amplitude is switched off at the beginning of The time-code format consists of 1-minute time frames. each second for a period of 100 ms (binary zero) or A time frame contains BCD-coded information of year, 200 ms (binary one). month, calendar day, day of the week, hours and minutes. At the switch-over to the next time frame, the carrier amplitude is reduced for a period of 500 ms. The prescence of the fast code during the first 500 ms at the beginning of the minute in not guaranteed. The transmission rate is 100 bits/s and the code contains information of hour, minute, day and month.

TELEFUNKEN Semiconductors 83 Rev. A2, 20-Jun-96 T4225B

Information on the US Transmitter

Station: WWVB Location: Fort Collins Frequency 60 kHz Geographical coordinates: 40__ 40’N, 105__ 03’W Transmitting power 10 kW Time of transmission: permanent

daylight savings time bits leap second warning bit minutes hours days UTI UTI year sign correction leap year indicator bit “0” = non leap year “1” = leap year

93 7529 e Example: UTC 18.42 h Time frame

P0 40 20 10 8421P1 20 10 8 4 2 1 P2 seconds 012354678910 11 12 13 14 15 16 17 18 19 20 minutes hours Frame-reference marker

Figure 25.

84 TELEFUNKEN Semiconductors Rev. A2, 20-Jun-96 T4225B

Time frame 1 minute (index count 1 second) Time frame 0 5 1015 2025 3035 40 45 50 55 0 5 10 4 1 2 1 2 8 4 8 4 4 2 1 8 2 1 8 10 40 20 P1 20 10 P2 80 40 20 10 P3 P4 P5 P0 PO SUB FRM ADD ADD 10 0 200

minutes hours days code dut1 Example: 18.42 h Time frame P0 40 20 10 8 4 2 1P1 20 10 8 4 21P2

seconds 59 0 1234 5 6 7 8 9 1011121314151617181920 minutes hours Frame-reference marker (FRM) Position-identifier marker P0 Position identifier marker P1

0.5 second: Binary one 0.8 second: Binary zero 0.2 second: Identifier markers P0...P5 0.8 s 0.2 s 0.5 s 93 7508 e “1” “0” “P”

Figure 26.

Modulation Time-Code Format The time-code format consists of 1-minute time frames. The carrier amplitude is 100% at the beginning of each A time frame contains BCD-coded information of second and is switched off after 500 ms (binary one) or minutes, hours and days. In addition, there are 6 position- after 800 ms (binary zero). identifier markers (P0 thru P5) and 1 frame-reference marker (FRM) with reduced carrier amplitude of 800 ms duration.

Ordering and Package Information Extended Type Number Package Remarks T4225B-MF No Die on foil T4225B-MC No Die in tray T4225B-MW No Wafer

TELEFUNKEN Semiconductors 85 Rev. A2, 20-Jun-96 M43C505

Low-Current 3- and 5-V Solution for Consumer Applications

D Wide supply voltage range (2.4 V to 5.5 V) Existing applications comprise temperature measurement and -control, battery charging, bicycle computers, D Very low current consumption timers, radio-controlled clocks and CD players. D 4096 8 bit ROM, 253 4 bit RAM Existing software modules for time keeping, calendar, D 16 programmable I/Os stop watches, display drivers for various multiplex rates, D 2-MHz fast system clock (1 MIPS) accurate dual-slope temperature measurement and interface software for TEMIC’s radio-controlled clock D 32-kHz crystal oscillator receivers are part of the comprehensive qFORTH soft- D 20 4 LCD temp.-compensated drivers ware library. Software is free of charge. D 2 external/ 3 internal interrupt sources A power-saving sleep- and stop mode increases battery life time significantly in hand-held applications while D Prescaler/ interval timer offering 1 MIPS computing power during active time. D Internal POR and brown-out function Internal POR, oscillator and pull-up/-down resistors simplify PCB layout and minimize system costs.

TST1 TST2 TCL NRST VDD VSS

System clock generation Sleep Power-on reset

RAM address registers ROM X 4096 x 8 bit Y RAM SP 253 x 4 bit Program counter RP Memory bus Instruction bus CCR Instruction Interrupt decoder TOS ALU controller

I/O bus I/O I/O + strobe C1 C2 32 kHz LCD VEE2 driver VEE1 4 4 Inputs I/O External Oscillator key int. interrupts Prescaler VREG 4 4

PORT 1 PORT 0 PORT 5PORT 4 INT7 AV DD AV SS COM0...3 OD INT2, S01...20 BUZZER 32 kHz 96 12020

Figure 1. Block diagram

TELEFUNKEN Semiconductors 87 07.97 M44C588

Versatile High–End Controller for General Purposes

D Various mask-selectable system-clock sources to High-end, battery-powered consumer applications such define application-specific system price/ as bicycle computers, feature watches, diver computers performance ratio and high-end, radio-controlled clocks/watches * all requiring both computing power and low current D Dual clock mode for minimum current consumption consumption * will benefit from the M44C588. D Wide supply voltage range (1.8 to 6.2 V) D 9 KByte ROM, 512 4 bit RAM The dual-clock mode and core frequencies of 4 MHz (2 MIPS) on the one hand and 32-kHz slow operation/ D Up to 32 I/Os incl. high-current ports sleep mode (consuming only micro-amps) on the other D 32-kHz crystal oscillator hand make the M44C588 the best solution for these tough requirements. D Up to 32 4 LCD segments D Prescaler The programmable I/Os with pull-up/-down options, integrated oscillators, 20-mA drive capability, internal D 8 external and 5 internal interrupts watchdog, POR and low-battery detection minimize the D Watchdog, POR and low-battery detection for number of system components, resulting in reduced enhanced system security system costs and PCB size. The integrated temperature- compensated display drivers for up to 128 LCD segments D Synchronous 8-bit serial port enable even sophisticated display solutions. Data transfer D Multi-function timer/ counter incl. IR/ RF remote- to external storage devices such as serial EEPROMs is control carrier generation simplified by the serial port.

VEE2 VEE1 C2 C1 OSCIN OSCOUT AVDD VSS VDD NRST TE SCLIN SCLOUT

I/O bus

I/O I/O Interrupt Interrupt I/O I/O & reset I/O serial Buzzer

Port 0 Port 1 Port B Port 6 96 11556

Figure 1. Block diagram

TELEFUNKEN Semiconductors 89 07.97