High-Frequency Circuits for Environments Affected by Radiation A thesis submitted to the University of Manchester for the degree of Doctor of Philosophy in the Faculty of Science and Engineering, formerly known as that of Engineering and Physical Sciences

MMXIX

James E Hibbert School of Electrical and Electronic Engineering This is not a blank page

2 Contents

1 Introduction 11

1.1 Motivation and Aims ...... 11

1.2 Conventions Used in this Document ...... 13

2 Overview of the Effect of Radiation on Semiconductors 15

2.1 Radiation Effects ...... 15

2.1.1 Search Strategy ...... 15

2.1.2 Single Event Effects ...... 16

2.1.3 Total Ionising Dose ...... 16

2.1.4 Displacement Damage ...... 17

2.2 Susceptibility ...... 17

2.2.1 Silicon ...... 18

2.2.2 III-V Compound Semiconductors ...... 19

2.3 Testing Methods ...... 20

3 VNA Error Correction 23

3.1 Formulation of the Calibration Problem ...... 23

3.2 SOLT and SOLR ...... 26

3.3 LRM and LRRM ...... 27

3.4 TRL ...... 28

3.5 Multiport Methods ...... 29

3.6 General Methods ...... 30

3 3.7 Differential Measurements ...... 30

3.8 Differential Calibration ...... 32

3.9 Uncertainty ...... 33

4 Radiation Tolerant Optical Modulator Drivers 37

4.1 Electromagnetic Simulation ...... 38

4.2 Differential Input Stage ...... 42

4.3 Output Amplifier ...... 44

4.3.1 Transistor Model Adjustments ...... 45

4.3.2 Transistor Selection ...... 50

4.3.3 Gate and Drain Line Design ...... 51

4.3.4 Termination and Bias Supplies ...... 54

4.4 Results and Discussion ...... 55

4.4.1 Calibration and Uncertainties ...... 55

4.4.2 Results for Differential Stage ...... 59

4.4.3 Results for TWA ...... 63

4.5 Conclusions ...... 68

5 Measurements on Irradiated GaAs and Silicon Devices 69

5.1 Tests on GaAs HEMTs ...... 69

5.1.1 Experimental Procedure ...... 69

5.1.2 Principle Components of Uncertainty ...... 71

5.1.3 Results and Discussion ...... 73

5.2 Test Results for Rotary Encoders ...... 76

5.2.1 Experimental Procedure ...... 76

5.2.2 Principle Components of Uncertainty ...... 78

5.2.3 Results and Discussion ...... 78

5.3 Conclusions ...... 80

4 6 Lossy Transmission Line Stubs 81

6.1 Background ...... 82

6.1.1 Transmission Line Parameter Calculation for Stub ...... 83

6.2 Implementation and EM Simulated Results ...... 85

6.2.1 Simulation and Evaluation of Match Standard ...... 86

6.2.2 Stub Parameter Calculation and Design ...... 88

6.3 Conclusions ...... 93

7 Conclusion and Further Work 97

7.1 Further Work ...... 98

Word Count: 30 000 ± 6000

5 Abstract

The reluctance of previous governments to make adequate provision for the long-term storage and disposal of nuclear waste has resulted in an imminent and significant decommissioning burden, as existing “temporary” solutions are well beyond the end of their useful lives. It is preferable to use remote handling solutions for decommissioning, in order to ensure worker safety; however the susceptibility of electronic devices to radiation damage is often unclear.

This document discusses factors affecting the survivability of electronics in radio-active environ- ments, and the design of GaAs circuits suitable for high-speed communications applications in such an environment. Techniques for performing accurate RF measurements and electromagnetic simulations are also discussed. Measurements of the designed devices are presented. Results of irradiation testing of a silicon rotary encoder and GaAs pHEMT transistors, on a related process to that used for the aforementioned circuits, are also presented, demonstrating Mrad hardness for the GaAs devices and krad hardness for the silicon; although the silicon and GaAs results are not directly comparable they are nevertheless of interest to illustrate the difference in radiation hardness between the two technologies, and the GaAs results suggest that the communications circuits designed on the process are likely to be highly radiation-tolerant. Neither the hardness of the encoders tested nor the GaAs process considered are believed to have been measured before. Analysis of a novel technique for improving the performance of certain common RF circuit elements at high frequencies, using stubs of an unusual form of lossy transmission line, is also described; an improvement in the matching of a load standard over frequency is demonstrated in simulation.

6 Declaration

That no portion of the work referred to in the thesis has been submitted in support of an application for another degree or qualification of this or any other university or other institute of learning.

7 Copyright Statement

The following four notes on copyright and the ownership of intellectual property rights must be included as written below:

i. The author of this thesis (including any appendices and/or schedules to this thesis) owns certain copyright or related rights in it (the “Copyright”) and he has given the University of Manchester certain rights to use such Copyright, including for administrative purposes. ii. Copies of this thesis, either in full or in extracts and whether in hard or electronic copy, may be made only in accordance with the Copyright, Designs and Patents Act 1988 (as amended) and regulations issued under it or, where appropriate, in accordance with licensing agreements which the University has from time to time. This page must form part of any such copies made. iii. The ownership of certain Copyright, patents, designs, trademarks and other intellectual property (the “Intellectual Property”) and any reproductions of copyright works in the thesis, for example graphs and tables (“Reproductions”), which may be described in this thesis, may not be owned by the author and may be owned by third parties. Such Intellectual Property and Reproductions cannot and must not be made available for use without the prior written permission of the owner(s) of the relevant Intellectual Property and/or Reproductions. iv. Further information on the conditions under which disclosure, publication and commercial- isation of this thesis, the Copyright and any Intellectual Property and/or Reproductions described in it may take place is available in the University IP Policy (see http://documents. manchester.ac.uk/DocuInfo.aspx?DocID=24420), in any relevant Thesis restriction dec- larations deposited in the John Rylands University Library, the John Rylands University Library’s regulations (see http://www.library.manchester.ac.uk/about/regulations) and in The University’s policy on Presentation of Theses

Here endeth.

8 Acknowledgements

Considerable gratitude is due to Robin Sloan and Barry Lennox for their supervision and encouragement during this PhD. Thanks are also extended to the company and staff at Semtech Inc. for their generosity in the provision of wafer space, without which the circuits described in this thesis would never have been realised, and also for the use of their equipment to perform measurements.

Assistance from Ruth Edge at DCF in the operation of the 60Co irradiator, and the performance of dosimetry, is also gratefully acknowledged.

The contribution of discussions with others, notably Philippa Stokoe and Charles Veys, is also much appreciated.

This project was supported financially by the EPSRC, Sellafield Ltd and the National Nuclear Laboratory (NNL).

9 Boughs, once green and toss’d by wind Lugged to distant shores; their fibres leached Arranged, reshaped, like tendrils of the mind Now coloured; with distant Cornish bleached Kaolin. The result? Paper, o’er which the scholars pore Assess the motion of the spheres, pens in hand clamp’d Grope for solutions; to them but a chore Enlightened but by dim electric lamp

10 Chapter 1

Introduction

The promises of the atomic age, of world peace and electricity “too cheap to meter” [1] are, thanks to generations of governmental ineptitude, lack of enthusiasm for policies extending beyond a Parliamental term [2], and Cold War politics, and paranoia discouraging reprocessing [3], yet to materialise. However the enthusiasm of the atomic pioneers has left the current generation with a burgeoning problem: the solutions developed to temporarily contain radiological waste have become, de facto, permanent and are now well beyond their design lifetime [4]. There is thus an urgent imperative to process and safely contain this material. Such efforts are, however, complicated by a variety of factors; the decaying nature of the facilities, and the intrinsically hazardous nature of manual inspection of radioactive material, as exemplified in the overexposures of divers reported in [5, 6], presents a strong motivation to employ automated inspection techniques where possible, and for reasons of cost control it is preferable to use commercial devices than dedicated radiation-hardened designs. However the survivability of such commercial devices is, by definition, often unclear; techniques to understand the factors affecting their survivability are therefore of interest to the industry. One class of devices believed to be generally highly tolerant to radiation are those fabricated using III-V compound semiconductors; these have often been used, due to their high carrier mobility, in high frequency devices, which are in themselves an area of active research. The premise of this PhD, therefore, was to understand the factors affecting the susceptibility of semiconductor devices to radiation, especially those related to the increased hardness of III-V devices, and if possible design circuits of use for applications in an active environment, such as in nuclear decommissioning or space.

1.1 Motivation and Aims

Some proposed strategies for investigation of the hazardous facilities in Sellafield and Fukushima rely on small, expendable robots to perform characterisation of the environment. As the irra- diated robots are themselves hazardous, requiring appropriate treatment and disposal, there is a clear motivation to increase the lifespan of the electronics employed in order to reduce the decommissioning burden, although issues such as battery life will also tend to place an upper bound on their lifetime.

In addition, the thick walls and shielding present in nuclear facilities tend to render the use

11 of wireless communications to transmit data to the operators challenging. There is therefore potential for a base station, transmitting to the outside world via a fixed link and communicating to other hardware over RF, to be of use. As this would not be limited by battery life, it would ideally be highly tolerant to radiation, permitting a “fit and forget” installation at the beginning of a project. A high throughput would also be potentially useful, in order to facilitate the use of technologies such as video streaming from multiple sources. An outline block diagram for such a system is shown in Figure 1.1.

Figure 1.1: Block diagram showing intended operation of rad-hard communications base-station. Unit would be inserted into facility early in the project, and be designed to tolerate the expected level of background radiation. Expendable autonomous platforms would be used to investigate the area in case of radioactive hotspots.

However, the design of rad-hard and RF circuits did not appear to be well understood within the industry. The aims of this project were, therefore, twofold: to investigate and understand the factors affecting the susceptibility of an electronic device to radiation, and to develop radiation- tolerant ICs suitable for such an environment. The latter took the form of a set of designs suitable for integration into the driver for a fibre-optic backhaul link for the aforementioned base station, on the grounds that fibre-optics are likely to be the most suitable technology for the potentially long distances involved; the Sellafield site covers some 6 km2 [7], and as such a medium-range fibre link is likely to be attractive in order to facilitate the central supervision of decommissioning activities in remote facilities.

12 1.2 Conventions Used in this Document

Conventions used in this document are, as far as possible, in accordance with current literature and industry practice. All abbreviations are glossed on first use. Syst`emeInternational (SI) units and prefixes are used throughout, with one significant exception: The SI unit for radiation dose is the Gray (Gy), with 1 Gy = 1 J kg−1 of deposited energy. However the literature overwhelmingly uses the CGS rad (100 erg g−1), with 1 Gy = 100 rad, and as such it is also used in this document. The term microstrip is used to describe a transmission line consisting of a conductive strip located over an infinite ground plane, with one or more dielectric layers interposed; although as Wheeler states [8] the former term is not at all descriptive of the line, it is common in the vernacular and rather less cumbersome than a more precise description. In general, references to S-parameters should be taken to refer to the pseudo-S parameters as described by Marks and Williams [9], normalised to an arbitrary reference impedance Zref; the distinction between the two will hopefully √be clarified in the discussion of calibration given in Chapter 3. A lowercase i is used to denote −1; this was done to minimise ridicule from the significant flux of physicists that was present in the building during the writing of this document, and to encourage the mathematics to co-operate. The former aim was successful; the latter less so.

13 Information-blank page inserted to ensure continuity of geometry should previous page not be printed on single-sided paper

14 Chapter 2

Overview of the Effect of Radiation on Semiconductors

This chapter presents a brief overview of the current state of the literature on radiation effects in semiconductors, at least as pertain to the nuclear environment, and compares the typical radiation tolerance of devices fabricated using some of the semiconductor processes in current use.

2.1 Radiation Effects

The general effects of radiation on electronics are reasonably well-known, and can be divided into three classes: Single Event Effects (SEE), Total Ionising Dose (TID) and displacement damage (DD). The first two are the result of charge deposition, although the energies and effects are substantially different; the last is the result of physical changes to the crystal lattice. They are not necessarily mutually exclusive; depending on the radiation environment to which a device is exposed, all three effects may be experienced.

2.1.1 Search Strategy

Ascertaining trends in radiation susceptibility is complicated by the sheer wealth of material on the subject, from a variety of sources dating back to the 1960s. Although some of this has been inevitably superseded, or is irrelevant to modern technologies, much of the fundamental physics is still valid. Most of the literature, particularly the earlier work, was a result of radiation hardening programmes for military and space applications; one objective was, therefore, to ascertain how much of this is relevant to the nuclear environment. The majority of relevant material appears to be published in the IEEE Transactions on Nuclear Science (TNS); this was therefore used as the primary resource for reading material, with interesting-looking references to other sources followed up as appropriate. The sheer volume of material does, however, make assimilation of it somewhat challenging.

15 2.1.2 Single Event Effects

Single Event Effects (SEEs) are a class of radiation effects characterised by being caused by a single particle strike (as distinguished from cumulative damage, which will be discussed in the next section). They were first studied during the 1960s (as a cause of latchup in circuits exposed to a radiation pulse from an atomic explosion e.g. [10]); effects caused by single particle strikes were first reported in the 1970s, with Binder et al [11] identifying galactic cosmic rays as the cause of anomalous operation in a communications satellite. In addition, several destructive failure mechanisms have been identified, such as SEB (Single Event Burnout) [12], and potentially (if uncontrolled) the aforementioned SEL (Single Event Latchup).

The basic mechanism for SEE is well-known, and consists of charge liberation as a result of an energetic particle strike, either via direct ionisation from charged particles or via recoil energy from high-energy neutrons, essentially delivering a pulse of current to the circuit node. This generally results in designs with smaller feature sizes being more susceptible; the smaller areas involved have substantially lower critical charge and as such are more vulnerable to lower energy particles, to an extent which the decreased sensitive volume does not compensate for [13, 14] (although this is not the case in DRAM as the node capacitance has remained fairly constant [15]) The physics of this interaction have been extensively modelled and several commercial simulation packages (e.g. CREME96 [16]) are available; Munteanu and Autran [17] give a good overview of the current state of the field. As shall be discussed in more detail later SEEs are relatively of less concern to the nuclear environment, so will not be discussed in detail here.

2.1.3 Total Ionising Dose

Total Ionising Dose damage is the degradation associated with the cumulative absorption of energy from ionising radiation. The basic mechanism is, once again, the generation of electron-hole pairs (EHPs) as a result of ionising radiation; however in this case the charges remain in the oxide layers rather than immediately migrating into the channel. As the mobility of electrons in oxide is substantially greater than that of holes [18], they quickly migrate to the interface, resulting in a net positive charge due to the trapped holes. The effect of this depends on the location of the oxide; charge buildup in gate oxides tends to result in the threshold voltage becoming more negative (i.e. enhancement-mode NFETs become “easier” to turn on, and PFETs “harder”). Charge can also be deposited in other oxides (e.g. isolation oxides and the buried oxide in Silicon on Insulator (SOI) processes), where they act to create parasitic inversion layers; this is discussed in more detail in Section 2.2.1.

One interesting aspect of TID damage is that the generated holes will tend to migrate through the oxide [19], and eventually either become trapped at the oxide-semiconductor interface or recombine. This means that TID degradation is a function of time as well as total dose. These time-dependent annealing effects have been extensively studied, and several mechanisms identified; in addition to the aforementioned recombination via tunnelling or thermal emission [20] other mechanisms have been identified, including electron tunnelling neutralising deeply-trapped holes, as demonstrated by Schwank [21]. In addition, radiation-liberated proton drift has been identified as causing a long-term increase in interface trap density [22, 23]. Therefore devices exposed to ionising radiation do, to some extent, self-heal, as the charge trapped in the oxides migrates and recombines; as would be expected, higher temperatures increase the rate of annealing by increasing the energy available for charge migration.

16 2.1.4 Displacement Damage

Displacement damage (DD) is arguably the most complicated radiation effect, consisting as it does of physical interactions between incident particles and the crystal lattice of the device. As such the physical mechanisms will not be discussed in detail here; Srour et al provide a good overview of the physics [24]. In essence, an energetic particle (which could be e.g. a neutron, proton, electron or secondary electron from Compton scattering) passing through the material will transfer some of its energy to the atoms comprising it. Provided this is above the threshold required to displace an atom it will move, with kinetic energy equal to that left over from the interaction. Typically particle energies (keV/MeV) are substantially higher than the threshold (eV), resulting in a series of interactions as the displaced atom encounters other atoms in the lattice (similar to the ionisation track produced by a heavy ion strike).

For practical calculations, the simplifying assumption that the energy loss of the particle is insignificant (i.e. its range is much greater than the thickness of the material) is usually made. This means the energy loss along the path is constant, and can be expressed in terms of a Non Ionising Energy Loss (NIEL), analogous to the Linear Energy Transfer figure used in SEE calculations [25], which can simply be multiplied by the particle flux to obtain an estimate of the energy transferred to the material, or displacement damage dose. This concept allows, within the limitations of validity of the assumptions made, displacement damage to be modelled as a single curve of damage against NIEL, as opposed to several curves for different particle energies [26]. This should give a linear relationship between NIEL and observed damage; however this is clearly dependent on the accuracy of the models used to determine the NIEL. This is an ongoing area of research; for example Inguimbert et al [27] propose an adjusted NIEL curve for electrons which eliminates the quadratic dependency noted by (e.g.) [28].

The effects of the defects introduced by displacement damage are generally to decrease carrier mobility and concentration, due to trapping and scattering [29, 30, 31]; as one would expect this acts to reduce device gain. Displacement damage effects will also vary over time as the generated defects migrate to more stable positions; this is evident in the references given above, as is the fact that annealing did not prompt a full parametric recovery, indicating that the lattice does not return to its former state.

2.2 Susceptibility

Although the effects discussed in the previous sections are generally applicable, circuits man- ufactured on certain substrates and process technologies are known to exhibit relatively less degradation. Quantifying this statement is challenging because of the sheer number of process variables involved; although certain substrates are regarded as being “rad-hard,” the methods used to fabricate the transistors themselves have a significant impact on the final result. Rad-hard flows, even for reasonably standard CMOS processing, have been available since at least the 1970s [32], and several rad-hard layouts have been described in the literature (e.g.) [33, 34, 35]; also modern processes have the interesting property of being generally quite intrinsically rad-hard due to their thinner oxides. Nevertheless this section will aim to give an overview of general radiation hardness trends in silicon (including SOI) and the common III-V compound semiconductors, focusing on TID damage as this is generally the limiting factor on mission lifetime.

In the event that it is necessary (usually due to budgetary constraints) to use a technology known

17 to be susceptible to radiation, it is of course possible to add additional mechanical shielding to reduce the absorbed dose. Energetic particles have a well-defined range in matter, and as such can be entirely prevented from reaching sensitive components; the thickness of material required to achieve this may be unacceptable for higher-energy particles, but is reasonable at lower energies. −tµ/ρ Gamma rays obey a simple exponential attenuation law I = I0e , where I is the intensity of the radiation (dimensionless), t the mass per unit area of the shielding employed (kg m−2) and µ/ρ the attenuation coefficient per density, a function of the material and the energy of the −zµ photon. This can be re-arranged to I = I0e , where z is the thickness of the shielding (m) and µ the attenuation per thickness of the material (m−1), which may be a more helpful form for certain applications. These have been determined for a range of materials and photon energies; see for example [36]. By way of example, the intensity of 1.5 MeV gamma radiation (similar in energy to the 1.3 MeV gammas emitted by 60Co decay) will be attenuated by 50 % by around 51 mm of Al (µ = 13.5 m−1) or 12 mm of Pb (µ = 59.2 m−1); these will mass approximately 12 g cm−2 and 14 g cm−2 respectively. This mass burden may be effectively reduced by good system design; it may be possible to use structural components for shielding, and combine several subsystems into a shielded ’vault,’ as was done on the current Juno mission to Jupiter [37].

2.2.1 Silicon

Silicon is the most common semiconductor substrate in use today, and as a result of extensive commercialisation bulk CMOS processes are extremely cheap, and hence highly desirable in an era of low budgets and austerity. However, the use of MOS structures and thick isolation oxides has traditionally made silicon circuits rather vulnerable to radiation damage, as charge can easily be trapped in them; this leads to the interesting phenomenon that the thinner gate oxides and use of better quality isolation oxides in newer processes make them more tolerant to radiation, as shown in the results presented in [38]. Core transistors in modern processes have sufficiently thin gate oxides that charge trapping in them is no longer a significant concern, as trapped charges are close enough to the interface to tunnel out of the oxide [39, 40], meaning that the main effect of radiation is to increase off-state leakage current as a result of charge buildup in STI/LOCOS isolation oxides. This increase can be several orders of magnitude [41, 42], presenting problems due to increased power dissipation and reductions in margin.

Silicon on Insulator (SoI), initially built on sapphire (SoS) and more recently on SiO2, has been used in rad-hard designs, as the structure has a smaller cross-section for charge capture and, due to the lack of parasitic pnpn structures, the attractive property of being latchup-immune; it also continues to be used in high-performance applications. However the presence of the thick buried oxide (BOX) presents a potential sensitive region; it forms the gate oxide of a parasitic transistor, and charge trapped in the oxide (assisted by the likely high defect density in such oxides) effectively biases this transistor. This is referred to as backgating, and results in a threshold voltage shift in the transistor [43, 44], as shown in Figure 2.1.

An alternative structure has been proposed to mitigate this [45] and modern transistors appear to use similar low-coupling layouts; as such the main effect evident in [46] is an increase in leakage current. However the newest FINFET designs appear to have much tighter coupling between the channel and the BOX, resulting in a noticeable threshold shift under irradiation. This is illustrated in recent results on 14 nm devices [47]; the bulk devices exhibit substantially increased off-state leakage due to charge trapping in the STI oxides, whereas the SOI devices show a threshold shift as a result of BOX trapping.

18 Figure 2.1: ID/VG curves for FDSOI transistor under irradiation [44]

Overall, modern silicon-based devices are fairly radiation-tolerant, with several authors reporting negligible effects even after doses in the hundreds of krad [48, 49, 50]. However, as shown in [47] above, it is possible that this will not continue to be the case for future generations of devices, although one could speculate that radiation hardness will be the least of the problems experienced by such sub deca-nanometre transistors.

2.2.2 III-V Compound Semiconductors

The family of compound semiconductors encompasses a wide variety of materials, including GaAs, GaN and other materials such as InP. Although the radiation responses of devices made using them obviously vary significantly, in general they are extremely total-dose hard; GaAs devices have demonstrated minimal degradation even after hundreds of Mrad [51, 52] and despite the relative immaturity of GaN technology it has also been shown to be very resilient [53, 54]. This is primarily due to difference in structures fabricated using them; most III-V devices use MES or MOD (HEMT) structures and as such do not have the gate and field oxides commonly found on Si devices, which essentially eliminates long-term charge trapping as a failure mechanism. This was qualitatively demonstrated by early experiments conducted on InP devices; initial tests on Metal Insulator Semiconductor FETs (MISFETs) showed a very poor radiation tolerance, of the order of 1 krad [55] but later results using JFETs demonstrated megarad tolerances [56], which was attributed to their lack of oxide layers (earlier results [57] showed a much higher tolerance, but the measurements appear to have been made a significant time after irradiation and as such may have been compromised by annealing effects). A similar effect has been demonstrated more recently in comparisons between MOS-HEMTs and HEMTs [58], although the thin oxides used are likely to encourage recombination, reducing the magnitude of the differences. As such the primary cause of total-dose degradation is likely to be displacement damage; this can be caused by secondary electrons from gamma irradiation, but most current research has focused on protons,

19 which are likely to be the primary source of displacement damage in space. A secondary cause is mechanisms unrelated to the device itself, such as reactions in passivation layers; at least one early study on HEMTs observed physical damage assumed to have been caused by chemical reactions [59].

There are also physical differences in charge generation between semiconductor materials. As determined theoretically by Klein-Shockley [60], and later substantiated by experimental data (see e.g. Table I in [61]), EHP creation energy has a linear dependence on bandgap; this will result in fewer EHPs being created in wide-bandgap semiconductors such as GaN for a given energy transfer (LET) from the incident particle, which has implications for SEE-type events where the immediate charge deposited in a circuit node is the primary concern. However it was discovered, after GaAs devices proved depressingly susceptible to SEE [62], that this is in practice masked by charge collection and dispersion effects; both GaAs and GaN have been shown to demonstrate quite a pronounced response to radiation pulses [63], extending over several decades in time, which is believed to be caused by slow charge release from traps in the substrate (the EL2 defect in GaAs has been implicated). This has also been shown to increase flicker noise in certain structures, which is a concern for analogue applications [64]; related work on HBTs [65] did not demonstrate this increase, demonstrating the dependence of a device’s structure in determining its radiation susceptibility.

2.3 Testing Methods

Testing and modelling of the susceptibility of a system to radiation is complicated by the difficulty of determining the radiation environment, and generating suitable conditions experimentally. For example, the majority of the dose accumulated whilst in proximity to a planet is the result of interactions with protons and electrons captured by the magnetosphere; these typically have energies up to a few hundreds and tens of MeV respectively [66, 67]. There are also occasional high-energy cosmic rays, which are a concern from an SEE perspective. In contrast, in a nuclear environment gamma is likely to be the primary contributor to dosage; although alpha and beta particles (He nuclei and leptons) are present, the low energy (<5 MeV) and high charge of alphas means they will not travel more than a few millimetres [68] and hence will not penetrate packaging; similarly, although a 1 MeV beta will travel around 2 mm in aluminium [69] it is unlikely that this will be a concern unless the device is physically proximate to the source (as any structural components around the circuit are likely to provide sufficient shielding). There will also be some neutron radiation, although given that relatively few fission products decay via neutron emission this is likely to be a result of spontaneous fission of unused fuel, and as such at a relatively low level of activity. This section will therefore focus on TID hardness as the primary figure of merit for a system.

In addition, it is generally impractical to test a system at the likely dose rate in the application – even in the highly energetic environment of Jupiter’s magnetosphere the Galileo probe only absorbed around 10 krad during a two-day orbit [70]. It is therefore necessary to test at an unrealistically high dose rate in order to produce results within an acceptable time. This has, unfortunately, been found to present problems, particularly when testing bipolar circuits; these often exhibit true dose-rate effects, where the dose rate affects the quantity of degradation experienced. Early work [71, 72] suggested this was due to devices exhibiting enhanced sensitivity to radiation at low dose rates, and as such the phenomenon was termed Enhanced Low Dose Rate Sensitivity (ELDRS); however later studies suggested it was more of the nature of a reduction in

20 sensitivity at higher dose rates (Reduced High Dose Rate Sensitivity, or RHDRS); the latter term is used in this document, as it better describes the physical mechanisms involved.

The mechanism for RHDRS is complex and several models have been proposed for it. Earlier work suggested oxygen vacancies in oxides acted as hole traps, reducing their mobility and hence increasing the time taken for holes to migrate to the Si-SiO2 interface; this causes a space charge to form at higher dose rates, resulting in additional radiation-generated holes becoming trapped nearer the interface, where they are more likely to recombine or become compensated [73]. Later work also recognised the contribution of hydrogen to the creation of traps, as a result of liberated protons de-passivating interface traps [74, 75]. More recently, several analytical models [76, 77] have been developed, theoretically allowing RHDRS sensitivity to be simulated (provided sufficient process data is available). The RHDRS phenomenon has traditionally been regarded as being exclusively confined to certain bipolar transistors (with particularly thick and soft oxides); however it has been observed [78, 79, 80] that modern nMOS exhibit a small true dose rate effect in their leakage currents, possibly due to the dominant radiation damage mechanism in smaller devices being charge capture in the isolation oxides.

A commonly used standard in the radiation effects community is MIL-STD-883:1019 [81], which attempts to provide a framework for conducting repeatable and representative TID tests using 60Co sources. It incorporates procedures for determining if the device under test (DUT) exhibits RHDRS, and (for non-RHDRS sensitive devices) use of annealing to allow accelerated testing at higher dose rates. Some of the procedures in it necessarily require adjustment to the particular test situation, and will often require preliminary investigations to e.g. determine the worst-case bias conditions. However it is a useful best-practice standard to follow, and ensures results will be generally comparable with those obtained by others.

21 -.../.-../.-/-./-.-/.–./.-/–./.

22 Chapter 3

VNA Error Correction

As discussed in Section 1.1, one aim of this PhD was to develop rad-hard RF circuits suitable for communications. A fundamental difficulty in the measurement of such devices is calibration; in contrast to those made close to DC, RF measurements of interest usually have a high (>50 dB) dynamic range, and losses due to cabling and test fixtures are almost always significant and frequently unpredictable. As such, the need for calibration as a routine part of the measurement process was recognised early on [82] and considerable effort has subsequently been devoted to the development of calibration procedures for vector network analysers. In the interests of generality, it is desirable that such procedures make minimal assumptions about the nature of the standards used; particularly in the increasingly common case of RF on-wafer (RFOW) measurements factors such as substrate leakage, coupling due to the close proximity of the probe tips, and fabrication tolerances make algorithms that make anything more than the most basic of assumptions subject to considerable uncertainty, particularly at higher frequencies. The basic problem of VNA calibration is one of constructing a system of equations relating data measured on the VNA to the physical behaviour of calibration standards, and solving it to establish the unknown non-idealities of the measurement path; as mentioned above, ideally the behaviour of the standards should not need to be completely known, although it is often desirable to be able to relate them to primary standards in order to establish traceability [83]. This section describes the calibration problem, and introduces popular current algorithms for solving it, with comments on their limitations and applicability; the focus is mainly on two-port systems, both for simplicity and to be in keeping with the literature, although more general techniques and the special case of two-port differential systems are also discussed.

3.1 Formulation of the Calibration Problem

The error model used for calibration depends on several factors, including the internal design of the VNA and the nature and magnitude of the coupling between ports. Early VNA designs used a sampling architecture similar to that shown (for a two-port VNA) in Figure 3.1. This is capable of measuring both reverse waves simultaneously, but only one of the two forward waves; a fundamental part of the calibration process is therefore to determine the unknown reflexion coefficient of the switch used to choose between signal paths (A74 in Figure 3.1). The nonideal

23 behaviour of the switch results in there being two sets of error terms, one for each state of the switch.

Figure 3.1: Block diagram for an exemplar three-sampler VNA (the HP 8720ES) [84]

More modern designs, such as that depicted in Figure 3.2, are capable of sampling all four incident and reflected waves; they can therefore obtain an estimate of the reflexion coefficient of the switch by measuring the resulting forward wave at the non-driven port. Since the behaviour of the switch tends to be quite repeatable and stable, it is possible to measure it during the calibration process and store the result, abrogating the requirement to measure all four waves during normal operation. Most, if not all, current VNAs are of the four-sampler type, so the three-sampler design will not be discussed in further detail here.

Several models have been developed for the error terms, with increasing numbers of parameters generally allowing for more sources of crosstalk between ports to be corrected. The simplest one in general use is the 8 term model; as shown in detail by Eul and Shiek [86] this is a reduction of an analysis of a four-sampler dual-reflectometer system, and as such incorporates the various nonidealities in the reflectometers (usually directional couplers) and general losses in the path to the DUT. It entirely disregards crosstalk between the measurement ports. This model is usually formulated in terms of error boxes, as shown in Figure 3.3; these are (somewhat fictitious) two-ports placed between the ports of an ideal measurement system and the DUT. This representation permits visualisation of the calibration process as one of removing the effects of these error boxes, which is in most cases a convenient and useful description of the problem. As noted in e.g. [86], when measuring ratioed quantities such as S-parameters it is possible to normalise the error terms to one of them; it is therefore only necessary to determine 7 terms to calibrate a system modelled by the 8-term model.

An extension of this model, and in fact the form in which it was originally posed by Rehnmark [88], includes two additional parameters. These model crosstalk “across” the DUT, i.e. between ports as would occur, for example, when measuring on-wafer with probes placed physically proximate to one another, or when measuring a DUT which has its ports on a single side. This gives 10 error

24 Figure 3.2: Block diagram for an exemplar four-sampler VNA (the HP 8510C) [85] terms for a VNA in which the switch terms have been corrected a priori, or 12 for a three-sampler VNA. The 10-term form appears to be little used in practice; many calibration methods do not provide sufficient information to determine all the terms, and the trend appears to be to use more sophisticated models if crosstalk is an issue. However calibrations such as SOLT provide sufficient information to solve the 12-term model.

Other, more general, models have been proposed; the most general in regular use appears to be the “leaky” model, with 16 terms for a two port system, as shown in Figure 3.4. Described by Speciale [90] and analysed in detail in 1991 by Butler et al [89], it incorporates terms for crosstalk between all nodes of the error boxes, both on the DUT and analyser side, giving a very general formulation suitable for even very non-ideal measurement systems. It is however questionable how useful this is in many practical situations; the additional information required for calibration requires more measurements to be taken, and the method presented in the paper requires fully known standards, which presents practical difficulties at higher frequencies. However it is of use for problems such as four-port measurement, or the measurement of differential devices, as will be discussed in more detail later.

25 Figure 3.3: 8-term error model for a switch-corrected VNA, in the error box formulation [87]

3.2 SOLT and SOLR

SOLT (Short, Open, Load, Thru) is one of the earliest forms of VNA calibration, and requires four known standards to calibrate a two-port system, comprising a zero-length through connection, paired one-port match (nonreflecting) standards, and two sets of paired one-port reflect standards. The last are usually implemented as a short and an open, although any standards of known reflexion coefficient can be used provided they are well separated on the Smith chart. It was originally developed for three-sampler VNAs, and as such solves a 10-term error model.

More recently some authors have exploited the additional redundancy obtained when using SOLT calibration, which provides sufficient information to solve a 10-term model, in a system with a 7-term error model, to simplify the calibration process. Arguably the most important improvement in this regard was made by Ferrero et al [91], who used this redundancy to reduce the requirement that the thru be known to that it merely be reciprocal, resulting in the SOLR (Short, Open, Load, Reciprocal) technique; the requirement of reciprocity is hardly arduous to achieve in practice, and allows several applications of practical interest, such as the calibration of systems where mechanical constraints preclude the use of straight lines and as such determination of the line parameters is difficult to impossible. One such example is that of calibration between adjacent ports in a typical four-port system, which will be discussed in more detail later. Ferrero and Pisani also proposed another variation on SOLT, termed Quick SOLT (QSOLT) [92], where the requirement to measure the one-port standards at both ports is removed; instead the standards are measured at one port and the thru used to provide the necessary information to determine the error parameters at the other port. This reduces the number of connexions that are required, which speeds calibration in a connectorised system, and, by using the same match standard for both ports, ensures the calibration has a consistent reference impedance.

The primary disadvantage of SOLT is the requirement that all the standards be known; although this is sometimes practicable in coaxial systems, it is in many cases difficult to achieve, particularly in the on-wafer case. Here probe contact repeatability and losses make it difficult to fabricate good quality open and short standards; successful calibrations up to moderate frequencies have been demonstrated using SOLT [93, 94]; however they tend to rely on performing an initial characterisation of the standards using a reference-level calibration, such as TRL.

26 Figure 3.4: 16-term error model for a switch-corrected VNA, in the error box formulation [89]

3.3 LRM and LRRM

Line Reflect Match (LRM) [95] and Line Reflect Reflect Match (LRRM) [96] are, as their names suggest, a closely related pair of calibration methods employing a match standard, used to set the reference impedance, a matched line, used to provide the connexion between ports necessary to determine certain of the error parameters, and one or two reflexion standards (usually, as with SOLT, nominal shorts and opens). The key difference between LR(R)M and SOLT is that the reflexion coefficient of the standards is not required to be known; as with TRL the measurements are only used to inform the selection of the solution to a quadratic equation. As such, they are of use for on-wafer calibration, where the closely coupled environment makes fabrication of reflective standards challenging. LRRM differs from LRM in that the additional standard is used to allow the match standard measured at one port to set the reference impedance for both ports; as noted by Davidson et al match standards tend to exhibit variance in their impedance, resulting in an inconsistent calibration (with a different reference impedance for each port) if two match standards are used. Both calibrations, in the enhanced form proposed by Davidson et al, acknowledge the non-ideal behaviour of the match standard, modelling it as a resistor in series with a reactance, determined as part of the calibration process; improvements to this model have been suggested [97, 98] to ameliorate some of the limitations of the original with regard to offset standards, at the cost of requiring more information about the standard. Properly performed LR(R)M calibrations have been shown to approach the accuracy of TRL at frequencies exceeding 100 GHz [99], although, as the calibration does not establish the propagation constant of the line, errors can occur when attempting to perform large reference plane translations with nonideal lines.

27 3.4 TRL

The TRL (Thru Reflect Line) calibration procedure was developed from the earlier TSD, and employs similar standards; namely a reflect and a pair of line standards of equal and known impedance but different lengths 1. The primary advantage of it as compared to TSD, as described in the paper introducing it [100], is the abrogation of the requirement for a short (i.e. a standard of known reflexion coefficient), it instead being replaced by a standard where only the sign of the reflexion coefficient is required to be known, in order to select a root. This is indubitably advantageous; however this ignores the primary advantage, at least from a metrology perspective, of TRL (and indeed TSD), which is that the reference impedance for the calibration is set not by some arbitrary resistive artefact but from that of the line standard. Although not explicitly acknowledged in the paper (the line standard being described as “reflexionless”), the calibration process, if properly performed, inherently calibrates the system to the characteristic impedance of the line, as discussed by Marks and Williams [9], and hence allows measurement of the true scattering parameters, rather than an impedance-transformed version thereof. This also permits the propagation constant γ to be determined, and hence facilitates the accurate movement of reference planes along the line. From a metrological perspective the use of the line as a standard facilitates the establishment of traceability; analytical solutions are known for certain lines, such as co-ax, permitting the uncertainty in the reference impedance to be determined directly from uncertainties in the line parameters. More complicated environments, such as microstrip, have published approximate analytical formulae, which are likely to yield less uncertain results than attempting to calibrate using a resistive standard with a variation of impedance over frequency that tends to be somewhat challenging to predict.

As such, the TRL technique, in the modified multiline form developed by Marks [101], has found favour as a reference-level calibration. It does, however, have some practical disadvantages. Firstly it solves for a 7-term error model, making it unsuited for systems where this is not applicable, such as those affected by crosstalk between ports. An issue of more practical significance, particularly for on-wafer measurement, is the number and length of the line standards required; each pair of lines (which, as discussed by Marks, should have a phase difference of approximately π/2 at midband to achieve the lowest error) tends to only be usable over approximately three octaves, as the problem becomes ill-conditioned for lines with a phase difference of nπ, and as such multiple standards are required for broadband calibration. These occupy substantial wafer space, particularly at low frequencies, and require repositioning of the probes for each standard, potentially resulting in additional uncertainties due to cable movement. An interesting hybridisation of LRM and elements of TRL has been developed [102] which avoids the issues with long lines by only employing one pair of (relatively short) line standards; these are used to estimate the propagation constant of the line, permitting accurate translation of the reference plane, and also to characterise the non-ideal match standard used to set the calibration reference impedance, in order to permit the transformation of the calibration back to the desired reference impedance.

1This is arguably LRL, as TRL as originally formulated requires a zero-length thru; however this distinction has become blurred and is somewhat arbitrary. If not using coaxial connectors a true thru connexion is often impracticable and may lead to issues due to the presence of evanescent modes

28 3.5 Multiport Methods

The above calibration methods, as described, are only suitable for two-port systems. It is often possible to extend them to the more general N-port case; this does, however, require a true multiport analyser, i.e. one with 2N receivers. Although modern high-performance analysers are of this type, some use fewer receivers and a switch matrix to select the signal path. The difficulties involved in calibrating such machines are discussed in [97, 103]; as with the issues in the calibration of a three versus four sampler design they will not be discussed in detail here.

Conceptually this extension is reasonably straightforward, if tedious, to perform. A generalisation of SOLT can be considered [104], requiring measurement of one-port standards at each port and the use of multiple thru connexions to obtain the error coefficients for the transmissive paths. Alternatively an extension of an 8-term calibration such as LRRM could be used, performing calibration on pairs of ports and using thru standards to resolve the ambiguity caused by the normalisation of each pair of error boxes to one of the parameters therein. These methods do, however, present practical issues in providing suitable thrus; it is difficult to envisage an experimental set-up which would permit straight connexions, as would be required to provide the well-defined line characteristics mandated by LRRM and TRL, to be made between adjacent ports without requiring significant cable movement. The solution proposed by Hayden [97], and implemented in a commercial piece of software, is to use the SOLR algorithm, which does not require a known line standard, to perform the calibration between pairs of ports, using a loopback standard such as that shown in Figure 3.5. A similar approach, with claimed better performance, is reported in [105]; this uses the 10-term model, instead of the switch-corrected 8-term model in LRRM-SOLR. Other techniques have been described, e.g. by Ferrero et al [106]; these are generally of the more “general” form discussed in the next section.

Figure 3.5: ISS Loopback Thru, as used for LRRM-SOLR Calibration

29 3.6 General Methods

The above calibration methods are all based on an explicit analytical solution to the calibration problem; they all require the measurement of the minimum number of standards required to solve for all the unknown terms in the system (including, with the exception of SOLT, some unknown parameters of the standards). In some cases this results in calibrations which do not use all the information available from the standard measurements; an example of this is the original TRL algorithm [100], which as discussed in the paper describing the multiline-TRL technique [101], did not use all the information present in the measurements of the line standards. There have, however, been developed a variety of methods (e.g. [107, 108, 109]) which, instead of solving an explicit analytical form of the problem, instead pose it as an overdetermined problem for optimisation, with a suitable number of free parameters corresponding to the error terms and unknown behaviour of the standards, and data from measurement of whatever standards are available. These are of interest as they allow a general solution to the calibration problem, incorporating as much information as is available; they also generally offer estimation of the residual uncertainties in the calibration “for free” as part of the process, aiding uncertainty estimation. However, as is often the case with optimisation methods, they tend to be computationally expensive, and the algorithm may exhibit slow or no convergence, or converge on a local optimum, unless suitable initial conditions are selected. One way of achieving this in practice is to use the error boxes determined from an initial analytical calibration as starting values for optimisation; as they will already be close, ideally unknowably so, to optimum, convergence will tend to be swift.

3.7 Differential Measurements

Differential systems are attractive to system designers, as they possess several advantages including reduced output swing requirements, which are attractive for modern low-voltage processes and mobile systems, increased immunity to common-mode noise, and consequent harmonic suppression.

However, their characterisation presents challenges. A single-ended circuit is (generally) described with reference to a single propagating mode2, and S-parameters are usually determined with respect to a single well-defined reference impedance; however a differential system (for simplicity considered for the purpose of this discussion to comprise a system with two differential ports) will, as shown by Tripathi [111], have at least two propagating modes of interest, the c and π mode, each of which will have unique propagation constants, and differing characteristic impedances for each mode and signal conductor. Although generalised S-parameter equations have been derived, permitting differing normalising impedances for each mode [112], the derivation and the resulting equations could be described as somewhat involved; the practical issue of setting the reference impedance when calibrating such a circuit also presents itself. In practice, simplifications can readily be made. In the common case of the circuit being symmetrical about the axis of propagation, as shown in Figure 3.6, the c and π mode characteristic impedances for each line will be identical, and the more general c and π modes reducing to the even (e) and odd (o) modes respectively; as defined by Cohn [113] the odd mode has voltages on each line equal in magnitude but opposite in sign, and the even mode has them equal in magnitude and sign. This work was extended by Bockelman and Eisenstadt [114] by assuming uncoupled feed lines; this results in equal even and odd mode impedances, and a consequent considerable simplification of the

2 This will, as discussed elsewhere, have a corresponding backwards mode with γ and Z0 opposite in sign; however this may be viewed as complementary to the forwards mode, rather than being distinct from it.

30 Figure 3.6: Example of a differential circuit with equal odd, and even, mode impedances for each line (Zo1 = Zo2 and Ze1 = Ze2) [110] mathematics, permitting the system to be easily described in terms of its mixed-mode parameters; these describe the response of the network to differential and common-mode stimulation, and also the conversion between differential and common-mode signals, according to Equation 3.1:

    bdm1 adm1   bdm2 Sdd Sdc adm2   =   (3.1) bcm1  Scd Scc acm1  bcm2 acm2

Where a and b are the vectors of incident and reflected waves for the two modes and ports, with the differential-mode waves being denoted by the dm subscript and the common-mode waves by cm. The mixed-mode scattering matrix Smm consists of four sub-matrices; Sdd and Scc describe the response of the system in terms of a single differential or common mode, and Sdc and Scd the conversion between the two modes.

Practical measurement of these parameters does, however, present challenges. True differential measurements, necessary if the large-signal parameters of a device are to be measured, require a system capable of generating differential and common-mode signals, implying a system capable of driving two ports simultaneously, with a controlled phase offset between the two. Such systems have been available for some time; systems have been reported using a hybrid to generate appropriate differential and common-mode excitations on demand [115, 116], although these tend

31 to be limited by the performance and bandwidth of the hybrid. Newer multiport systems feature multiple sources to achieve the same effect [117, 118]; however they are still not so common as to be ubiquitous, and as discussed by Dunsmore additional calibration steps need to be taken to level the power delivered to each half of the differential ports.

A possible alternative approach, at least in a small-signal regime, is to establish a correspondence between S-parameters measured on a 2N-port single ended system and the mixed-mode parameters for the N-port differential system resulting from pairing the ports. This transformation logically follows from the above derivation of the mixed-mode parameters; if the normalising impedance for the mixed-mode parameters is chosen to be equal to that of the single-ended S-parameters (i.e. Ze = Zo = Z0), it is relatively straightforward to work through the algebra for the various combinations of common-mode and differential stimulus and response to obtain the relationship between the two sets of parameters. The transformation matrix for a two-port differential system, as presented in [115] is given by Equation 3.2:

−1 Smm = MSM (3.2)

Where ports 1 and 2, and 3 and 4, are combined, and M is given by:

1 −1 0 0 0 0 1 −1 M =   (3.3) 1 1 0 0 0 0 1 1

It is useful to note that, as M is orthogonal, M−1 = MT .

This provides a method for transformation of single-ended S-parameters; however it is important to understand the limitations of this approach. The restriction that the calibration reference impedance be equal for odd and even modes is not too onerous in practice, as in general the ports will be spaced sufficiently widely for this assumption to hold; however it would imply that the reference plane for calibration must be set to be before any transition to closely-coupled lines. In addition, as discussed by Bockelman et al [119], the accumulation of uncertainties is likely to result in greater uncertainty in measurements determined by transformation of S-parameters; this will be particularly apparent for parameters such as the mode conversion terms, which are likely to be low in magnitude.

3.8 Differential Calibration

As discussed above, it is possible to measure differential systems using a single-ended system, appropriately calibrated, provide it satisfies the conditions for the single-ended to mixed-mode transformation to be valid. There are, however, likely to be additional caveats pertaining to the error model used; on-wafer differential measurements are typically conducted using probes with two closely spaced signal conductors (either in a GSGSG configuration, as shown in Figure 3.7, or sometimes, for low-frequency measurements, in a GSSG arrangement), and as such crosstalk between the two signal conductors is likely to be an issue. This may well lead to poor results when using algorithms, such as the aforementioned LRRM-SOLR hybrid, which ignore crosstalk.

32 Figure 3.7: GSGSG Differential Probe (Cascade Microtech Infinity) on wafer

However crosstalk between the differential ports is less likely to be significant, and as such the fully coupled “leaky” error model, with 4n2 = 64 terms in the case of a 4-port system is likely to be inappropriate; it requires more information to solve and, as discussed by Teppati and Ferrero [120], may give poor results if the coupling between the ports changes between calibration and measurement. They instead suggest a “half-leaky” model as being appropriate, with coupling between ports in a pair but no coupling between the differential ports. Obtaining sufficient information to solve this model is likely to be difficult; the method presented by Teppati requires known standards, which is not ideal.

In addition to the above approach of regarding the problem as one of calibrating a multiport single-ended system, at least one method has been developed which aims to calibrate each mode (differential and common) separately. This is known as multimode TRL [121, 122]; as the name suggests, it is a generalisation of TRL to lines supporting multiple propagating modes, offering the exciting prospect of being able to calibrate an arbitrary differential system, rather than one for which Equation 3.2 is valid. There do, however, appear to be some potential practical issues with the approach; as discussed in the paper (and is the case for a conventional TRL calibration), as the reference impedance for the calibration is set to that of the lines used for it, it is necessary to determine the even and odd-mode impedances of the lines if the reference impedance is to be known. In addition, and possibly of more practical significance, the assignment of propagation constants to modes fails if they are equal. This would appear to render the technique unsuited to a system calibrated using uncoupled lines (i.e. where the aforementioned mixed-mode transformation is valid). However it appears a potentially useful technique for reference-level calibrations of differential devices, providing the well-known benefits of single-mode TRL.

3.9 Uncertainty

Walters et al [123] made the point that relatively few VNA measurements reported in the literature attempt to estimate measurement uncertainties; although their paper was published in 1992, this regrettably still appears to be the case today. This unsatisfactory situation is most probably because of the complexity and poorly understood nature of the topic. In most common measurement scenarios the measurand is generally a single real quantity, correlations between sources of uncertainty are often insignificant, and it is often possible to obtain a reasonable estimation of the problem by hand by propagation through a measurement model. However microwave measurements tend to take the form of a frequency vector of correlated, complex, variables. These are usually described by multivariate distributions, the manipulation of which

33 has been an area of relatively recent development [124, 125]. Propagation of uncertainties for such data is also often challenging, due to the number of correlations which are required to be considered. Finally, as discussed in [126], even fairly trivial derived measurements tend to involve nonlinear equations. The familiar expressions for propagation of uncertainty assume relationships between measurands and derived quantities which are fairly linear about the value of the measurand; however it is in many cases unclear as to whether this is a valid assumption.

The above factors mean hand analysis of such data is impracticable, and it is possible that poor software support has discouraged workers in the field from attempting the analysis. However considerable progress has, in recent years, been made in understanding the problem as posed and in producing suitable general methods and software to solve it, as evidenced by recent guidance from EURAMET pertaining to the evaluation of VNAs [127]. The trend has been to consider the propagation of uncertainties through a measurement model representing the VNA, as opposed to a classical Type A analysis as undertaken by Walters et al; this permits individual components of the uncertainty to be identified and analysed, and would be expected to give a more general solution. Such a model can be considered a generalisation of the aforementioned error models, incorporating uncertainties in the determination of the calibration co-efficients, noise, drift and any other phenomena identified as contributing to the uncertainty of the final result. Several such models have been proposed; that of Wollensack et al [128] is shown in Figure 3.8. Although perhaps not as general as the model proposed by Garelli and Ferrero [129], which is based on a generalisation of the 12-term error model, it is adequate for the usual situation of switch-corrected data.

Figure 3.8: VNA uncertainty model used in VNA Tools II [128]. S is the corrected data, C the influence of cables and connectors, E and D the calibration error boxes and their drift, W and V the switch term error boxes and their drift, and M the raw data from the VNA with associated errors R due to noise and non-linearity.

The model can then be used to evaluate the effects of uncertain inputs on data measured using the system. The noise and non-linearity of the VNA can be established by evaluation of the system, or often by Type B methods, such as manufacturer data; in general the non-idealities of the analyser can be expected to be a relatively insignificant contribution to the overall uncertainty budget. The effects of cable movement, where applicable, can be similarly evaluated. The modelling of the transitions and non-repeatability introduced by connectors has been an area of active research, in order to facilitate the establishment of traceability to primary standards [130];

34 however this is generally only suitable for relatively well-behaved electromagnetic environments, such as co-ax. In an on-wafer environment, where the discontinuity due to the transition through the probes is electromagnetically complicated, the repeatability of the connexion (including, for on-wafer measurements, that associated with probe positioning) is again best characterised by measurement.

Finally, and perhaps most significant to the overall result, is the effect of the uncertainties associated with the calibration standards. Once again, considerable research has been done as pertains to coaxial standards, motivated by the desire for traceable measurements; coaxial airlines have long been used as primary standards, as their parameters can be calculated exactly [131, 132, 133], and coaxial reflective standards have been modelled sufficiently well as to be used in reference calibrations [134]. However the situation as pertains to on-wafer measurements is once again less straightforward. Calibration techniques such as LRRM use a match standard to set the reference impedance for the calibration; although it is possible to measure its DC resistance, its behaviour over frequency is difficult to determine. The behaviour of reflective standards is also likely to be ill-defined due to substrate losses and possibly issues of contact repeatability. One possible approach is to make use of on-wafer line standards for reference calibrations; at least in the common case of quasi-TEM propagation these can be modelled by closed-form methods with reasonable accuracy for certain geometries [8, 135, 136], permitting calculation of the uncertainty associated with their use. These can then be used to perform a reference TRL calibration, to which a calibration performed using lumped standards can be compared, using, for example, the method of Marks et al [137, 138], to yield an estimate of the uncertainty associated with the lumped-element calibration. Alternatively a hybrid calibration approach, most probably effected by means of an overdetermined optimisation calibration with appropriate weighting, could be performed, using a pair of lines to set the reference impedance at higher frequencies, and the match at lower frequencies. Such approaches, whilst somewhat unsatisfactory with regard to establishing traceability to primary standards, are likely to be sufficient in many cases.

Propagation through the model can be accomplished using either conventional linear uncertainty propagation or by numerical (Monte Carlo) methods. The latter is implemented in the NIST Microwave Uncertainty Framework [139], and is attractive due to its relative simplicity and the generality of the approach; it propagates distributions as well as uncertainties, and does not require linearisation of the model [126]. However, the large number of computations required can be time-consuming. In contrast, linear propagation of uncertainties (LPU) will tend to be faster, and yield good results provided the variance of the variables is not so great as to make the linearisation inaccurate. An elegant method of uncertainty propagation through “automatic differentiation” has been developed by Hall [140]; this facilitates the use of software to perform the computation, and has been implemented in VNA Tools II [141, 128]. The utility of good software support in this regard cannot be overstated; both the aforementioned packages allow the user to measure standards, the DUT, and perform calibration, with end to end propagation of uncertainties and a consequent considerable saving in time and effort.

35 Text added to satisfy minimum ink density requirements on blank pages to minimise warping

36 Chapter 4

Design of Components for Radiation Tolerant Optical Modulator Drivers

The past two decades have seen a substantial increase both in the volume of data transferred across the globe, with Internet traffic continuing to increase exponentially [142, 143], and the speed of the links used to transfer it. This has been made possible by impressive enhancements in the data rates achievable, facilitated by the proliferation of high-bandwidth links, such as fibre optics, and the hardware to drive them. Although modulation schemes for high-speed links have historically tended to use simple two-level Non Return to Zero (NRZ) signalling, the desire to increase spectral efficiency and avoid the requirement for very wideband drivers has prompted a shift towards multi-level schemes such as 4-level Pulse Amplitude Modulation (PAM4) [144]. These bring with them design challenges; the use of multiple levels requires a higher SNR for successful decoding, and makes for smaller eyes in the time domain1. As such, drivers intended for use with such schemes are required to meet challenging specifications with regard to linearity. In addition, the optical modulators used to drive fibre links typically require large (>3 Vpp) voltage swings [145, 146]; achieving these directly is often impracticable, particularly with relatively low-voltage semiconductor processes, and as such differential drivers tend to be employed to effectively double the swing, whilst conferring other advantages with regard to harmonic and common-mode rejection.

During the course of the PhD opportunity arose to design components suitable for use in a PAM4 optical modulator driver on the WIN PP1015 process, a variant of the PP101x 100 nm gate length pHEMT process with a 100 µm substrate and a passivation layer for increased tolerance to moisture [147]. A differential driver and travelling wave amplifier were designed, together forming the portion of an optical system shown in Figure 4.1; as can be seen, the differential driver is intended to receive modulation data from an external source, reject any common-mode components present, and provide a clean feed to the TWA, which acts to provide sufficient voltage

1An eye diagram is a common method of showing the effects of jitter and amplitude variation in the time domain. It is constructed by overlaying the waveforms of multiple bits, acquired at the same trigger point, resulting in an eye shape, the opening in the middle indicating the tolerance to time and amplitude variation available in the system

37 Figure 4.1: Block diagram showing the function of the differential driver and TWA in the context of the overall system. Note PAM4 input data. gain to drive the modulator. This chapter describes the design of these circuits, and presents measured data for both. Methods for ensuring robust electromagnetic simulations are also briefly discussed.

4.1 Electromagnetic Simulation

Although Maxwell’s equations are generally valid, and can hence be used to determine the field behaviour of arbitrary structures, they do not tend to have closed-form analytical solutions except in contrived cases. Techniques have, however, been developed to discretise a problem of arbitrary geometry into a set of structures (such as tetrahedra) whose field distribution can be represented by basis functions which have computable solutions. The Agilent/Keysight Advanced Design System (ADS) integrates two such solvers: MOMENTUM, based on the Methods Of Moments approach for electromagnetics developed by Harrington in the 1960s [148], which discretises the structure into rectangular and triangular elements, formulates Maxwell’s equations in integral form and solves them using a Green’s function approach, and the Finite Element Method (FEM) solver, which discretises the structure using tetrahedra and formulates the equations in differential form. The continued decrease in the cost of computation has led to EM simulations being used throughout the design process, rather than solely as a final verification step, although good engineering judgement is still vital to provide a reasonable starting point for refinement of the design.

However it is important to realise that EM simulation is not a panacea for accuracy; indeed, if the behaviour of the simulator is not well understood, the results may give an impression of precision which is entirely specious. An EM solution is computed only for a discretised form of the design; as such the solution will inevitably have quantisation error at some level, particularly for curved shapes, which are inherently difficult to represent accurately with straight sided objects. In addition, idiosyncrasies or implementation issues in the solver can result in inaccurate solutions. It is therefore important to verify the accuracy of the solver, in much the same way as one would verify any other measurement method, by using it to evaluate a problem with a known solution. This is somewhat complicated by the potential for the accuracy of the solution to depend on the geometry of the problem: although one can, for example, verify the calibration of a VNA by measurement of a coaxial airline of known geometry and thus with a known analytical solution, and thus be confident that measurements of a microstrip line will also be accurate, to perform the same procedure with an EM solver does not verify that the solver gives correct solutions in an environment with multiple dielectrics, or indeed that its discretisation of the problem is fine enough to give an accurate solution in general. It became apparent during the course of this work that, quite often, the FEM and MOMENTUM solvers gave entirely different results for notionally the same problem, with no obvious cause; in addition certain of the port calibration options in

38 MOMENTUM would occasionally give unexpected results. The problem of determining which solution was correct therefore became of paramount importance to establish confidence in the design procedure.

Sonnet Software, a developer of an EM solver, have attempted to address the problem of verification [149], and their suggestions were used as guidance. Since the difference between solvers appeared to be of the nature of a gross inaccuracy, rather than subtle numerical differences, their method of fully de-embedding a line to give a zero-length thru was used [150]. Provided the solver has calculated the line modes correctly, this should give S11 = S22 = 0 and S21 = S12 = 1.

Figure 4.2: Thru de-embedding results for FEM and MOMENTUM EM simulators; detail view of S21 omits results for FEM with default port scaling

This procedure was used to evaluate the FEM and MOMENTUM simulators, using as a test structure a 200 µm long, 10 µm wide line on the first metallisation layer of the process (M1). Solutions were calculated at 26 frequency points, with a separation of 4.4 GHz, from 0-110 GHz. The ports for the FEM simulation were set to use a TML feed; although the documentation concerning this is scanty, this would appear to be designed to excite the structure with a calibrated waveguide port, and presumably remove the effect of evanescent modes excited by the discontinuity between the feed and the structure [151]. Ports for the MOMENTUM simulations were calibrated using TML, where a virtual feed of length λ/2 is added by the solver, to ensure no evanescent modes are present at the port, and calibration structures simulated to allow the effect of the feed to be removed [152]. The TML-zero length feed was also evaluated; although again somewhat scantily documented this appears to be a variant of the TML calibration which does not add an additional feed line; as such the fringing capacitance at the end of the line will be removed, but

39 there is potential for higher order evanescent modes to exist. A final simulation was run with one port calibrated using TML and the other with TML-zero length; this was intended to evaluate the effect of mixing calibrations, as would be required if simulating a structure, such as many IC layouts, with geometry that precluded using TML calibration for both ports due to the virtual feed intersecting other regions of the structure.

The results of this process are shown in Figure 4.2, where TML0 refers to TML-zero length calibration. As expected, the TML-zero length calibration was unable to accurately de-embed the line, although the error is relatively small and is conservative in that it over-estimates losses. The TML calibration with MOMENTUM results in very good de-embedding; the calculated S21 phase is <0.005° at 100 GHz. As may be expected, mixing port calibrations produces results somewhere in between. As can be seen, the FEM results with the default port sizes are non-physical, suggesting that the calculation of the propagation constant for the line was substantially in error. Extending the ports to 100x the dimensions of the line resolves this, producing similar or better results to the MOMENTUM solver with TML calibration.

Although the FEM solver produces good results with the correct settings, the MOMENTUM solver was preferred due to its apparently more robust behaviour; further investigation into the limitations and requirements for accurate FEM solutions would be required to validate this conclusion.

In addition, it is unclear whether the EM stackup provided by WIN gives valid results for objects on the second metal layer (M2). According to the process manual [153] this should be separated from the first metal (M1) by either a thin layer of silicon nitride (SiN) or, in an airbridge environment, by a much thicker layer of air (or the protective coating in the case of PP1015). However, as can be seen in Figure 4.3, the M2 layer is located in the latter position in the stack; this is presumably to avoid over-estimation of coupling between the M1 and M2 lines in airbridges, but means that the thickness of lines formed using both metal layers (double metal lines) will be substantially greater than expected, as can be seen in the 3D EM view shown in Figure 4.4, and that the effective substrate thickness for M2 lines will be slightly greater than expected. Unfortunately this was only discovered too late in the design process to rectify it; however an estimate of the effect of the change in substrate geometry on the line behaviour can be estimated using Wheeler’s empirical formulae [8], reproduced below:

Figure 4.3: EM stackup provided by WIN; note positioning of M2 layer

40 Figure 4.4: MOMENTUM model generated for double-metal line using WIN-supplied EM stackup

  s         2  2 42.4  4h 14 + 8/r 4h 14 + 8/r 4h 1 + 1/r  √ 2 Z0 = ln 1 + 0  0 + 0 + π  r + 1  w 11 w 11 w 1  (4.1)

Where Z0 is the impedance of the line, r is the relative permittivity of the dielectric (a homoge- neous GaAs dielectric with r = 12.9 was assumed), h the thickness of the dielectric (taken to be 100 µm, as is the case for the PP1015 process, although there is little difference in the results of interest if a 50 µm substrate, as is used for PP1010, is considered), and w0 the effective width of the conductor, given by:

1 + 1/r t 4e w0 = w + ∆w = w + ln (4.2) π s 2 2 2  t   1/π  + h w/t + 1.10

1+1/r Where t is the thickness of the conductor, and w its width. The 2 term accounts for the fact that the line is not embedded in the dielectric; this may not be correct in the case of PP1015, where the lines are embedded in the passivation layer, but as r for the passivation layer is low (2.9) this expression should not give significantly erroneous results. t, w and h must be in the same consistent system of units.

41 The additional width (∆w) calculated using Equation 4.2, normalised to the nominal width, is plotted in Figure 4.5a for a range of line widths for double metal lines both of the nominal and Process Development Kit (PDK) thicknesses (3.5 µm and 5.8 µm respectively). The effect of this on the estimated impedance of the lines is plotted in Figure 4.5b.

(a) Normalised estimated additional effective width (b) Estimated Z0 for double metal lines of 5.8 µm for double metal lines on a 100 µm GaAs substrate and 3.5 µm thickness on a 100 µm GaAs substrate

Figure 4.5: Effect of additional double metal line thickness on characteristic impedance

As can be seen, the additional thickness given by the PDK stackup results in a considerable increase in effective width, particularly for narrower high-Z lines as would be used to form matching components in a TWA. However the effect on the characteristic impedance of the lines is significantly lower, to the extent of being negligible; the difference is of the order of 4% for narrow lines, which is likely to be considerably less than other sources of error in the modelling of a first-pass design.

Finally, the effect of the additional effective substrate thickness on the impedance of a line fabricated on the M2 layer is plotted in Figure 4.6, again compared to the calculated impedance of an M2 line with nominal stackup height. In order to give a worst-case result, and to simplify the calculations, a homogeneous 100 µm GaAs dielectric underneath the line was assumed, with air above; this would be expected to give maximum field confinement in the substrate, and, as the dielectric constant of GaAs is the largest of those of the materials comprising the stack, maximum change in the effective capacitance of the line. As can be seen, the difference in impedance due to the additional height above the plane is negligible, giving confidence that the simulations performed using the PDK EM stackup give meaningful results despite the discrepancies between it and that in the process handbook.

4.2 Differential Input Stage

The primary function of the input stage is to condition the signal, attenuating common-mode components and providing a clean differential feed to the output stage. Non-DC common-mode components would tend to arise from non-idealities in the signal source, or asymmetries in the

42 Figure 4.6: Estimated Z0 for 2 µm thick M2 lines at nominal and PDK height on an 100 µm substrate feed; in a communications system the common-mode component of the signal is not used to convey information, and as such amplifying it wastes power and may compromise the output due to intermodulation. Key minimum specifications for the input stage are given in Table 4.1:

Sdd11 (dB at freq.) CMRR (dB at freq.) -15 (14 GHz) 15 (DC-30 GHz) 10 (30-40 GHz)

Table 4.1: Specifications for Differential Input Stage

Sdd11 is the return loss for a differential signal; CMRR was defined to be Sdd21/Scc21, in other words the ratio of differential to common-mode gains into a matched load. In addition it was mandated that the output signals have a suitable DC offset (∼−0.3 V) to provide appropriate gate bias to the output amplifier, avoiding the need for coupling capacitors.

The design arrived at is entirely conventional. Two 2x15 µm transistors form a long-tailed pair, with a 4x15 µm transistor acting as the tail current source. The DC offset to the next stage is formed by load resistors on the pair, with the undesirable side effect of limiting the performance of the stage and compromising the output match at low frequencies. Resistive input termination is used to meet the requirement for low-frequency matching (although, due to a misunderstanding regarding the intended source impedance, they are oversized by a factor of two); a capacitor at the midpoint of the termination provides for termination of common-mode signals. The input and output lines are sized to provide a slight improvement in matching by partially compensating the parasitic capacitances. The circuit is designed to require only a single −3.3 V DC supply; the gate bias for the differential pair is derived through a potential divider from this, and the current source is self-biased through a resistor on its source, which acts to keep the source in regulation.

43 The airbridges required for the DC supply are mirrored on the non-supply side of the design, in order to minimise asymmetry and hence maintain good common-mode rejection.

4.3 Output Amplifier

The output amplifier is intended to be a dual single-ended, as opposed to a true differential, design, as the differential input stage provides common-mode rejection and a single-ended design is considerably simpler to implement. Due to the requirement for wide bandwidth and flat gain, this was designed as a travelling wave amplifier (TWA). This topology, first described in detail in the 1940s by Ginzton [154], uses the input and output conductances of the active devices to form the shunt elements of an artificial transmission line; the series components are formed by additional inductive elements. If the lines are designed such that the phase difference between successive gain elements on the input and output lines is equal the output signals will add in phase, resulting in the travelling waves propagating down the line increasing in amplitude as they do so.

If properly designed, this offers amplification over a very wide bandwidth, although the literature does not appear to agree on the specific bandwidth attainable; 0.8 Fmax, where Fmax is the maximum frequency of oscillation of the device, is proposed as a suitable heuristic by Beyer et al [155], although Agarwal et al suggest [156] a TWA is capable of delivering gain up to Fmax. The two are not necessarily in contradiction; Agarwal et al employ capacitive coupling to lower the gate capacitance seen by the line, and state that this is mandatory to achieve the full theoretical bandwidth. This appears credible as a theoretical limit but may not be practicable, as the maximum gain of the active elements will be unity at this frequency, and their analysis neglects conductor losses in the lines. This wide range of maxima may be due to several factors, including differing definitions of gain and, perhaps more importantly, the difficulty of accurately measuring Fmax; given the frequencies concerned a direct measurement is often impracticable, so an extrapolation of either the maximum gain Gmax or Mason’s unilateral power gain U [157] is commonly used. As shown in the analysis performed by Teppati [158] either of these methods tends to lead to a large uncertainty in Fmax, which is likely to render unreliable such heuristics as mentioned above.

Disadvantages of the TWA include low gain, in comparison to a multistage design fabricated using the same number of gain elements; the gain of a TWA scales with N 2, where N is the number of stages, whereas that of a conventional design will be log-linear in N (i.e. be raised to the power of N). The noise figure also tends to be somewhat mediocre, although this can be reduced by employing unconventional termination arrangements [159, 160]. However, if wideband amplification up to the limits of the gain elements used is desired, the TWA is the only viable choice.

This design, however, is more intended to provide a starting point for refinement, and explore layout options; the bandwidth of the system is in any case limited by that of the input stage. As such, the gain-bandwidth of the amplifier was not maximised, and attempts were instead made to ensure a flat group delay over the ∼50 GHz design bandwidth of the input stage; particularly when employing advanced multi-level modulation schemes, flat group delay is of substantial importance to avoid inter-symbol interference (ISI) and consequent horizontal eye closure [161, 162].

44 4.3.1 Transistor Model Adjustments

Although the process development kit (PDK) provided by WIN includes two HEMT models, derived from HEMTs measured in coplanar waveguide (CPW) configurations (with a source airbridge and the source terminal exposed) and microstrip (with no source airbridge and the source grounded via a via). These configurations are illustrated (not to scale) in Figures 4.7a and 4.7b respectively. However, previous work on the PP1010 variant of the process [163] has suggested the supplied models are somewhat inaccurate, particularly when, as is required to simulate a cascode design, the CPW model is employed in a common-gate configuration. Time constraints, and uncertainty over the effect of the current source topology used for the design on the behaviour of the devices, meant that the accuracy of the models was not evaluated in detail for the input stage described in Section 4.2; however the more relaxed schedule, and the importance of accurate capacitance values in ensuring a successful design, permitted more investigation to be undertaken for the TWA design. In view of the lack of available data this took the form of a best-effort attempt with the data supplied with the PDK, which did not include transistors with a unit gate width below 25 µm in a microstrip configuration or 15 µm in CPW; it is also of generally unknown provenance, and hence the location of the reference planes is debatable, although comments in the files suggest that at least the CPW devices were measured by a Professor Sloan, who is believed to be competent in conducting such measurements.

(a) Layout for microstrip HEMT (b) Layout for CPW HEMT

Figure 4.7: Microstrip and CPW Transistor Layouts

The well-known simplified non-unilateral small-signal equivalent circuit model shown in Figure 4.8 was assumed. The Y-parameter matrix for this circuit, in a common-source configuration, is given by Equation 4.3:

iωCgs ! + iωCgd −iωCgd 1+iωCgsRi gm (4.3) − iωCgd y0 + iωCgd 1+iωCgsRi

45 Figure 4.8: Simple MES/MOD-FET small-signal equivalent intrinsic circuit [164]

Where y0 = 1/Rds + iωCds, and gm = gm0 exp(−iωτ) is the complex transconductance incorpo- rating a phase shift component. The subscripts have been adjusted from Figure 4.8 to make the terminals to which the intrinsics are connected more explicit.

The device capacitances Cgs,Cds and Cgd, together with the transconductance gm, gate-drain resistance Rds, and gate resistance Ri can then be calculated by manipulation of this matrix:

  −ω −1 Cgs = − = (4.4) Y11 + Y12

  Y12 Cgd = −= (4.5) ω

  Y12 + Y22 Cds = = (4.6) ω

Y21 − Y12 gm = iωCgs (4.7) Y11 + Y12

1 Rds = (4.8) < (Y12 + Y22)

 1  Ri = < (4.9) Y11 + Y12

Similar equations can readily be derived for FETs in a common-gate configuration.

The WIN measured data were imported as S-parameter blocks into ADS, and compared with simulations using the WIN models at the same bias points and gate widths. The simulation

46 frequency was fixed to 4 GHz; this was selected to minimise the effect of uncompensated extrinsics, whilst avoiding low-frequency anomalies evident in the measured data. Equations 4.4-4.9 were implemented as AEL functions and evaluated for the Y-parameters obtained by transformation of the S-parameters from the simulations, and the calculated intrinsic parameters thus obtained exported to MATLAB to facilitate least-squared curve fitting to the data. Gate widths in the range 25 µm to 100 µm were used to calculate the fitted curves, and the additional data available for the CPW devices used to verify the applicability of the fit to smaller gate widths.

As expected, a first-order polynomial was sufficient to describe the scaling relationship with gate −1 width for Cgs,Cgd and Rds ; however this was found to be inadequate to describe the relationship between Cds and gate width, as evidenced by the systematic deviations in the residuals shown in Figure 4.9.

(a) CPW devices (b) Microstrip devices

st nd Figure 4.9: Normalised residuals ((fitted - source)/source data) for Cds with 1 and 2 order polynomial fits. Note that only the data for unit gate widths 25 µm, 50 µm, 75 µm and 100 µm were used to perform fitting. Lines are to guide the eye. Note that residuals for linear fit are truncated for CPW.

A quadratic fit to the data resulted in generally good agreement, although slight non-monotonicity can be observed for gate widths in the range 0 µm to 20 µm. Both sets of measured data also exhibited a non-negligible zero gate-width intercept for the extracted capacitances, especially pronounced for Cds for the microstrip device. Although there is not sufficient data available for smaller devices to confirm whether this is physically meaningful or an artefact of over-fitting it is possible that the layout of the device could give rise to such behaviour; as can be seen in Figure 4.7a, the source vias are considerably larger than the intrinsic device, and could be expected to couple to the drain line, resulting in an additional Cds component which would be present even for a zero-width device and hence would appear to be the cause of the observed intercept. There does not appear to be a similar mechanism identifiable for the CPW device; it is suggested that the intercept is more a result of over-fitting in this case, and the non-linearity in the data is due to the source airbridge, which has a fixed minimum width independent of the gate width, and as such would be expected to contribute proportionally more capacitance to a smaller device. The intercepts for the other capacitances suggest that both the measured and modelled data do not represent full de-embedding up to the intrinsic device, resulting in the (fairly

47 constant) gate manifold capacitance being included; this hypothesis, rather than that proposed by Shinghal of the “effective gate width” being a constant value greater than suggested in the PDK, is supported by the absence of such an intercept in the data for Gds, which is expected to be purely a function of gate width due to the general absence of DC conductive paths away from the channel.

Plots of the intrinsics extracted from modelled and measured data, excepting gm, are shown −1 in Figure 4.10 along with the fitted curves; note that Gds = Rds has been plotted as it is the conductance that is expected to be linear with gate width:

Figure 4.10: Measured and Modelled Transistor Intrinsics at 4 GHz; markers denote measured datapoints used to fit curves

As can be seen, the parameters derived from the measured and modelled data are in poor

48 agreement, although they are of the same form. The divergence between the CPW measured and modelled data for gate widths <25 µm is of particular concern given that higher frequency designs tend to use smaller gate widths; the overall impression is that either WIN’s model fitting was poor, possibly to the extent of not using the correct transistor size, or their measured data are suspect. In view of the aforementioned reasonable provenance of at least some of the data, together with the fact that Shinghal also reported poor agreement between modelled and measured data, it seems reasonable to conclude that the former hypothesis is more likely to be correct. It was therefore decided to adjust the models to better match the data.

Figure 4.11: Cell developed to incorporate conductance corrections discussed in this section

Since the parameters of the WIN models do not appear to be accessible through ADS, making direct adjustment of them challenging, the approach taken was to create a parameterised cell, as shown in Figure 4.11, consisting of the WIN models with suitable additional capacitances and resistances to bring the simulated cell intrinsics in line with those calculated from the measured data. This approach made it impracticable to consider the effects of Ri; as such it was neglected in the analysis. Additionally, gm would be expected to be dependent on the DC bias; since there was no obvious way to adjust it, no such adjustment was performed. In general, the difference in the co-efficients of the functions fitted to the measured and modelled data were used to form another polynomial, representing the additional conductance required to align the two data sets; to correct Cds a slightly different approach was taken for the microstrip device, involving computing a suitable correction capacitance on the assumption that the modelled data was linear in 1/Cds. This was roughly valid over the range of gate widths considered, although it would be expected to result in less accurate correction outside of that, and be unstable for very low gate widths. The extracted parameters for the modified cell are shown in Figure 4.12, and compared with those extracted from the measured data.

As can be seen, the adjustment was generally successful in aligning the measured and modelled data, although some divergence can be observed, particularly for large devices, due to the suboptimal method used to correct Cds. This was considered acceptable for the TWA design, which was intended from the outset to use much smaller devices; although some further work could be performed to incorporate a more robust correction method, a preferable strategy would of course be to adjust the models directly.

49 Figure 4.12: Measured and Corrected Modelled Transistor Intrinsics at 4 GHz; lines are to guide the eye

4.3.2 Transistor Selection

A cascode topology (consisting of a device in a common-source configuration driven by the input signal to the cell, and itself driving a device in a common-gate configuration) was selected for the design; this is a common choice for distributed amplifiers as the high input impedance of the cascode reduces the Miller capacitance of the cell, broadening the bandwidth of the amplifier, and the high output impedance reduces losses in the drain lines [165, 156]. Two finger 15 µm devices were selected, somewhat arbitrarily, on the grounds that they were the smallest devices for which measured (CPW) data were available, and a design implemented using them would be expected to provide a reasonable difference in performance from previous designs on the process using 25 µm devices. The common-gate device was increased in size to 2x18 µm during the design process, in order to aid matching of the drain line; as the common-gate device has a high output impedance, dominated by Rds, over most of the frequency band increasing its periphery does not significantly affect losses, and gate-source capacitance of the common-source device, being significantly greater than the drain-source capacitance of the common-gate device, results in it being the primary constraint on the bandwidth of the artificial lines. Although the cascode configuration, in isolation, was, as is often the case [166], only marginally stable, no special measures were necessary to stabilise the amplifier overall. It appears credible that in the TWA configuration the input and output impedances provided by the artificial line, being in the cascode’s region of stability, result in a design which is stable even with reflective port

50 terminations, although further theoretical investigation would be useful to substantiate this conclusion, in particular the potential for oscillations within the amplifier and the effect of the inherent variation of line impedance over frequency.

The nominal bias values given in Table 4.2 were selected to achieve approximately maximum transconductance from the CS device, and provide headroom for the CG device. Limited gain control, whilst maintaining flatness, can be achieved by adjustment of the CG bias (VG2).

VG1 (V) VG2 (V) VD (V) −0.35 1.1 4.0

Table 4.2: Nominal Bias Voltages for TWA. VG1 is the common-source gate voltage, VG2 the common-gate gate voltage and VD the drain voltage for the cascode

4.3.3 Gate and Drain Line Design

The gate and drain lines in a TWA are used to compensate the input and output capacitances of the transistors, in theory forming an artificial transmission line presenting a uniform impedance in both directions. Such structures have interesting properties; they obey similar laws to other periodic structures, such as crystals [167], and can be used as slow-wave structures [168] and for low-loss high power RF transmission for fusion applications [169]. The artificial lines in TWAs can be analysed in several ways; one approach (as used by many authors e.g. [156, 170]) treat it as an LC periodic structure, forming a constant-k filter with a mid-series impedance given by Equation 4.10 [171]:

s  2  0 L ω Z0 = 1 − 2 (4.10) C ωc

Where L is the inductance of the√ inductors connecting the transistors, C the capacitance seen looking into them, and ωc = 2/ LC the cutoff frequency of the filter, i.e. the frequency beyond which it attenuates signals.

An alternative approach is to analyse the line as a transmission line, periodically loaded with the transistor susceptances iB. This will have a characteristic impedance given by Equation 4.11 [172, 173]:

 b b  ±Z0 sinh γl + cosh γl − 0 2 2 Z0 = s (4.11)  b 2 cosh γl + sinh γl − 1 2

Where Z0, γ and l are the impedance, propagation constant and length of the unloaded line, and b the loading impedance or admittance, normalised to the unloaded line impedance or admittance respectively; in the case of a capacitive load C it will be iωCZ0. The propagation constant of the line can be calculated from Equation 4.12:

51 b cosh γ 0l = cosh γl + sinh γl (4.12) 2

Where γ 0 is the propagation constant of the loaded line.

An illustrative comparison of a loaded and constant-k line with identical loading capacitance and design low-frequency characteristic impedances is shown in Figure 4.13. As can be seen, the loaded line displays a significantly lower cutoff frequency, which could present issues for the designer. Another interesting attribute, albeit somewhat irrelevant for the purpose at hand, of the loaded line is the existence of further passbands at higher frequencies; one is evident starting at 500 GHz.

Figure 4.13: Calculated impedances over frequency for representative 50 Ω constant-k and loaded lines with 30 fF shunting capacitance, representing Cgs. Constant-k line has 75 pH series inductors; loaded line has 100 Ω 1 ps connecting lines, equivalent to about 120 µm M2 lines on PP1015 (vp ∼ 1.2 × 108 m s−1)

The loaded line is arguably a better description, particularly in a MMIC implementation, where the tight coupling to the ground plane tends to render inaccurate the lumped-element representations of lines as inductors. It also makes more explicit the relationship between line impedance, the impedance of the loaded line, and the phase shift of the line sections, which is vital to ensure the travelling waves on the gate and drain lines are in phase in order to give constructive√ addition of the drain line waves; the lumped-element representation implies a fixed delay of LC per section, suggesting that the only solution to achieve the phase matching condition with uniform lines is to use capacitive division to equalise the input and output capacitance of the device. However, the equations for the loaded line are somewhat intractable for synthetic purposes, due to the appearance of various terms both inside and outside of the hyperbolic functions, and the interdependence of Z0, γ l and ω make them somewhat frustrating to use for tuning purposes.

52 However for short, lossless, lines, where sinh γl ≈ iβl, Equation 4.11 can be approximated by Equation 4.13:

0 ±iZ0βl ±Z0 Z0 ≈ p = r (4.13) iβl (iωCZ0 + iβl) ωCZ0 + 1 βl

For the purposes of synthesis, this can be readily re-arranged to make βl the subject, allowing the electrical length of the line to be obtained for a given Z0 and loading impedance:

Z ωC βl 0 =  2 (4.14) Z0 0 − 1 Z0

This provides a method to synthesise suitable line parameters for a known loading admittance, provided the approximation is valid; since low-loss lines have a propagation constant which scales with frequency, and a characteristic impedance which is relatively invariant with frequency, this can be ensured by the choice of a suitably low frequency for calculation, and verified by the use of Equation 4.11 with the parameters thus derived.

If βl << Z0ωC Equation 4.13 can be further simplified to:

r 0 ±iZ0βl Z0βl Z0 ≈ √ = (4.15) i ωCZ0βl ωC

Which can be seen to be equivalent to Equation 4.10 with the well-known approximation ωL ≈ Z0βl for short lines and large impedances. However, as shown in Figure 4.14, this approximation tends to be rather inaccurate for realisable line impedances. This may not be an issue in practice; due to the coupling between input and output, the susceptances loading the line are not Cgs and the output susceptance of the cascode, and instead vary in a complicated way with frequency [174], and coupling within the structure is likely to result in the actual impedance and propagation constant of the lines differing from the ideal, and as such any analytical approach is only likely to serve as a starting point for optimisation. However it is possibly desirable to use a reasonably accurate analytical solution as said starting point, and Equation 4.14 is fairly straightforward in its formulation.

This approximate method was used for the design of the TWA; the interconnecting lines for the design were selected to give a notional 50 Ω impedance at 30 GHz, resulting in the line presenting a reasonable output impedance match over most of the band; designing for a good match at higher frequencies resulted in the line’s cutoff frequency falling within the amplifier’s band of operation. The lines were implemented on the M2 layer, in order to maximise their characteristic impedance and hence the accuracy of the approximation in Equation 4.13; it was discovered that the large vias on the PP1015 process made it impracticable to use a conventional layout with two vias per common-source device, at least in a microstrip layout, as even the shortest possible line connecting the gates was excessively long; an unconventional shared via layout was therefore adopted, it being considered that current would largely flow in the side of the via nearest to the device, minimising the detrimental effect of the shared via impedance.

53 Figure 4.14: Loaded line impedances, calculated using Equation 4.11, for βl values calculated 0 using Equations 4.14 (solid line) and 4.15 (dashed line) for a nominal 50 Ω Z0

This also resulted in an unconventional layout having to be adopted for the drain line, as the spacing between the grounding vias for the common-gate devices was not sufficient to permit the drain line to be routed to a free area of the chip, as would usually be the case. It was therefore implemented in an Ω shape in the space between the cells; this has the undesirable effect of forcing the transistor airbridges to carry the full drain current, and as such the number of stages was (somewhat arbitrarily) chosen to be 6 to keep the airbridges within their rated current capability. The layout was refined using EM simulation with the aim of ensuring that the coupling between the drain line and the metallisation surrounding the transistors was not significant, and the gate grounding capacitor-on-via for the common-gate device adjusted to bring the self-resonant frequency for the combination to slightly above the amplifier’s band of operation, in order to avoid it affecting the response beyond providing a small and useful gain peak.

4.3.4 Termination and Bias Supplies

The gate and drain lines in a TWA are, conventionally, terminated in a suitable matched impedance; this approach was taken for this design for simplicity and to reduce the design risk associated with alternative arrangements. The gate line termination is, as would be expected, to provide a good match for the driving signal; the drain line termination is to terminate the backwards propagating signals, as, although attenuated by the phase mismatch between them, if not terminated their reflexions would cause unpredictable interference with the forward- propagating signals. The gate and drain line terminations in this design are similar, comprising pairs of resistors grounded through large (2 pF) capacitor-on-vias. The resistors were initially set to 100 Ω to give a 50 Ω termination; those for the drain termination were subsequently heuristically adjusted to approximately 120 Ω to provide a good balance between gain and flatness thereof. Once again, the layout was refined via EM simulation to provide a good match to the rest of the

54 TWA.

The RF isolation of the DC feed arrangements also requires some consideration, especially at lower frequencies, in order to avoid inadvertently loading the amplifier or providing undesired connexions for signals. This was reasonably straightforward for the gate line supply (VG1); a somewhat crude solution of a high-value (∼1 kΩ) isolation resistor sufficed. This was also adopted for the common-gate bias (VG2), although a resistor was provided for each device to avoid providing an additional signal path between the cells. Such a solution could not be adopted for the drain line (VD), due to the significantly higher currents involved; instead a rectangular inductor, as large as could reasonably be accommodated without increasing the area of the chip, was employed. This was bypassed by a 250 Ω resistor to de-Q the resonator thus formed. The small area of vacant space next to the drain bias pad was used for the provision of decoupling capacitance, in order to avoid, insofar as possible, the unpredictable behaviour of off-chip components affecting the response of the device.

The total area of the design, including pads, is approximately 1170x725 µm, and the simulated DC current draw approximately 55 mA.

4.4 Results and Discussion

Due to the limited availability of measurement equipment, and the timings of the wafer runs, it has only proven possible, through the extreme generosity of Semtech Inc., to perform full measurements of the differential stage at the time of writing. Measurements were conducted using a 4-port Keysight PNA-X N5290A, consisting of a PNA-X N5247B with N5293A extension heads permitting measurement from 900 Hz to 110 GHz. The devices were probed using Cascade Infinity GSGSG probes on a Cacade Summit 12000 probe station, along with two DC probe needles to supply DC bias to the drain and gate pads. A photograph of the setup is shown in Figure 4.15, and the chip with the RF and drain bias probes in place in Figure 4.16. As time constraints did not permit exploration of the system’s true differential measurement capability, the only measurements performed were small-signal (−20 dBm) four-port S-parameter measurements; these were converted to their mixed-mode equivalents using the equations presented in Section 3.7.

Some preliminary results for the TWA have also been obtained, using the same measurement equipment and port power but with GSG probes. A photograph of the TWA with probes in place is shown in Figure 4.17.

4.4.1 Calibration and Uncertainties

For measurement of the differential stage, port calibration was performed at 801 points from 0.01 GHz to 110 GHz using the LRRM-SOLR algorithm (see Section 3.5). Difficulties were experienced in obtaining a successful calibration, initially due to poor probe planarisation resulting from poor planarity of the contact substrate and, after this had been rectified, anomalies at high frequencies, which may be due to crosstalk between the probe tips invalidating the assumption of a non-leaky system implicit in the calibration algorithm. However, an apparently good calibration was obtained for most frequencies below about 70 GHz, which exceeds the usable frequency range of the design. There is, however, an anomaly present in the corrected transmission data for the loopback thru, which demonstrates nonphysical behaviour from about 26 GHz to 36 GHz. The

55 Figure 4.15: Overview of setup used for probing

Figure 4.16: Differential input stage with GSGSG RF probes and DC probe needle in place

56 Figure 4.17: TWA with RF probes and DC probe needle in place

cause of this is unclear; as can be seen from Figure 4.18 it is only evident in the S21 measurement, and not in the reciprocal S12, and it is not evident in any of the other corrected data. As sufficient data were not available to allow uncertainty estimation by propagation through a measurement model, uncertainties were instead estimated from the corrected measurements of the standards. As time did not permit multiple calibrations or touchdowns to be made, as would be required for a conventional estimation of variance from multiple measurements, the covariance matrices for the data were instead estimated by exploiting redundancies in the corrected S-parameter data, making the usual assumptions of normally distributed uncertainties, which were assumed to be primarily associated with the determination of the error boxes, and additionally assuming no covariance with frequency or between parameters other than as discussed below.

The symmetry of the problem was used to identify subsets of each S-matrix which could reasonably be assumed to be drawn from the same distribution. An assumption of reciprocity meant that the Sij terms could be assumed to be independent samples from the same distribution as that describing the Sjis. It was then assumed that, as the standards being measured were symmetrical about both their X and Y axes, the corrected S-parameters would be symmetrical about the S14 − S41 diagonal, i.e. that S13 would be drawn from the same distribution as S24 and so forth. Finally it was assumed that the parameters on each diagonal were also similarly related; this is possibly somewhat dubious in the case of the Siis, although it appears reasonable in most cases, as the open and short standards should present a similar load at each port, and the corrected port matches seen when measuring Sii for appropriate thru standards should also be fairly similar for a good calibration. However it was recognised that the impedance presented by the load standards could, due to the tolerances of the resistors, legitimately vary even for a consistent calibration, invalidating the requisite assumption of equal mean, and as such the load measurements were excluded from the analysis.

This effectively resulted in the following S-matrix being assumed for each standard, where Sa denotes a complex random variable described by its (unknown) mean and covariance matrix.

57 Figure 4.18: Corrected S-parameter data for selected standards, indicating the quality of the calibration achieved. Shaded regions show expanded uncertainties (k = 2). Note anomalous behaviour of S21 for loopback standard, and slight non-physical behaviour of corrected short at high frequencies. Equivalent parameters for other ports are generally similar, except in the aforementioned case of the loopback thru

  Sa Sb Sc Sd Sb Sa Sd Sc S =   (4.16) Sc Sd Sa Sb Sd Sc Sb Sa

The covariances matrices for the real and imaginary components of each S-parameter were esti- mated from the associated parameters described above. The covariance matrices thus determined for each standard were pooled, resulting in a final 801x4x4x2x2 matrix of covariances, comprising a 2x2 covariance matrix for each frequency point and sij. These were then associated with the measured data. As the transformation between single-ended and mixed-mode parameters is linear, propagation of uncertainties to the mixed-mode representations was straightforward, necessitating only the transformation of the covariance matrices in accordance with Equation 3.2, albeit using |M|. The final propagation of uncertainties onto the magnitude and phase data reported in this section was accomplished as described by Hall [175], with the Jacobian matrices derived by hand.

The TWA measurements were taken at 750 points from 0.1 GHz to 75 GHz, with correction performed using the LRRM technique. The preliminary data available do not contain sufficient

58 information to permit any credible uncertainty estimation.

4.4.2 Results for Differential Stage

The measured data for the differential stage, together with simulated data for comparison purposes, are shown in Figures 4.19-4.26, for nominal bias values of VG = −2 V, and VD = −3.3 V; data were also obtained at other bias points close to these, but the performance of the device is similar. The simulated data were obtained by electromagnetic co-simulation of the layout, including the probe pads, so should be expected to be relatively free of unexpected effects due to the probing arrangements. All shaded regions show expanded uncertainties for the measurements (k = 2).

Figure 4.19: S21 for differential and common-mode excitations

59 Figure 4.20: CMRR (Sdd21/Scc21)

Figure 4.21: S11 for differential and common-mode excitations

60 Figure 4.22: S22 for differential and common-mode excitations

Figure 4.23: Sdd11 and Sdd22

61 Figure 4.24: Forward mode conversion terms

Figure 4.25: Differential and common-mode reverse isolation

62 Figure 4.26: Differential mode group delay (gddd21)

As can be seen, the simulated and measured results demonstrate reasonable agreement, at least at low frequencies. In general, the measured data are objectively better than the simulations; in measurement the design exhibits rather greater bandwidth, a flatter response and around 1 dB less attenuation over most of the band. This appears to be due to the absence of the pole at ∼45 GHz which is apparent in the simulated data. The most plausible explanation for this appears to be poor port calibration in the EM simulations; at the time they were conducted the necessity of using one of the TML options to achieve accurate results had not been realised, and it appears that the calibration options used resulted in a considerable over-estimation of the electrical length of the lines in the design.

However, due to the aforementioned misunderstanding concerning the design impedance, the input match is still poor and fails to meet the specification in Table 4.1, although the output match is somewhat better. However the latter is largely set by the resistors used to provide bias to the next stage; consequently it would be difficult to improve without adjusting the DC current through the stage, e.g. by using larger transistors. Common-mode rejection is generally quite reasonable at lower frequencies, as would be expected given the symmetry of the design; it comfortably exceeds the specification. Conversion between differential and common-mode is similarly satisfactory, and as would be expected given the low and relatively flat differential gain the group delay is also flat across the band.

4.4.3 Results for TWA

The simulated and measured results for the TWA are shown in Figures 4.27-4.32, for nominal gate and drain bias values (VG1 = −0.35 V,VG2 = 1.1 V,VD = 4 V); measurements were also obtained for some slightly higher values of VG1, but these do not convey significant further information. No off-chip decoupling, at least in proximity to the chip, was provided, which is

63 likely the cause of the anomalous low-frequency behaviour of the design; this would not be an issue if the circuit were integrated into a practical implementation.

Figure 4.27: S21 and S12 Magnitude

64 Figure 4.28: Rollett Stability Factor (K) for TWA. Y-axis scale truncated to better show limits of stability

Figure 4.29: S11

65 Figure 4.30: S22

Figure 4.31: S11 and S22 (dB)

66 Figure 4.32: Group Delay for TWA. Low-frequency anomalies in measured data likely due to decoupling; Y-axis scale truncated to show data of interest. Variance in measured data generally <10 ps 10 GHz to 50 GHz

As can be seen, the simulated and measured data are in poor agreement. The simulated data demonstrate a reasonably flat ∼10 dB S21 over an approximately 60 GHz bandwidth, after which the response peaks and rapidly rolls off thereafter. In contrast, the measured data demonstrate approximately 3 dB lower S21 over most of the band, with significantly increased ripple and what appears to be a substantial resonance around 70 GHz. It is tempting to identify this with the resonance observed in the simulated data at a somewhat higher frequency, which appears to be due to the common-gate device’s gate grounding circuit going self-resonant, and similarly identify the peak at around 25 GHz with the similar, but smaller, peak observed in the simulated data. An additional deleterious effect of this resonance is to introduce a region of conditional stability to what, in simulation, is a strong and unconditionally stable design (Figure 4.28). As with any multi-device design, there is also the potential for internal oscillations, which may not be visible in external measurements, especially if they are out of the measurement band; although it would be hoped that these would be observable on the setup used for the measurements, the method described by Ohtomo [176] of analysing the cells making up the design might permit the overall stability of the circuit to be quantified.

S22 could be described as qualitatively similar in measurement and simulation; the generally poorer match and increased phase shift observed could be ascribed to the probe launches, which did not form part of the simulation, and the near-180° shift observed at low frequencies could well be attributed to the aforementioned lack of decoupling. S11 differs considerably between measurement and simulation, suggesting poor modelling of the input characteristics of the transistors; this is somewhat surprising given the relatively simple gate line design, although it may be due to the shared source vias or possibly the way the lines are coupled into the gate manifolds.

Group delay variation is, however, reasonable up to moderate frequencies; although it varies significantly at low frequencies in both measurement and simulation, indicative of poor DC

67 bias arrangements, from 10 GHz to 50 GHz both sets of data vary by less than 10 ps, which is comparable with that for other designs with similar bandwidth [177, 178].

4.5 Conclusions

In conclusion, two significant components of an optical modulator driver have been designed, the process of which has identified several issues and idiosyncrasies with the workflow used. Relatively good agreement between measured and modelled data has been demonstrated for the relatively simple differential stage, although the performance of the TWA is disappointing; further work is required to analyse this and determine how much of this is due to inaccurate modelling of the passive components in the circuit versus poor models for the active devices, and evaluate whether the model adjustments performed were a factor. Further characterisation using suitable time-domain signals would also be useful to fully characterise the suitability of the design for practical applications with complex modulation schemes. However it appears likely that the TWA at least is an interesting but ultimately flawed design; the requirement for the drain airbridges to carry the DC current limits the number of stages that can practically be used – although a design with varying gate peripheries [179, 180, 181] may allow this to be increased – and may compromise the thermal characteristics of the design.

Unfortunately it has not been possible to characterise the radiation hardness of the designs described in this chapter, due to the availability of equipment and the circuits not having been diced; it was felt that the owners of the other circuits on the wafer might object to their designs being irradiated. However some characterisation of pullouts fabricated on the closely related PP1010 process has been conducted, and is described in the next chapter; it should, however, be cautioned that it is possible that the thick passivation layer present in PP1015 may compromise the hardness of the design, by providing a location for charges to accumulate.

68 Chapter 5

Measurements on Irradiated GaAs and Silicon Devices

As discussed in Chapter 2, determining the likely radiation tolerance of a particular device is challenging a priori, due to the significant effect of the geometry of the device on its susceptibility, and the general black-box nature of most commercial off the shelf (CoTS) components. Although testing such devices was not the main focus of this PhD, due to the reasonably well-understood nature of the physics of radiation damage, some tests were undertaken on GaAs HEMTs and silicon rotary encoders. This chapter presents these results.

5.1 Tests on GaAs HEMTs

As discussed in Section 2.2.2, it is believed that devices fabricated using III-V compound semiconductors, such as GaAs, are highly radiation tolerant. However this tends not to be purely due to the semiconductors used being intrinsically rad-hard, but is more because of the lack of dielectric layers in typical III-V devices. In addition, results such as those reported in [59] suggest that unexpected behaviours of the process can result in device degradation at much lower doses than would otherwise be expected. It is therefore prudent to characterise a particular process for radiation hardness, rather than relying on axioms concerning the hardness, or otherwise, of a particular material. As no such characterisation appears to have been undertaken on the WIN PP101X family of GaAs processes, it was therefore decided to perform radiation hardness testing on an available set of transistor pullouts fabricated on the PP10-10 variant of the process; this is a fairly typical 100 nm gate length pHEMT process, with a 50 µm thick GaAs substrate and no significant passivation layers.

5.1.1 Experimental Procedure

The 8 dice available were divided into four groups of two dice each (referred to hereafter as Samples I-IV). Samples I and II were irradiated using the 60Co gamma irradiator at the University’s Dalton Cumbrian Facility (DCF), and Samples III and IV used as controls. Due to the handling issues

69 inherent in using bare dice, the samples were irradiated unbiased (with all terminals floating), and equipment availability meant that it was not practicable to make measurements both pre and post irradiation. Samples I and II were placed in the irradiator together, and irradiated at the maximum achievable dose rate of approximately 40 krad min−1 for 60 min. Sample I was then removed and Sample II irradiated for a further 420 min (the maximum practicable over a single working day). Dosimetry data provided by DCF was used to calculate the total dose delivered (approximately 2.4 Mrad for Sample I and 20 Mrad for Sample II). The devices were then transported back to the University for measurement; although it was intended to measure them as soon as possible after irradiation, to avoid the possibility of any space charges developed recombining, equipment and setup problems meant that although DC measurements were made approximately two days afterwards it was not possible to complete the RF measurements until approximately two weeks later.

Small-signal S-parameter measurements were performed on-wafer using the University’s HP 8510C 50 GHz VNA system, a Cascade Microtech Summit 9000 probe station and Cascade Microtech 100 µm pitch ACP GSG probes. DC bias was supplied by an HP 4142B Source/Monitor Unit and associated HP 41420A/41421B units and fed through the bias tees built in to the 8510C. The nominal port output power was set to −5 dBm with the intention of maximising the dynamic range of the measurements whilst avoiding gain compression of the devices under test. Power meter measurements at the VNA front panel suggested the actual output power was of the order of 5 dB lower; probe and cable losses were not characterised but would be expected to be of a similar order. The temperature of the room was neither measured nor controlled, but was not believed to vary significantly over the course of the measurements. Device and calibration standard measurements were acquired using METAS VNA Tools II; as discussed in Section 3.9 this facilitates modelling of the sources of error in the measurement and their propagation through to the final result. Calibration data were obtained by measurement of a Cascade Microtech Impedance Standard Substrate (ISS), and the calibration performed set the reference plane to the probe tips; a lack of suitable on-wafer standards precluded further de-embedding of the access lines to the devices, and as such only comparison within the set of results obtained here is possible. DC monitoring was also performed, in order to identify any gross aberrations due to the irradiation; none were observed, and as the data are generally of poor quality they are not presented in this section.

The supplied dice contained several test structures and pull-outs, although time constraints permitted only the measurement of a cascode cell, consisting of a 2x12 µm common source and 2x15 µm common gate device; this was selected as it was expected that the larger effective device area would increase any susceptibility to radiation. The devices were measured at two sets of nominal bias voltages, intended to be approximately at maximum transconductance (gm(max)) and cutoff, and cold (unbiased) measurements were also taken. These are summarised in Table 5.1; VG2 is the voltage on the gate of the common-gate device in the cascode:

VG (V) VG2 (V) VD (V) 0.0 2.0 0.0 1.0 2.0 4.0 −0.35 2.0 4.0

Table 5.1: Summary of bias points used in the experiment

As the dice were substantially non-co-planar with each other or the ISS, the measurement

70 procedure adopted was to planarise the probes (using pads other than those associated with the device under test), and perform all the measurements for a particular device. All measurements were performed thrice; the order in which measurements at a particular bias were performed within a set was alternated pseudo-randomly, and the probes lifted and replaced, without intentional variation of their XY position, between each measurement.

5.1.2 Principle Components of Uncertainty

The dosimetry data used to calculate the radiation dose received by the devices was determined and provided by DCF. Dose measurements were conducted within the cells of a test rack, giving a spatial resolution of approximately 2.5 cm horizontally, as shown schematically in Table 5.2. The sample boxes used to prevent handling damage to the samples occupied two of these cells; Sample I was placed in cells 1F A and B, and Sample II in 1F C and D.

Dose Rate at position (krad min−1) ABCD 1F 33.326 48.568 47.074 32.519 1B 24.976 30.998 33.299 25.489 2F 18.818 23.207 23.134 18.913 2B 14.903 17.150 16.674 14.743

Table 5.2: Dose rates for cells closest to the 60Co source (at top)

It was assumed that the dose received exhibits a linear variation across the dosimeter reference plane and exponentially with distance from the source, i.e. can be modelled by Equation 5.1; analysis of the data suggests it is better modelled by an inverse-square law, however the exponential function is considerably better behaved numerically and the variation in distance to the source is relatively small.

−by D = e (D0 − a|x|) (5.1)

Where D0 is the dose received directly in front of the source and a and b are fitting parameters.

Least-squares fitting of this model to the dosimetry data was performed, giving a = 5.9 −1 −1 −1 −1 krad min cm , b = 0.13 cm and D0 = 55.3 krad min . Comparison of the fitted curves to the dosimetry data suggested that this model is reasonable for at least the two rows of the rack closest to the source, where the DUTs were placed; although it is likely that the model over-estimates the dose received at the centre of the rack, none of the samples were located there, and it appears preferable to accept this than attempt to fit a higher order polynomial to the limited data available. The quoted uncertainty of the dosimetry data was ±3 %, which was assumed to imply a standard uncertainty of ±1 %, and the uncertainty in the positioning was estimated as being ±5 mm both in the distance to the source and horizontally. As the devices were approximately centred in the sample boxes the average of the dose rates for the two cells occupied by the box was used to calculate the nominal dose rate. The calculated total doses received by each sample, assuming negligible uncertainty in the irradiation timings and no covariance between the parameters, is given in Table 5.3.

71 Sample Dose (Mrad) I 19.7 ± 3.8 II 2.39 ± 0.47

Table 5.3: Total Ionising Dose for each sample, with expanded uncertainties (k = 2)

Uncertainties for the S-parameter measurements were estimated using VNA Tools II. This was used to perform the data capture, calibration, and correction, thus ensuring an unbroken chain of (linear) uncertainty propagation. The calibration standards were modelled as shown in Table 5.4, with “Unknown” denoting a free parameter for optimisation/calculation:

Standard Model Open Unknown capacitance Short Unknown reflectance Load (50.00 ± 0.15) Ω; unknown series inductance Line CPW line with uncertain dimensions

Table 5.4: Standard models used for calibration

Figure 5.1: CPW model analysed by Heinrich, showing parameter definitions [182]. χ is the conductivity of the conductor

The ISS nominal 1 ps line was modelled using the Heinrich model implemented in VNA Tools II and shown in Figure 5.1 [182] with the dimensions given in Table 5.5 and the material parameters in Table 5.6; the material parameters were, where possible, obtained from the ISS datasheet, with standard uncertainties of ±5 % of the value generally assumed. The dimensions were estimated using the positioning micrometers on the prober, with standard uncertainties estimated at ±5 % of the value, with the exception of that of the length of the line, which was dominated by the estimated ±10 µm uncertainty in the probe skate. An educated guess was made for the thickness of the conductor.

Finally, the repeatability of the probe contact was estimated from the variance of repeated measurements of the same standard. Cable repeatability was taken from the manufacturer’s datasheets; this is likely to provide a worst-case bound, as the movement experienced by the cables during the measurements were considerably less than the gross excursions characterised by the manufacturer. The assumed probe and cable standard uncertainties at 50 GHz are summarised in Table 5.7. The trace noise of the VNA was characterised using VNA Tools II; the linearity and

72 L(µm) Wg (µm) W (µm) S (µm) t (µm) 150 ± 10 127 ± 6 50.8 ± 2.5 25.4 ± 1.3 2.5 ± 0.3

Table 5.5: Dimensions used for ISS 1 ps line model

χ (0) r tan δ (35.0 ± 1.8) × 106 9.90 ± 0.05 (1.0 ± 0.5) × 10−3

Table 5.6: Material parameters used for CPW line model drift was assumed to be similar to that for an 8510C system previously characterised at METAS, the data for which were supplied with the application.

Transmission (mag) Transmission (°) Reflexion (mag) Probe ±3 × 10−3 ±0.75 ±5 × 10−3 Cable ±3 × 10−3 ±2 ±1 × 10−3

Table 5.7: Repeatability of cables and probe contact on devices

An initial LRRM calibration was performed, and its coefficients used as the starting point for an optimisation calibration to determine whether any improvement could be obtained. A reasonable calibration was obtained to 50 GHz, albeit with larger uncertainties below about 100 MHz, where the response of the analyser started to roll off.

5.1.3 Results and Discussion

S-parameter data for the device biased at gm(max) (VG = −0.35 V,VG2 = 2 V and VD = 4 V) are presented in Figures 5.2-5.5; the “cold” data exhibited anomalous behaviour, possibly due to the DC supplies floating rather than being driven to 0 V, and as such are not presented here, and the data at the other bias point used do not convey significant further information. All shaded regions show expanded uncertainties for the measurements (k = 2). The data for the two dice exposed to each dose of radiation are plotted separately, and denoted by (A) and (B); the CTRL devices were not irradiated.

As can be seen, no significant change in any S-parameter was observed for the radiation doses to which the devices were subjected.

73 Figure 5.2: S11 for cascode device after various γ radiation doses

Figure 5.3: S12 for cascode device after various γ radiation doses

74 Figure 5.4: S21 for cascode device after various γ radiation doses

Figure 5.5: S22 for cascode device after various γ radiation doses

75 5.2 Test Results for Rotary Encoders

In addition to the measurements on GaAs devices, some testing was conducted on rotary encoders. These are components designed to provide an output indicating the position of a rotating shaft, and are used to provide feedback for systems such as those involving motor control. As much decommissioning activity is performed using remote manipulation, the radiation tolerance of such components is of clear relevance to the decommissioning industry, and, although not directly comparable with the GaAs results provides some indication of the relative hardness of GaAs and silicon devices. Several encoders, manufactured by Avago with part number HEDR-5420, were obtained; as shown in Figure 5.6a these are of the optical type, using a photo-emitter to illuminate a codewheel, which is patterned with alternating reflective/transmissive strips. A photodetector array and appropriate signal conditioning circuitry is used to detect the reflected light and produce a quadrature output (channels A and B), as shown in Figure 5.6b; no index signal is provided. Investigation of the units revealed the IC used to be a multichip module, most probably the the AEDR-8100 [183], integrating the LED and signal processing dice under a plastic lens, raising the possibility of a non-electronic failure mechanism due to the lens fogging. The photo-emitter is most likely a III-V semiconductor, and as such would be expected to be highly tolerant to radiation; however the signal processing circuit is almost certainly silicon, and as such is likely to be the limiting factor in device survivability under irradiation. It is unclear to what extent results obtained from these would translate to other encoders; although it appears reasonable to speculate that devices from other manufacturers may share design characteristics, and hence perform similarly, even nominally identically specified devices from different manufacturers have been shown to exhibit significant differences in behaviour under irradiation [184].

5.2.1 Experimental Procedure

The four encoders tested (Units I-IV) were divided into two groups. Units I and II were irradiated using the DCF 60Co gamma source whilst biased at 5 V, and Units III and IV irradiated unbiased, with all terminals floating; the literature suggests that irradiation under bias may increase the recombination rate of EHPs, and hence increase the device’s tolerance to radiation. The devices were initially irradiated at 67 rad min−1, as determined using DCF’s dosimetry equipment, with the device characteristics being recorded at 1 krad total dose and every 2 krad thereafter; however as the devices proved considerably less susceptible to radiation than originally anticipated a modified technique was adopted, consisting of constant time irradiations with the removal of a lead attenuator between each one, resulting in a doubling of the dose rate. In this manner the devices were irradiated to 120 krad total dose.

After each stage of irradiation, the rise and fall times of the signals on the two output channels (A and B) were measured using the measurement features of an Agilent 2024a DSO; the DC current drawn by the devices was also measured using a Fluke 8010a DMM. Four measurements were conducted of each parameter at each level of irradiation. Due to time constraints, no annealing was performed before measuring the device parameters; it is therefore possible that the results may be affected by dose-rate effects, although, as CMOS devices do not tend to exhibit RHDRS, they should still be reasonably representative.

76 (a) Basic operation [185]

(b) Output signals [183]

Figure 5.6: Block Diagram and output signals for Avago Encoders. Reflexion from the pattern on the codewheel is used to detect movement; edge rate of quadrature channels A and B gives angular velocity, and their phase direction

77 5.2.2 Principle Components of Uncertainty

The uncertainty in the dose received is once again likely to be dominated by the uncertainty in the positioning of the devices. Unfortunately this was not well recorded, and detailed dosimetry data for the experiment is not available. However, since the devices were situated towards the rear of the chamber, the variation in dose with distance would be expected to be considerably less than experienced in the experiment described in Section 5.1, and as such the accuracy of the fitting parameters in Equation 5.1 is less crucial; the dosimetry data used for the aforementioned experiment suggests the change in dose rate across the width of the chamber is negligible, so only the variation due to the uncertainty in the y axis was considered. The fitting parameter b was found to be approximately 0.0428 cm−1 at the rear of the chamber for the available dosimetry data; as discussed, the exponential model used in Equation 5.1 is only an approximation to the reality, although it is reasonably accurate providing the range of y is restricted. The total doses received were calculated assuming negligible timing uncertainty and an uncorrelated uncertainty of ±2 cm in the y position for each stage of irradiation.

The rise-time measurements proved to be fairly repeatable within a set, with the standard deviation of each set of measurements being usually <5 ns (approximately 5 %). However it was subsequently discovered that the method used to generate an edge in the output signals, comprising the application of a light percussive force to the encoder to stimulate a movement of the codewheel, was flawed; the rise/fall times of the signal are affected by the nature of the force used, giving very poor reproducibility. Since there does not appear to be a significant difference in degradation between the biased and unbiased units it has therefore been decided to take the mean of the measurements for all devices, and both channels, giving 8 measurements of rise and fall time at each total dose, with a standard uncertainty estimated from the sample and expanded by a factor of t0.025,8 = 2.3.

However the method used to measure the DC current appears to be sound, and as such results are presented for each encoder. It is uncertain when the Fluke 8010a used for the measurements was last calibrated; as such its quoted one-year uncertainty of ±(0.3 %+1 count) was tripled. However the current measurements are likely of dubious value in any case; the current drawn by the device would be expected to be dominated by the photo-emitter, which, as mentioned above, is likely to be highly radiation tolerant, and the temperature of the chamber was neither measured nor controlled; conversation with the experimental officer suggested it could exceed 40 ◦C whilst the irradiator was operational, which would be expected to affect the current draw.

5.2.3 Results and Discussion

The DC current draw for the four devices is plotted in Figure 5.7, and the rise and fall times in Figures 5.8.

As can be seen, the DC current draw does not appear to vary significantly under irradiation; as discussed in Section 5.2.2 this is to be expected, given the potential for factors such as the temperature change within the chamber to affect it. However the output signals from the devices exhibit a clear degradation in rise and fall times, which is approximately linear with dose. This is initially somewhat counter-intuitive; the asymmetry between rise and fall times suggests the device has open-drain outputs, corroborated by the presence of what appear to be pullup resistors on the PCB, and as such one would expect the negative voltage shift due to radiation-induced charge trapping to give faster fall times and slower rise times. However it is likely that the drive

78 Figure 5.7: DC current consumption for encoders under irradiation. Error bars denote expanded uncertainties (k = 2). The anomalous 0 mA reading for Unit IV at 1 krad was due to a temporary connexion issue

Figure 5.8: Rise and fall times for encoders under irradiation. Error bars denote expanded uncertainties (k = 2 for dose; k = 2.3 for times)

79 stage for the output transistor is push-pull, resulting in both rise and fall times being affected by degradation in both the N and P transistors; under this assumption the higher rate of degradation in the fall times, which are, at least in part, determined by the switching time of the P device, can then tentatively be identified as being due to the generally larger size, and hence greater sensitive area, of such devices, due to the lower mobility of holes in silicon.

It should be noted that the devices appeared to remain functional throughout, although the fidelity of the output to the position of the codewheel could not be verified. This is likely due to the slow speed and hence relaxed timing margins of the device; however it suggests that it may be possible to use such encoders in a moderately active environment without them necessarily being a significant constraint on the lifetime of the system as a whole.

5.3 Conclusions

Although the results for the two sets of devices are clearly not comparable, as their intended functions are substantially different, the difference in radiation tolerance between silicon MOSFETs and GaAs HEMTs is clear, and in accordance with the literature.

As can be seen, the GaAs devices measured are extremely tolerant to radiation, demonstrating no significant change in their RF behaviour after gamma irradiation to (20 ± 4) Mrad. By way of context, this is approximately 30x the total dose experienced by the Galileo spacecraft in its time in the energetic environment around Jupiter [70]. This result is in accordance with the literature discussed in Section 2.2.2, and supports the hypothesis that GaAs devices, such as those discussed in the previous chapter, would have intrinsically high survivability in an environment with radiation hazards. Some further work could be performed on the PP1015 variant, as used for the devices described in Chapter 4; as alluded to in that chapter, it is possible that the passivation layer could act as a charge trap. In addition, it would be useful to characterise the impact, if any, of irradiation on the low-frequency (1/f) noise of the devices; deep traps are believed to contribute to this [186, 187, 188], and have been shown to be affected by radiation [189, 190].

In contrast, the silicon devices exhibited significant degradation in their output characteristics after a total dose of (60 ± 7) krad, although no device failures were observed at the highest total dose tested. Whether this level of radiation tolerance is adequate will depend on the application; however it does not appear improbable that it will be sufficient for many decommissioning applications. It appears likely that the devices are fabricated on an older, larger geometry process; as such more recent designs may be less susceptible to total-dose degradation.

80 Chapter 6

Use of Lossy Transmission Line Stubs to Improve Matching of Microstrip Loads

Resistive match standards are an important element in several common calibration algorithms, in particular SOLT/SOLR and the LR(R)M family [191, 96, 86, 92, 91], where they are used to set the reference impedance for the calibration. However, such structures are known to have unsatisfactory characteristics above DC, where circuit parasitics result in both a change in reactance [192] and a quadratic variation in resistance [193] with frequency, exacerbated in the case of a microstrip design by the need for a highly reactive grounding via.

It is possible to remove the effects of undesired reactances; careful optimisation of the geometry of the design can yield good results, as demonstrated by the 90 GHz load presented in [194], and (as is well known) lumped or distributed matching elements can be used to compensate for undesired reactances, as in [195, 196]. In addition, some calibration algorithms, such as LRRM and its developments [96, 97], use a model for the load which permits the removal of reactive elements, assuming they can be modelled, to a reasonable approximation, as a series inductance. Elimination of the variation in the real component of impedance with frequency is rather more complex, but can be achieved by adding line standards to allow a partial TRL [101] calibration to characterise the match standard, as suggested in [102], or by employing a better model of the standard [94]; however it is arguably desirable to improve the behaviour of the load standard at the design stage if possible, as this also has the advantage of improving performance if similar structures are used for termination as part of a larger design, as in Chapter 4, where it is clearly impossible to compensate for poor analogue performance in software.

It has been suggested (Robin Sloan, personal communication, 2016) that intentionally lossy matching stubs can achieve this, but this does not appear to have been extensively investigated; Monje et al [197] employ a fully distributed lossy stub as the load standard, a concept which was recently further developed by Morimoto et al [198] and Lomakin et al [199], but this has the disadvantage of poor low frequency performance, which would be particularly problematic for designs such as that described in Chapter 4. Shinghal ([163], page 231) mentions en passant their use to ensure stability of a TWA, but does not provide analysis nor justification for this approach.

81 This chapter, therefore, presents a rudimentary analysis of such a stub, and EM simulation results and comparison with non-lossy stubs for its implementation as a matching element for a microstrip load standard on a commercial MMIC process.

6.1 Background

Short stubs of open or short circuited transmission line are commonly used components for the matching of microwave circuits, and the basic theory is well-known (see for example [200]). For an ideal, lossless, line with a purely imaginary propagation constant γ = iβ, the open or short circuit at the end of the stub is transformed back in accordance with Equation 6.1:

Zl + iZ0 tan βl Zin(−l) = Z0 (6.1) Z0 + iZl tan βl

Where Zin is the transformed impedance at some distance l from the end of the line, and Z0 the characteristic impedance of the line, which is conventionally computed using Equation 6.2:

r L Z0 = (6.2) C

Where L and C are the per unit length inductance and capacitance of the line, and Zl the terminating impedance at the end of the line. For the common case of an open-circuit stub with infinite terminating impedance, this reduces to:

Zin(−l) = iZ0 cot βl (6.3)

Equation 6.3 shows that, for the ideal lossless stub, the only impedances that can be realised are purely imaginary (or zero or infinite). This is not an issue if the stub is being used to compensate for an undesired admittance, but clearly precludes their use for compensating for variations in resistance of the type discussed above. However, in the more general case of a lossy line, with a complex propagation constant γ = α + iβ, the trigonometric functions are replaced with their hyperbolic counterparts [201]:

Zl + Z0 tanh γl Zin(−l) = Z0 (6.4) Z0 + Zl tanh γl

And a more general form of Equation 6.2 is used:

s (R + iωL) Z0 = (6.5) (G + iωC)

Where R and G are the per unit length resistance and conductance of the line.

82 For a line with R >> ωL and ωC >> G (as is typically the case for a resistor fabricated on a MMIC process with an insulating substrate), this reduces to:

r r −iR R Z0 ≈ = (1 − i) (6.6) ωC 2ωC

Similarly, the propagation constant will tend to:

r √ ωRC γ ≈ iωRC = (1 + i) (6.7) 2

Both the characteristic impedance and propagation constant of the line will have real and imaginary components equal in magnitude, and varying with the square root of the frequency. This is in contrast to a lossless, or slightly lossy, line, where the impedance is primarily real and fairly constant over a wide range of frequencies.

Given that it is desired that the stub have little effect on the behaviour of the standard at low frequencies, it is clearly preferable to employ an open-ended rather than a short-circuited stub. Equation 6.4 can therefore be reduced to:

r r R ωRC Zin(−l) = Z0 coth γl ≈ (1 − i) coth l(1 + i) (6.8) 2ωC 2

6.1.1 Transmission Line Parameter Calculation for Stub

Design of such a stub clearly necessitates determination of Z0 and γ for the line. It is ideally desirable to determine these from the geometry of the line, to permit the use of simple expressions to synthesise solutions; however the unusual electromagnetic behaviour of the line raises questions as to how to approach this. The standard approaches for calculating the parameters of a microstrip line tend to follow an electrostatic approach, and assume a quasi-TEM propagation mode [8, 202, 203]; however their applicability to the situation under consideration here is unclear, as the finite conductivity of the conductor will clearly result in there being a non-negligible E-field in the direction of propagation. A full analytical solution to any microstrip problem is necessarily complicated by the discontinuity in the dielectric, and given the complexity of the general analytical solution for the relatively simple geometry of the coaxial line [131] it is not proposed to perform a full analysis of this problem. However, as a first assumption it would appear reasonable to assume the dominant mode is one which is approximately TEM, albeit with an E-field component within the conductor directed along the axis of propagation with a magnitude of J/σ, and proceed by verifying that the use of expressions intended to determine the line parameters in the lossless case is both theoretically sound and leads to values for Z0 and γ in agreement with those extracted from EM simulations.

As discussed in Marks and William’s 1992 paper [9], the use of circuit parameters in Equations 6.2 and 6.5 is arguably not generally valid; these equations relate Z0 and γ, which are properties of the fields on the line, to a set of circuit parameters, without establishing the relationship between the fields and parameters. They instead derive more general equations relating Z0 and γ to the (normalised) fields associated with a propagating mode, which are valid in situations, such as

83 waveguides, where the analogies with circuit theory required to derive Equations 6.2 and 6.5 are arguably somewhat meaningless. These can be applied to the problem at hand to relate the RLGC parameters of the line to its material properties, both providing synthesis equations and a measure of confidence in the validity of line parameters extracted from EM simulated results. The aforementioned equations are reproduced below:

Z Z  1 0 2 0 2 C = 2  |et| dS − µ |hz| dS (6.9) |v0| S S Z Z  1 0 2 0 2 L = 2 µ |ht| dS −  |ez| dS (6.10) |i0| S S Z Z  ω 00 2 00 2 G = 2  |et| dS + µ |hz| dS (6.11) |v0| S S Z Z  ω 00 2 00 2 R = 2 µ |ht| dS +  |ez| dS (6.12) |i0| S S

Where the integration is over the cross section of the line, v0 and i0 are normalising parameters 0 00 0 00 used to define the magnitude of Z0, µ = µ + iµ and  =  + i the complex permeability and permittivity of the substrate respectively (with metal conductivity being absorbed into the 00 term), and the waves on the line assumed to be propagating in the +z direction with a propagation constant γ = α + iβ.

As can be seen, the capacitance of the line is governed by the transverse electric and axial magnetic fields. If we assume the model suggested above, whereby the only axially directed fields are the J and E fields within the conductor, the second integral in the expression will vanish, and the capacitance will be similar in magnitude to the pure TEM case. A similar argument can be advanced for L.

Similarly, if we assume the only losses in the line to be ohmic losses in the conductor (i.e. µ00 = 0, and 00 = 0 outside the conductor), and the axial E-field within the conductor to be given by Ohm’s Law (i.e. ez = jz/σ), the first integral in the calculation of R will vanish and the second reduce to1:

Z Z Z 00 2 σ 2 σ 2  |ez| dS = |ez| dS = |ez| dA (6.13) S ω S ω A

Where dA is the area of the conductor, as the axial E-field is zero elsewhere.

If we define the field normalisation i0 by applying Amp`ere’slaw around the boundary of the cross section of the line, i.e.:

I Z Z i0 = ht · dl = j · dS = σ ez dA (6.14) S A 1The normalisation of σ by ω is required in order to permit it to be absorbed into ; this can be seen by writing Maxwell’s curl equation for H for the case of a lossy dielectric  = 0 − i00, J = σE and the usual assumption of iωt 0 00 σ an e time dependence, giving ∇ × H = iωE + σE = iωE( − i( + ω ))

84 Then Equation 6.12 reduces to:

ω  σ Z  1  Z  R |e |2 A σ |e |2 A = 2 z d = 2 z d (6.15) |i | ω A R A 0 σ A ez dA

In general, the distribution of ez will be nonuniform over A. However, provided the skin depth of the conductor is considerably greater than its smallest dimension, ez will be approximately constant over the cross-section of the conductor. Equation 6.15 will then reduce to:

1  Z  1 R σ|e |2 A = 2 2 z 1 d = (6.16) 2 R A σA σ |ez| A 1 dA

The skin depth for the mesa resistor, given approximately by Equation 6.17, is approximately 2.5 µm at 100 GHz, which is considerably greater than its 0.19 µm thickness; it therefore appears reasonable to assume that Equation 6.16 is applicable, and the resistance of the line will be approximately equal to its DC value.

r 2 δs = (6.17) ωµσ

Finally, if the dielectric is lossless (µ00 = 0 and 00 = 0 outside the conductor), the G term can immediately be seen to be zero.

The above gives confidence that conventional methods for computing the parameters of microstrip lines will give reasonably accurate results for the field distribution assumed.

6.2 Implementation and EM Simulated Results

In order to validate the theory stated above, electromagnetic simulations were performed using stackup data for the WIN Semiconductor PP1010 process, selected on the grounds that it has been used for previous designs developed at the University. This is an 0.1 µm gate length GaAs PHEMT process, with a 2 mil (50 µm) substrate thickness, and provides two types of resistor: a thin film resistor (TFR) with a resistance of 50 Ω/2 and a mesa resistor with a resistance of 137 Ω/2 [153]. The stubs were designed on the mesa layer, as its higher resistivity maximised the loss of the lines, and ensured the simplifying assumptions made in Equations 6.6 and 6.7 were valid over a broader frequency range.

The Keysight Advanced Design System 2017 (ADS) was used to perform all simulations. As discussed in Section 4.1, it integrates two EM solvers: one employing the Method of Moments (MO- MENTUM) and the other the Finite Element Method (FEM). As discussed in the aforementioned section, obtaining agreement between the two solvers proved challenging; although adjusting the port settings and adding a length of feed line to permit the fields to stabilise improved agreement between them, it was eventually decided to use MOMENTUM for all calculations, with TML calibrated ports. All EM simulations were performed from 0 GHz to 100 GHz; adaptive frequency sweeps were used to obtain initial results, followed by linear sweeps at 26 frequency points (4 GHz

85 intervals) to provide more detail and check for unexpected narrowband phenomena, although in practice no significant discrepancies between data obtained from the two sets of sweeps were noted. The mesh density was set to 30 cells/wavelength, and edge meshing used; although no quantitative comparisons were performed this is expected to increase the accuracy of the results compared to the default settings of 20 cells/wavelength and no edge meshing, as the smaller mesh cells would permit more granularity in the determination of the fields.

6.2.1 Simulation and Evaluation of Match Standard

The microstrip resistor was implemented using a TFR in order to ensure the applicability of the results to standards previously designed on the process. The width of the resistor was chosen to be as close to the width of the terminating via and feed line as permitted by the design rules, with the aim of minimising the effect of the discontinuity in width between the two. As mentioned above, a short (75 µm total metal length) feed line was added, with the aim of minimising the effect of evanescent modes; the 35 µm width gives an impedance of 50 Ω at low frequencies, reducing to around 47 Ω by 100 GHz. The reference plane shift for the port was initially set to 70 µm, i.e. 5 µm from the leftmost point of the load, in order to minimise the effect of the impedance transformation along the length of the feed line, whilst avoiding attempting to de-embed beyond the discontinuity in the line caused by the load resistor; further simulations were conducted with a 50 µm reference plane shift, in order to permit the effect of the resistive stubs to be separated from that of the additional length of line necessary to accommodate them. The simulation layout is shown in Figure 6.1.

Figure 6.1: Layout for 50 Ω microstrip standard, showing EM port

S11 for the microstrip load is shown in Figures 6.2a and 6.2b. As can be seen, the reactance looking into the load increases significantly across the band, and the real component of the impedance also increases slightly, which together contribute to the rather poor return loss of > − 20 dB above 60 GHz. The shift in reference plane results in this being transformed through the additional line length, resulting in some of the reactance appearing real. The calculated change in resistance and reactance are shown in Figure 6.3 for the two reference plane shifts described above.

86 (a) Return loss

(b) Smith chart

Figure 6.2: EM simulated performance of 50 Ω microstrip match standard

87 Figure 6.3: Change in reactance and resistance over frequency for microstrip match standard

A simple model fitting exercise was then undertaken, in order to better understand the origins of the increase in reactance and provide confirmation of the plausibility of the results; as the propagation constant of the TFR, approximated using Equation 6.7, is of the order of 1.2 × 104 rad m−1 at 100 GHz, and hence the resistor has a (round-trip) length of ∼0.1λ, it would be expected that a lumped approximation would be reasonable for much of the frequency band of interest. The optimisation function in ADS was used to fit a model consisting of a parallel RC arrangement, representing the resistor, in series with an inductor, representing the via, to the EM simulated data. The model proposed by Walker et al [192], comprising a similar arrangement but with the capacitor in parallel with the series combination of inductor and resistor, was also evaluated, but did not give as satisfactory an agreement, with larger residuals and what appeared to be less plausible parameter values. The equivalent circuit thus obtained is shown in Figure 6.4.

6.2.2 Stub Parameter Calculation and Design

As discussed in Section 6.1.1, it appears to be appropriate to model the line using the conventional RLGC model, with parameters derived using methods developed for microstrip lines. These were therefore used to develop a simple analytical model for the line. As previously discussed, G and L are likely to have an insignificant effect on the line parameters; they were therefore ignored. Computation of R was straightforward; the bulk conductivity was derived from the resistance and layer thickness given in the process manual to be 3.84 × 104 0, giving (unsurprisingly) 137 Ω/width/m. Determination of the line capacitance was less straightforward; the multiple dielectrics in microstrip do not permit a straightforward analytical solution to the problem, so empirical approximations tend to be used instead. The situation is further complicated in a MMIC process by any additional dielectric layers, such as those used for passivation, around the conductors; many published solutions are only valid for a single homogeneous dielectric below the conductor and assume the dielectric above the conductor has r = 1. However the PP1010

88 Figure 6.4: Equivalent circuit for microstrip load. R = 50 Ω, L = 20 pH, C = 4.3 fF. Values for L and C obtained by optimisation process considered here does not feature significant thicknesses of such layers around the mesa layer used for the lossy line, and as such it is reasonable to assume approximations derived for a single dielectric are valid. Wheeler’s formula, in the form proposed by Bogatin with Schneider’s eff [204], was used, and is reproduced in Equation 6.18; Svaˇcina’sapproximation [136] was also evaluated but appeared to exhibit some numerical instability for the geometries under evaluation, giving unexpected filling factors and results.

1 C = 12.670eff   s  (6.18)  1 8h 8h 8h 2  ln 1 +  + + π2   2 weff weff weff 

Where h is the height of the dielectric (in this case 50 µm GaAs, r = 12.9), weff is as in 1+1/r Equation 4.2, but omitting the multiplication by 2 , and eff is given by Equation 6.19:

r !−1 r + 1 r − 1 10h eff = + 1 + (6.19) 2 2 w

Figure 6.5: Lossy mesa line used for parameter extraction. Small M1 regions are to establish a conductive path from the port. Line was parameterised in width and length.

89 Figure 6.6: EM simulated and calculated Z0 for lossy line. Colours indicate width; line styles indicate real and imaginary components of simulated and calculated results

The line parameters were then calculated using Equations 6.6 and 6.7 and compared to those extracted from EM simulations of a length of lossy line, shown in Figure 6.5, using the equations −γl for e and Z0 derived by Einstadt and Eo in [205]. Simulations were performed from 1 GHz to 100 GHz for line widths from 5 µm to 25 µm, in 5 µm increments, and line lengths from 50 µm to 300 µm in 50 µm increments. As may be expected the calculated γ values exhibited apparent numerical instability for the longer line lengths, so only the results for lines of length 50 µm and 100 µm were used for further analysis; however the calculated Z0s were in good agreement for all line lengths, varying by <1 %, so the full set of values was used. The mean values of the extracted parameters for various line widths are plotted, along with the calculated values, in Figures 6.6 and 6.7.

As can be seen, the calculated and extracted impedances are generally in agreement, with their imaginary components being almost identical for all line widths, although a marked divergence can be observed in the real component for the narrower line widths. The agreement between the two sets of γ values is less good, with the divergence again becoming more pronounced at higher frequencies and for narrower lines. The reason for this is unclear; although the simple model used does not account for inductance or conductance, their inclusion would affect the real and imaginary components of Z0 equally. Extraction of the RLGC parameters for the simulated data, using the relations γZ0 = R + iωL and γ/Z0 = G + iωC, did not provide further insight; although they suggested the line has a significant, negative, inductance component (which is not forbidden by Equation 6.10, although it suggests that the assumption of zero axial electric field external to the conductor was in error), incorporation of this into the calculations affected both

90 (a) α

(b) β

Figure 6.7: EM simulated and calculated γ for lossy line. Colours indicate width; line styles indicate real and imaginary components of simulated and calculated results

91 the real and imaginary components of impedance equally, as expected. It is possible that the calibration of the EM ports was imperfect, or that this is indicative of the presence of additional modes; further work is required to investigate this. However, in general the results suggest that the assumptions made in deriving Equation 6.6 are reasonable as a first approximation.

Figure 6.8: Layout for microstrip load with lossy matching stubs

The calculated values were used to determine suitable dimensions for the stubs in the layout shown in Figure 6.8. In view of the somewhat intractable nature of Equation 6.8, MATLAB was used to calculate the input admittance of stubs of various dimensions, from 5 µm to 15 µm in width and 0 µm to 200 µm in length, and select that which best compensated the change in admittance of the load over frequency; this is equivalent to minimising Equation 6.20:

2 X  1  < (Yl,f + 2Ystub,f ) − (6.20) 50 f

Where Yl is the admittance of the load, Ystub is the admittance of the lossy stub, given by Equation 6.8, the summation is over all frequency points under consideration and the multiplication by two is to account for the admittance of both stubs.

This function was evaluated for the aforementioned range of stub widths and lengths, and is plotted against stub length in Figure 6.9. As can be seen, increasing the stub length beyond around 100 µm does not significantly decrease the value of the function, suggesting that very long stubs will not significantly improve performance over the entire frequency range, and will be wasteful of area. In general, wider stubs offer better performance; however it should be

92 Figure 6.9: Equation 6.20 plotted against stub length for various widths cautioned that, in practice, if the stub is excessively wide the variation in the fields across its width may become significant, invalidating the implicit assumption that the stub behaves as a lumped admittance, and excessively wide stubs will require more area. The layout in Figure 6.8 was EM simulated with stubs of 5 µm and 10 µm width and 40 µm and 70 µm length, selected to provide an indication of the accuracy of the theory and the magnitude of the changes effected by the addition of the stubs. The simulated conductance for these combinations is plotted in Figure 6.10, along with the calculated admittances and the admittance of the load, simulated at the same reference plane, without the stubs.

As can be seen, the agreement between the EM simulated and calculated data is somewhat poor, although they are of the same form. As predicted, the 40 µm stubs are insufficient to fully compensate the decrease in conductance with frequency, although they still offer an improvement in matching compared to the load without stubs. This is evident in the return loss plot in Figure 6.11; both 10 µm width stubs provide a useful ∼4 dB improvement in return loss towards the top of the band. Since all the data lie towards the middle of the Smith chart, and the variation in impedance is relatively small, it is not a helpful way to visualise the data in this case.

6.3 Conclusions

In conclusion, a preliminary analysis of an unusual type of transmission line stub has been undertaken. A very simple theoretical approach has been shown to give reasonable agreement with results obtained by electromagnetic simulation, and the design arrived at to be capable of compensating a decrease in admittance to provide a small but respectable improvement in the return loss of a microstrip load resistor at high frequencies.

The main application for the technique would appear to be in increasing the quality of broadband

93 Figure 6.10: Simulated and calculated conductance for 50 Ω (20 m0) load with various stub geome- tries. Colours indicate width; line styles denote simulated and calculated results. Conductance without stubs also plotted for comparison

Figure 6.11: Simulated S11 for load with various stub geometries. Conductance without stubs also plotted for comparison

94 on-wafer terminations, where the compact nature of it is likely to facilitate matching in space- constrained layouts, rather than providing improved loads for calibrations relying on resistive standards; the addition of the stubs results in a somewhat unpredictable variance of impedance over frequency, which is likely to confound methods, such as LRRM, which attempt to use a model of the load to remove the effects of reactances. Another potential application is for the provision of small loading admittances at high frequencies, for example to improve stability. Although this work is conceptually similar to the lossy printed stubs described at the start of the section, the application is somewhat different; the frequencies are rather higher, and the function of the lossy stub is to, using minimal additional area, improve the quality of broadband terminations, rather than to use the stub as the only terminating impedance in the circuit.

Further measurement work is obviously required to validate these conclusions; since to conclude whether the stub is beneficial will inevitably require the calibration reference impedance for said measurements to be, at a minimum, well-known this is likely to require a TRL calibration and careful experimental work, lest an erroneous impression of performance be arrived at. Additional useful further work would be to evaluate the performance of alternative geometries; although Morimoto et al consider a radial geometry, their results demonstrate considerable variance between samples and differ from the theory, making it difficult to draw definite conclusions as to its validity.

95 Consummatum est

96 Chapter 7

Conclusion and Further Work

In conclusion, investigations have been undertaken into several areas of relevance for the develop- ment of electronic circuits capable of functioning in the presence of radiation, with a particular focus on GaAs circuits for communications. The designs developed are believed to be highly radiation tolerant, and perform respectably well it is hoped that it may serve as a vehicle for future development. During the design of the circuits, some useful insights into the behaviour of a commercial electromagnetic simulator were obtained; these may be of use for future workers in the field, and at least some of them are likely to be relevant to other electromagnetic simulation packages.

One interesting concept which does not appear to have been extensively covered in the literature is the use of intentionally lossy lines; although only simulated results have been thus far obtained, they suggest that the technique has promise in applications outside of those described in the existing literature. The theoretical approach employed is somewhat different from that used by previous authors, and yields some useful approximations for the MMIC case considered; although the modern proliferation of computing power renders them less important for design purposes, they provide some intuitive insight and justification for a simple synthetic approach.

Finally, some measurements of device degradation have been undertaken. These are generally in accordance with those found in the literature, with the GaAs devices measured demonstrating extremely high total ionising dose hardness and the silicon devices being more susceptible. The results are useful in that neither the process used to fabricate the GaAs circuits nor the specific rotary encoder tested are believed to have been tested for radiation hardness before; they can therefore be used to inform component selection for future projects. The GaAs results may prove of particular use as the WIN foundry is relatively low cost and does not claim radiation hardness as a feature of its process; poor radiation tolerance would therefore have been less unexpected than it would for, for example, a process with pretensions to use in aerospace applications.

97 7.1 Further Work

The most fruitful area for additional research is likely to be the lossy stubs discussed in Chapter 6; if the theoretical and calculated results are confirmed by measurement the technique appears to be of practical benefit for certain applications in MMIC design. As discussed in the aforementioned chapter, further investigations into optimising the geometry of the stub, in particular whether radial shapes are of benefit, will be of use to quantify the performance improvement attainable. In addition it would be useful to identify the cause of the discrepancy in real impedance between the simulated and calculated line parameters, ideally by a more comprehensive theoretical analysis of the modes supported by the line geometry.

The significant discrepancies between the measured and simulated results for the TWA discussed in Chapter 4 are also worthy of investigation. Although it is possible that the model adjustments made are at least partially responsible, simulation of the design without the adjustments did not significantly affect the alignment of simulated and measured data. The most plausible reason, at this time, appears to be poor EM modelling of the relatively compact layout; it remains to be determined which aspect of this was most significant, although the points where the transistor models feed into the EM models (i.e. the common-gate grounding circuit and the gate and drain lines) are potentially suspect. The challenges in determining this lie, as ever, in achieving accurate EM port calibration and ensuring that the reference planes are set correctly; the interface between EM simulated portions of the design and the device models are also an area of uncertainty, as the models do not include, for example, coupling between the parts of the design represented by them and the rest of the layout. This may be especially problematic for the TWA design due to the use of the transistor airbridges as a crucial component of the drain line, as they are part of the device models and are not EM simulated.

Further radiation tolerance measurements would also be of use; although the aggregate data for the encoders appears reasonable, it may be beneficial to devise an improved experimental procedure, with better reproducibility and ideally the provision for detecting a failure of the device to correctly report motion of the codewheel. Since no degradation of the GaAs devices was observed, further testing to much higher doses, and if possible observation of their noise characteristics, is an obvious area of further work; unfortunately it does not appear to be practicable to measure their characteristics whilst being irradiated, due to both the difficulty of routeing RF cables out of the chamber and the tendency of polymers to degrade under γ irradiation.

Finally, the institutional decadence of the University of Manchester cannot go unrecognised. The short-termist focus on fashionable areas of research, together with a small-minded and target-focused bureaucracy, has resulted in fundamental electronics being neglected at every stage. It is unfortunate when, as typified by the short-sighted and fiscally motivated MECD project and consequent systematic rundown of the former UMIST campus, an institute of learning puts monetary profit ahead of student education and research quality.

98 References

[1] L. Strauss, “Remarks Prepared for Delivery at the Founders’ Day Dinner, National Associa- tion of Science Writers,” p. 9, 1954. [2] S. Hinson, “New Nuclear Power,” House of Commons Library, Tech. Rep. June, 2018. [3] A. Andrews, “Nuclear Fuel Reprocessing: U.S. Policy Development,” The Library of Congress, Tech. Rep., 2006.

[4] The National Audit Office, “The Nuclear Decommissioning Authority: Taking forward decommissioning,” 2008. [Online]. Available: http://www.nao.org.uk/publications/0708/ the nuclear decommissioning au.aspx [5] United States NRC, “IE Information Notice No. 82-31: Overexposure of Diver during Work in Fuel Storage Pond,” United States NRC, Tech. Rep., 1982.

[6] IAEA, “Exposure of a worker in excess of statutory annual dose lim- its,” 2010. [Online]. Available: https://www-news.iaea.org/ErfView.aspx?mId= b882511c-0517-4698-8d56-df42e0d60739 [7] Sellafield Ltd, “About Us.” [Online]. Available: https://www.gov.uk/government/ organisations/sellafield-ltd/about [8] H. Wheeler, “Transmission-Line Properties of a Strip on a Dielectric Sheet on a Plane,” IEEE Transactions on Microwave Theory and Techniques, vol. 25, no. 8, pp. 631–647, aug 1977. [9] R. Marks and D. Williams, “A General Waveguide Circuit Theory,” Journal of Research of the National Institute of Standards and Technology, vol. 97, no. 5, p. 533, sep 1992. [10] J. Leavy and R. Poll, “Radiation-Induced Integrated Circuit Latchup,” IEEE Transactions on Nuclear Science, vol. 16, no. 6, pp. 96–103, 1969. [11] D. Binder, E. C. Smith, and A. B. Holman, “Satellite Anomalies from Galactic Cosmic Rays,” IEEE Transactions on Nuclear Science, vol. 22, no. 6, pp. 2675–2680, 1975.

[12] A. E. Waskiewicz, J. W. Groninger, V. H. Strahan, and D. M. Long, “Burnout of Power MOS Transistors with Heavy Ions of Californium-252,” IEEE Transactions on Nuclear Science, vol. 33, no. 6, pp. 1710–1713, 1986. [13] R. C. Baumann, “Radiation-induced soft errors in advanced semiconductor technologies,” IEEE Transactions on Device and Materials Reliability, vol. 5, no. 3, pp. 305–315, 2005.

99 [14] D. G. Mavis, P. H. Eaton, and M. D. Sibley, “SEE characterization and mitigation in ultra-deep submicron technologies,” 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, pp. 105–112, 2009. [15] C. Slayman, “Soft error trends and mitigation techniques in memory devices,” 2011 Pro- ceedings - Annual Reliability and Maintainability Symposium, pp. 1–5, 2011.

[16] “CREME96,” 2016. [Online]. Available: https://creme.isde.vanderbilt.edu/ [17] D. Munteanu and J. L. Autran, “Modeling and simulation of single-event effects in digital devices and ICs,” IEEE Transactions on Nuclear Science, vol. 55, no. 4, pp. 1854–1878, 2008.

[18] R. C. Hughes, “Hole mobility and transport in thin SiO2 films,” Applied Physics Letters, vol. 26, no. 8, pp. 436–438, 1975. [19] F. McLean, H. Boesch, and J. McGarrity, “Hole transport and recovery characteristics of SiO2 gate insulators,” IEEE Transactions on Nuclear Science, vol. 23, no. 6, pp. 1506–1512, 1976.

[20] P. J. McWhorter, S. L. Miller, and W. M. Miller, “Modeling the anneal of radiation-induced trapped holes in a varying thermal environment,” IEEE Transactions on Nuclear Science, vol. 37, no. 6, pp. 1682–1689, 1990. [21] J. R. Schwank, P. S. Winokur, P. J. McWhorter, F. W. Sexton, P. V. Dressendorfer, and D. C. Turpin, “Physical mechisms contributing to device rebound,” IEEE Transactions on Nuclear Science, vol. 31, no. 6, pp. 1434–1438, 1984. [22] J. R. Schwank, D. M. Fleetwood, M. R. Shaneyfelt, and P. S. Winokur, “Latent Thermally Activated Interface-Trap Generation in MOS Devices,” IEEE Electron Device Letters, vol. 13, no. 4, pp. 203–205, 1992.

[23] D. M. Fleetwood, M. J. Johnson, T. L. Meisenheimer, P. S. Winokur, W. L. Warren, and S. C. Witczak, “1/f noise, hydrogen transport, and latent interface-trap buildup in irradiated MOS devices,” IEEE Transactions on Nuclear Science, vol. 44, no. 6, pp. 1810–1817, 1997. [24] J. Srour, C. Marshall, and P. Marshall, “Review of displacement damage effects in silicon devices,” IEEE Transactions on Nuclear Science, vol. 50, no. 3, pp. 653–670, 2003.

[25] G. P. Summers, E. A. Burke, and M. A. Xapsos, “Displacement Damage Analogues to Ionising Radiation Effects,” Radiation Measurements, vol. 24, no. 1, pp. 1–8, 1995. [26] S. R. Messenger, E. A. Burke, G. P. Summers, and R. J. Walters, “Application of displace- ment damage dose analysis to low-energy protons on silicon devices,” IEEE Transactions on Nuclear Science, vol. 49, no. 6, pp. 2690–2694, 2002.

[27] C. Inguimbert, P. Arnolda, T. Nuns, and G. Rolland, “”Effective NIEL” in Silicon: Cal- culation Using Molecular Dynamics Simulation Results,” IEEE Transactions on Nuclear Science, vol. 57, no. 4, pp. 1915–1923, 2010. [28] S. R. Messenger, G. P. Summers, E. A. Burke, R. J. Walters, and M. A. Xapsos, “Modelling solar cell degradation in space: A comparison of the NRL displacement damage dose and the JPL equivalent fluence approaches,” Progress in Photovoltaics: Research and Applications, vol. 9, no. 2, pp. 103–121, 2001.

100 [29] J. W. McClory and J. C. Petrosky, “Temperature dependent electrical characteristics of neutron irradiated AlGaN/GaN HFETs,” IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 1969–1974, 2007. [30] J. Warner, C. D. Cress, S. Messenger, R. Walters, S. Ringel, and J. Park, “A deep level transient spectroscopy study of electron and proton irradiated p+n GaAs diodes,” IEEE Transactions on Nuclear Science, vol. 57, no. 4, pp. 282–285, 2010. [31] B. D. Weaver, T. J. Anderson, A. D. Koehler, J. D. Greenlee, J. K. Hite, D. I. Shahin, F. J. Kub, and K. D. Hobart, “On the Radiation Tolerance of AlGaN/GaN HEMTs,” ECS Journal of Solid State Science and Technology, vol. 5, no. 7, pp. Q208–Q212, 2016. [32] G. F. Derbenwick and B. L. Gregory, “Process Optimization of Radiation-Hardened CMOS Integrated Circuits,” IEEE Transactions on Nuclear Science, vol. 22, no. 6, pp. 2151–2156, 1975. [33] L. J. Palkuti and R. Pryor, “Radiation-Hard CMOS/SOS Standard Cell Circuits,” IEEE Transactions on Nuclear Science, vol. 23, no. 6, pp. 1715–1719, dec 1976. [34] W. J. Snoeys, T. A. Palacios Gutierrez, and G. Anelli, “A new NMOS layout structure for radiation tolerance,” IEEE Transactions on Nuclear Science, vol. 49 I, no. 4, pp. 1829–1833, 2002. [35] K. Kobayashi, K. Kubota, M. Masuda, Y. Manzawa, J. Furuta, S. Kanda, and H. Onodera, “A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI,” IEEE Transactions on Nuclear Science, vol. 61, no. 4, pp. 1881–1888, 2014. [36] Kaye & Laby, “Tables of Physical & Chemical Constants (16th edition 1995). 4.2.2 Attenu- ation of photons,” 2005. [37] S. Kayali, W. McAlpine, H. Becker, and L. Scheick, “Juno radiation design and implemen- tation,” IEEE Aerospace Conference Proceedings, 2012. [38] J. V. Osborn, R. C. Lacoe, D. C. Mayer, and G. Yabiku, “Total Dose Hardness of Three Commercial CMOS Microelectronics Foundries,” IEEE Transactions on Nuclear Science, vol. 45, no. 3, pp. 1458–1463, 1998. [39] N. S. Saks, M. G. Ancona, and J. A. Modolo, “Radiation Effects in MOS Capacitors with Very Thin Oxides at 80K,” IEEE Transactions on Nuclear Science, vol. 31, no. 6, pp. 1249–1255, 1984. [40] J. A. Felix, M. R. Shaneyfelt, D. M. Fleetwood, T. L. Meisenheimer, J. R. Schwank, R. D. Schrimpf, P. E. Dodd, E. P. Gusev, and C. D’Emic, “Radiation-Induced Charge Trapping in Thin Al2O3/SiOxNy/Si(100) Gate Dielectric Stacks,” IEEE Transactions on Nuclear Science, vol. 50, no. 6, pp. 1910–1918, 2003. [41] M. R. Shaneyfelt, P. E. Dodd, B. L. Draper, and R. S. Flores Sandia, “Challenges in hardening technologies using shallow-trench isolation,” IEEE Transactions on Nuclear Science, vol. 45, no. 6, pp. 2584–2592, 1998. [42] M. McLain, H. J. Barnaby, K. E. Holbert, R. D. Schrimpf, H. Shah, A. Amort, M. Baze, and J. Wert, “Enhanced TID susceptibility in sub-100 nm bulk CMOS I/O transistors and circuits,” IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 2210–2217, 2007.

101 [43] V. Ferlet-Cavrois, O. Musseau, J.-L. Leray, J.-L. Pelloie, and C. Raynaud, “Total dose effects on a fully-depleted SOI NMOSFET and its lateral parasitic transistor,” IEEE Transactions on Electron Devices, vol. 44, no. 6, pp. 965–971, jun 1997. [44] P. Paillet, M. Gaillardin, V. Ferlet-Cavrois, A. Torres, O. Faynot, C. Jahan, L. Tosti, and S. Cristoloveanu, “Total ionizing dose effects on deca-nanometer fully depleted SOI devices,” IEEE Transactions on Nuclear Science, vol. 52, no. 6, pp. 2345–2352, 2005. [45] J. R. Schwank, M. R. Shaneyfelt, B. L. Draper, and P. E. Dodd, “BUSFET-a radiation- hardened SOI transistor,” IEEE Transactions on Nuclear Science, vol. 46, no. 6, pp. 1809–1816, 1999.

[46] R. Arora, Z. E. Fleetwood, E. X. Zhang, N. E. Lourenco, J. D. Cressler, D. M. Fleetwood, R. D. Schrimpf, A. K. Sutton, G. Freeman, and B. Greene, “Impact of technology scaling in sub-100 nm nMOSFETs on total-dose radiation response and hot-carrier reliability,” IEEE Transactions on Nuclear Science, vol. 61, no. 3, pp. 1426–1432, 2014. [47] H. Hughes, P. McMarr, M. Alles, E. Zhang, C. Arutt, B. Doris, D. Liu, R. Southwick, and P. Oldiges, “Total ionizing dose radiation effects on 14 nm FinFET and SOI UTBB technologies,” IEEE Radiation Effects Data Workshop, vol. 2015-Novem, 2015. [48] M. Gaillardin, P. Paillet, V. Ferlet-Cavrois, O. Faynot, C. Jahan, and S. Cristoloveanu, “Total ionizing dose effects on triple-gate FETs,” IEEE Transactions on Nuclear Science, vol. 53, no. 6, pp. 3158–3165, 2006.

[49] M. Gaillardin, S. Girard, P. Paillet, J. L. Leray, V. Goiffon, P. Magnan, C. Marcan- della, M. Martinez, M. Raine, O. Duhamel, N. Richard, F. Andrieu, S. Barraud, and O. Faynot, “Investigations on the vulnerability of advanced CMOS technologies to MGy dose environments,” IEEE Transactions on Nuclear Science, vol. 60, no. 4, pp. 2590–2597, 2013. [50] J. Jiang, W. Shu, K.-s. Chong, T. Lin, N. K. Z. Lwin, J. S. Chang, and J. Liu, “Total Ionizing Dose (TID) Effects on Finger Transistors in a 65nm CMOS Process,” in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 5–8. [51] J. Y. Chang, M. H. Badawi, and A. DeCicco, “Neutron/gamma induced damage mechanisms and synergistic effects in GaAs MESFETs,” IEEE Transactions on Nuclear Science, vol. 36, no. 6, pp. 2068–2075, 1989.

[52] A. Meulenberg, H. L. A. Hung, K. E. Peterson, and W. T. Anderson, “Total Dose and Transient Radiation Effects on GaAs MMIC’s,” IEEE Transactions on Electron Devices, vol. 35, no. 12, pp. 2125–2132, 1988. [53] S. A. Vitusevich, N. Klein, A. E. Belyaev, S. V. Danylyuk, M. V. Petrychuk, R. V. Konakova, A. M. Kurakin, A. E. Rengevich, A. Y. Avksentyev, B. A. Danilchenko, V. Tilak, J. Smart, A. Vertiatchikh, and L. F. Eastman, “Effects of gamma-irradiation on AlGaN/GaN-based HEMTs,” Physica Status Solidi (A) Applied Research, vol. 195, no. 1 SPEC, pp. 101–105, 2003. [54] O. Aktas, A. Kuliev, V. Kumar, R. Schwindt, S. Toshkov, D. Costescu, J. Stubbins, and I. Adesida, “60Co gamma radiation effects on DC, RF, and pulsed I-V characteristics of AlGaN/GaN HEMTs,” Solid-State Electronics, vol. 48, no. 3, pp. 471–475, 2004.

102 [55] W. T. Anderson, G. E. Davis, J. S. Mateer, and D. L. Lile, “Ionizing Radiation Effects in InP MISFETs,” IEEE Transactions on Nuclear Science, vol. 31, no. 6, pp. 1467–1470, 1984. [56] W. T. Anderson and J. B. Boos, “Radiation Effects in InP JFETs,” IEEE Transactions on Nuclear Science, vol. 32, no. 6, pp. 4001–4004, 1985.

[57] D. L. Lile, M. J. Taylor, L. J. Messick, C. R. Zeisse, and D. A. Collins, “Radiation Tolerance of NMOS Technology on Indium Phosphide,” IEEE Electron Device Letters, vol. 5, no. 3, pp. 94–96, 1984. [58] X. Sun, O. I. Saadat, J. Chen, E. X. Zhang, S. Cui, T. Palacios, D. M. Fleetwood, and T. P. Ma, “Total-Ionizing-Dose Radiation Effects in AlGaN/GaN HEMTs and MOS-HEMTs,” IEEE Transactions on Nuclear Science, vol. 60, no. 6, pp. 4074–4079, 2013. [59] M. J. O’Loughlin, “Radiation Effects in High Electron Mobility Transistors: Total Dose Gamma Irradiation.” IEEE Transactions on Nuclear Science, vol. NS-34, no. 6, pp. 1808– 1811, 1987. [60] C. A. Klein, “Bandgap Dependence and Related Features of Radiation Ionization Energies in Semiconductors,” Journal of Applied Physics, vol. 39, no. 4, pp. 2029–2038, 1968. [61] P. J. Sellin and J. Vaitkus, “New materials for radiation hard semiconductor dectectors,” Nu- clear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 557, no. 2, pp. 479–489, 2006. [62] D. McMorrow, T. R. Weatherford, S. Buchner, A. R. Knudson, J. S. Melinger, L. H. Tran, and A. B. Campbell, “Single-event phenomena in GaAs devices and circuits,” IEEE Transactions on Nuclear Science, vol. 43, no. 2 PART 1, pp. 628–644, 1996. [63] D. M. Cardoza, S. D. LaLumondiere, M. A. Tockstein, S. C. Witczak, Y. Sin, B. J. Foran, W. T. Lotshaw, and S. C. Moss, “Single event transients induced by picosecond pulsed X-ray absorption in III-V heterojunction transistors,” IEEE Transactions on Nuclear Science, vol. 59, no. 6, pp. 2729–2738, 2012. [64] D. M. Hiemstra, “Dose rate and total dose dependence of the 1/f noise performance of a GaAs operational amplifier during irradiation,” IEEE Transactions on Nuclear Science, vol. 42, no. 6, pp. 1615–1621, 1995.

[65] ——, “Dose rate and total dose 1/f noise performance of GaAs heterojunction bipolar transistors,” IEEE Transactions on Nuclear Science, vol. 43, no. 6, pp. 3076–3080, 1996. [66] N. Divine and H. B. Garrett, “Charged particle distributions in Jupiter’s magnetosphere,” Journal of Geophysical Research: Space Physics, vol. 88, no. A9, pp. 6889–6903, 1983. [67] E. Stassinopoulos and J. Raymond, “The space radiation environment for electronics,” Proceedings of the IEEE, vol. 76, no. 11, pp. 1423–1442, 1988. [68] Kaye & Laby, “Tables of Physical & Chemical Constants (16th edition 1995). 4.5.1 Range and stopping power of ions in various materials,” 2005. [Online]. Available: http://www.kayelaby.npl.co.uk/atomic and nuclear physics/4 5/4 5 1.html [69] ——, “Tables of Physical & Chemical Constants (16th edition 1995). 4.5.3 Range of electrons and beta particles,” 2005. [Online]. Available: http://www.kayelaby.npl.co.uk/ atomic and nuclear physics/4 5/4 5 3.html

103 [70] P. D. Fieseler, S. M. Ardalan, and A. R. Frederickson, “The radiation effects on Galileo spacecraft systems at Jupiter,” IEEE Transactions on Nuclear Science, vol. 49 I, no. 6, pp. 2739–2758, 2002. [71] E. Enlow, R. Pease, W. Combs, R. Schrimpf, and R. Nowlin, “Response of advanced bipolar processes to ionizing radiation,” IEEE Transactions on Nuclear Science, vol. 38, no. 6, pp. 1342–1351, 1991. [72] R. Nowlin, D. Fleetwood, and R. Schrimpf, “Saturation of the dose-rate response of bipolar transistors below 10 rad(SiO/sub 2/)/s: implications for hardness assurance,” IEEE Transactions on Nuclear Science, vol. 41, no. 6, pp. 2637–2641, dec 1994.

[73] D. M. Fleetwood, S. L. Kosier, R. N. Nowlin, R. D. Schrimpf, R. A. Reber, M. DeLaus, P. S. Winokur, A. Wei, W. E. Combs, and R. L. Pease, “Physical mechanisms contributing to enhanced bipolar gain degradation at low dose rates,” IEEE Transactions on Nuclear Science, vol. 41, no. 6, pp. 1871–1883, 1994. [74] S. C. Witczak, R. C. Lacoe, D. C. Mayer, D. M. Fleetwood, R. D. Schrimpf, and K. F. Galloway, “Space charge limited degradation of bipolar oxides at low electric fields,” IEEE Transactions on Nuclear Science, vol. 45, no. 6 PART 1, pp. 2339–2351, 1998. [75] H. P. Hjalmarson, R. L. Pease, S. C. Witczak, M. R. Shaneyfelt, J. R. Schwank, A. H. Edwards, C. E. Hembree, and T. R. Mattsson, “Mechanisms for Radiation Dose-Rate Sensitivity of Bipolar Transistors,” IEEE Transactions on Nuclear Science, vol. 50, no. 6, pp. 1901–1909, 2003.

[76] S. Rashkeev, C. Cirba, D. Fleetwood, R. Schrimpf, S. Witczak, A. Michez, and S. Pantelides, “Physical model for enhanced interface-trap formation at low dose rates,” IEEE Transactions on Nuclear Science, vol. 49, no. 6, pp. 2650–2655, 2002. [77] N. L. Rowsey, M. E. Law, R. D. Schrimpf, D. M. Fleetwood, B. R. Tuttle, and S. T. Pan- telides, “Mechanisms Separating Time-Dependent and True Dose-Rate Effects in Irradiated Bipolar Oxides,” IEEE Transactions on Nuclear Science, vol. 59, no. 6, pp. 3069–3076, 2012. [78] S. C. Witczak, R. C. Lacoe, J. V. Osborn, J. M. Hutson, and S. C. Moss, “Dose-rate sensitivity of modern nMOSFETs,” IEEE Transactions on Nuclear Science, vol. 52, no. 6, pp. 2602–2608, 2005.

[79] A. Johnston, R. Swimm, and T. Miyahira, “Low Dose Rate Effects in Shallow Trench Isolation Regions,” IEEE Transactions on Nuclear Science, vol. 57, no. 6, pp. 3279–3287, 2010. [80] D. M. Fleetwood, “Evolution of Total Ionizing Dose Effects in MOS Devices With Moore’s Law Scaling,” IEEE Transactions on Nuclear Science, vol. 65, no. 8, pp. 1465–1481, aug 2018. [81] Department of Defence, “MIL-STD-883K Method 1019.9,” 2016. [Online]. Avail- able: https://landandmaritimeapps.dla.mil/Downloads/MilSpec/Docs/MIL-STD-883/ std883mthd1000.pdf

[82] B. Hand, “Developing Accuracy Specifications for Automatic Network Analyser Systems,” Hewlett-Packard Journal, vol. 21, no. February 1970, pp. 16–19, 1970.

104 [83] Ken Wong, “Traceability of vector network analyzer measurements,” in 2008 72nd ARFTG Microwave Measurement Symposium. IEEE, dec 2008, pp. 157–167. [84] Agilent Technologies, “Theory of Operation: Signal Separation,” in Service Guide: Agilent Technologies 8719ET/20ET/22ET 8719ES/20ES/22ES Network Analyzers, 2006, ch. 12, pp. 12–19.

[85] ——, “S-parameter Test Set Signal Flow,” in 8510C Network Analyser System: Operating and Programming Manual, 3rd ed., 2001, ch. 3, pp. 3–9. [86] H.-J. Eul and B. Schiek, “A generalized theory and new calibration procedures for network analyzer self-calibration,” IEEE Transactions on Microwave Theory and Techniques, vol. 39, no. 4, pp. 724–731, apr 1991. [87] R. B. Marks, “Formulations of the Basic Vector Network Analyzer Error Model including Switch-Terms,” in 50th ARFTG Conference Digest. IEEE, dec 1997, pp. 115–126. [88] S. Rehnmark, “On the Calibration Process of Automatic Network Analyzer Systems (Short Papers),” IEEE Transactions on Microwave Theory and Techniques, vol. 22, no. 4, pp. 457–458, apr 1974. [89] J. Butler, D. Rytting, M. Iskander, R. Pollard, and M. Vanden Bossche, “16-term error model and calibration procedure for on-wafer network analysis measurements,” IEEE Transactions on Microwave Theory and Techniques, vol. 39, no. 12, pp. 2211–2217, 1991. [90] R. Speciale, “A Generalization of the TSD Network-Analyzer Calibration Procedure, Cov- ering n-Port Scattering-Parameter Measurements, Affected by Leakage Errors,” IEEE Transactions on Microwave Theory and Techniques, vol. 25, no. 12, pp. 1100–1115, dec 1977. [91] A. Ferrero and U. Pisani, “Two-port network analyzer calibration using an unknown ’thru’,” IEEE Microwave and Guided Wave Letters, vol. 2, no. 12, pp. 505–507, dec 1992.

[92] ——, “QSOLT: A New Fast Calibration Algorithm for Two Port S Parameter Measurements,” in 38th ARFTG Conference Digest, vol. 20, no. 2. IEEE, dec 1991, pp. 15–24. [93] M. Imparato, T. Weller, and L. Dunleavy, “On-wafer calibration using space-conservative (SOLT) standards,” in 1999 IEEE MTT-S International Microwave Symposium Digest (Cat. No.99CH36282), vol. 4. IEEE, 1999, pp. 1643–1646. [94] S. Padmanabhan, P. Kirby, J. Daniel, and L. Dunleavy, “Accurate broadband on-wafer SOLT calibrations with complex load and thru models,” in 61st ARFTG Conference Digest, Spring 2003. IEEE, 2003, pp. 5–10. [95] H.-J. Eul and B. Schiek, “Thru-Match-Reflect: One Result of a Rigorous Theory for De- Embedding and Network Analyzer Calibration,” in 18th European Microwave Conference, 1988. IEEE, oct 1988, pp. 909–914. [96] A. Davidson, K. Jones, and E. Strid, “LRM and LRRM Calibrations with Automatic Determination of Load Inductance,” in 36th ARFTG Conference Digest, vol. 18. IEEE, nov 1990, pp. 57–63.

[97] L. Hayden, “An enhanced Line-Reflect-Reflect-Match calibration,” in 2006 67th ARFTG Conference, vol. 10. IEEE, jun 2006, pp. 143–149.

105 [98] S. Liu, I. Ocket, A. Lewandowski, D. Schreurs, and B. Nauwelaers, “An Improved Line- Reflect-Reflect-Match Calibration With an Enhanced Load Model,” IEEE Microwave and Wireless Components Letters, vol. 27, no. 1, pp. 97–99, jan 2017. [99] R. Doemer and A. Rumiantsev, “Verification of the wafer-level LRM+ calibration technique for GaAs applications up to 110 GHz,” in 65th ARFTG Conference Digest, 2005. Spring 2005, vol. 130. IEEE, 2005, pp. 15–19. [100] G. Engen and C. Hoer, “Thru-Reflect-Line: An Improved Technique for Calibrating the Dual Six-Port Automatic Network Analyzer,” IEEE Transactions on Microwave Theory and Techniques, vol. 27, no. 12, pp. 987–993, dec 1979.

[101] R. Marks, “A multiline method of network analyzer calibration,” IEEE Transactions on Microwave Theory and Techniques, vol. 39, no. 7, pp. 1205–1215, jul 1991. [102] D. F. Williams and R. B. Marks, “LRM Probe-Tip Calibrations using Nonideal Standards,” IEEE Transactions on Microwave Theory and Techniques, vol. 43, no. 2, pp. 466–469, 1995. [103] J. Martens, D. Judge, and J. Bigelow, “Multiport vector network analyzer measurements,” IEEE Microwave Magazine, vol. 6, no. 4, pp. 72–81, dec 2005. [104] H. Heuermann, “GSOLT: the calibration procedure for all multi-port vector network analyzers,” in IEEE MTT-S International Microwave Symposium Digest, 2003, vol. 3. IEEE, 2003, pp. 1815–1818. [105] A. Rumiantsev, H. Heuermann, and S. Schott, “A robust broadband calibration method for wafer-level characterization of multiport devices,” in 2007 69th ARFTG Conference. IEEE, jun 2007, pp. 1–5. [106] V. Teppati, A. Ferrero, D. Parena, and U. Pisani, “A simple calibration algorithm for partially leaky model multiport vector network analyzers,” 65th ARFTG Microwave Mea- surements Conference Digest 2005, no. 4, pp. 5–9, 2005.

[107] H. Van Hamme and M. Vanden Bossche, “Flexible vector network analyzer calibration with accuracy bounds using an 8-term or a 16-term error correction model,” IEEE Transactions on Microwave Theory and Techniques, vol. 42, no. 6, pp. 976–987, jun 1994. [108] D. F. Williams, J. C. Wang, and U. Arz, “An optimal vector-network-analyzer calibration algorithm,” IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 12, pp. 2391–2401, 2003. [109] J. Hoffmann, P. Leuchtmann, J. Ruefenacht, and R. Vahldieck, “A Stable Bayesian Vector Network Analyzer Calibration Algorithm,” IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. 4, pp. 869–880, apr 2009.

[110] G. Zysman and A. Johnson, “Coupled Transmission Line Networks in an Inhomogeneous Dielectric Medium,” IEEE Transactions on Microwave Theory and Techniques, vol. 17, no. 10, pp. 753–759, oct 1969. [111] V. Tripathi, “Asymmetric Coupled Transmission Lines in an Inhomogeneous Medium,” IEEE Transactions on Microwave Theory and Techniques, vol. 23, no. 9, pp. 734–739, sep 1975.

106 [112] R. Schwindt and C. Nguyen, “Generalized scattering parameters for two coupled transmission-line structures in an inhomogeneous medium,” Microwave and Optical Tech- nology Letters, vol. 12, no. 6, pp. 335–342, aug 1996. [113] S. Cohn, “Shielded Coupled-Strip Transmission Line,” IEEE Transactions on Microwave Theory and Techniques, vol. 3, no. 5, pp. 29–38, oct 1955. [114] D. Bockelman and W. Eisenstadt, “Combined differential and common-mode scattering pa- rameters: theory and simulation,” IEEE Transactions on Microwave Theory and Techniques, vol. 43, no. 7, pp. 1530–1539, jul 1995. [115] ——, “Pure-mode network analyzer for on-wafer measurements of mixed-mode S-parameters of differential circuits,” IEEE Transactions on Microwave Theory and Techniques, vol. 45, no. 7, pp. 1071–1077, jul 1997. [116] T. Zwick and U. Pfeiffer, “Pure-mode network analyzer concept for on-wafer measurements of differential circuits at millimeter-wave frequencies,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 3, pp. 934–937, mar 2005. [117] J. Dunsmore, “New methods and non-linear measurements for active differential devices,” in IEEE MTT-S International Microwave Symposium Digest, 2003, vol. 3. IEEE, 2003, pp. 1655–1658. [118] Keysight Technologies, “Testing differential amplifiers under real operating conditions,” in PNA-X Microwave Network Analysers - Brochure, 2018, p. 26. [Online]. Available: https://literature.cdn.keysight.com/litweb/pdf/5990-4592EN.pdf?id=1900906-1-eng [119] D. Bockelman, W. Eisenstadt, and R. Stengel, “Accuracy estimation of mixed-mode scatter- ing parameter measurements,” IEEE Transactions on Microwave Theory and Techniques, vol. 47, no. 1, pp. 102–105, 1999. [120] V. Teppati and A. Ferrero, “On-wafer calibration algorithm for partially leaky multiport vector network analyzers,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 11, pp. 3665–3671, nov 2005. [121] C. Seguinot, P. Kennis, J.-F. Legier, F. Huret, E. Paleczny, and L. Hayden, “Multimode TRL. A new concept in microwave measurements: theory and experimental verification,” IEEE Transactions on Microwave Theory and Techniques, vol. 46, no. 5, pp. 536–542, may 1998. [122] M. Wojnowski, V. Issakov, G. Sommer, and R. Weigel, “Multimode TRL Calibration Technique for Characterization of Differential Devices,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 7, pp. 2220–2247, jul 2012. [123] P. Walters, R. Pollard, J. Richardson, P. Gamand, and P. Suchet, “On-wafer measurement uncertainty for 3-terminal active millimetre-wave devices,” in GaAs IC Symposium Technical Digest 1992. IEEE, 1992, pp. 55–58. [124] R. Willink and B. D. Hall, “A classical method for uncertainty analysis with multidimensional data,” Metrologia, vol. 39, no. 4, pp. 361–369, aug 2002. [125] ——, “An extension to GUM methodology: degrees-of-freedom calculations for correlated multidimensional estimates,” pp. 1–30, nov 2013. [Online]. Available: http://arxiv.org/abs/1311.0343

107 [126] N. Ridler and M. Salter, “A generalised approach to the propagation of uncertainty in complex S-parameter measurements,” in 64th ARFTG Microwave Measurements Conference, Fall 2004., no. 1. IEEE, 2004, pp. 1–14. [127] EURAMET Technical Committee for Electricity and Magnetism, Guidelines on the Evalua- tion of Vector Network Analysers (VNA), 3rd ed. EURAMET, 2018. [128] M. Wollensack, J. Hoffmann, J. Ruefenacht, and M. Zeier, “VNA Tools II: S-parameter uncertainty calculation,” in 79th ARFTG Microwave Measurement Conference, no. June. IEEE, jun 2012, pp. 1–5. [129] M. Garelli and A. Ferrero, “A Unified Theory for S-Parameter Uncertainty Evaluation,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 12, pp. 3844–3855, dec 2012. [130] M. Zeier, J. Hoffmann, P. H¨urlimann,J. R¨ufenacht, D. Stalder, and M. Wollensack, “Establishing traceability for the measurement of scattering parameters in coaxial line systems,” Metrologia, vol. 55, no. 1, pp. S23–S36, feb 2018. [131] W. Daywitt, “Exact Principle Mode Field for a Lossy Coaxial Line,” IEEE Transactions on Microwave Theory and Techniques, vol. 39, no. 8, pp. 1313–1322, 1991. [132] P. Leuchtmann and J. R¨ufenacht, “On the Calculation of the Electrical Properties of Precision Coaxial Lines,” IEEE Transactions on Instrumentation and Measurement, vol. 53, no. 2, pp. 392–397, 2004. [133] M. Kossel, P. Leuchtmann, and J. R¨ufenacht, “Traceable Correction Method for Complex Reflection Coefficient Using Calculable Air Line Impedance Standards,” IEEE Transactions on Instrumentation and Measurement, vol. 53, no. 2, pp. 398–405, 2004. [134] N. M. Ridler and A. G. Morgan, “New primary reference standard for vector network analyser calibration at millimetre wavelengths in coaxial line,” Measurement Science and Technology, vol. 19, no. 6, p. 065103, jun 2008. [135] G. Ghione and C. Naldi, “Parameters of coplanar waveguides with lower ground plane,” Electronics Letters, vol. 19, no. 18, p. 734, 1983. [136] J. Svacina, “Analysis of multilayer microstrip lines by a conformal mapping method,” IEEE Transactions on Microwave Theory and Techniques, vol. 40, no. 4, pp. 769–772, apr 1992. [137] D. F. Williams, R. B. Marks, and A. Davidson, “Comparison of On-Wafer Calibrations,” in 38th ARFTG Conference Digest, vol. 20. IEEE, dec 1991, pp. 68–81. [138] R. B. Marks, J. A. Jargon, and J. R. Juroshek, “Calibration Comparison Method for Vector Network Analyzers,” in 48th ARFTG Conference Digest, no. 303. IEEE, dec 1996, pp. 38–45. [139] D. F. Williams, “NIST Microwave Uncertainty Framework,” 2017. [Online]. Available: https://www.nist.gov/services-resources/software/wafer-calibration-software [140] B. D. Hall, “Calculating measurement uncertainty using automatic differentiation,” Mea- surement Science and Technology, vol. 13, no. 4, pp. 421–427, 2002. [141] M. Zeier, J. Hoffmann, and M. Wollensack, “Metas.UncLib - A measurement uncertainty calculator for advanced problems,” Metrologia, vol. 49, no. 6, pp. 809–815, 2012.

108 [142] Cisco, “The History and Future of Internet Traffic,” 2015. [Online]. Available: https://blogs.cisco.com/sp/the-history-and-future-of-internet-traffic [143] ——, “Cisco Visual Networking Index: Forecast and Trends, 2017-2022 White Paper,” Tech. Rep., 2019. [Online]. Available: https://www.cisco.com/c/en/us/solutions/collateral/ service-provider/visual-networking-index-vni/white-paper-c11-738429.html

[144] IEEE Computer Society, “Amendment 10: Media Access Control Parameters, Physical Layers, and Management Parameters for 200 Gb/s and 400 Gb/s Operation,” in IEEE Std 802.3bs-2017. IEEE Standards Association, 2017. [145] N. Kikuchi, E. Yamada, Y. Shibata, and H. Ishii, “High-Speed InP-Based Mach-Zehnder Modulator for Advanced Modulation Formats,” in 2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS). IEEE, oct 2012, pp. 1–4. [146] R. Palmer, L. Alloatti, D. Korn, P. C. Schindler, R. Schmogrow, W. Heni, S. Koenig, J. Bolten, T. Wahlbrink, M. Waldow, H. Yu, W. Bogaerts, P. Verheyen, G. Lepage, M. Pantouvaki, J. Van Campenhout, P. Absil, R. Dinu, W. Freude, C. Koos, and J. Leuthold, “Silicon-organic hybrid MZI modulator generating OOK, BPSK and 8-ASK signals for up to 84 Gbit/s,” IEEE Photonics Journal, vol. 5, no. 2, pp. 8–15, 2013. [147] WIN Semiconductor, “PP10-10 & PP10-11 Technology Summary,” 2012. [148] R. Harrington, “Matrix methods for field problems,” Proceedings of the IEEE, vol. 55, no. 2, pp. 136–149, 1967.

[149] Sonnet Software, “Chapter 1: Introduction,” in Evaluation of Electromagnetic Software, 1997, ch. 1. [Online]. Available: http://www.sonnetsoftware.com/products/sonnet-suites/ benchmarking-ch1.html [150] ——, “Chapter 7: Limit Tests,” in Evaluation of Electromagnetic Software, 1997, ch. 7. [Online]. Available: http://www.sonnetsoftware.com/products/sonnet-suites/ benchmarking-ch7.html [151] Keysight Technologies, “Ports for FEM,” in ADS 2017 Update 1 Manual, 2017, pp. 275–278. [152] ——, “Ports for Momentum,” in ADS 2017 Update 1 Manual, 2017, pp. 254–274. [153] WIN Semiconductor, “PP10-11 Layout Design Manual,” p. 5, 2017.

[154] E. Ginzton, W. Hewlett, J. Jasberg, and J. Noe, “Distributed Amplification,” Proceedings of the IRE, vol. 36, no. 8, pp. 956–969, aug 1948. [155] J. Beyer, S. Prasad, R. Becker, J. Nordman, and G. Hohenwarter, “MESFET Distributed Amplifier Design Guidelines,” IEEE Transactions on Microwave Theory and Techniques, vol. 32, no. 3, pp. 268–275, mar 1984. [156] B. Agarwal, A. Schmitz, J. Brown, M. Matloubian, M. Case, M. Le, M. Lui, and M. Rodwell, “112-GHz, 157-GHz, and 180-GHz InP HEMT traveling-wave amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 46, no. 12, pp. 2553–2559, 1998. [157] S. Mason, “Power Gain in Feedback Amplifier,” Transactions of the IRE Professional Group on Circuit Theory, vol. CT-1, no. 2, pp. 20–25, jun 1954.

109 [158] V. Teppati, S. Tirelli, R. Lovblom, R. Fluckiger, M. Alexandrova, and C. R. Bolognesi, “Accuracy of Microwave Transistor fT and fMAX Extractions,” IEEE Transactions on Electron Devices, vol. 61, no. 4, pp. 984–990, apr 2014. [159] D. E. Meharry and W. Kong, “Reduction of Noise in Wideband Distributed Amplifiers,” in 2007 IEEE/MTT-S International Microwave Symposium. IEEE, jun 2007, pp. 2099–2102. [160] K. W. Kobayashi, D. Denninghoff, D. Miller, and S. Member, “A Novel 100 MHz – 45 GHz Input-Termination-Less Distributed Amplifier Design With Low-Frequency Low-Noise and High Linearity Implemented With A 6 Inch 0.15µm GaN-SiC Wafer Process Technology,” IEEE Journal of Solid-State Circuits, vol. 51, no. 9, pp. 2017–2026, 2016. [161] L. Zhang and T. Kwasniewski, “Optimal equalization for reducing the impact of channel group delay distortion on high-speed backplane data transmission,” AEU - International Journal of Electronics and Communications, vol. 64, no. 7, pp. 671–681, jul 2010. [162] H. Li, G. Balamurugan, J. Jaussi, and B. Casper, “A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS,” in ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC). IEEE, sep 2018, pp. 238–241. [163] P. Shinghal, “Ultra-Broadband GaAs pHEMT MMIC Cascode Travelling Wave Amplifier (TWA) Design for Next Generation Instrumentation,” Ph.D. dissertation, University of Manchester, 2016. [164] R. Minasian, “Simplified GaAs m.e.s.f.e.t. model to 10 GHz,” Electronics Letters, vol. 13, no. 18, p. 549, 1977. [165] Y. Ayasli, R. Mozzi, J. Vorhaus, L. Reynolds, and R. Pucel, “A monolithic GaAs 1 - 13-GHz traveling-wave amplifier,” IEEE Transactions on Electron Devices, vol. 29, no. 7, pp. 1072–1077, jul 1982. [166] H. F. Hammad, A. P. Freundorfer, and Y. M. Antar, “Comprehensive study of multiband unconditional stabilization of common-source and common-gate MESFET transistors using feedback,” IEEE Journal of Solid-State Circuits, vol. 37, no. 10, pp. 1260–1270, 2002. [167] A. Lines, G. Nicoll, and A. Woodward, “Some properties of waveguides with periodic structure,” Proceedings of the IEE - Part III: Radio and Communication Engineering, vol. 97, no. 48, pp. 263–276, jul 1950. [168] L. Brillouin, “Wave guides for slow waves,” Journal of Applied Physics, vol. 19, no. 11, pp. 1023–1041, 1948. [169] J. L. Doane, “Design of Circular Corrugated Waveguides to Transmit Millimeter Waves at ITER,” Fusion Science and Technology, vol. 53, no. 1, pp. 159–173, jan 2008. [170] J. Shohat, I. Robertson, and S. Nightingale, “10-Gb/s driver amplifier using a tapered gate line for improved input matching,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 10, pp. 3115–3120, oct 2005. [171] G. A. Campbell, “Physical Theory of the Electric Wave-Filter,” Bell System Technical Journal, vol. 1, no. 2, pp. 1–32, nov 1922. [172] ——, “XXX. On loaded lines in telephonic transmission,” The London, Edinburgh, and Dublin Philosophical Magazine and Journal of Science, vol. 5, no. 27, pp. 313–330, mar 1903.

110 [173] D. Pozar, “8.1: Periodic Structures,” in Microwave Engineering, 3rd ed. John Wiley & Sons, 2005, pp. 372–378. [174] J. Shohat, I. D. Robertson, and S. J. Nightingale, “Investigation of drain-line loss and the S22 kink effect in capacitively coupled distributed amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 12, pp. 3767–3773, 2005. [175] B. D. Hall, “On the propagation of uncertainty in complex-valued quantities,” Metrologia, vol. 41, no. 3, pp. 173–177, jun 2004. [176] M. Ohtomo, “Stability analysis and numerical simulation of multidevice amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 41, no. 6, pp. 983–991, 1993. [177] G. Wolf, H. Happy, S. Demichel, R. Leblanc, F. Blache, R. Lefevre, and G. Dambrine, “A metamorphic GaAs HEMT distributed amplifier with 50 GHz bandwidth and low noise for 40 Gbits/s,” in IEEE MTT-S International Microwave Symposium Digest, 2005. IEEE, 2005, pp. 2231–2233. [178] L. Diego, B. Haentjens, C. A. Mjema, I. Barrutia, A. Herrera, and Y. Haentjens, “A DC to 40 GHz, High Linearity Monolithic GaAs Distributed Amplifier with Low DC Power Consumption as a High Bit-Rate Pre-Driver,” in 2018 15th European Radar Conference (EuRAD). IEEE, sep 2018, pp. 497–500. [179] C. Paoloni and S. Kosslowsky, “Graphical design method for traveling wave amplifier based on filter theory,” in 1993 IEEE MTT-S International Microwave Symposium Digest. IEEE, 1993, pp. 273–276. [180] J. Chen and A. M. Niknejad, “Design and Analysis of a Stage-Scaled Distributed Power Amplifier,” IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 5, pp. 1274–1283, may 2011. [181] K. Fujii, “A DC to 22GHz, 2W high power distributed amplifier using stacked FET topology with gate periphery tapering,” in 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), vol. 2016-July. IEEE, may 2016, pp. 270–273. [182] W. Heinrich, “Quasi-TEM description of MMIC coplanar lines including conductor-loss effects,” IEEE Transactions on Microwave Theory and Techniques, vol. 41, no. 1, pp. 45–52, 1993. [183] Avago Technologies, “AEDR-8000 Series Reflective Surface Mount Optical Encoders Datasheet,” pp. 1–8, 2009. [Online]. Available: http://docs.avagotech.com/docs/ AV02-0971EN [184] F. Roig, L. Dusseau, A. Khachatrian, N. J. H. Roche, A. Privat, J. R. Vaille, J. Boch, J. H. Warner, F. Saigne, S. P. Buchner, D. McMorrow, P. Ribeiro, G. Auriel, B. Azais, R. Marec, P. Calvel, F. Bezerra, and R. Ecoffet, “Modeling and investigations on TID-ASETs synergistic effect in LM124 Operational amplifier from three different manufacturers,” IEEE Transactions on Nuclear Science, vol. 60, no. 6, pp. 4430–4438, 2013. [185] Avago Technologies, “HEDR-54xx Series Mid-Sized Housed Encoder Data Sheet,” 2012. [Online]. Available: http://docs.avagotech.com/docs/AV02-3576EN [186] J. R. Kirtley, T. N. Theis, P. M. Mooney, and S. L. Wright, “Noise spectroscopy of deep level (DX) centers in GaAs-Al x Ga 1-x As heterostructures,” Journal of Applied Physics, vol. 63, no. 5, pp. 1541–1548, mar 1988.

111 [187] L. Ren and M. Leys, “1/f Noise in an AlxGa1-xAs/GaAs heterostructure between 77 and 300 K,” Physica B: Condensed Matter, vol. 192, no. 4, pp. 303–310, dec 1993. [188] A. El Hdiy and S. Mouetsi, “Identification of traps in an epitaxied AlGaAs/GaAs/AlGaAs quantum well structure,” Journal of Applied Physics, vol. 108, no. 3, p. 034513, aug 2010.

[189] S. T. Lai, D. Alexiev, and B. D. Nener, “Comparison between deep level defects in GaAs induced by gamma, 1 MeV electron, and neutron irradiation,” Journal of Applied Physics, vol. 78, no. 6, pp. 3686–3690, sep 1995. [190] S. M. Tunhuma, F. D. Auret, M. J. Legodi, and M. Diale, “The fine structure of electron irradiation induced EL2-like defects in n -GaAs,” Journal of Applied Physics, vol. 119, no. 14, p. 145705, apr 2016. [191] A. Davidson, E. Strid, and K. Jones, “Achieving greater on-wafer S-parameter accuracy with the LRM calibration technique,” in 34th ARFTG Conference Digest, vol. 16, no. 503. IEEE, nov 1989, pp. 61–66. [192] D. Walker, D. Williams, and J. M. Morgan, “Planar Resistors for Probe Station Calibration,” in 40th ARFTG Conference Digest, vol. 22. IEEE, dec 1992, pp. 1–9. [193] D. F. Williams and R. B. Marks, “LRM Probe-Tip Calibrations with Imperfect Resistors and Lossy Lines,” in 42nd ARFTG Conference Digest. IEEE, dec 1993, pp. 32–36. [194] N. Jain and D. Wells, “Design of a DC-to-90-GHz resistive load,” IEEE Microwave and Guided Wave Letters, vol. 9, no. 2, pp. 69–70, 1999.

[195] D. Lacombe, “A Multioctave Microstrip 50-Ω Termination (Short Papers),” IEEE Transac- tions on Microwave Theory and Techniques, vol. 20, no. 4, pp. 290–292, apr 1972. [196] F. Giannini, C. Paoloni, and M. Ruggieri, “A Very Broadband Matched Termination Utilizing Non-Grounded Radial Lines,” in 17th European Microwave Conference, 1987. IEEE, oct 1987, pp. 1027–1031. [197] R. Monje, V. Vassilev, A. Pavolotsky, and V. Belitsky, “High quality microstrip termination for MMIC and millimeter-wave applications,” in IEEE MTT-S International Microwave Symposium Digest, 2005., vol. 2005, no. C. IEEE, 2005, pp. 1827–1830. [198] Y. Morimoto, M. Memarian, X. Li, and T. Itoh, “Open-End Microstrip Line Terminations Using Lossy Gray-Scale Inkjet Printing,” IEEE Transactions on Microwave Theory and Techniques, vol. 65, no. 12, pp. 4861–4870, dec 2017. [199] K. Lomakin, M. Sippel, G. Gold, J. Frohlich, K. Helmreich, M. Ankenbrand, and J. Franke, “Low reflective aerosol Jet printed broadband matched load up to 67 GHz,” in 2018 11th German Microwave Conference (GeMiC). IEEE, mar 2018, pp. 379–382.

[200] D. Pozar, “2.3: The Terminated Lossless Transmission Line,” in Microwave Engineering, 3rd ed. John Wiley & Sons, 2005, pp. 57–64. [201] ——, “2.7: Lossy Transmission Lines,” in Microwave Engineering, 3rd ed. John Wiley & Sons, 2005, pp. 79–86.

[202] D. Homentcovschi, “An analytical solution to the microstrip line problem,” IEEE Transac- tions on Microwave Theory and Techniques, vol. 38, no. 6, pp. 766–769, jun 1990.

112 [203] A. Djordjevic and T. Sarkar, “Closed-form formulas for frequency-dependent resistance and inductance per unit length of microstrip and strip transmission lines,” IEEE Transactions on Microwave Theory and Techniques, vol. 42, no. 2, pp. 241–248, feb 1994. [204] E. Bogatin, “Design rules for microstrip capacitance,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 11, no. 3, pp. 253–259, 1988.

[205] W. Eisenstadt and Y. Eo, “S-parameter-based IC interconnect transmission line charac- terization,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 15, no. 4, pp. 483–490, 1992.

113