ACADEMIC REGULATIONS AND COURSE STRUCTURE CHOICE BASED CREDIT SYSTEM MLR20
EMBEDDED SYSTEMS for
Master of Technology (M.Tech)
M. Tech. - Regular Two Year Degree Program (For batches admitted from the academic year 2020 - 2021)
MLR Institute of Technology (Autonomous) Laxman Reddy Avenue, Dundigal Hyderabad – 500043, Telangana State www.mlrinstitutions.ac.in Email: [email protected]
FOREWORD
The autonomy is conferred on MLR Institute of Technology by UGC based on its performance as well as future commitment and competency to impart quality education. It is a mark of its ability to function independently in accordance with the set norms of the monitoring bodies like UGC and AICTE. It reflects the confidence of the UGC in the autonomous institution to uphold and maintain standards it expects to deliver on its own behalf and thus awards degrees on behalf of the college. Thus, an autonomous institution is given the freedom to have its own curriculum, examination system and monitoring mechanism, independent of the affiliating University but under its observance.
MLR Institute of Technology is proud to win the credence of all the above bodies monitoring the quality in education and has gladly accepted the responsibility of sustaining, if not improving upon the standards and ethics for which it has been striving for more than a decade in reaching its present standing in the arena of contemporary technical education. As a follow up, statutory bodies like Academic Council and Boards of Studies are constituted with the guidance of the Governing Body of the College and recommendations of the JNTU Hyderabad to frame the regulations, course structure and syllabi under autonomous status.
The autonomous regulations, course structure and syllabi have been prepared after prolonged and detailed interaction with several expertise solicited from academics, industry and research, in accordance with the vision and mission of the college to order to produce quality engineering graduates to the society.
All the faculty, parents and students are requested to go through all the rules and regulations carefully. Any clarifications, if needed, are to be sought, at appropriate time and with principal of the college, without presumptions, to avoid unwanted subsequent inconveniences and embarrassments. The Cooperation of all the stake holders is sought for the successful implementation of the autonomous system in the larger interests of the college and brighter prospects of engineering graduates.
PRINCIPAL MLR Institute of Technology
M. Tech. - Regular Two Year Degree Program (For batches admitted from the academic year 2020 - 21)
For pursuing two year post graduate Masters Degree Programme of study in Engineering (M.Tech) offered by MLR Institute of Technology under Autonomous status and herein referred to as MLRIT (Autonomous):
All the rules specified herein approved by the Academic Council will be in force and applicable to students admitted from the Academic Year 2020-21 onwards. Any reference to “Institute” or “College” in these rules and regulations shall stand for MLR Institute of Technology (Autonomous).
All the rules and regulations, specified hereafter shall be read as a whole for the purpose of interpretation as and when a doubt arises, the interpretation of the Chairman, Academic Council is final. As per the requirements of statutory bodies, the Principal, MLR Institute of Technology shall be the Chairman, Academic Council.
1. ADMISSION Admission into first year of two year M. Tech. degree Program of study in Engineering: Eligibility: Admission to the above programme shall be made subject to eligibility, qualification and specialization as prescribed by the University from time to time. Admissions shall be made on the basis of merit/rank obtained by the candidates at the qualifying Entrance Test conducted by the University or on the basis of any other order of merit as approved by the University, subject to reservations as laid down by the Govt. From time to time
2. AWARD OF M. Tech. DEGREE A student shall be declared eligible for the award of the M. Tech. Degree, if he pursues a course of study in not less than two and not more than four academic years. However, he is permitted to write the examinations for two more years after two academic years of course work, failing which he shall forfeit his seat in M. Tech. programme.
The student shall register for all 68 credits and secure all the 68 credits. The minimum instruction days in each semester are 68.
3. BRANCH OF STUDY The following specializations are offered at present for the M. Tech. programme of study. 1. Aerospace Engineering 2. Computer Science and Engineering 3. Embedded Systems 4. Thermal Engineering
4. COURSE REGISTRATION 4.1 A ‘Faculty Advisor or Counselor’ shall be assigned to each student, who will advise him on the Post Graduate Programme (PGP), its Course Structure and Curriculum, Choice / Option for Courses, based on his competence, progress, pre-requisites and interest.
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4.2 Academic Section of the College invites ‘Registration Forms’ from students within 15 days from the commencement of class work, ensuring ‘DATE and TIME Stamping’. The Registration Requests for any ‘CURRENT SEMESTER’ shall be completed BEFORE the commencement of SEEs (Semester End Examinations) of the ‘PRECEDING SEMESTER’.
4.3 A Student can apply Registration, ONLY AFTER obtaining the ‘WRITTEN APPROVAL’ from his Faculty Advisor, which should be submitted to the College Academic Section through the Head of Department (a copy of it being retained with Head of Department, Faculty Advisor and the Student).
4.4 If the Student submits ambiguous choices or multiple options or erroneous entries - during Registration for the Course(s) under a given/ specified Course Group/ Category as listed in the Course Structure, only the first mentioned Course in that Category will be taken into consideration.
4.5 Course Registration are final and CANNOT be changed, nor can they be inter-changed; further, alternate choices will also not be considered. However, if the Course that has already been listed for Registration (by the Head of Department) in a Semester could not be offered due to any unforeseen or unexpected reasons, then the Student shall be allowed to have alternate choice - either for a new course (subject to offering of such a course), or for another existing course (subject to availability of seats), which may be considered. Such alternate arrangements will be made by the Head of Department, with due notification and time-framed schedule, within the FIRST WEEK from the commencement of Class-work for that Semester.
5. ATTENDANCE The programmes are offered on a unit basis with each subject being considered a unit. 5.1 Attendance in all classes (Lectures/Laboratories etc.) is compulsory. The minimum required attendance in each theory / Laboratory etc. is 75% including the days of attendance in sports, games, NCC and NSS activities for appearing for the End Semester examination. A student shall not be permitted to appear for the Semester End Examinations (SEE) if his attendance is less than 75%.
5.2 Condonation of shortage of attendance in each subject up to 10% (65% and above and below75%) in each semester shall be granted by the College Academic Committee.
5.3 Shortage of Attendance below 65% in each subject shall not be condoned.
5.4 Students whose shortage of attendance is not condoned in any subject are not eligible to write their end semester examination of that subject and their registration shall stand cancelled.
5.5 A prescribed fee shall be payable towards condonation of shortage of attendance.
5.6 A Candidate shall put in a minimum required attendance at least three (3) theory courses in I Year I semester for promoting to I Year II Semester. In order to qualify for the award of the M.Tech. Degree, the candidate shall complete all the academic requirements of the courses, as per the course structure.
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5.7 A student shall not be promoted to the next semester unless he satisfies the attendance requirement of the present Semester, as applicable. They may seek readmission into that semester when offered next. If any candidate fulfills the attendance requirement in the present semester, he shall not be eligible for readmission in to the same class.
6. EVALUATION The performance of the candidate in each semester shall be evaluated course-wise, with a maximum of 100 marks for theory and 100 marks for practical’s, on the basis of Internal Evaluation and End Semester Examination.
For the theory courses 70 marks shall be awarded for the performance in the Semester End Examination and 30 marks shall be awarded for Continuous Internal Evaluation (CIE). The Continuous Internal Evaluation shall be made based on the average of the marks secured in the two Mid Term-Examinations conducted, one in the middle of the Semester and the other, immediately after the completion of Semester instructions. Each mid-term examination shall be conducted for a total duration of 120 minutes.
Continues Internal Examination (CIE) Subjective Paper shall contain three questions. Question 1 & 2 with internal choice from unit-I, question 3 & 4 with internal choice from unit-II and question no 5 & 6 may be having a, b sub questions with internal choice from first half part of unit-III for CIE-I. For CIE-II 1 & 2 questions from unit-4, questions 3 & 4 from unit-5 and question no 5 & 6 from remaining half part of unit-3. The first mid-term examination shall be conducted for the first 50% of the syllabus, and the second mid-term examination shall be conducted for the remaining 50% of the syllabus. Question no. 1 to 6 carries 10 Marks.
Semester End Examination (SEE) The Semester End Examination will be conducted for 70 marks examination shall be conducted for a total duration of 180 minutes. Question paper consists of Part–A and Part-B with the following. Part-A is a compulsory question consisting of 5 questions, one from each unit and carries 4 marks each. Part-B to be answered 5 questions carrying 10 marks each. There will be two questions from each unit and only one should be answered.
6.1 For practical courses, 70 marks shall be awarded for performance in the Semester End Examinations and 30 marks shall be awarded for day-to-day performance as Internal Marks.
6.2 For conducting laboratory end examinations of all PG Programmes, one internal examiner and one external examiner are to be appointed by the Chief Controller of Examination in one week before for commencement of the lab end examinations.
6.3 There shall be a seminar presentations during II year I semester. For seminar, a student under the supervision of a faculty member, shall collect the literature on a topic and critically review the literature and submit it to the department in a report form and shall make an oral presentation before
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MLR Institute of Technology the Departmental Academic Committee consisting of Head of the Department, Supervisor and two other senior faculty members of the department. For each Seminar there will be only internal evaluation of 100 marks. A candidate has to secure a minimum of 50% of marks to be declared successful. If he fails to fulfill minimum marks, he has to reappear during the supplementary examinations.
6.4 A candidate shall be deemed to have secured the minimum academic requirement in a Course if he secures a minimum of 40% of marks in the Semester End Examination and a minimum aggregate of 50% of the total marks in the Semester End Examination and Continuous Internal Evaluation taken together.
6.5 In case the candidate does not secure the minimum academic requirement in any subject (as specified in 6.6) he has to re appear for the Semester End Examination in that course.
6.6 A candidate shall be given one chance to re-register for the courses if the internal marks secured by a candidate is less than 50% and failed in that course for maximum of two courses and should register within four weeks of commencement of the class work. In such a case, the candidate must re-register for the courses and secure the required minimum attendance. The candidate’s attendance in the re- registered course(s) shall be calculated separately to decide upon his eligibility for writing the Semester End Examination in those courses. In the event of the student taking another chance, his Continuous Internal Evaluation (internal) marks and Semester End Examination marks obtained in the previous attempt stands cancelled. 6.7 In case the candidate secures less than the required attendance in any course, he shall not be permitted to write the Semester End Examination in that course. He shall re-register for the course when next offered. 6.8 Offering one open elective courses in III-Semester along with core and specialized courses as a part of inculcating knowledge to the student.
7. EXAMINATIONS AND ASSESSMENT - THE GRADING SYSTEM 7.1 Marks will be awarded to indicate the performance of each student in each Theory Course, or Lab/Practicals, or Seminar, or Project, etc., based on the % marks obtained in CIE + SEE (Continuous Internal Evaluation + Semester End Examination, both taken together) as specified in Item6above, and a corresponding Letter Grade shall be given. 7.2 As a measure of the student’s performance, a 10-point Absolute Grading System using the following Letter Grades (UGC Guidelines) and corresponding percentage of marks shall be followed: % of Marks Secured Letter Grade Grade (Class Intervals) (UGC Guidelines) Points 90% and above O 10 ( 90% , ≤ 100% ) (Outstanding) Below 90% but not less than 80% A+ 9 ( 80% , < 90% ) (Excellent) Below 80% but not less than 70% A 8 ( 70% , < 80% ) (Very Good) Below 70% but not less than 60% B+ 7 ( 60% , < 70% ) (Good) Below 60% but not less than 50% B 6
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MLR Institute of Technology ( 50% , < 60% ) (above Average) Below 50% F 0 ( < 50% ) (FAIL) Absent AB 0
7.3 A student obtaining F Grade in any Course shall be considered ‘failed’ and is be required to reappear as ‘Supplementary Candidate’ in the Semester End Examination (SEE), as and when offered. In such cases, his Internal Marks (CIE Marks) in those Courses will remain the same as those he obtained earlier.
7.4 A student not appeared for examination then ‘AB’ Grade will be allocated in any Course shall be considered ‘failed’ and will be required to reappear as ‘Supplementary Candidate’ in the Semester End Examination (SEE), as and when offered.
7.5 A Letter Grade does not imply any specific Marks percentage and it will be the range of marks percentage.
7.6 In general, a student shall not be permitted to repeat any Course(s) only for the sake of ‘Grade Improvement’ or ‘SGPA / CGPA Improvement’.
7.7 A student earns Grade Point (GP) in each Course, on the basis of the Letter Grade obtained by him in that Course. The corresponding ‘Credit Points’ (CP) are computed by multiplying the Grade Point with Credits for that particular Subject / Course. Credit Points (CP) = Grade Point (GP) x Credits …. For a Course
7.8 The Student passes the Course only when he gets GP >=6 (B Grade or above).
7.9 A student earns Grade Point (GP) in each Course, on the basis of the Letter Grade obtained by him in that Course (excluding Mandatory non-credit Courses). Then the corresponding ‘Credit Points’ (CP) are computed by multiplying the Grade Point with Credits for that particular Course. Credit Points (CP) = Grade Point (GP) x Credits …. For a Course
7.10 The Semester Grade Point Average (SGPA) is calculated by dividing the Sum of Credit Points (CP)secured from ALL Courses registered in a Semester, by the Total Number of Credits registered during that Semester. SGPA is rounded off to TWO Decimal Places. SGPA is thus computed as SGPA = { } / { } …. For each Semester,
where ‘i’ is the Course indicator index (takes into account all Courses in a Semester), ‘N’ is the no. of Courses ‘REGISTERED’ for the Semester (as specifically required and listed under the Course Structure of the parent Department), is the no. of Credits allotted to that ix Course, and represents the Grade Points (GP) corresponding to the Letter Grade awarded for that ith Course.
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MLR Institute of Technology Illustration of Computation of SGPA Grade Grade Credit Point Course Credit Letter Point (Credit x Grade) Course1 3 A 8 3 x 8 = 24 Course2 4 B+ 7 4 x 7 = 28 Course3 3 B 6 3 x 6 = 18 Course4 3 O 10 3 x10= 30 Course5 3 C 5 3 x 5 = 15 Course6 4 B 6 4 x 6 = 24
Thus, SGPA =139/20 =6.95
7.11 The Cumulative Grade Point Average (CGPA) is a measure of the overall cumulative performance of a student over all Semesters considered for registration. The CGPA is the ratio of the Total Credit Points secured by a student in ALL registered Courses in ALL Semesters, and the Total Number of Credits registered in ALL the Semesters. CGPA is rounded off to TWO Decimal Places. CGPA is thus computed from the I Year Second Semester onwards, at the end of each Semester, as per the formula CGPA = { } / { } … for all S Semesters registered (i.e., up to and inclusive of S Semesters, S 2)
where ‘M’ is the TOTAL no. of Courses (as specifically required and listed under the Course Structure of the parent Department) the Student has ‘REGISTERED’ from the 1st Semester onwards upto and inclusive of the Semester S (obviously M > N), ‘j’ is the Course indicator index (takes into account all Courses from 1 to S Semesters), is the no. of Credits allotted to the jth Course, and represents the Grade Points (GP) corresponding to the Letter Grade awarded for that jth Course. After registration and completion of I Year I Semester however, the SGPA of that Semester itself may be taken as the CGPA, as there are no cumulative effects.
For CGPA Computation Semester 1 Semester 2 Semester 3 Semester 4 Semester 5 Semester 6 Credits : 20 Credits : 22 Credits : 25 Credits : 26 Credits : 26 Credits : 25 SGPA : 6.9 SGPA : 7.8 SGPA : 5.6 SGPA : 6.0 SGPA : 6.3 SGPA : 8.0
Thus, CGPA = 20 x 6.9 + 22 x 7.8 + 25 x 5.6 + 26 x 6.0 + 26 x 6.3 + 25 x 8.0 ______= 6.73 144
7.12 For Calculations listed in Item 7.6 – 7.10, performance in failed Courses (securing F Grade) will also be taken into account, and the Credits of such Courses will also be included in the multiplications and summations.
7.13 No SGPA/CGPA is declared, if a candidate is failed in any one of the courses of a given semester.
7.14 Conversion formula for the conversion of GPA into indicative percentage is % of marks scored = (final CGPA -0.50) x 10
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8. EVALUATION OF PROJECT/DISSERTATION WORK Every candidate shall be required to submit a thesis or dissertation on a topic approved by the Project Review Committee.
8.1 A Project Review Committee (PRC) shall be constituted with Head of the Department as Chairperson, Project Supervisor and one senior faculty member of the Departments offering the M. Tech. programme.
8.2 Registration of Project Work: A candidate is permitted to register for the project work after satisfying the attendance requirement of all the courses, both theory and practical.
8.3 After satisfying 8.2, a candidate has to submit, in consultation with his Project Supervisor, the title, objective and plan of action of his project work to the PRC for approval. Only after obtaining the approval of the PRC the student can initiate the Project work.
8.4 If a candidate wishes to change his supervisor or topic of the project, he can do so with the approval of the PRC. However, the PRC shall examine whether or not the change of topic/supervisor leads to a major change of his initial plans of project proposal. If yes, his date of registration for the project work starts from the date of change of Supervisor or topic as the case may be.
8.5 A candidate shall submit his project status report in two stages at least with a gap of three months between them.
8.6 The work on the project shall be initiated at the beginning of the II year and the duration of the project is two semesters. A candidate is permitted to submit Project Thesis only after successful completion of all theory and practical courses with the approval of PRC not earlier than 40 weeks from the date of registration of the project work. For the approval of PRC the candidate shall submit the draft copy of thesis to the Head of the Department and make an oral presentation before the PRC.
8.7 After approval from the PRC, the soft copy of the thesis should be submitted to the College for ANTI-PLAGIARISM for the quality check and the plagiarism report should be included in the final thesis. If the copied information is less than 30%, then only thesis will be accepted for submission.
8.8 Three copies of the Project Thesis certified by the supervisor shall be submitted to the College.
8.9 For Dissertation Phase-I in II Year I Sem. there is an internal marks of 100, the evaluation should be done by the PRC for 50 marks and Supervisor will evaluate for 50 marks. The Supervisor and PRC will examine the Problem Definition, Objectives, Scope of Work and Literature Survey in the same domain. A candidate has to secure a minimum of 50% of marks to be declared successful for Project Phase-I. If he fails to fulfill minimum marks, he has to reappear during the supplementary examination.
8.10 For Dissertation Phase-II (Viva Voce) in II Year II Sem. There is an internal marks of 50, the evaluation should be done by the PRC for 25 marks and Supervisor will evaluate for 25 marks. The PRC will examine the overall progress of the Project Work and decide the Project is eligible for final
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MLR Institute of Technology submission or not. There is an external marks of 150 and the same evaluated by the External examiner appointed by the Chief Controller of Examinations and he secures a minimum of 40% of marks in the Semester End Examination and a minimum aggregate of 50% of the total marks in the Semester End Examination and Continuous Internal Evaluation taken together.
8.11 If he fails to fulfill as specified in 8.10, he will reappear for the Viva-Voce examination only after three months. In the reappeared examination also, fails to fulfill, he will not be eligible for the award of the degree.
8.12 The thesis shall be adjudicated by one examiner selected by the Chief Controller of Examinations. For this, the HOD of the Department shall submit a panel of 3 examiners, eminent in that field, with the help of the guide concerned and Head of the Department.
8.13 If the report of the examiner is not favorable, the candidate shall revise and resubmit the Thesis. If the report of the examiner is unfavorable again, the thesis shall be summarily rejected.
8.14 If the report of the examiner is favorable, Project dissertation shall be conducted by a board consisting of the Supervisor, Head of the Department and the external examiner who adjudicated the Thesis.
8.15 The Head of the Department shall coordinate and make arrangements for the conduct of Project dissertation.
8.16 For Audit Course(Non-Credit Courses) offered in a Semester, after securing 65% attendance and has secured not less than 40% marks in the SEE, and a minimum of 50% of marks in the sum Total of the CIE and SEE taken together in such a course, then the student is PASS and will be qualified for the award of the degree. No marks or Letter Grade shall be allotted for these courses/activities. However, for non credit courses ‘SATISFACTORY’ or “UNSATISFACTORY’ shall be indicated instead of the letter grade and this will not be counted for the computation of SGPA/CGPA.
9 AWARD OF DEGREE AND CLASS 9.1 A Student who registers for all the specified Courses/ Courses as listed in the Course Structure, satisfies all the Course Requirements, and passes the examinations prescribed in the entire PG Programme (PGP), and secures the required number of 90 Credits (with CGPA ≥ 6.0), shall be declared to have ‘QUALIFIED’ for the award of the M.Tech. Degree in the chosen Branch of Engineering and Technology with specialization as he admitted.
9.2 Award of Class After a student has satisfied the requirements prescribed for the completion of the programme and is eligible for the award of M. Tech. Degree, he shall be placed in one of the following three classes based on the CGPA: Class Awarded Grade to be Secured First Class with CGPA ≥ 8.00 Distinction First Class ≥ 7.00 to < 8.00 CGPA Second Class ≥ 6.00 to < 7.00 CGPA
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9.3 A student with final CGPA (at the end of the PGP) < 6.00 will not be eligible for the Award of Degree.
10. WITHOLDING OF RESULTS If the student has not paid the dues, if any, to the college or if any case of indiscipline is pending against him, the result of the student will be withheld and he will not be allowed into the next semester. His degree will be with held in such cases.
11. TRANSITORY REGULATIONS 11.1 If any candidate is detained due to shortage of attendance in one or more courses, they are eligible for re-registration to maximum of two earlier or equivalent courses at a time as and when offered. 11.2 The candidate who fails in any course will be given two chances to pass the same course; otherwise, he has to identify an equivalent course as per MLR18 Academic Regulations. 12 SUPPLEMENTARY EXAMINATIONS Supplementary examinations for the odd semester shall be conducted with the regular examinations of even semester and vice versa, for those who appeared and failed or absent in regular examinations. Such candidates writing supplementary examinations may have to write more than one examination.
13. REVALUATION Students shall be permitted for revaluation after the declaration of end semester examination results within due dates by paying prescribed fee. After revaluation if there is any betterment in the grade, then improved grade will be considered. Otherwise old grade shall be retained.
14. AMENDMENTS TO REGULATIONS The Academic Council of MLR Institute of Technology reserves the right to revise, amend, or change the regulations, scheme of examinations, and / or syllabi or any other policy relevant to the needs of the society or industrial requirements etc., without prior notice.
15. GENERAL 15.1 Credit: A unit by which the course work is measured. It determines the number of hours of instructions required per week. One credit is equivalent to one hour of teaching (lecture Or tutorial) or two hours of practical work/field work per week. 15.2 Credit Point: It is the product of grade point and number of credits for a course. 15.3 Wherever the words “he”, “him”, “his”, occur in the regulations, they include “she”, “her”. 15.4 The academic regulation should be read as a whole for the purpose of any interpretation. 15.5 In the case of any doubt or ambiguity in the interpretation of the above rules, the decision of the Chairman of the Academic Council is final.
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MALPRACTICES RULES - DISCIPLINARY ACTION FOR /IMPROPER CONDUCT IN EXAMINATIONS S. Nature of Malpractices / Improper Conduct Punishment No Possesses or keeps accessible in examination hall, any paper, note book, programmable calculators, Cell phones, pager, palm computers or any other form of material concerned with or related to the Expulsion from the examination hall and cancellation of 1 (a) course of the examination (theory or practical) in the performance in that course only. which he is appearing but has not made use of (material shall include any marks on the body of the candidate which can be used as an aid in the course of the examination) Gives assistance or guidance or receives it from Expulsion from the examination hall and cancellation of any other candidate orally or by any other body the performance in that course only of all the candidates (b) language methods or communicates through cell involved. In case of an outsider, he will be handed over phones with any candidate or persons in or outside to the police and a case is registered against him. the exam hall in respect of any matter. Expulsion from the examination hall and cancellation of Has copied in the examination hall from any the performance in that course and all other courses the paper, book, programmable calculators, palm candidate has already appeared including practical 2 computers or any other form of material relevant examinations and project work and shall not be to the course of the examination (theory or permitted to appear for the remaining examinations of practical) in which the candidate is appearing. the courses of that Semester/year. The Hall Ticket of the candidate is to be cancelled and sent to the Principal. The candidate who has impersonated shall be expelled from examination hall. The candidate is also debarred and forfeits the seat. The performance of the original candidate who has been impersonated, shall be cancelled in all the courses of the examination (including practical’s and project work) already appeared and shall Impersonates any other candidate in connection not be allowed to appear for examinations of the 3 with the examination. remaining courses of that semester/year. The candidate is also debarred for two consecutive semesters from class work and all examinations. The continuation of the course by the candidate is course to the academic regulations in connection with forfeiture of seat. If the imposter is an outsider, he will be handed over to the police and a case is registered against him.
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MLR Institute of Technology Expulsion from the examination hall and cancellation of performance in that course and all the other courses the candidate has already appeared including practical Smuggles in the Answer book or additional sheet examinations and project work and shall not be or takes out or arranges to send out the question permitted for the remaining examinations of the courses 4 paper during the examination or answer book or of that semester/year. The candidate is also debarred for additional sheet, during or after the examination. two consecutive semesters from class work and all examinations. The continuation of the course by the candidate is course to the academic regulations in connection with forfeiture of seat. Uses objectionable, abusive or offensive language in the answer paper or in letters to the examiners 5 Cancellation of the performance in that course. or writes to the examiner requesting him to award pass marks. Refuses to obey the orders of the Addl. Controller of examinations / any officer on duty or misbehaves or creates disturbance of any kind in and around the examination hall or organizes a walk out or instigates others to walk out, or threatens the addl. Controller of examinations or In case of students of the college, they shall be expelled any person on duty in or outside the examination from examination halls and cancellation of their hall of any injury to his person or to any of his performance in that course and all other courses the relations whether by words, either spoken or candidate(s) has (have) already appeared and shall not be written or by signs or by visible representation, 6 permitted to appear for the remaining examinations of assaults the addl. Controller of examinations, or the courses of that semester/year. The candidates also are any person on duty in or outside the examination debarred and forfeit their seats. In case of outsiders, they hall or any of his relations, or indulges in any will be handed over to the police and a police case is other act of misconduct or mischief which result registered against them. in damage to or destruction of property in the examination hall or any part of the College campus or engages in any other act which in the opinion of the officer on duty amounts to use of unfair means or misconduct or has the tendency to disrupt the orderly conduct of the examination. Expulsion from the examination hall and cancellation of performance in that course and all the other courses the candidate has already appeared including practical examinations and project work and shall not be Leaves the exam hall taking away answer script or permitted for the remaining examinations of the courses 7 intentionally tears of the script or any part thereof of that semester/year. The candidate is also debarred for inside or outside the examination hall. two consecutive semesters from class work and all examinations. The continuation of the course by the candidate is course to the academic regulations in connection with forfeiture of seat.
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MLR Institute of Technology Expulsion from the examination hall and cancellation of the performance in that course and all other courses the candidate has already appeared including practical Possess any lethal weapon or firearm in the 8 examinations and project work and shall not be examination hall. permitted for the remaining examinations of the courses of that semester/year. The candidate is also debarred and forfeits the seat. Student of the colleges expulsion from the examination hall and cancellation of the performance in that course If student of the college, who is not a candidate for and all other courses the candidate has already appeared the particular examination or any person not including practical examinations and project work and 9 connected with the college indulges in any shall not be permitted for the remaining examinations of malpractice or improper conduct mentioned in the courses of that semester/year. The candidate is also clause 6 to 8. debarred and forfeits the seat. Person(s) who do not belong to the College will be handed over to police and, a police case will be registered against them. Expulsion from the examination hall and cancellation of the performance in that course and all other courses the Comes in a drunken condition to the examination candidate has already appeared including practical 10 hall. examinations and project work and shall not be permitted for the remaining examinations of the courses of that semester/year. Cancellation of the performance in that course and all Copying detected on the basis of internal other courses the candidate has appeared including 11 evidence, such as, during valuation or during practical examinations and project work of that special scrutiny. semester/year examinations. If any malpractice is detected which is not covered in the above clauses 1 to 11 shall be reported to 12 the principal for further action to award suitable punishment.
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COURSE STRUCTURE
I M.Tech I Semester Hours per Scheme of Examination Week Maximum Marks Course Course Title Category Credits Code L T P Internal External Total (CIE) (SEE) B45501 Embedded Networking PCC 3 - - 3 30 70 100 30 70 System Design with B45502 PCC 3 - - 3 100 Embedded Linux
Microcontrollers for 30 70 B45503 PCC 3 - - 3 100 Embedded System Design Professional Elective 30 70 PEC 3 - - 3 100 Course-I Professional Elective 30 70 PEC 3 - - 3 100 Course-II 30 70 B45510 Simulation Lab PCC - - 3 1.5 100 30 70 Microcontrollers for B45511 PCC - - 3 1.5 100 Embedded System Lab
Audit Course-I AC 2 - - - 30 70 100 Total 17 - 6 18 240 560 800
I M.Tech II Semester Hours per Scheme of Examination Week Maximum Marks Course Course Title Category Credits Code L T P Internal External Total (CIE) (SEE) RTL Simulation And 70 B45512 PCC 3 - - 3 30 100 Synthesis With PLDS VLSI Design Verification 30 70 B45513 PCC 3 - - 3 100 and Testing Advanced Digital Signal 30 70 B45514 PCC 3 - - 3 100 Processing Professional Elective 30 70 PEC 3 - - 3 100 Course-III Professional Elective 30 70 PEC 3 - - 3 100 Course-IV Advanced Embedded 30 70 B45521 PCC - - 3 1.5 100 Systems Lab VLSI Design Verification 70 B45522 PCC - - 3 1.5 30 100 and Testing Lab Audit Course-II AC 2 - - - 30 70 100 Total 17 - 6 18 240 560 800
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 15
MLR Institute of Technology
II M.Tech I Semester Hours per Scheme of Examination Course Week Maximum Marks Course Title Category Credits Code L T P Internal External Total (CIE) (SEE) Professional Elective Course-V PEC 3 - - 3 30 70 100 Open Elective Course OEC 3 - - 3 30 70 100 B45529 Dissertation Phase – I PWC - - 16 8 100 - 100 B45530 Technical Seminar SEM 2 - - 2 100 - 100 Total 8 - 16 16 260 140 400
II M.Tech II Semester Hours per Scheme of Examination Week Maximum Marks Course Course Title Category Credits Code L T P Internal External Total (CIE) (SEE) B45531 Dissertation Phase – II PWC - - 32 16 50 150 200 Total - - 32 16 50 150 200
PROFESSIONAL ELECTIVES PE-I PE-II B45504 Modern Digital Signal Processing B45507 Parallel Processing Programming Languages for Embedded B45505 Software B45508 CAD of Digital System design
B45506 VLSI signal processing B45509 Embedded Real Time Operating Systems PE-III PE-IV B45515 Memory Technologies B45518 Device Drivers of Embedded Systems B45516 SoC Design B45519 Network Security and Cryptography B45517 Linux OS B45520 Embedded Systems and IoT PE-V B45523 Data Communication Networks B45524 Digital Signal Processors and Architectures B45525 Nano Materials and Nano Technology
OPEN ELECTIVES B45526 Principles of signal Processing B45527 Applications of IoT B45528 Waste to Energy
AUDIT COURSE I AUDIT COURSE II B4AC01 English for Research Paper Writing B4AC03 Disaster Management B4AC02 Research Methodology and IPR B4AC04 Constitution of India
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 16
MLR Institute of Technology
I M.TECH I SEMESTER SYLLABUS
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 17
MLR Institute of Technology EMBEDDED NETWORKING
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45501 PCC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Understand the Embedded Communication Protocols Develop a network based on Embedded systems Know about interfaces and buses
OUTCOMES:
At the end of the course students can able to:
Understand the Embedded Communication Protocols Develop a network based on Embedded systems Interfaces the hardware and know to uses the buses
UNIT-I Embedded Communication Protocols Classes: 11
Embedded Networking: Introduction – Serial/Parallel Communication – Serial communication protocols - RS232 standard – RS485 – Synchronous Serial Protocols -Serial Peripheral Interface (SPI) – Inter Integrated Circuits (I2C) – PC Parallel port programming - ISA/PCI Bus protocols –Firewire.
UNIT-II USB and CAN Bus Classes: 8
USB bus – Introduction – Speed Identification on the bus – USB States – USB bus communication: Packets – Data flow types –Enumeration –Descriptors –PIC 18 Microcontroller USB Interface – C Programs –CAN Bus – Introduction - Frames –Bit stuffing –Types of errors –Nominal Bit Timing – PIC microcontroller CAN Interface – A simple application with CAN. UNIT-III Ethernet Basics Classes: 12
Elements of a network – Inside Ethernet – Building a Network: Hardware options – Cables, Connections and network speed – Design choices: Selecting components –Ethernet Controllers –Using the internet in local and internet communications – Inside the Internet protocol. UNIT-IV Embedded Ethernet Classes: 07
Exchanging messages using UDP and TCP – Serving web pages with Dynamic Data – Serving web pages that respond to user Input – Email for Embedded Systems – Using FTP – Keeping Devices and Network secure.
UNIT-V Wireless Embedded Networking Classes: 07
Wireless sensor networks – Introduction – Applications – Network Topology – Localization –Time Synchronization - Energy efficient MAC protocols –SMAC – Energy efficient and robust routing Data Centric routing.
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 18
MLR Institute of Technology TEXT BOOKS:
1. Embedded Systems Design: A Unified Hardware/Software Introduction - Frank Vahid, Tony Givargis, John & Wiley Publications, 2002 2. Parallel Port Complete: Programming, interfacing and using the PCs parallel printer port -Jan Axelson, Penram Publications, 1996.
REFERENCE BOOKS: 1. Advanced PIC microcontroller projects in C: from USB to RTOS with the PIC18F series -Dogan Ibrahim, Elsevier 2008. 2. Embedded Ethernet and Internet Complete - Jan Axelson, Penram publications, 2003. 3. Networking Wireless Sensors - Bhaskar Krishnamachari , Cambridge press 2005.
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M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 19
MLR Institute of Technology System Design with Embedded Linux
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45502 PCC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Familiarize of Real Time Operating systems Apply the knowledge of device drivers Learn the concepts of Embedded Linux
OUTCOMES:
At the end of the course students can able to :
Familiarity of the embedded Linux development model. Write, debug, and profile applications and drivers in embedded Linux. Understand and create Linux BSP for a hardware platform
UNIT-I Introduction to Real Time Operating Systems: Characteristics of RTOS, Tasks Specifications and types, Real-Time Scheduling Algorithms, Concurrency, Inter-process Communication and Synchronization mechanisms, Priority Inversion, Inheritance and Ceiling. Embedded Linux Vs Desktop Linux, Embedded Linux Distributions, System calls, Static and dynamic libraries, Cross tool chains
UNIT-II Embedded Linux Architecture, Kernel Architecture – HAL, Memory manager, Scheduler, File System, I/O and Networking subsystem, IPC, User space, Start-up sequence
UNIT-III Board Support Package Embedded Storage: MTD, Architecture, Drivers, Embedded File System Embedded Device Drivers: Communication between user space and kernel space drivers, Character and Block Device Drivers, Interrupt handling, Kernel modules Embedded Drivers: Serial, Ethernet, I2 C, USB, Timer, Kernel Modules
UNIT-IV Porting Applications Real-Time Linux: Linux and Real time, Programming, Hard Real-time Linux
UNIT-V Building and Debugging: Bootloaders, Kernel, Root file system, Device Tree
TEXT BOOKS: 1. Chris Simmonds “Mastering Embedded Linux Programming” - Second Edition, PACKT Publications Limited. 2. Karim Yaghmour, “Building Imbedded Linux Systems”, O'Reilly & Associates 3. P Raghvan, Amol Lad, Sriram Neelakandan, “Embedded Linux System Design and Development”,
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 20
MLR Institute of Technology Auerbach Publications
REFERENCES: 1. Christopher Hallinan, “Embedded Linux Primer: A Practical Real World Approach”, Prentice Hall, 2nd Edition, 2010. 2. Derek Molloy, “Exploring Beagle Bone: Tools and Techniques for Building with Embedded Linux”, Wiley, 1st Edition, 2014
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 21
MLR Institute of Technology
MICROCONTROLLERS FOR EMBEDDED SYSTEM DESIGN
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45503 PCC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Provide an overview of Design Principles of Embedded System. Understand about the role of firmware, operating systems in correlation with hardware systems. Know the architecture of ARM Processor Familiarize to write code and compile in Cortex and DSP processors
OUTCOMES:
At the end of the course students can able to:
Compare and select ARM processor core based SoC with several features/peripherals based on requirements of embedded applications. Identify and characterize architecture of Programmable DSP Processors Develop small applications by utilizing the ARM processor core and DSP processor based platform.
UNIT-I
ARM Cortex-M3 processor: Applications, Programming model – Registers, Operation - modes, Exceptions and Interrupts, Reset Sequence Instruction Set, Unified AssemblerLanguage, Memory Maps, Memory Access Attributes, Permissions, Bit-Band Operations, Unaligned and Exclusive Transfers. Pipeline, Bus Interfaces.
UNIT-II
Exceptions, Types, Priority, Vector Tables, Interrupt Inputs and Pending behaviour, Fault Exceptions, Supervisor and Pendable Service Call, Nested Vectored Interrupt Controller, Basic Configuration, SYSTICK Timer, Interrupt Sequences, Exits, Tail Chaining, Interrupt Latency.
UNIT-III
LPC 17xx microcontroller- Internal memory, GPIOs, Timers, ADC, UART and other serial interfaces, PWM, RTC, WDT.
UNIT-IV
Programmable DSP (P-DSP) Processors: Harvard architecture, Multi port memory, architectural structure of P-DSP- MAC unit, Barrel shifters, Introduction to TI DSP processor family
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MLR Institute of Technology
UNIT-V
VLIW architecture and TMS320C6000 series, architecture study, data paths, cross paths, Introduction to Instruction level architecture of C6000 family, Assembly Instructions memory addressing, for arithmetic, logical operations
TEXTBOOKS:
1. Joseph Yiu, “The definitive guide to ARM Cortex-M3”, Elsevier, 2nd Edition
2. Venkatramani B. and Bhaskar M. “Digital Signal Processors: Architecture, Programming and Applications” , TMH , 2nd Edition
REFERENCES:
1. Sloss Andrew N, Symes Dominic, Wright Chris, “ARM System Developer's Guide: Designing and Optimizing”, Morgan Kaufman Publication.
2. Steve furber, “ARM System-on-Chip Architecture”, Pearson Education
3. Frank Vahid and Tony Givargis, “Embedded System Design”, Wiley
4. Technical references and user manuals on www.arm.com, NXP Semiconductor www.nxp.com and Texas Instruments www.ti.com
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 23
MLR Institute of Technology
SIMULATION LAB
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45510 PCC - - 3 1.5 30 70 100
OBJECTIVES:
The course should enable the students to:
Write a code and simulate any digital function in Verilog HDL Know the difference between synthesizable and non-synthesizable code Understand library modelling, behavioral code and the differences between then Understand logic verification using Verilog simulation
OUTCOMES:
At the end of the course students can able to
Write a Code and simulate for any digital function in Verilog HDL Differentiate synthesizable and non-synthesizable code Exercise library modelling, behavioral code and the differences between then Practice logic verification using Verilog simulation
Simulate and implement the following designs on FPGA/CPLD boards
1. Design and Simulation of adder, Ripple Adder. 2. Design of any two combinational circuits. 3. Design of 4 bit binary to gray converter 4. Design of higher order Multiplexer/ De-multiplexer. 5. Design of 4- Bit Multiplier, Divider. 6. Design of flip flops: SR, D, JK, T. 7. Design of 4-bit binary, BCD counters or any sequence counter 8. Design of a N-bit shift register. 9. Design of Sequence Detector (Finite State Machine- Mealy and Moore Machines). 10. Design of ALU to Perform – ADD, SUB, AND-OR, 1’s and 2’s Compliment, Multiplication, and Division.
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 24
MLR Institute of Technology
MICROCONTROLLERS FOR EMBEDDED SYSTEMS LAB
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45511 PCC - - 3 1.5 30 70 100
OBJECTIVES:
The course should enable the students to:
Design of embedded systems design tools and hardware programmers Equip skills in both simulation and practical implementation of the basic building blocks Familiarize to write code and compile in ARM
OUTCOMES:
At the end of the course students can able to:
Design of embedded systems design tools and hardware programmers Equip the skills in both simulation and practical implementation of the basic building blocks Practice to write code and compile in ARM
Note: Minimum of 10 experiments has to be conducted.
The following programs have to be tested on 89C51 Development board/equivalent using Embedded C Language on Keil IDE or Equivalent.
1. Program to toggle all the bits of Port P1 continuously with 250 mS delay. 2. Program to toggle only the bit P1.5 continuously with some delay. Use Timer 0, mode 1 to create delay. 3. Program to interface a switch and a buzzer to two different pins of a Port such that the buzzer should sound as long as the switch is pressed. 4. Program to interface LCD data pins to port P1 and display a message on it. 5. Program to interface keypad. Whenever a key is pressed, it should be displayed on LCD. 6. Program to interface seven segment display unit. 7. Program to transmit a message from Microcontroller to PC serially using RS232. 8. Program to receive a message from PC serially using RS232. 9. Program to get analog input from Temperature sensor and display the temperature value on PC Monitor. 10. Program to interface Stepper Motor to rotate the motor in clockwise and anticlockwise directions 11. Program to Sort RTOS on to 89C51 development board. 12. Program to interface Elevator.
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MLR Institute of Technology
I M.TECH II SEMESTER SYLLABUS
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 26
MLR Institute of Technology
RTL SIMULATION AND SYNTHESIS WITH PLDs
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45512 PCC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Provide an overview of Design Principles of Embedded System. Understanding about the role of ASIC design flow and RTL source codes.
OUTCOMES:
At the end of the course students can able to:
Familiarity of Finite State Machines, RTL design using reconfigurable logic. Design and develop IP cores and Prototypes with performance guarantees Use EDA tools like Cadence, Mentor Graphics and Xilinx
UNIT-I Top down approach to design, Design of FSMs (Synchronous and asynchronous), Static timing analysis, Meta-stability, Clock issues, Need and design strategies for multi-clock domain designs.
UNIT-II Design entry by Verilog/VHDL/FSM, Verilog AMS.
UNIT-III Programmable Logic Devices, Introduction to ASIC Design Flow, FPGA, SoC, Floor planning, Placement, Clock tree synthesis, Routing, Physical verification, Power analysis, ESD protection.
UNIT-IV Design for performance, Low power VLSI design techniques. Design for testability.
UNIT-V IP and Prototyping: IP in various forms: RTL Source code, Encrypted Source code, Soft IP, Netlist, Physical IP, Use of external hard IP during prototyping
TEXTBOOKS: 1. 1. Richard S. Sandige, “Modern Digital Design”, MGH, International Editions. 2. 2. Donald D Givone, “Digital principles and Design”, TMH
REFERENCES: 1. 1. Charles Roth, Jr. and Lizy K John, “Digital System Design using VHDL”, Cengage Learning. 2. 2. Samir Palnitkar, “Verilog HDL, a guide to digital design and synthesis”, Prentice Hall. 3. 3. Doug Amos, Austin Lesea, Rene Richter, “FPGA based prototyping methodology manual”, Xilinx 4. 4. Bob Zeidman, “Designing with FPGAs & CPLDs”, CMP Books.
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 27
MLR Institute of Technology VLSI DESIGN VERIFICATION AND TESTING
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45513 PCC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Understand the VLSI design flows and their Synthesis approach.. Analyze the various Designing verification processes. Design complex circuits and testing them using various Testing methods.
OUTCOMES:
At the end of the course students can able to:
Recall the VLSI design flows and their Synthesis approach Analyze the various Designing verification processes Design complex circuits and Testing them using various Testing methods
UNIT-I VLSI HIGH LEVEL DESIGN Classes: 12
Introduction MOS and related VLSI technology , VLSI Design flows, Transformations for High Level Synthesis, Scheduling, Allocation and Binding, Introduction to HLS: Scheduling, Allocation and Binding Problem, Scheduling Algorithms, Binding and Allocation Algorithms UNIT-II LOGIC SYNTHESIS AND VERIFICATION Classes: 12
Logic Optimization and Synthesis, Two level Boolean Logic Synthesis, Heuristic Minimization of Two-Level Circuits, Finite State Machine Synthesis, Multilevel Implementation Binary Decision Diagram: Introduction and construction, Ordered Binary Decision Diagram, Operations on Ordered Binary Decision Diagram
UNIT-III TEMPORAL LOGIC AND MODEL CHECKING Classes: 12 Introduction and Basic Operations on Temporal Logic, Syntax and Semantics of CLT, Equivalence between CTL Formulas, Verification Techniques, Model Checking Algorithm, Symbolic Model Checking
UNIT-IV DIGITAL VLSI TESTING AND DFT Classes: 12
Introduction to Digital VLSI Testing, Functional and Structural Testing, Fault Equivalence, Fault Simulation and Testability Measures
UNIT-V CMOS IC TESTING Classes: 12
Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras, D-Algorithm, ATPG for Synchronous Sequential Circuits, Scan Chain based Sequential Circuit Testing, Built in Self Test, Memory Testing
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MLR Institute of Technology
TEXT BOOKS:
1. Basic VLSI design by Douglas A, Pucknell, Kamran Eshraghian, Prantice Hall, 1996 3rd edition. 2. VLSI DESIGN - K. Lal Kishore, V.S.V Prabhakar, I.K International, 2009. 3. CMOS VLSI Design- Neil H.E Weste, David Harris, AyanBanerjee, Pearson Education, 1999
REFERENCE BOOKS:
1. D. D. Gajski, N. D. Dutt, A.C.-H. Wu and S.Y.-L. Lin, High-Level Synthesis: Introduction to Chip and System Design, Springer, 1st edition, 1992. 2. S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Prentice Hall, 2nd edition, 2003. 3. G. De Micheli. Synthesis and optimization of digital circuits, 1st edition, 1994. 4. M. Huth and M. Ryan, Logic in Computer Science modeling and reasoning about systems, Cambridge University Press, 2nd Edition, 2004 5. Bushnell and Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal Circuits, Kluwer Academic Publishers, 2000
WEB REFERENCES: 1. VLSI Design, CMOS VLSI design(nptel links) ,VLSI Expert.com
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MLR Institute of Technology
ADVANCED DIGITAL SIGNAL PROCESSING
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45514 PCC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
.Understand the concept of digital signal processing Apply numerical problems and design of alogritms Know about DSP processors
OUTCOMES:
At the end of the course students can able to:
To understand theory of different filters and algorithms To understand theory of multirate DSP, solve numerical problems and write algorithms To understand theory of prediction and solution of normal equations To know applications of DSP at block level.
UNIT-I Overview of DSP, Characterization in time and frequency, FFT Algorithms, Digital filter design and structures: Basic FIR/IIR filter design &structures, design techniques of linear phase FIR filters,IIR filters by impulse invariance, bilinear transformation, FIR/IIR Cascaded lattice structures, parallel realization of IIR.
UNIT-II Multi rate DSP, Decimators and Interpolators, Sampling rate conversion, multistage decimator & interpolator, poly phase filters, QMF, digital filter banks, Applications in subband coding.
UNIT-III Linear prediction & optimum linear filters, stationary random process, forward-backward linear prediction filters, solution of normal equations, AR Lattice and ARMA Lattice-Ladder Filters, Wiener Filters for Filtering and Prediction.
UNIT-IV Adaptive Filters, Applications, Gradient Adaptive Lattice, Minimum mean square criterion, LMS algorithm, Recursive Least Square algorithm
UNIT-V Estimation of Spectra from Finite-Duration Observations of Signals. Nonparametric Methods for Power Spectrum Estimation, Parametric Methods for Power Spectrum Estimation, Minimum- Variance Spectral Estimation, Eigen analysis Algorithms for Spectrum Estimation.
TEXTBOOKS:
1. J. G. Proakis and D.G. Manolakis, “Digital signal processing: Principles, Algorithm and Applications”, 4th Edition, Prentice Hall, 2007. 2. N. J. Fliege, “Multirate Digital Signal Processing: Multirate Systems -Filter Banks – Wavelets”, 1st
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 30
MLR Institute of Technology Edition, John Wiley and Sons Ltd, 1999.
REFERENCES:
1. Bruce W. Suter, “Multirate and Wavelet Signal Processing”,1st Edition, Academic Press, 1997. 2. M. H. Hayes, “Statistical Digital Signal Processing and Modeling”, John Wiley & Sons Inc., 2002. 3. S. Haykin, “Adaptive Filter Theory”, 4th Edition, Prentice Hall, 2001. 4. D. G. Manolakis, V. K. Ingle and S. M. Kogon, “Statistical and Adaptive Signal Processing”, McGraw Hill, 2000
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 31
MLR Institute of Technology
ADVANCED EMBEDDED SYSTEMS LAB Course Code Category Hours / Week Credits Maximum Marks L T P C CIA SEE Total B45521 PCC - - 3 1.5 30 70 100
OBJECTIVES:
At the end of the course students can able to:
Familiar with the basic concepts and terminology of the target area, the embedded systems design flow. Understand of the embedded system architecture. Give them opportunity to apply and test those methods in practice; Make measurements with the specified accuracy.
OUTCOMES: At the end of the course students can able to:
Explain the basic concepts and terminology of the target area, the embedded systems design flow. Draw the embedded system architecture. Write a code, test and practice Make measurements with the specified accuracy.
Note: A. The following programs are to be implemented on ARM based Processors/Equivalent.
The following Programs are to be implemented on ARM Processor
1. Simple Assembly Program for a. Addition | Subtraction | Multiplication | Division b. Operating Modes, System Calls and Interrupts c. Loops, Branches 2. Write an Assembly programs to configure and control General Purpose Input/Output (GPIO) port pins. 3. Write an Assembly programs to read digital values from external peripherals and execute them with the Target board. 4. Program for reading and writing of a file 5. Program to demonstrate Time delay program using built in Timer / Counter feature on IDE environment 6. Program to demonstrates a simple interrupt handler and setting up a timer 7. Program demonstrates setting up interrupt handlers. Press button to generate an interrupt and trace the program flow with debug terminal. 8. Program to Interface 8 Bit LED and Switch Interface 9. Program to implement Buzzer Interface on IDE environment 10. Program to Displaying a message in a 2 line x 16 Characters LCD display and verify the result in debug terminal. 11. Program to demonstrate I2C Interface on IDE environment 12. Program to demonstrate I2C Interface – Serial EEPROM 13. Demonstration of Serial communication. Transmission from Kit and reception from PC using Serial Port on IDE environment use debug terminal to trace the program. 14. Generation of PWM Signal 15. Program to demonstrate SD-MMC Card Interface.
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MLR Institute of Technology
VLSI DESIGN VERIFICATION AND TESTING LAB
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45522 PCC - - 3 1.5 30 70 100
OBJECTIVES:
The course should enable the students to:
Simulate any digital function in Verilog HDL. Know the difference between synthesizable and non-synthesizable code. Learn design techniques as per current industrial needs. Design and test the logic verification using CADENCE simulation tools.
OUTCOMES:
At the end of the course students can able to :
Simulate any digital function in Verilog HDL. Design any digital circuits. Use CAD tools such as CADENCE to know the simulation flow.
Programs:
1. Write a tickle code to synthesize a combinational circuit. 2. Perform the placement of any combinational l circuit using cadence tools 3. Write a HDL code to design a counter and perform complete PD flow. 4. Design a NAND gate and perform AC and DC analysis. 5. Design a NOR gate and perform AC and DC analysis. 6. Perform post-layout simulation of NAND and NOR logic gate. 7. Design and test a current mirror. 8. Design a single stage op-amp.
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MLR Institute of Technology
PROFESSIONAL ELECTIVE -I
MODERN DIGITAL SIGNAL PROCESSING
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45504 PEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Understand the design of various types of digital filters and implement them using various implementation structures and study the advantages & disadvantages of a variety of design procedures and implementation structures. understand the concept and need for Multi-rate signal Processing and their applications in various fields of Communication & Signal Processing Understand difference between estimation & Computation of Power spectrum and the need for Power Spectrum estimation. Study various Parametric & Non parametric methods of Power spectrum estimation techniques and their advantages & disadvantages Understand the effects of finite word/register length used in hardware in implementation of various filters and transforms using finite precision processors.
OUTCOMES:
At the end of the course students can able to :
Design of various types of digital filters and implement them using various implementation structures and study the advantages & disadvantages of a variety of design procedures and implementation structures. Apply the concept and need for Multi-rate signal Processing and their applications in various fields of Communication & Signal Processing Difference between estimation & Computation of Power spectrum and the need for Power Spectrum estimation. Explain Parametric & Non parametric methods of Power spectrum estimation techniques and their advantages & disadvantages Explain the effects of finite word/register length used in hardware in implementation of various filters and transforms using finite precision processors.
UNIT-I REVIEW OF DFT, FFT, IIR FILTERS AND FIR FILTERS Classes: 11
Introduction to filter structures (IIR & FIR).Implementation of Digital Filters, specifically 2nd Order Narrow Band Filter and 1st Order All Pass Filter. Frequency sampling structures of FIR, Lattice structures, Forward prediction error, Backward prediction error, Reflection coefficients for lattice realization, Implementation of lattice structures for IIR filters, Advantages of lattice structures
UNIT-II NON-PARAMETRIC METHODS Classes: 8
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 34
MLR Institute of Technology Estimation of spectra from finite duration observation of signals, Non-parametric Methods: Bartlett, Welch & Blackman-Tukey methods, Comparison of all Non-Parametric methods
UNIT-III PARAMETRIC METHODS Classes: 12
Autocorrelation & Its Properties, Relation between auto correlation & model parameters, AR Models - Yule- Walker & Burg Methods, MA & ARMA models for power spectrum estimation, Finite word length effect in IIR digital Filters – Finite word-length effects in FFT algorithms.
UNIT-IV MULTI RATE SIGNAL PROCESSING Classes: 07
Introduction, Decimation by a factor D, Interpolation by a factor I, Sampling rate conversion by a rational factor I/D, Multistage Implementation of Sampling Rate Conversion, Filter design & Implementation for sampling rate conversion. Examples of up-sampling using an All Pass Filter.
UNIT-V APPLICATIONS OF MULTI RATE SIGNAL PROCESSING Classes: 07
Design of Phase Shifters, Interfacing of Digital Systems with Different Sampling Rates, Implementation of Narrow Band Low Pass Filters, Implementation of Digital Filter Banks, Subband Coding of Speech Signals, Quadrature Mirror Filters, Transmultiplexers, Over Sampling A/D and D/A Conversion TEXT BOOKS: 1. Digital Signal Processing: Principles, Algorithms & Applications - J.G.Proakis& D. G. Manolakis, 4th Ed., PHI. 2. Discrete Time signal processing - Alan V Oppenheim & Ronald W Schaffer, PHI. 1. 3. DSP – A Practical Approach – Emmanuel C. Ifeacher, Barrie. W. Jervis, 2 ed., Pearson Education.
REFERENCE BOOKS:
1. Modern spectral Estimation: Theory & Application – S. M .Kay, 1988, PHI. 2. Multi Rate Systems and Filter Banks – P.P.Vaidyanathan – Pearson Education. 3. Digital Signal Processing: A Practitioner's Approach, Kaluri V. Rangarao, Ranjan K. Mallik ISBN: 978- 0-475-01769-2, 210 pages, November 2006 John Weley. 4. Digital Signal Processing – S.Salivahanan, A.Vallavaraj, C.Gnanapriya, 2000,TMH
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 35
MLR Institute of Technology PROGRAMMING LANGUAGES FOR EMBEDDED SOFTWARE
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45505 PEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Write an embedded C application of moderate complexity. Develop and analyze algorithms in C++. Differentiate interpreted languages from compiled languages.
OUTCOMES:
At the end of the course students can able to:
Write an embedded C program for moderate complexity applications. Develop and analyze algorithms in C++. Differentiate interpreted languages from compiled languages.
UNIT-I EMBEDDED ‘C’ PROGRAMMING Classes: 06
Bitwise operations, Dynamic memory allocation, OS services, Linked stack and queue, Sparse matrices, Binary tree, Interrupt handling in C, Code optimization issues, Writing LCD drives, LED drivers, Drivers for serial port communication, Embedded Software Development Cycle and Methods (Waterfall, Agile)
UNIT-II OBJECT ORIENTED PROGRAMMING Classes: 06
Introduction to procedural, modular, object-oriented and generic programming techniques, Limitations of procedural programming, objects, classes, data members, methods, data encapsulation, data abstraction and information hiding, inheritance, polymorphism
UNIT-III CPP PROGRAMMING Classes: 06
‘cin’, ‘cout’, formatting and I/O manipulators, new and delete operators, Defining a class, data members and methods, ‘this’ pointer, constructors, destructors, friend function, dynamic memory allocation
UNIT-IV OVERLOADING AND INHERITANCE Classes: 07
Need of operator overloading, overloading the assignment, overloading using friends, type conversions, single inheritance, base and derived classes, friend classes, types of inheritance, hybrid inheritance, multiple inheritance, virtual base class, polymorphism, virtual functions
UNIT-V TEMPLATES Classes: 06
Function template and class template, member function templates and template arguments, Exception Handling: syntax for exception handling code: try-catch- throw, Multiple Exceptions.
UNIT-VI SCRIPTING LANGUAGES Classes: 06
Overview of Scripting Languages – PERL, CGI, VB Script, and Java Script PERL: Operators, Statements Pattern Matching etc. Data Structures, Modules, Objects, Tied Variables, Inter process Communication Threads, Compilation & Line Interfacing
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MLR Institute of Technology
TEXT BOOKS:
1. Michael J. Pont , “Embedded C”, Pearson Education, 2nd Edition, 2008 2. Randal L. Schwartz, “Learning Perl”, O’Reilly Publications, 6th Edition 2011 3. A. Michael Berman, “Data structures via C++”, Oxford University Press, 2002
REFERENCE BOOKS:
1. Robert Sedgewick, “Algorithms in C++”, Addison Wesley Publishing Company, 1999 2. Abraham Silberschatz, Peter B, Greg Gagne, “Operating System Concepts”, John Willey & Sons, 2005 3. B. A. Forouzan, R. F. Gillberg, “C Programming and Data Structures”, Cengage Learning, India, 3rd Edition, 2014. MOOC COURSE: 1. https://www.edx.org/professional-certificate/dartmouth-imtx-c-programming-with-linux
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 37
MLR Institute of Technology VLSI SIGNAL PROCESSING
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45506 PEC 3 - - 3 30 75 100
OBJECTIVES:
The course should enable the students to:
Introduce techniques for altering the existing DSP structures to suit VLSI implementations. Introduce efficient design of DSP architectures suitable for VLSI
OUTCOMES:
At the end of the course students can able to:
Ability to modify the existing or new DSP architectures suitable for VLSI. Understand the concepts of folding and unfolding algorithms and applications. Ability to implement fast convolution algorithms. Low power design aspects of processors for signal processing and wireless applications.
UNIT -I Introduction to DSP: Typical DSP algorithms, DSP algorithms benefits, Representation of DSP algorithms Pipelining and Parallel Processing: Introduction, Pipelining of FIR Digital filters, Parallel Processing, Pipelining and Parallel Processing for Low Power
UNIT –II Folding and Unfolding: Folding- Introduction, Folding Transform, Register minimization Techniques, Register minimization in folded architectures, folding of Multirate systems
UNIT -III Systolic Architecture Design: Introduction, Systolic Array Design Methodology, FIR Systolic Arrays, Selection of Scheduling Vector, Matrix Multiplication and 2D Systolic Array Design, Systolic Design for Space Representations contain Delays.
UNIT -IV Fast Convolution: Introduction – Cook-Toom Algorithm – Winogard algorithm – Iterated Convolution – Cyclic Convolution – Design of Fast Convolution algorithm by Inspection
UNIT -V Low Power Design: Scaling Vs Power Consumption, Power Analysis, Power Reduction techniques, Power Estimation Approaches
TEXT BOOKS: 1. VLSI Digital Signal Processing- System Design and Implementation – Keshab K. Parthi, Wiley Inter Science, 1998. 2. VLSI and Modern Signal processing – Kung S. Y, H. J. While House, T. Kailath, Prentice Hall, 1985. REFERENCES: 1. Design of Analog – Digital VLSI Circuits for Telecommunications and Signal Processing – Jose E. France, Yannis Tsividis, Prentice Hall, 1994. 2. VLSI Digital Signal Processing – Medisetti V. K, IEEE Press (NY), 1995.
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 38
MLR Institute of Technology
PROFESSIONAL ELECTIVES-II
PARALLEL PROCESSING
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45507 PEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Study how parallel computers work and how to analyze the correct designs of parallel architectures, especially within the technological constraints. Study of modern parallel computer architectures and parallel processing techniques and their applications from basic concepts to state-of-the-art computer systems. Provides in-depth coverage of fundamentals, design complexity, power, reliability and performance coupled with treatment of parallelism at all levels. Designing the computer systems of the future.
OUTCOMES:
At the end of the course students can able to:
Remember how parallel computers work and how to analyze the correct designs of parallel architectures, especially within the technological constraints. Explain modern parallel computer architectures and parallel processing techniques and their applications from basic concepts to state-of-the-art computer systems. Provides in-depth coverage of fundamentals, design complexity, power, reliability and performance coupled with treatment of parallelism at all levels. Designing the computer systems of the future.
UNIT-I INTRODUCTION TO PARALLEL PROCESSING CLASSES: 9
Need for parallel processing -limitations of uni-processors Concepts and Terminology-von Neumann Computer Architecture-Flynn's Classical Taxonomy-General Parallel Terminology-Limits and Costs of Parallel Programming-Parallel Computer Memory Architectures-Shared Memory-Distributed Memory- Hybrid Distributed-Shared Memory
UNIT-II PARALLEL PROCESSING PARADIGMS CLASSES: 11 parallel processing paradigms - pipelining, vector processing, instruction, thread, data level parallelism (ILP, TLP, DLP), GPUs, GPGPUs, accelerators, simultaneous-multithreading (SMT), multi/many-core processors, shared-memory multiprocessors, distributed multi-computing, and cloud/datacenter computing
UNIT-III ADDRESS THE ARCHITECTURAL SUPPORT FOR PARALLEL CLASSES: 9 PROCESSING Address the architectural support for parallel processing -parallel memory organization and design- parallel cache design and cache coherence strategies- shared-memory vs distributed-memory systems- processor/core design- communication networks for parallel computers- emerging technologies for parallel processing for memory, interconnect, processing
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MLR Institute of Technology
UNIT-IV PARALLEL PROGRAMMING Classes: 8 Principles of parallel programming design and examples of parallel programs for each category-Parallel Programming Models-Overview-Shared Memory Model-Threads Model-Distributed Memory / Message Passing Model-Data Parallel Model-Hybrid Model-SPMD and MPMP-Designing Parallel Programs- Automatic vs. Manual Parallelization-Understand the Problem and the Program-Partitioning- Communications-Synchronization-Data Dependencies-Load Balancing
UNIT-V MODERN PARALLEL COMPUTERS Classes:8 Modern parallel computers (commercial as well as experimental) design- Parallel Examples-Array Processing-PI Calculation-Simple Heat Equation-1-D Wave Equation
TEXT BOOKS:
1. 1.“Parallel Computer Organization and Design”, Michel Dubois, Murali Annavaram, and Per Stenstrom, Cambridge University Press, 2012
REFERENCE BOOKS: 1. “Advanced Computer Architecture: Parallelism, Scalability, Programmability”, by Kai Hwang, McGraw Hill 1993. As you can see this is a bit old but has many of the fundamentals of the field. 2. “Parallel Computer Architecture: A Hardware/Software Approach”, by David Culler J. P. Singh, Morgan Kaufmann, 1999. 3. “Scalable Parallel Computing: Technology, Architecture, Programming” Kai Hwang and Zhiwei Xu, McGraw Hill 1998. 4. ”Introduction to Parallel Computing,” second edition Ananth Grama Gupta, Karypis, Kumar, Pearson, Adison Wesley, 2003. 5. “Principles and Practices of Interconnection Networks,” William J. Dally and Brian Towles, Morgan Kaufmann 2003.
WEB REFERENCES: 1. https://computing.llnl.gov/tutorials/parallel_comp/OverviewRecentSupercomputers.2008.pdf 2. http://www-users.cs.umn.edu/~karypis/parbook/ 3. http://www.mcs.anl.gov/~itf/dbpp/
E-TEXT BOOKS:
1. https://dl.acm.org/citation.cfm?id=2838851 2. https://computing.llnl.gov/tutorials/parallel_comp/
MOOC COURSE:
1. https://www.mooc-list.com/tags/parallel-programming 2. https://www.mooc-list.com/course/intro-parallel-programming-udacity
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MLR Institute of Technology
CAD OF DIGITAL SYSTEM DESIGN
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45508 PEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Learn adequate knowledge of VLSI physical design automation. Understand the concepts of data structures and algorithms for physical design To design a systems with partitioning and floor planning. Understand the logic and high level synthesis. Learn the physical design automation of FPGA and MCM.
OUTCOMES:
At the end of the course students can able to
Apply the knowledge of VLSI physical design automation. Understand the concepts of data structures and algorithms for physical design Design systems with partitioning and floor planning. Explain the logic and high level synthesis. Implement physical design automation of FPGA and MCM.
VLSI PHYSICAL DESIGN AUTOMATION AND FABRICATION OF UNIT-I Classes: 09 DEVICES New Trends in Physical Design Cycle, Design Styles, System Packaging Styles, Fabrication Materials, Fabrication of VLSI Circuits, Design Rules, Layout of Basic Devices. UNIT-II DATA STRUCTURES AND BASIC ALGORITHMS Classes: 08
Complexity Issues and NP-hardness, Basic Algorithms, Basic data structures, Graph algorithms for physical design. PARTITIONING, FLOOR PLANNING, PIN ASSIGNMENT AND UNIT-III Classes: 10 PLACEMENT Problem Formulation, Classification of Partitioning Algorithms, Group Migration Algorithms, Simulated Annealing and Evolution, Performance Driven Partitioning, Floor planning: Chip planning, Pin Assignment, Placement: Problem Formulation, Classification of Placement Algorithms, Simulation Based Placement Algorithms, Partitioning Based Placement Algorithms.
UNIT-IV LOGIC & HIGH LEVEL SYNTHESIS AND VERIFICATION Classes: 09
Binary-decision Diagrams, Two-level Logic Synthesis, High-level Synthesis , Internal Representation of the Input Algorithm, Allocation, Assignment and Scheduling , High-level Transformations.
UNIT-V PHYSICAL DESIGN AUTOMATION OF FPGA AND MCM Classes: 09
FPGA Technologies, Physical Design Cycle for FPGAs: Partitioning, Routing, MCM Technologies :MCM Physical Design Cycle, Partitioning, Placement, Routing.
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MLR Institute of Technology
TEXT BOOKS:
1. N.A. Sherwani, "Algorithms for VLSI Physical Design Automation", Kluwer Academic Publishers, 2002. 2. S.H. Gerez, "Algorithms for VLSI Design Automation", John Wiley & Sons, 2002.
REFERENCE BOOKS: 1. Sadiq M. Sait, Habib Youssef, “VLSI Physical Design automation: Theory and Practice”, World scientific 1999. 1. Steven M.Rubin, “Computer Aids for VLSI Design”, Addison Wesley Publishing 1987.
WEB REFERENCES:
1. wakerly.org/DDPP/DDPP4student/Supplementary sections/CAD.pdf 2. https://link.springer.com/article/10.1007/BF02973507
E-TEXT BOOKS: 1. https://doc.lagout.org/...Algorithms/Algorithms%20for%20VLSI%20Physical%20Design. 2. https://doc.lagout.org/...Algorithms/Algorithms%20for%20VLSI%20Design%20Automa..
MOOC COURSE: 1. http://nptel videos.iitm.ac.in/softlinks/117101007 . 2. https://online courses.nptel.ac.in/noc18_cs11/course
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 42
MLR Institute of Technology
EMBEDDED REAL TIME OPERATING SYSTEMS
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45509 PEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Understand UNIX programming language. Create scheduling of tasks in RTOS. Develop case studies for real time applications
OUTCOMES:
At the end of the course students can able to:
Write an UNIX programming language. Create scheduling of tasks in RTOS. Develop case studies for real time applications
UNIT – I Introduction: Classes: 06
Introduction to UNIX/LINUX, Overview of Commands, File I/O,( open, create, close, lseek, read,write), Process Control ( fork, vfork, exit, wait, waitpid, exec.
UNIT - II Real Time Operating Systems: Classes: 06
Brief History of OS, Defining RTOS, The Scheduler, Objects, Services, Characteristics of RTOS, Defining a Task, asks States and Scheduling, Task Operations, Structure, Synchronization, Communication and Concurrency. Defining Semaphores, Operations and Use, Defining Message Queue, States, Content, Storage, Operations and Use
UNIT - III: Objects, Services and I/O: Classes: 06
Pipes, Event Registers, Signals, Other Building Blocks, Component Configuration, Basic I/O Concepts, I/O Subsystem
UNIT - IV Exceptions, Interrupts and Timers: Classes: 07
Exceptions, Interrupts, Applications, Processing of Exceptions and Spurious Interrupts, Real Time Clocks, Programmable Timers, Timer Interrupt Service Routines (ISR), Soft Timers, Operations.
UNIT - V Case Studies of RTOS: Classes: 06
RT Linux, Micro C/OS-II, Vx Works, Embedded Linux, Tiny OS and Basic Concepts of Android OS.
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MLR Institute of Technology
TEXT BOOKS:
1. Real Time Concepts for Embedded Systems – Qing Li, Elsevier, 2011
REFERENCE BOOKS:
1. Embedded Systems- Architecture, Programming and Design by Rajkamal, 2007, TMH. 2. Advanced UNIX Programming, Richard Stevens 3. Embedded Linux: Hardware, Software and Interfacing – Dr. Craig Hollabaugh
MOOC COURSE:
1. https://www.edx.org/professional-certificate/dartmouth-imtx-c-programming-with-linux
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MLR Institute of Technology
PROFESSIONAL ELECTIVES –III
MEMORY TECHNOLOGIES
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45515 PEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Design different memories Understand the various advanced memories Compare different types of memories
OUTCOMES:
At the end of the course students can able to:
Design different memories Explain the various types of advanced memories Explain the various advanced memories
UNIT-I RANDOM ACCESS MEMORIES Classes: 06
Random Access Memories (SRAMs), SRAM Cell Structures, MOS SRAM Architecture, MOS SRAM Cell and Peripheral Circuit, Bipolar SRAM, Advanced SRAM Architectures, Application Specific SRAMs. DRAMs, MOS DRAM Cell, Bi-CMOS DRAM, Error Failures in DRAM, Advanced DRAM, Design and Architecture, Application Specific DRAMs. SRAM and DRAM Memory controllers.
UNIT-II NON -VOLATILE MEMORIES Classes: 06
Non -Volatile Memories: Masked ROMs, PROMs, Bipolar & CMOS PROM, EEPROMs, Floating Gate EPROM Cell, OTP EPROM, EEPROMs, Non -volatile SRAM, Flash Memories.
UNIT-III SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS Classes: 06
Semiconductor Memory Reliability and Radiation Effects: General Reliability Issues, RAM Failure Modes and Mechanism, Nonvolatile Memory, Radiation Effects, SEP, Radiation Hardening Techniques. Process and Design Issues, Radiation Hardened Memory Characteristics, Radiation Hardness Assurance and Testing.
ADVANCED MEMORY TECHNOLOGIES AND HIGH -DENSITY MEMORY UNIT-IV Classes: 07 PACKING TECHNOLOGIES Advanced Memory Technologies and High -density Memory Packing Technologies: Ferroelectric Random Access Memories (FRAMs), Gallium Arsenide (GaAs) FRAMs, Analog Memories, Magneto Resistive Random Access Memories (MRAMs), Experimental Memory Devices.
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MLR Institute of Technology
UNIT-V MEMORY HYBRIDS Classes: 06 Memory Hybrids (2D & 3D), Memory Stacks, Memory Testing and Reliability Issues, Memory Cards High Density Memory Packaging
TEXT BOOKS:
1. Ashok K Sharma, “Advanced Semiconductor Memories: Architectures, Designs and Applications”, Wiley Interscience
REFERENCE BOOKS: 1. 1.Kiyoo Itoh, “VLSI memory chip design”, Springer International Edition. 2. 2.Ashok K Sharma,” Semiconductor Memories: Technology, Testing and Reliability, PHI.Edition, 2014.
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 46
MLR Institute of Technology SOC DESIGN
Course Code Category Hours / Week Credits Maximum Marks
To L T P C CIA SEE tal B45516 PEC 10 3 - - 3 30 70 0
OBJECTIVES:
The course should enable the students to:
Gain knowledge of entry-level industrial standard ASIC or FPGA designer. 2.Understant the issues and tools related to ASIC/FPGA Design and Implementation. 3. Understanding of basics of System on Chip and Platform based design.
OUTCOMES:
At the end of the course students can able to :
Apply the knowledge of entry-level industrial standard ASIC or FPGA designer. Describe the issues and tools related to ASIC/FPGA Design and Implementation. Explain the basics of System on Chip and Platform based design.
UNIT – I
Introduction to the System Approach: System Architecture, Components of the system, Hardware & Software, Processor Architectures, Memory and Addressing. System level interconnection, An approach for SOC Design, System Architecture and Complexity.
UNIT – II Processors: Introduction , Processor Selection for SOC, Basic concepts in Processor Architecture, Basic concepts in Processor Micro Architecture, Basic elements in Instruction handling. Buffers: minimizing Pipeline Delays, Branches, More Robust Processors, Vector Processors and Vector Instructions extensions, VLIW Processors, Superscalar Processors.
UNIT – III Memory Design for SOC: Overview of SOC external memory, Internal Memory, Size, Scratchpads and Cache memory, Cache Organization, Cache data, Write Policies, Strategies for line replacement at miss time, Types of Cache, Split – I, and D – Caches, Multilevel Caches, Virtual to real translation , SOC Memory System, Models of Simple Processor – memory interaction.
UNIT – IV Interconnect Customization and Configuration: Inter Connect Architectures, Bus: Basic Architectures, SOC Standard Buses , Analytic Bus Models, Using the Bus model, Effects of Bus transactions and contention time. SOC Customization: An overview, Customizing Instruction Processor, Reconfiguration Technologies, Mapping design onto Reconfigurable devices, Instance- Specific design, Customizable Soft Processor, Reconfiguration - overhead analysis and trade-off analysis on reconfigurable Parallelism.
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MLR Institute of Technology
UNIT – V Application Studies / Case Studies: SOC Design approach, AES algorithms, Design and evaluation, Image compression – JPEG compression.
TEXT BOOKS:
1. Michael J. Flynn and Wayne Luk, “Computer System Design System-on-Chip”, Wiley India Pvt. Ltd. 2. Steve Furber, “ARM System on Chip Architecture “, 2nd Edition, 2000, Addison Wesley Professional.
REFERENCE BOOKS:
1. Ricardo Reis, “”Design of System on a Chip: Devices and Components”, 1st Edition, 2004, Springer 2. Jason Andrews, “Co-Verification of Hardware and Software for ARM System on Chip Design (Embedded Technology)”, Newnes, BK and CDROM. 3. Prakash Rashinkar, Peter Paterson and Leena Singh L, “System on Chip Verification – Methodologies and Techniques”, 2001, Kluwer Academic Publishers.
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MLR Institute of Technology
LINUX OS
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45517 PEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Write an embedded C application of moderate complexity. Develop and analyze algorithms in C++. Differentiate interpreted languages from compiled languages.
OUTCOMES:
At the end of the course students can able to :
Write an embedded C application of moderate complexity. Develop and analyze algorithms in C++. Differentiate interpreted languages from compiled languages.
UNIT-I GNU Development tools: Classes: 09
GNU Development tools: Compilation tools and its functionalities, Debugging applications, Using Make, Creating Libraries.
UNIT-II Operating Systems Concepts: Classes: 10
Structure of Linux Operating System, Process Management, Memory Management, File System Management, I/O Management, Networking Subsystem.
UNIT-III Introduction Linux Kernel: Classes: 12
Linux installation, partitioning, Compilation of open sources, Configuration & Compilation of kernel sources, Kernel modules, Implementing System Calls.
UNIT-IV Linux Kernel Concepts: Classes: 10
The proc file system, Unified Device Model and systems, Memory Management and Allocation, User and Kernel Space communication, Interrupt Handling. Kernel Debugging.
UNIT-V Linux Device drivers: Classes: 08
Skeleton of device drivers, Character Driver, Block Drivers, Building driver into the kernel
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 49
MLR Institute of Technology Networking in Linux: Sockets, a sample example
TEXT BOOKS:
1. Programming Embedded Systems, 2nd Edition With C and GNU Development Tools by Michael Barr, Anthony Massa. 2. Michael Beck (1998), “ Linux Kernel Internals”, Addison Wealey 3. Doug Abbott. (2003), “Linux for Embedded and Real time Applications”, Newnes publishers.
REFERENCE BOOKS:
1. Understanding the Linux Kernel, Third Edition Daniel P. Bovet , Marco Cesati, 3rd edition, Orally Publications 2. Linux Device Drivers, 3rd edition, Linux Device Drivers, 3rd Edition Jonathan Corbet, Alessandro Rubini , Greg Kroah-Hartman, Orally Publications 3. Advanced Programming in UNIX Environment– Richard Stevens, Addison-Wesley, 1992. 4. Linux Kernel Development, Robert Love, 2nd Edition, 2006, Pearson Education.
MOOC COURSES: 1. https://www.edx.org/professional-certificate/dartmouth-imtx-c-programming-with-linux
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MLR Institute of Technology
PROFESSIONAL ELECTIVES -IV
DEVICE DRIVERS OF EMBEDDED SYSTEMS
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45518 PEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Explain the architecture of Embedded Systems and Operating System Fundamentals. Describe the fundamentals of Real Time Operating Systems. Explain the internals of operating systems and its kernel. Describe the fundamentals of device drivers Develop the Device Drivers and Real Time Operating Systems.
OUTCOMES:
At the end of the course students can able to:
Draw and explain the architecture of Embedded Systems and Operating System Fundamentals. Describe the fundamentals of Real Time Operating Systems. Explain the internals of operating systems and its kernel. 4.Describe the fundamentals of device drivers 5. Develop the Device Drivers and Real Time Operating Systems.
UNIT-I INTRODUCTION Classes: 09
Embedded System Architecture fundamentals- Hardware and Software abstraction models - Operating Systems fundamentals- Process Creation-Scheduling-Memory Management-Inter Process Synchronization – Inter Process Communication - Real time OS overview.
UNIT-II RTOS FUNDAMENTALS Classes: 10
Study of Real time OS principles and requirements, Application specific requirements, Throughput and latency requirements - Schedulers, tasks and processes - Memory management - Code and footprint optimization - Study of current and emerging RTOS.
UNIT-III OS INTERNALS AND KERNELS Classes: 12
Internal components of Operating systems, study, compare and contrast of various OS platforms. Unix/Linux kernel fundamentals-Process Scheduling-Kernel Synchronization, I/O devices-Architecture-Character, Block Device handling, file systems- The Ext2 file System-The Virtual File System and peripheral devices.
UNIT-IV DEVICE DRIVERS Classes: 10
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 51
MLR Institute of Technology Fundamentals of device drivers-Character and Block Devices -Polling and Interrupts-The Hardware, device enumeration and configuration, Data transfer and management mechanisms
UNIT-V CASE STUDIES Classes: 08
Study and Implementation of RTOS -Study and Implementation of Kernel modification - Study and Implementation of Device Driver development – Kernel Module Development – Simple Character Device Driver Development
Note: Tools used during laboratory works: Keil, Cypress PSoC, Windows Mobile, Linux, VxWorks, Symbian platforms.
TEXT BOOKS:
1. Product documentation from ARM (KEIL), Cypress, Windows Mobile, VxWorks, Symbian 2. Charles Crowley, “Operating Systems: A Design-Oriented Approach”, Irwin Professional Publishing, 1996.
REFERENCE BOOKS:
1. Abrah Silberschatz, Peter B. Galvin and Greg Gagne, “Operating system concepts”, Wiley, 9th edition, 2012. 2. Robert Love, “Linux Kernel Development”, Addison Wesley, 3rd edition, 2010. 3. Daniel P. Bovet, Marco Cesati, “Understanding the Linux Kernel”, O′Reilly, 3rd edition, 2005. 4. Wolfgang Mauerer , “Professional Linux Kernel Architecture”, Wrox, 2008. 5. M Beck, H Bohme M Dziadzka, U Kunitz, R Magnus, D Verworner, “Linux Kernel –Internals”, Addision Wesley, Second Edition, 1998. MOOC COURSE: 1. https://www.edx.org/professional-certificate/dartmouth-imtx-c-programming-with-linux
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MLR Institute of Technology
NETWORK SECURITY AND CRYPTOGRAPHY
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45519 PEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Know techniques involved to support real-time traffic and congestion control. Determine related hardware and software components to meet the designed network. Demonstrate the knowledge of network planning and optimization. Analyze critically and reflect on the relations and interrelations of the designed network. Provided with Protocol for quality of service (Qos) to different applications
OUTCOMES:
At the end of the course students can able to:
Remember the techniques involved to support real-time traffic and congestion control. Determine related hardware and software components to meet the designed network. Demonstrate the knowledge of network planning and optimization. Analyze critically and reflect on the relations and interrelations of the designed network. Provided with Protocol for quality of service (Qos) to different applications
UNIT-I INTRODUCTION TO SECURITY Classes: 11
Basic notions of security, security properties (confidentiality, integrity and availability), security vulnerabilities, threats and attacks, the use of attack trees in evaluating and classifying security vulnerabilities and threats, security models, policies and mechanisms
UNIT-II CRYPTOGRAPHIC METHODS (OR PRIMITIVES) Classes: 8
Classical encryption techniques, Feistel encryption and decryption, symmetrical (or conventional) ciphers, block cipher and stream cipher principles and operations, introduction to number theory, asymmetrical (or public-key) ciphers cryptographic hash functions, Message Authentication Code (MACs), digital signatures
UNIT-III ESTABLISHING TRUST, CRYPTOGRAPHIC (OR SECURITY) PROTOCOLS Classes: 12
Diffie-Hellman key exchange, symmetric key distributions, digital certificates and Public Key Infrastructures (PKIs), user identification and authentication, single sign on, cryptographic protocol analysis and design
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MLR Institute of Technology
UNIT-IV NETWORK AND INTERNET SECURITY Classes: 07
IP security, web security, email security, Wireless Local Area Network (WLAN) security, e-commerce security, Cloud computing security
UNIT-V PROTOCOLS FOR QOS SUPPORT Classes: 07
RSVP - Goals & Characteristics, Data Flow, RSVP operations, Protocol Mechanisms - Multiprotocol Label Switching Operations, Label Stacking, Protocol details - RTP - Protocol Architecture, Data Transfer Protocol, RTCP. TEXT BOOKS:
1. Stallings, Cryptography and Network Security: Principles and Practice, 5/e (Prentice Hall, 2010).
REFERENCE BOOKS:
1. Kaufman, Perlman and Speciner, Network Security: Private Communications in a Public World, second edition (Prentice Hall, 2003) 2. Goodrich and Tamassia, Introduction to Computer Security (2010, Addison-Wesley).
WEB REFERENCES:
1. 1.https://www.wiley.com/en-ca/Information+Security%3A 2. 2.http://www.avirubin.com/books/book1/
E-TEXT BOOKS:
1. 1.https://onlinelibrary.wiley.com/doi/book/10.1002/0471224391 2. 2.hJp://cseweb.ucsd.edu/~mihir/papers/gb.pdf
MOOC COURSE
1. 1.https://www.mooc-list.com/course/mathematical-foundations-cryptography-coursera 2. 2.https://www.mooc-list.com/course/basic-cryptography-and-programming-crypto-api-coursera
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MLR Institute of Technology
EMBEDDED SYSTEMS WITH IOT
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45520 PEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Understand fundamentals of IoT and embedded system including essence, basic design strategy and process modeling. Introduce students a set of advanced topics in embedded IoT and lead them to understand research in network. Develop comprehensive approach towards building small low cost embedded IoT system. Understand fundamentals of security in IoT Learn to implement secure infrastructure for IoT Learn real world application scenarios of IoT along with its societal and economic impact using case studies
OUTCOMES:
At the end of the course students can able to:
Discuss the fundamentals of IoT and embedded system including essence, basic design strategy and process modeling. Introduce a set of advanced topics in embedded IoT and lead them to understand research in network. Develop comprehensive approach towards building small low cost embedded IoT system. Explain the fundamentals of security in IoT Implement secure infrastructure for IoT Apply real world application scenarios of IoT along with its societal and economic impact using case studies
UNIT-I INTRODUCTION TO EMBEDDED SYSTEM AND INTERNET OF THINGS CLASSES: 9
Embedded Systems:
Application Domain and Characteristic of Embedded System, Real time systems and Real-time scheduling, Processor basics and System-On-Chip, Introduction to ARM processor and its architecture.
IOT:Definition and characteristics of IoT, Internet of Things: Vision, Emerging Trends, Economic Significance, Technical Building Blocks, Physical design of IoT, Things of IoT, IoT Protocols, Logical design of IoT, IoT functional blocks, IoT communication models, IoT Communication APIs, IoT enabling technologies, IoT levels and deployment templates, IoT Issues and Challenges, Applications.
UNIT-II EMBEDDED IOT PLATFORM DESIGN METHODOLOGY CLASSES: 11
Purpose and requirement specification, Process specification, Domain model specification, information model specification, Service specifications, IoT level specification, Functional view specification, Operational view
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MLR Institute of Technology specification, Device and component integration, Application development
UNIT-III PILLARS OF EMBEDDED IOT AND PHYSICAL DEVICES CLASSES: 9
Horizontal, verticals and four pillars of IoT, M2M: The internet of devices, RFID: The internet of objects, WSN: The internet of transducer, SCADA: The internet of controllers, DCM: Device, Connect and Manage, Device: Things that talk, Connect: Pervasive Network, IoT Physical Devices and Endpoints: Basic building blocks of and IoT device, Exemplary device: ▪ Raspberry Pi, Raspberry Pi interfaces, ▪ Programming Raspberry Pi with Python, ▪ Beagle board and Other IoT Devices.
UNIT-IV IOT PROTOCOLS AND SECURITY Classes: 8
Protocol Standardization for IoT, M2M and WSN Protocols, SCADA and RFID Protocols, Issues with IoT Standardization, Unified Data Standards, Protocols – IEEE 802.15.4, BACNet Protocol, Modbus, KNX, Zigbee Architecture, Network layer, APS layer. IoT Security: Vulnerabilities of IoT, Security Requirements, Challenges for Secure IoT, Threat Modeling, Key elements of IoT Security: Identity establishment, Access control, Data and message security, Non-repudiation and availability, Security model for IoT.
UNIT-V WEB OF THINGS AND CLOUD OF THINGS Classes:8
Web of Things versus Internet of Things, Two Pillars of the Web, Architecture Standardization for WoT, Platform Middleware for WoT, Unified Multitier WoT Architecture, WoT Portals and Business Intelligence. Cloud of Things: Grid/SOA and Cloud Computing, Cloud Middleware, Cloud Standards – Cloud Providers and Systems, Mobile Cloud Computing, The Cloud of Things Architecture.
TEXT BOOKS:
1. Introduction to Embedded Systems - Shibu K.V, Mc Graw Hill. 2. Vijay Madisetti, Arshdeep Bahga, “Internet of Things: A Hands-On Approach”
REFERENCE BOOKS:
1. Embedded Systems - Raj Kamal, TMH
WEB REFERENCES:
2. https://www.bharathuniv.ac.in/colleges1/downloads/courseware_ece/notes/BEI605-%20Embedded- System.pdf 3. https://www.ics.uci.edu/~givargis/pubs/C62.pdf 4. https://www.tutorialspoint.com/internet_of_things/internet_of_things_tutorial.pdf 5. https://www.cisco.com/c/dam/en_us/solutions/trends/iot/introduction_to_IoT_november.pdf
E-TEXT BOOKS:
1. http://read.pudn.com/downloads158/ebook/757537/Embedded%20Systems%20Design%20-%202ed%20- %200750655461.pdf 2. http://www.internet-of-things-research.eu/pdf/IoT- From%20Research%20and%20Innovation%20to%20Market%20Deployment_IERC_Cluster_eBook_978- 87-93102-95-8_P.pdf 3. http://www.buyya.com/papers/IoT-Book2016-C1.pdf
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 56
MLR Institute of Technology
MOOC COURSE:
1. https://www.mooc-list.com/tags/iot 2. https://www.mooc-list.com/tags/embedded-systems
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 57
MLR Institute of Technology
PROFESSIONAL ELECTIVE – V
DATA COMMUNICATION NETWORKS
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45523 PEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Understand the function of OSI layer in communication
Aware about the network security
OUTCOMES:
At the end of the course students can able to
Explain the function of OSI layer in communication
Aware about the network security
UNIT-I PHYSICALLAYER CLASSES: 9
Network Hardware, Topology, Network Software, Reference Models, Example Networks, Uses of Computer Networks, ARPANET, Connection Oriented Networks, X.25, Frame Relay, ATM
PHYSICALLAYER: The Theoretical Basis for Data Communication, The Public Switched Telephone Network, The Mobile Telephone System
CLASSES: UNIT-II DATA LINK LAYER & MEDIUM ACCESS CONTROL SUB LAYER 11
DATA LINK LAYER: Data Link Layer Design Issues, Error Detection and Correction, Elementary Data Link Protocols, Sliding Window Protocols, Example Data Link Protocols
MEDIUM ACCESS CONTROL SUB LAYER: The Channel Allocation Problem, Multiple Access Protocols, Ethernet, Wireless LANs, Broadband Wireless, Bluetooth, RFID, Data Link Layer Switching
UNIT-III NETWORK LAYER& TRANSPORT LAYER CLASSES: 9
NETWORK LAYER: Network Layer Design Issues, Routing Algorithms, Congestion Control Algorithms, Quality of Service, Internetworking, The Network Layer in the Internet.
TRANSPORT LAYER: The Transport Service, Elements of Transport Protocols, Congestion Control Algorithms, The Internet Transport Protocols: UDP, The Internet Transport Protocols: TCP, Performance
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 58
MLR Institute of Technology Issues, Delay Tolerant Networks.
UNIT-IV APPLICATION LAYER: Classes: 8
APPLICATION LAYER:DNS--The Domain Name System, The World Wide Web, Real-time Audio and Video, Content Delivery and Peer-To-Peer, SMTP and HTTP Protocol
UNIT-V NETWORK SECURITY Classes:8
Cryptography, Symmetric-Key Algorithms, Public-Key Algorithms, Digital Signatures, Management Of Public Keys, IPsec, Firewalls, Virtual Private Networks, Wireless Security, Security Issues And Challenges in Wireless Networks, Authentication Protocols, Email Security, Web Security, Social Issues
TEXT BOOKS:
1. Communications and networking Fourth Edition Behrouz A. Forouzan DeAnza CollegeMcGraw-Hill Forouzan Networking Series
REFERENCE BOOKS:
1. Stallings, Cryptography and Network Security: Principles and Practice, 5/e (Prentice Hall, 2010).
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 59
MLR Institute of Technology DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45524 PEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Understand fundamentals of digital signal processors and its architectures Remember the functional blocks and features of DSP’s . Interface the required hardware with DSP’s. Use the DSP’s in real-time applications
OUTCOMES:
At the end of the course students can able to:
Draw and explain fundamentals of digital signal processors and its architectures Remember the functional blocks and features of DSP’s . Interface the required hardware with DSP’s. 4. Use the DSP’s in real-time applications
CLASSES: UNIT-I INTRODUCTION TO DIGITAL SIGNAL PROCESSORS 9
Introduction to DSP- Evolution of DSP’s-General purpose and special purpose DSP’s-Fixed and floating point DSP’s- selection of DSP- Basic architectures of DSP- Von neuman- Harward- modified harward architecture(VLIW) – comparison of architectures- Introduction to Commercial DSP’s – Introduction to 8/16 bit DSP’s
CLASSES: UNIT-II ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES 11
Architectures for Programmable DSP Devices: Basic Architectural features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address Generation UNIT, Programmability and Program Execution, Speed Issues, Features for External interfacing.
CLASSES: UNIT-III PROGRAMMABLE DIGITAL SIGNAL PROCESSORS 9
Programmable Digital Signal Processors: Commercial Digital signal-processing Devices, Addressing modes of TMS320C54XX DSPs, Memory space of TMS320C54XX Processors, Program Control, TMS320C54XX Instructions and Programming, interrupt programming.
UNIT-IV ANALOG DEVICES FAMILY OF DSP DEVICES Classes: 8
Analog Devices Family of DSP Devices: Analog Devices Family of DSP Devices – ALU and MAC block diagram, Shifter Instruction, Base Architecture of ADSP 2100, ADSP-2181 high performance Processor.
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 60
MLR Institute of Technology Introduction to Black fin Processor
INTERFACING MEMORY AND I/O PERIPHERALS TO PROGRAMMABLE UNIT-V Classes:8 DSP DEVICES
Interfacing Memory and I/O Peripherals to Programmable DSP Devices: Memory space organization, External bus interfacing signals, Memory interface, Parallel I/O interface, Programmed I/O, Interrupts and I/O, Direct memory access (DMA).
TEXT BOOKS:
1. Digital Signal Processing – Avtar Singh and S. Srinivasan, Thomson Publications, 2004. 2. A Practical Approach To Digital Signal Processing - K Padmanabhan, R. Vijayarajeswaran, Ananthi. S, New Age International, 2006/2009 3. Embedded Signal Processing with the Micro Signal Architecture: Woon-Seng Gan, Sen M. Kuo, Wiley- IEEE Press, 2007
REFERENCE BOOKS:
1. Digital Signal Processors, Architecture, Programming and Applications – B. Venkataramani and M. Bhaskar, 2002, TMH. 2. Digital Signal Processing – Jonatham Stein, 2005, John Wiley. 3. DSP Processor Fundamentals, Architectures & Features – Lapsley et al. 2000, S. Chand & Co. 4. Digital Signal Processing Applications Using the ADSP-2100 Family by The Applications Engineering Staff of Analog Devices, DSP Division, Edited by Amy Mar, PHI 5. The Scientist and Engineer's Guide to Digital Signal Processing by Steven W. Smith, Ph.D., California Technical Publishing, ISBN 0-9660176-3-3, 1997 6. Embedded Media Processing by David J. Katz and Rick Gentile of Analog Devices, Newnes ,ISBN 0750679123, 2005 WEB7. REFERENCES:
1. http://www.ti.com/processors/dsp/media-processors/audio/overview.html 2. https://dl.acm.org/citation.cfm?id=882108
E-TEXT BOOKS:
1. https://books.google.co.in/books?id=FghwqsTuqNYC&source=gbs_similarbooks 2. https://books.google.co.in/books/about/Digital_Signal_Processors.html?id=2A_2- v3raKEC&redir_esc=y
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 61
MLR Institute of Technology
NANO MATERIALS AND NANO TECHNOLOGY
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45525 PEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Learn the basic science behind the fabrication of nonmaterial’s Study the new solutions for current problems and competing technologies for future applications. Study an inter disciplinary projects applicable to wide areas. Study the fabrication process and characterization of devices to achieve precisely designed systems.
OUTCOMES:
At the end of the course students can able to:
Learn the basic science behind the fabrication of nonmaterial’s Apply the new solutions for current problems and competing technologies for future applications. Find an inter disciplinary projects applicable to wide areas. Explain the fabrication and characterization of devices to achieve precisely designed systems
CLASSES: UNIT-I NANOMATERIALS IN ONE AND HIGHER DIMENSIONS 09
Basic concept of Nano science and technology, Quantum wire, Quantum well, Quantum dot, properties and technological advantages of Nano materials, carbon nanotubes and application, material processing by Sol, Gel method, Chemical vapor deposition and physical vapour deposition, principles of SEM,TEM and AFM.
CLASSES: UNIT-II APPLICATIONS OF ONE AND HIGHER DIMENSION NANO-MATERIALS 09
Application of Fullerene, CNT, Graphene and other carbon nonmaterial’s, Mechanical, Thermal application, Electronic applications and biological applications.
NANO-LITHOGRAPHY, MICRO ELECTRO-MECHANICAL SYSTEM (MEMS) CLASSES: UNIT-III AND NANO-PHONICS 11
Necessity for a clean room, different types of clean rooms, Lithography, Printing, Chemical process, Etching techniques, the modern process, optical micro, nanolithography, Applications of nanolithography. Introduction to Micro sensors and MEMS, Evolution of Micro sensors & MEMS, MEMS types, MEMS sensors, Applications and Advantages of MEMS technology. Photons and electrons, similarities and differences, free space propagation, confinement of photons and electrons, nanoscale optical interaction, axial and lateral nanoscopic
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 62
MLR Institute of Technology localization, nanoscale confinement of electronics interactions.
CLASSES: UNIT-IV CARBON NANOTUBES, SYNTHESIS AND APPLICATIONS 08
History, types of CNTs, synthesis methods, CVD method, Laser ablation and electric arc processes growth mechanisms, purification methods, applications Lithiumion battery, fuel cell sensor applications, applications to nanoelectronics, nanocomposites.
CLASSES: UNIT-V INTERDISCIPLINARY ARENA OF NANOTECHNOLOGY 08
Energy challenge in the 21st Century and nanotechnology, conventional and unconventional fissile fuels, nanotechnology in fuel production, renewable energy sources, photovoltaics, hydrogen production, fuel cells, thermoelectricity, implementation of renewable energy technologies.
TEXT BOOKS:
1. Nanoscale Materials in Chemistry edited by Kenneth J. Klabunde and Ryan M. Richards, 2ndedn, John Wiley and Sons, 2009. 2. Nanocrystalline Materials by A I Gusev and A A Rempel, Cambridge International Science Publishing, 1st Indian edition by Viva Books Pvt. Ltd. 2008. 3. Springer Handbook of Nanotechnology by Bharat Bhushan, Springer, 3rdedn, 2010 1. Carbon Nanotubes: Synthesis, Characterization and Applications by Kamal K. Kar, Research Publishing Services; 1stedn, 2011, ISBN-13: 978-9810863975.
REFERENCE BOOKS:
1. Springer Handbook of Nanotechnology by Bharat Bhushan, Springer, 3rdedn, 2010 2. Carbon Nanotubes: Synthesis, Characterization and Applications by Kamal K. Kar, Research Publishing Services; 1stedn, 2011, ISBN-13: 978-9810863975. 3. Understanding Nano materials by Malkiat S. Johal (Apr 26, 2011) WEB REFERENCES:
1. http://web.pdx.edu/~pmoeck/phy381/workbook%20nanoscience.pdf
E-TEXT BOOKS:
1. https://www.researchgate.net/publication/233796186_Introduction_to_Nanoscience_and_Nanotechnol ogy 2. http://elibrary.bsu.az/books_250/N_229.pdf
MOOC COURSE:
1. http://nptel.ac.in/syllabus/118104008/ 2. https://www.coursera.org/learn/nanotechnology1
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 63
MLR Institute of Technology
PEN ELECTIVES
PRINCIPLES OF SIGNAL PROCESSING
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45526 OEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Identify various signals and systems. Understand various transformation techniques and apply them to find spectral domain representation of various signals. Apply convolution and correlation operations between various signals and systems. Develop the digital filter designs. Understand Multirate digital signal processing concepts.
OUTCOMES:
At the end of the course students can able to
Identify various signals and systems. Apply various transformation techniques and apply them to find spectral domain representation of various signals. Apply convolution and correlation operations between various signals and systems. Develop the digital filter designs. Explain the Multirate digital signal processing concepts.
UNIT-I INTRODUCTION TO DIGITAL SIGNAL PROCESSING Classes: 09
Introduction, A digital Signal – Processing system, the sampling process, Discrete time sequences, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), linear time-invariant systems, Digital filters, Decimation and interpolation.
UNIT-II DIGITAL FILTERS Classes: 09
IIR Filters: IIR Analog filter approximations - Butterworth and Chebyshev, Design of IIR Digital filters from analog filters: Impulse invariant techniques, Bilinear transformation method..FIR Filters: Characteristics of FIR Digital Filters, Frequency response, Design of FIR Filters: Fourier Method. Window Techniques, Comparison of IIR & FIR filters.
UNIT-III MULTIRATE DIGITAL SIGNAL PROCESSING Classes: 09
Introduction. Down sampling, Decimation. Up sampling, Interpolation, Sampling Rate Conversion, conversion of
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 64
MLR Institute of Technology band pass signals. Concept of re-sampling. Applications of multi rate signal processing.
UNIT-IV ARCHITECTURE OF ARM PROCESSORS Classes: 09
Introduction to the architecture, Programmer’s model- operation modes and states, registers, special registers, floating point registers, Behavior of the application program status register(APSR)
UNIT-V DIGITAL SIGNAL PROCESSORS Classes: 09
TMS320C54XX processors, memory space of TMS320C54XX processors, Program control, TMS320C54XX instructions and programming, On-Chip peripherals, Interrupts of TMS320C54XX processors
TEXT BOOKS:
1. John G. Proakis, Dimitris G. Manolakis , Digital Signal Processing, Pearson Prentice Hall, 2007. 2. B.P. Lathi, Signals, Systems & Communications, BS Publications 2013 . 3. Sophocles J. Orfanidis, Introduction to Signal Processing, Pearson Prentice Hall, 1998. 4. Avtar Singh and S. Srinivasan, “Digital Signal Processing”, CENGAGE Learning, 2004
REFERENCE BOOKS:
1. 1.A.V. Oppenheim, Signals and Systems - A.S. Willsky and S.H. Nawab, 2 Ed., 2. Li Tan, Digital Signal Processing - Fundamentals and Applications - Elsevier. 2008. 3. Robert J. Schilling. Sandra L, Harris, Fundamentals of Digital Signal Processing using Matlab – Thomson 2007
WEB REFERENCES:
1. 1.http://www.freebookcentre.net/special-books-download/An-Introduction-to-Signal-Processing-(T.- OHaver).html 2. 2.https://www.sciencedirect.com/science/article/pii/B9780123965028000012 3. 3.Applied Digital Signal Processing (1st Edition)
E-TEXT BOOKS:
1. 1. http://gen.lib.rus.ec/book/index.php?md5=69531D2C9E6A3A5111E2CC1977F75F59 2. 2.http://www.freebookcentre.net/special-books-download/Introduction-to-DSP-(Digital-Signal- 3. Processing).html
MOOC COURSES: 1. 1.https://www.mooc-list.com/course/digital-signal-processing-coursera 2. 2.http://nptel.ac.in/courses/117102060/
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 65
MLR Institute of Technology APPLICATIONS OF IOT
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45527 OEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Understand Embedded Systems and IoT. Categorize different IoT systems Solve real time problems using IoT
OUTCOMES:
At the end of the course students can able to
Understand the concept of IOT and M2M Study IOT architecture and applications in various fields Study the security and privacy issues in IOT.
UNIT-I
IoT& Web Technology The Internet of Things Today, Time for Convergence, Towards the IoT Universe, Internet of Things Vision, IoT Strategic Research and Innovation Directions, IoT Applications, Future Internet Technologies, Infrastructure, Networks and Communication, Processes, Data Management, Security, Privacy & Trust, Device Level Energy Issues, IoT Related Standardization, Recommendations on Research Topics.
UNIT-II
M2M to IoT – A Basic Perspective– Introduction, Some Definitions, M2M Value Chains, IoT Value Chains, An emerging industrial structure for IoT, The international driven global value chain and global information monopolies. M2M to IoT-An Architectural Overview– Building an architecture, Main design principles and needed capabilities, An IoT architecture outline, standards considerations.
UNIT-III
IoT Architecture -State of the Art – Introduction, State of the art, Architecture Reference Model- Introduction, Reference Model and architecture, IoT reference Model, IoT Reference Architecture- Introduction, Functional View, Information View, Deployment and Operational View, Other Relevant architectural views.
UNIT-IV
IoT Applications for Value Creations Introduction, IoT applications for industry: Future Factory Concepts, Brownfield IoT, Smart Objects, Smart Applications, Four Aspects in your Business to Master IoT, Value Creation from Big Data and Serialization, IoT for Retailing Industry, IoT For Oil and Gas Industry, Opinions on IoT Application and Value for Industry, Home Management, eHealth.
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 66
MLR Institute of Technology
UNIT-V
Internet of Things Privacy, Security and Governance Introduction, Overview of Governance, Privacy and Security Issues,
TEXTBOOKS
1. Vijay Madisetti and Arshdeep Bahga, “Internet of Things (A Hands-on-Approach)”, 1st Edition, VPT, 2014. 2. Francis daCosta, “Rethinking the Internet of Things: A Scalable Approach to Connecting Everything”, 1st Edition, Apress Publications, 2013. 3. Cuno Pfister, “Getting Started with the Internet of Things”, O Reilly Media, 2011.
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 67
MLR Institute of Technology
WASTE TO ENERGY
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B45531 OEC 3 - - 3 30 70 100
OBJECTIVES:
The course should enable the students to:
Use wastes by renewable energy Aware about Energy sources OUTCOMES:
At the end of the course students can able to:
Convert wastes into renewable energy Aware about Energy sources
UNIT-I INTRODUCTION TO ENERGY FROM WASTE Classes: 06
Unit-I: Introduction to Energy from Waste: Classification of waste as fuel – Agro based, Forest residue, Industrial waste - MSW – Conversion devices – Incinerators, gasifiers, digestors
UNIT-II BIOMASS PYROLYSIS Classes: 06
Biomass Pyrolysis: Pyrolysis – Types, slow fast – Manufacture of charcoal – Methods - Yields and application – Manufacture of pyrolytic oils and gases, yields and applications.
UNIT-III BIOMASS GASIFICATION: GASIFIERS Classes: 06
Yrolysis-Biomass Gasification: Gasifiers – Fixed bed system – Downdraft and updraft gasifiers – Fluidized bed gasifiers – Design, construction and operation – Gasifier burner arrangement for thermal heating – Gasifier engine arrangement and electrical power – Equilibrium and kinetic consideration in gasifier operation.
UNIT-IV BIOMASS COMBUSTION Classes: 07
Biomass Combustion: Biomass stoves – Improved chullahs, types, some exotic designs, Fixed bed combustors, Types, inclined grate combustors, Fluidized bed combustors, Design, construction and operation - Operation of all the above biomass combustors.
UNIT-V BIOGAS Classes: 06
Biogas: Properties of biogas (Calorific value and composition) - Biogas plant technology and status - Bio energy system - Design and constructional features - Biomass resources and their classification - Biomass conversion processes - Thermo chemical conversion - Direct combustion - biomass gasification - pyrolysis and liquefaction - biochemical conversion - anaerobic digestion - Types of biogas Plants – Applications - Alcohol production from biomass - Bio diesel production - Urban waste to energy conversion - Biomass energy
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 68
MLR Institute of Technology programme in India.
TEXT BOOKS:
1. Non Conventional Energy, Desai, Ashok V., Wiley Eastern Ltd., 1990. Model Curriculum of Engineering & Technology PG Courses [Volume -II] [ 380 ]
REFERENCES:
1. Biogas Technology - A Practical Hand Book - Khandelwal, K. C. and Mahdi, S. S., Vol. I & II, Tata McGraw Hill Publishing Co. Ltd., 1983. 2. Food, Feed and Fuel from Biomass, Challal, D. S., IBH Publishing Co. Pvt. Ltd., 1991. 3. Biomass Conversion and Technology, C. Y. WereKo-Brobby and E. B. Hagan, John Wiley & Sons, 1996.
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 69
MLR Institute of Technology
AUDIT COURSE-I
ENGLISH FOR RESEARCH PAPER WRITTING
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B4AC01 AC 2 - - - 30 70 100
OBJECTIVES:
Students will be able to:
Understand that how to improve your writing skills and level of readability. Learn about what to write in each section. Understand the skills needed when writing a Title.
OUTCOMES:
At the end of the course students can able to:
Discuss that how to improve your writing skills and level of readability. Learn about what to write in each section. Apply the skills needed when writing a Title.
UNIT-I PLANNING AND PREPARATION Classes: 13
Word Order, Breaking up long sentences, Structuring Paragraphs and Sentences, Being Concise and Removing Redundancy, Avoiding Ambiguity and Vagueness.
UNIT-II STRUTURE OF THE PAPER Classes: 13
Clarifying Who Did What, Highlighting Your Findings, Hedging and Criticizing, Paraphrasing and Plagiarism, Sections of a Paper, Abstracts. Review of the Literature, Methods, Results, Discussion, Conclusions, The Final Check.
UNIT-III KEY SKILLS Classes: 12
Key skills are needed when writing a Title; key skills are needed when writing an Abstract, key skills are needed when writing an Introduction, skills needed when writing a Review of the Literature.
UNIT-IV RESULTS AND DISCUSSION Classes: 12
Skills are needed when writing the Methods, skills needed when writing the Results, skills are needed when writing the Discussion, skills are needed when writing the Conclusions
UNIT-V SUBMISSION Classes: 10
Useful phrases, how to ensure paper is as good as it could possibly be the first- time submission
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 70
MLR Institute of Technology TEXT BOOKS:
1. Goldbort R (2006) Writing for Science, Yale University Press. 2. Day R (2006) How to Write and Publish a Scientific Paper, Cambridge University Press.
REFERENCE BOOKS:
1. Highman N (1998), Handbook of Writing for the Mathematical Sciences, SIAM. Highman’sbook . 2. Adrian Wallwork, English for Writing Research Papers, Springer New York Dordrecht Heidelberg London, 2011. WEB REFERENCES:
1. https://www.springer.com/in/book/9781441979223 2. http://www.phdmanagement.sssup.it/documenti/syllabus/VII/English%20for%20Papers%20exercise s.pdf
E-TEXT BOOKS:
3. http://saba.kntu.ac.ir/eecd/ecourses/Seminar90/2011%20English%20for%20Writing%20Research%20 Papers.pdf 4. https://books.google.co.in/books/about/English_for_Writing_Research_Papers.html?id=I6_8kSeQ4LY C 5. https://www.nature.com/scitable/ebooks/english-communication-for-scientists-14053993/writing- scientific-papers-14239285
MOOC COURSES:
1. https://www.coursera.org/specializations/academic-english 2. https://www.mooc-list.com/tags/academic-writing
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 71
MLR Institute of Technology
RESEARCH METHODOLOGY AND IPR
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B4AC02 AC 2 - - 30 70 100
OBJECTIVES:
At the end of this course, students will be able to:
Understand research problem formulation. Analyze research related information. Follow research ethics. Understand that today’s world is controlled by Computer, Information Technology, but tomorrow world will be ruled by ideas, concept, and creativity. Understanding that when IPR would take such important place in growth of individuals &nation, it is needless to emphasis the need of information about Intellectual Property Right to be promoted among students in general & engineering in particular. Understand that IPR protection provides an incentive to inventors for further research work and investment in R & D, which leads to creation of new and better products, and in turn brings about, economic growth and social benefits. OUTCOMES:
At the end of the course students can able to:
Explain research problem formulation. Analyze research related information. Follow research ethics. Know the today’s world is controlled by Computer, Information Technology, but tomorrow world will be ruled by ideas, concept, and creativity. Know IPR would take such important place in growth of individuals &nation, it is needless to emphasis the need of information about Intellectual Property Right to be promoted among students in general & engineering in particular. Explain IPR protection provides an incentive to inventors for further research work and investment in R & D, which leads to creation of new and better products, and in turn brings about, economic growth and social benefits.
UNIT-I RESEARCH PROBLEM Classes: 13
Meaning of research problem, Sources of research problem, Criteria Characteristics of a good research problem, Errors in selecting a research problem, Scope and objectives of research problem. Approaches of investigation of solutions for research problem, data collection, analysis, interpretation, Necessary instrumentations.
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 72
MLR Institute of Technology
UNIT-II LITERATURE STUDIES AND TECHNICAL WRITING Classes: 12
Effective literature studies approaches, analysis Plagiarism, Research ethics, Effective technical writing, how to write report, Paper Developing a Research Proposal, Format of research proposal, a presentation and assessment by a review committee.
UNIT-III NATURE OF INTELLECTUAL PROPERTY Classes: 12
Patents, Designs, Trade and Copyright. Process of Patenting and Development: technological research, innovation, patenting, development. International Scenario: International cooperation on Intellectual Property. Procedure for grants of patents, Patenting under PCT.
UNIT-IV Classes: 11 PATENT RIGHTS
Scope of Patent Rights. Licensing and transfer of technology. Patent information and databases. Geographical Indications.
UNIT-V NEW DEVELOPMENTS IN IPR Classes: 12
Administration of Patent System. New developments in IPR; IPR of Biological Systems, Computer Software etc. Traditional knowledge Case Studies, IPR and IITs.
TEXT BOOKS:
1. Stuart Melville and Wayne Goddard, “Research methodology: an introduction for science & engineering students’” 2. Wayne Goddard and Stuart Melville, “Research Methodology: An Introduction” 3. Ranjit Kumar, 2nd Edition, “Research Methodology: A Step by Step Guide for beginners” 4. Halbert, “Resisting Intellectual Property”, Taylor & Francis Ltd, 2007. REFERENCE BOOKS:
1. Mayall, “Industrial Design”, McGraw Hill, 1992. 2. Niebel, “Product Design”, McGraw Hill, 1974. 3. Asimov, “Introduction to Design”, Prentice Hall, 1962. 4. Robert P. Merges, Peter S. Menell, Mark A. Lemley, “Intellectual Property in New Technological Age”, 2016.
WEB REFERENCES:
1. http://nptel.ac.in/courses/107108011/ 2. https://www.pdfdrive.net/introduction-1-research-methodology-11-the-concept-of-the-research- e875404.html
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 73
MLR Institute of Technology
E-TEXT BOOKS:
1. https://www.pdfdrive.net/essentials-of-research-design-and-methodology-e13410517.html 2. https://www.pdfdrive.net/fundamental-of-research-methodology-and-statistics-e19852556.html
MOOC COURSES: 1. https://www.mooc-list.com/tags/research-methods 2. https://www.coursera.org/learn/research-methods 3. https://www.edx.org/course/introduction-social-research-methods-edinburghx-socrmx 4. https://www.openlearning.com/courses/SPPP2542x
M.Tech Embedded Systems- Academic Regulations & Syllabus – MLR20 Page 74
MLR Institute of Technology
AUDIT COURSE-II
DISASTER MANAGEMENT
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B4AC03 AC 2 - - - 30 70 100
OBJECTIVES:
At the end of this course, students will be able to:
Learn to demonstrate a critical understanding of key concepts in disaster risk reduction and humanitarian response. Critically evaluate disaster risk reduction and humanitarian response policy and practice from multiple perspectives. Develop an understanding of standards of humanitarian response and practical relevance in specific types of disasters and conflict situations. Critically understand the strengths and weaknesses of disaster management approaches, planning and programming in different countries, particularly their home country or the countries they work in.
OUTCOMES:
At the end of the course students can able to:
Demonstrate a critical understanding of key concepts in disaster risk reduction and humanitarian response. Evaluate disaster risk reduction and humanitarian response policy and practice from multiple perspectives. Develop an understanding of standards of humanitarian response and practical relevance in specific types of disasters and conflict situations. Explain the strengths and weaknesses of disaster management approaches, planning and programming in different countries, particularly their home country or the countries they work in.
UNIT-I NATURAL AND MANMADE DISASTERS Classes: 13
Disaster: Definition, Factors And Significance; Difference Between Hazard And Disaster; Economic Damage, Loss Of Human And Animal Life, Destruction of Ecosystem.
Natural Disasters: Earthquakes, Volcanisms, Cyclones, Tsunamis, Floods, Droughts And Famines, Landslides And Avalanches.
Man-made disaster: Nuclear Reactor Meltdown, Industrial Accidents, Oil Slicks And Spills, Outbreaks Of Disease And Epidemics, War And Conflicts.
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UNIT-II DISASTER PRONE AREAS IN INDIA Classes: 12
Study Of Seismic Zones; Areas Prone To Floods And Droughts, Landslides And Avalanches; Areas Prone To Cyclonic And Coastal Hazards With Special Reference To Tsunami; Post-Disaster Diseases And Epidemics.
UNIT-III DISASTER PREPAREDNESS AND MANAGEMENT Classes: 10
Preparedness: Monitoring Of Phenomena Triggering A Disaster Or Hazard; Evaluation Of Risk: Application Of Remote Sensing, Data From Meteorological And Other Agencies, Media Reports: Governmental And Community Preparedness.
UNIT-IV RISK ASSESSMENT Classes: 10
Disaster Risk: Concept And Elements, Disaster Risk Reduction, Global And National Disaster Risk Situation. Techniques Of Risk Assessment, Global Co-Operation In Risk Assessment And Warning, People’s Participation In Risk Assessment. Strategies for Survival.
UNIT-V DISASTER MITIGATION Classes: 15
Meaning, Concept And Strategies Of Disaster Mitigation, Emerging Trends In Mitigation. Structural Mitigation And Non-Structural Mitigation, Programs Of Disaster Mitigation In India.
TEXT BOOKS:
1. R. Nishith, Singh AK, “Disaster Management in India: Perspectives, issues and strategies “’New Royal book Company. 2. Sahni, PardeepEt.Al. (Eds.),” Disaster Mitigation Experiences And Reflections”, Prentice Hall Of India, New Delhi. REFERENCE BOOKS:
1. Goel S. L. , Disaster Administration And Management Text And Case Studies” ,Deep &Deep Publication Pvt. Ltd., New Delhi. 2. Geomatics Solutions for Disaster Management by Jonathan Li, Zlatanova, Andrea Fabbri, Springer- 2007.
WEB REFERENCES:
1. https://lecturenotes.in/subject/424/disaster-management-dm 2. https://www.coursehero.com/file/9623955/Lecture-3-Notes-Disaster-Management-Part-1/
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E-TEXT BOOKS: 1. http://www.ekalavvya.com/disaster-management-in-india-volume-i-free-ebook/ 2. https://www.taylorfrancis.com/books/e/9781420058635 3. https://think-asia.org/bitstream/handle/11540/5035/disaster-management-handbook.pdf?sequence=1 4. https://www.kopykitab.com/An-Introduction-to-Disaster-Management-eBook-by-S-Vidyanathan-isbn- 9788190849784
MOOC COURSES:
1. https://www.mooc-list.com/tags/disaster-management 2. https://www.coursera.org/learn/disaster-preparedness
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CONSTITUTION OF INDIA
Course Code Category Hours / Week Credits Maximum Marks
L T P C CIA SEE Total B4AC04 AC 2 - - - 30 70 100
OBJECTIVES:
At the end of this course, students will be able to:
Understand the premises informing the twin themes of liberty and freedom from a civil rights perspective. Address the growth of Indian opinion regarding modern Indian intellectuals’ constitutional role and entitlement to civil and economic rights as well as the emergence of nationhood in the early years of Indian nationalism. Address the role of socialism in India after the commencement of the Bolshevik Revolution in 1917 and its impact on the initial drafting of the Indian Constitution.
OUTCOMES:
At the end of the course students can able to :
Discuss the premises informing the twin themes of liberty and freedom from a civil rights perspective. Address the growth of Indian opinion regarding modern Indian intellectuals’ constitutional role and entitlement to civil and economic rights as well as the emergence of nationhood in the early years of Indian nationalism. Address the role of socialism in India after the commencement of the Bolshevik Revolution in 1917 and its impact on the initial drafting of the Indian Constitution.
UNIT-I INTRODUCTION Classes: 13
Constitution’ meaning of the term,, Indian Constitution: Sources and constitutional history, Features: Citizenship, Preamble, Fundamental Rights and Duties, Directive Principles of State Policy.
UNIT-II UNION GOVERNMENT AND ITS ADMINISTRATION STRUCTURE OF THE Classes: 12 INDIAN UNION Federalism, Centre- State relationship, President: Role, power and position, PM and Council of ministers, Cabinet and Central Secretariat, Lok Sabha, Rajya Sabha.
UNIT-III STATE GOVERNMENT AND ITS ADMINISTRATION GOVERNOR Classes: 10
Role and Position, CM and Council of ministers, State Secretariat: Organization, Structure and Functions
UNIT-IV LOCAL ADMINISTRATION DISTRICT’S ADMINISTRATION HEAD Classes: 12
Role and Importance, Municipalities: Introduction, Mayor and role of Elected Representative, CEO of Municipal Corporation, Pachayati raj: Introduction, PRI: Zila Pachayat, Elected officials and their roles, CEO Zila Pachayat: Position and role, Block level: Organizational Hierarchy (Different departments), Village level: Role
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MLR Institute of Technology of Elected and Appointed officials, Importance of grass root democracy
UNIT-V ELECTION COMMISSION ELECTION COMMISSION Classes: 13
Role and Functioning, Chief Election Commissioner and Election Commissioners, State Election Commission: Role and Functioning, Institute and Bodies for the welfare of SC/ST/OBC and women.
TEXT BOOKS:
1. The Constitution of India, 1950 (Bare Act), Government Publication. 2. Dr. S. N. Busi, Dr. B. R. Ambedkar framing of Indian Constitution, 1st Edition, 2015. 3. M. P. Jain, Indian Constitution Law, 7th Edn., Lexis Nexis, 2014. 4. D.D. Basu, Introduction to the Constitution of India, Lexis Nexis, 2015.
REFERENCE BOOKS:
1. ‘Indian Polity’ by Laxmikanth 2. ‘Indian Administration’ by Subhash Kashyap 3. ‘Indian Constitution’ by D.D. Basu 4. ‘Indian Administration’ by Avasti and Avasti WEB REFERENCES:
1. https://lecturenotes.in/subject/424/Constitution of India 2. https://www.coursehero.com/file/9623955/Lecture-3-Notes- Constitution of India
E-TEXT BOOKS:
1. http://www.ekalavvya.com/ Constitution of India -volume-i-free-ebook/ 2. https://www.taylorfrancis.com/books/e/9781420058635 3. https://think-asia.org/bitstream/handle/11540/5035/ConstitutionofIndia-handbook.pdf?sequence=1 4. https://www.kopykitab.com/An-Introduction-to-Disaster-Management-eBook-by-S-Vidyanathan-isbn- 9788190849784
MOOC COURSES:
1. https://www.mooc-list.com/tags/ Constitution of India 2. https://www.coursera.org/learn/ Constitution of India
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