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Study of leakage current mechanisms in ballistic deflection transistors

Conference Paper · January 2009 DOI: 10.1145/1531542.1531584 · Source: DBLP

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Vikas Kaushal Quentin Diduck IBM Institute of Electrical and Electronics Engineers

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Martin Margala University of Louisiana at Lafayette

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The user has requested enhancement of the downloaded file. Study of Leakage Current Mechanisms In Ballistic Deflection Transistors Vikas Kaushal, Quentin Diduck, Martin Margala Department of Electrical and Computer Engineering University of Massachusetts Lowell Lowell, USA 01854 [email protected], [email protected], [email protected]

ABSTRACT various novel ballistic devices, only a few have been In this paper, the Ballistic Deflection Transistor (BDT) is demonstrated to work at room temperature. reviewed for variations in performance of the device including However, this concept is vital for the smooth progress of leakage with respect to geometry modifications. Monte Carlo and semiconductor industry as the traditional scaling limits of Field Silvaco modeling tools are used to study current leakage Effect and Bipolar devices are quickly being reached with current mechanism in BDT. Low power selection criteria and theory leakage power essentially limiting further development [1]. behind position of deflector in the device are examined. Since Researchers have used various models and simulation tools to ballistic conduction is not dissipative, power loss should be low. study the electro-magnetic properties of materials, and to frame Leakage can be reduced by placing deflector at about 25% of its design guidelines for these mesoscopic structures to investigate own length lower than the exact centre of the device. Current the leakage mechanisms. Leakage reduction to continue Moore's leakages that occurred during device operation are compared with law will not only require new material solutions but also needs a each other and with the output current. It is observed that proper system design. Leakages significantly depend on material magnitude of leakage current is distinct at different ports of the system configuration, supply voltage, architecture and device. For a specific set of parameters, leakage is comparable to temperature. By using current lithographic techniques and high the output which essentially motivates to choose optimum device mobility materials, the fabrication of nanometer-scale devices architecture. showing ballistic (or quasi-ballistic) transport at room temperature is possible. Devices showing ballistic behavior fabricated using GaAs/AlGaAs heterojunction operating at low temperature have Categories and Subject Descriptors been demonstrated [2], [3]. In addition to the material system and B.8.2 [Performance and Reliability]: Performance Analysis and lithographic techniques, performance of these devices can further Design Aids. be improved by optimizing the geometry [4]. Essentially, optimum performance of any device is related to minimum General Terms leakage and this performance-leakage relation is valid in ballistic Measurement, Performance, Design, Experimentation, Theory. devices as well. These new concepts are based on the fact that the only scattering that the ballistic experience are those from the designed device boundaries. By simply tailoring the Keywords boundary of a ballistic device, the transport can be, to a Ballistic Transport, Deflection Transistors, Current Leakage large extent, modified and controlled in order to reduce power mechanism, Geometry, Monte Carlo Simulation, Silvaco dissipation. Simulation. In this paper, we investigate several important aspects 1. INTRODUCTION relevant to the leakage mechanisms in BDT [5]. As modeling tools are often capable of addressing various device While conventional planar are nowadays the most functionalities, we use physical simulations to study leakage common devices, in the medium-long term they are going to be mechanisms and dark current associated with the device. We also substituted by more promising architectures that offer better show that the leakage is dependent on BDT’s architecture and scalability perspectives for very small channel (10nm and output is comparable to the leakages for a specific set of beyond) devices. However, the nature of electronic transport parameters (geometry and power selection) chosen. changes qualitatively when the size of electronic device is reduced below the electron mean free path. At this scale, devices do not follow 2. BDT OVERVIEW Ohm’s law but exhibit non-Ohmic ballistic behavior. Among Our group invented and initially reported about the idea of BDT. Permission to make digital or hard copies of all or part of this work for BDT is a novel structure which is based upon an electron steering personal or classroom use is granted without fee provided that copies are and a ballistic deflection effect. BDT utilizes two dimensional not made or distributed for profit or commercial advantage and that electron gas (2DEG) heterostructure with a gated microstructure copies bear this notice and the full citation on the first page. To copy to achieve ballistic transport at room temperature. To achieve otherwise, or republish, to post on servers or to redistribute to lists, ballistic transport at room temperature, a two step lithographic requires prior specific permission and/or a fee. GLSVLSI’09, May 10–12, 2009, Boston, Massachusetts, USA. technique is used rather than one step lithography, in case of low Copyright 2009 ACM 978-1-60558-522-2/09/05...$5.00.

165 temperature device operations. Since the typical mean free path of attracting electrons towards right drain, some of the electrons 2DEG at 300K in a compound III-IV semiconductor is 100- were still heading towards left and top drain. This leads to an 200nm, the material system chosen is a lattice matched layers of architectural leakage. It is then observed that the position of InGaAs-InAlAs on an InP substrate. The frequency of this device triangular deflector plays a significant role in device performance is estimated to be 1.02THz [4]. In Figure 1, an SEM image of the and thus the leakage can be reduced by placing deflector at about BDT is shown. The bright area represents 2DEG and the dark 25% of its own length lower than the exact centre of the device. regions are removed material from the 2DEG structure. 2DEG has high electrical conductivity and dark areas are non-conductive.

Figure 2. Overview of simulator interface. Right gate is positively biased and left gate is negatively biased. Number of Figure 1. A BDT is pictured with 500nm gates (including the conducting electrons shown are 4023 [5]. angled region) and 80nm gate-channel spacing, the top-left and top-right ports are drain ports, bottom-left and bottom- right ports are gates, top drain port is a Vdd bias port that 3.1.2 Silvaco Simulations controls gain, and the bottom port is the source [4]. Third theoretical study of our device was performed using 3D Silvaco simulations. The investigation of dark current is done. 3. LEAKAGE MECHANISMS IN BDT The following models were used: Boltzmann statistics, Shockley- 3.1 Theoretical Study and Simulations Read-Hall and electric field dependent mobility: γ Various Simulation models have been used to describe the μμν=+()()1EEEγ + EE ( 0 SAT crit) ()() CRIT operational behavior of BDT and to obtain the performance ….(1) optimization through modeling. It is found that the leakage where μ is the field-dependent mobility, μo is the low-field mechanism observed in BDT is by far the most unique in its own mobility, VSAT is the , E is the electric field and sense. Leakages through device layers (due to process technology ECRIT is the electric field at which peak velocity occurs. Impact and materials system) and leakages due to device geometry are ionization was used to simulate the on-state breakdown: given attention in the present study. ∞ CRIT ααnp,,=×− npexp(EE np , ) ………………………… (2) 3.1.1 Monte Carlo Simulations where the n and p indices stand for electrons and holes First ever simulation on BDT, which is a full custom Monte Carlo CRIT respectively. The α and E parameters were extracted from simulation, used classical billiard model, which treats electrons as n,p np, ballistic Newtonian particles with effective mass and a thermal literature data. distribution under the influence of electromagnetic fields [5]. This simulation assumes operation at room temperature and it is Undoped InGaAs cap 10nm believed that, at room temperature, leakage current increases with Undoped InAlAs Si Planar doped 30nm VDC due to thermal runaway. Thermal runaway leads to device destruction if the applied voltage is not reduced. Thermal Undoped InAlAs spacer 2DEG 20nm runaway occurs when the dissipated power exceeds a critical maximum power and the material temperature does not stabilize Undoped InGaAs channel 50nm anymore. Now, since our device operates at voltages below KT/e limit, there should not be any problem of runaway associated with Undoped InAlAs buffer 450nm this which should essentially reduce the leakage. It is also known InP Substrate that ballistic conduction is not intrinsically dissipative, so the power consumption will be very less and so does the leakage. Second simulation model developed by our group is a ballistic Figure 3. Schematic cross section of InGaAs/InAlAs/InP nanoelectronic device Monte Carlo simulator which models deflection transistor structure (bottom). ballistic electron transport stochastically [5]. Figure 2 shows the trajectory of electrons in BDT. Device length and width is which steers electron towards right or left depending on the 1700nm each. It is noticed that even if the positive gate was polarity of the gate voltage. For the Silvaco simulation purpose,

166 450nm undoped InAlAs buffer structure is used over a 635μm InP substrate. This follows by a 50 nm undoped In0.53Ga0.47As which works as a channel after forming 2DEG with 20nm In0.53Al0.47As spacer layer at their heterostructure junction. The Si-planar doping layer with a doping density of 2 × 1012 cm-2 is used. The undoped In0.53Al0.47As Schottky layer is 30 nm. Then, the 10 nm thick undoped In0.53Ga0.47As cap layer is used. Hall measurements of this structure yielded an electron sheet density of ns = 9.832 × 11 -2 4 2 10 cm and of μH = 1.206 × 10 cm /Vs at 300 K. We calculated the dark current through simulation when all ports of the device were zero biased. The calculated result showed that the dark current was -4.717 × 10-17 Amperes. The left gate leakage current obtained was -3.318 × 10-17Amperes. The gate leakage currents observed at high gate voltages is due to the Figure 4. IV characteristic of the left drain port as a function doping in the InAlAs layer which serves as the Schottky contact of push-pull gate voltage (in reference to the left gate), layer. This could also be the possible reason for the tunneling. comparison of these currents with ideal output is also shown.

3.2 Experimental Study In the recent experiments, we designed and fabricated three 3.2.1 Experimental Output Versus Ideal Output different set of devices with different geometries. Table 1 shows the variation in device performance due to different applied ratios. Figure 4 shows the experimental I-V curves for right as well as It is observed that the top drain current leakage is comparable to left drain terminals and comparison of these outputs with ideal the output current which shows that the leakage through top drain output current. As shown, when the gates are biased in push-pull is significant. Two reasons can be given to this behavior. Firstly, mechanism (when the left gate is at -0.5V, the right gate will be at the electron pull towards the top drain (due to electron +0.5V), drain current first increases as a function of gate voltage momentum) is much larger than the pull towards the left and right then decreases. The fact that the current rises and then falls as a drain outputs (due to deflection). This is because of the fact that, function of gate bias is attributed to the channel first being top drain terminal strengthens the electric field which drifts pinched off, then as the gate voltage is further increased, the electron towards itself. Secondly, since deflector’s size is not electrons are steered from the right drain into the left drain, and optimized yet and the dimensions are larger, it is more probable then eventually the channel pinches off again. It can be observed for electrons to move into the top drain without any deflection. that left and right output currents follow the ideal output trend but Left gate current leakage is also comparable to the output which the required separation of peaks is not attained. It is imperative to implies that electrons migration takes place between channel and have a maximum separation between these two peaks for gate which are separated by 120nm. Due to the fact that the push- transistor to show its optimum performance. To make perfect pull gate voltage sweep is from -5V to +5V, electrons in the digital logic circuit they have to be in “one up other down” channel feel more attracted towards the positive gate and even fashion. This particular result implies that, essentially, the lost 120nm wide separation is not enough to prevent this movement of current here is the leakage current. electrons and thus leakage. It is observed that the right gate current leakage is minimal. 3.2.2 Leakage dependence on Geometry Table 1. Device performance variation with geometry There is an inevitable impact of device geometry on the output variation. This table compares all the leakage currents at and leakage current. Several devices of different geometries is some specific ratios of device parameters where the output fabricated on separate runs. Optimization of the geometry is current is optimum. Each drain is given a bias of 2V. (see imperative for any deflection transistor to operate at room Figure 7) temperature to produce high gain and low power dissipation. Maximum Top Drain Left Gate Right Gate Device with larger dimensions does not follow the ballistic Left Drain Current Set Name Current Current behavior as the channel length is larger than mean free path, but Current Leakage Leakage Leakage they still operate on the principle of deflection. The primary (Amperes) (Amperes) (Amperes) (Amperes) ballistic interaction of electrons is with the deflector which itself s/c=0.85 is of the order of mean free path. At this regime, most of the quantum effects like phase does not hold good, but (b/a, b and 6.16E-6 4.833E-7 4.97E-7 1.14E-11 interestingly billiard model still applies, particularly in reference y fixed) to the deflector. It is observed that with the change in dimensions b/a =2.27 in larger structures, drain output current changes significantly and (s/c, b and 4.85E-6 1.14E-6 6.23E-7 1.159E-11 thus the performance variation is observed [4]. It implies that y fixed) current leakage mechanism does exist, in accordance with the b=168nm geometrical variation. BDT is unique in the sense that it has six ports and leakage mechanism at each port is distinct. (s/c, b/a 5.24E-6 1.064E-6 5.14E-7 1.11E-11 fixed)

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Figure 5. Variation in the output current with b/a. Figure 5 shows a variation in the output current with Figure 7. Variation of different leakage currents with push- variation in the ratio b/a [4]. In this ratio, “b”=250nm and “a” pull gate voltage sweep. changes. The results here indicate that the output current rises with the reduction in value of “a”. It suggests that the output 4. CONCLUSION current is inversely related to top drain current leakage since We discussed the leakage mechanism associated with BDT. Study widening of “a” means easing electrons to drift through without of its leakage mechanisms includes all sorts of different parts of any physical encounter with deflector. We also note that the the device to investigate accordingly. First we discussed various change in output current with “a” is steeper for smaller values of simulation models which explain leakage mechanism. We used 'b/a” which indicates that the effect of small variations in larger Monte Carlo and Silvaco simulations to study the leakage. We “a” values is higher. Triangular deflective structure plays a major found that as ballistic conduction is not dissipative, power loss is role in the operation of the device. As we scale down the low. Leakage can be reduced by placing deflector at about 25% of deflector, the performance of the device is enhanced because of its own length lower than the exact centre of the device. We also the larger percentage of electron-deflector interactions. This fabricated devices with three sets of different geometries and theoretical concept is studied and it is observed that output current measured the output response and leakages associated with each significantly depends on the deflector size. of these sets. It is observed that the leakage depends significantly In Figure 6 we plotted the left drain output current as a on the device structure. For a specific set of parameters, leakages function of deflector size for a 2V bias. We notice that the output were comparable to the output. It has motivated us to optimize current of the device falls with the deflector size. The fall in device geometry and dimensions. Study showed that deflector output current is inversely proportional to the deflector size. The plays a major role in the device leakage mechanism. -8 -6 slope and intercept calculated are -1.069 × 10 and 6.984 × 10 5. REFERENCES respectively with an error of 1.75 × 10-8 and -3.69 × 10-7 respectively. It is important to study all the current leakages [1] W. Haensch, E. J. Nowak, R. H. Dennard, P. M. Solomon, together when the time specification is same. We showed relative A. Bryant, O. H. Dokumaci, A. Kumar, X. Wang, J. B. trend of these leakages in Figure 7. It is noticed that while the left Johnson, M. V. Fischetti, “ CMOS devices beyond” gate current leakage rises with the gate voltage sweep from -5V to IBM Journal of Research and Development, Vol 50 , Issue +5V, the right gate current leakage (of the order of E-11) is 4/5 (July 2006) Pages: 339 – 361 almost constant for whole of the sweep. It is due to the fact that [2] L. Worschech, H. Q. Xu, A. Forchel, and L. Samuelson, the electrons in the vicinity of left gate are strongly attracted by “Bias-voltageinduced asymmetry in nanoelectronic Y- the +5V which essentially results into movement of electrons branches,” Appl Phys. Lett., vol. 79, pp. 3287–3289, 2001. across the channel gate separation of 120nm (Note: These are devices with larger dimensions). It is also observed that top drain [3] A. M. Song, A. Lorke, A. Kriele, J. P. Kothaus, W. current is higher among all the three, which again solidifies the Wegscheider, and M. Bichler, “Nonlinear electron transport fact that deflector plays a significant role in the performance of in an asymmetric microjunction: a ballistic rectifier,” Phys. the device. Rev. Lett., vol. 80, pp. 3831–3834, 1998. [4] V. Kaushal, Q. Diduck, M. Margala, “Performance optimization of room temperature deflection transistors through modified geometry,” 1st Microsystems and Nanoelectronics Research Conference, pp.145-148, 2008. [5] Q. Diduck, M.Margala, M.J. Feldman, “A Terahertz transistor based on geometrical deflection of ballistic current,” Symposium Digest, IEEE MTT-S International, pp. 345-347, 2006.

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device Simulator”, IEEE International Symposium on Figure 6. Variation in the output current with deflector size Nanoscale Architecture (NANOARCH), pp. 38-45, 2007. (b).

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