Legacy documentation refer to the Altium Wiki for current information

Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Technical hardware reference manual for Altium's Desktop NanoBoard FPGA implementation platform

Legacy documentation refer to the Altium Wiki for current information

CAUTION

THIS EQUIPMENT INCLUDES EXPOSED ELECTRONIC COMPONENTS THAT ARE HIGHLY SENSITIVE TO DAMAGE FROM STATIC ELECTRICITY. USERS ARE CAUTIONED TO ALWAYS FOLLOW STANDARD ANTISTATIC PROCEDURES WHEN INSTALLING, HANDLING OR USING THIS EQUIPMENT.

THIS EQUIPMENT MUST ALWAYS BE POWERED DOWN WHEN MAKING ANY CONFIGURATION CHANGES, FOR EXAMPLE WHEN REMOVING OR INSERTING ANY ACCESSORY DEVICES OR WHEN CONNECTING THESE DEVICES TO ANY OTHER EQUIPMENT. FAILURE TO FOLLOW THESE INSTRUCTIONS MAY RESULT IN DAMAGE TO THE SUPPLIED EQUIPMENT OR CONNECTED DEVICES. USER ASSUMES ALL RESPONSIBILITY FOR THE ELECTRICAL COMPATIBILITY OF ANY USER-PROVIDED DEVICES CONNECTED TO THIS EQUIPMENT.

THIS EQUIPMENT IS INTENDED FOR PROFESSIONAL USE IN A LABORATORY ENVIRONMENT ONLY AND CONTAINS EXPOSED ELECTRONIC COMPONENTS AND CIRCUITS THAT ARE VULNERABLE TO MECHANICAL OR PHYSICAL DAMAGE. USERS ARE CAUTIONED TO HANDLE THIS EQUIPMENT ACCORDINGLY.

DAMAGE TO THE SUPPLIED EQUIPMENT DUE TO MISHANDLING OR MISUSE, NOT LIMITED TO STATIC, MECHANICAL, PHYSICAL OR ELECTRICAL DAMAGE WILL VOID ANY WARRANTY OTHERWISE PROVIDED FOR THIS EQUIPMENT.

IN NO EVENT SHALL ALTIUM, ITS DIRECTORS, OFFICERS, EMPLOYEES OR AGENTS BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES (INCLUDING DAMAGES FOR LOSS OF PROFITS, LOSS OF BUSINESS LOSS OF USE OR DATA, INTERRUPTION OF BUSINESS AND THE LIKE), EVEN IF ALTIUM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ARISING FORM ANY DEFECT OR ERROR IN THIS EQUIPMENT OR ITS DOCUMENTATION. WARNING

THIS EQUIPMENT IS INTENDED FOR PROFESSIONAL USE IN A LABORATORY ENVIRONMENT ONLY. IT GENERATES AND CAN RADIATE RADIO FREQUENCY ENERGY. IT HAS NOT BEEN TESTED FOR COMPLIANCE PURSUANT TO REGULATIONS REGARDING RADIO FREQUENCY INTERFERENCE. OPERATION OF THIS EQUIPMENT MAY CAUSE INTERFERENCE WITH COMMUNICATIONS OR OTHER EQUIPMENT. USERS ARE ADVISED TO BE AWARE OF THIS POTENTIAL AND TO TAKE WHATEVER MEASURES NECESSARY TO PREVENT THIS INTERFERENCE.

Software, hardware, documentation and related materials: Copyright © 2008 Altium Limited. All Rights Reserved. The material provided with this notice is subject to various forms of national and international intellectual property protection, including but not limited to copyright protection. You have been granted a non-exclusive license to use such material for the purposes stated in the end-user license agreement governing its use. In no event shall you reverse engineer, decompile, duplicate, distribute, create derivative works from or in any way exploit the material licensed to you except as expressly permitted by the governing agreement. Failure to abide by such restrictions may result in severe civil and criminal penalties, including but not limited to fines and imprisonment. Provided, however, that you are permitted to make one archival copy of said materials for back up purposes only, which archival copy may be accessed and used only in the event that the original copy of the materials is inoperable. Altium, Altium Designer, Board Insight, DXP, Innovation Station, LiveDesign, NanoBoard, NanoTalk, OpenBus, P-CAD, SimCode, Situs, TASKING, and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or its subsidiaries. All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed. v8.0 31/3/08.

Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Table of Contents

Introduction to the Desktop NanoBoard NB2DSK01 2 Board communications ...... 3 The NanoBoard chain...... 3 The Hard Devices chain...... 4 The Soft Devices chain...... 4 NanoTalk...... 5 Chaining multiple Desktop NanoBoards ...... 5 Connecting Production PCBs ...... 6 Key Features of the Desktop NanoBoard NB2DSK01...... 6 Functional overview of the Desktop NanoBoard NB2DSK01 ...... 8 Compatibility with the NanoBoard-NB1...... 9 A word about ESD...... 9 Common ESD prevention techniques...... 10

Setting up the Desktop NanoBoard NB2DSK01 11 What’s in the box ...... 11 System requirements ...... 12 Altium Designer software...... 12 Important note on FPGA vendor tools ...... 13 Connecting the Desktop NanoBoard NB2DSK01...... 13 Testing the PC to NanoBoard connection...... 14 Detecting the NanoBoard...... 15 Choosing the JTAG connection ...... 16 Downloading a test project to the Desktop NanoBoard NB2DSK01...... 16 Troubleshooting Desktop NanoBoard NB2DSK01 connection problems ...... 19 Where to go to from here ...... 19

Desktop NanoBoard NB2DSK01 resources 20 System resources ...... 21 Power...... 21 NanoTalk Controller...... 23 Configuration PROM...... 24 System JTAG programming port ...... 24 Common-Bus SRAM...... 25 Common-Bus SDRAM...... 25 Common-Bus Flash memory ...... 25 Independent SRAM...... 26 Host status LEDs ...... 26 FPGA daughter board connectors ...... 27 Peripheral board connectors...... 27 NanoBoard-PC interface – Parallel port ...... 28 NanoBoard-PC interface – USB port ...... 28 NanoTalk Master-Slave headers ...... 29 Stereo Audio ...... 30 User Board headers...... 32 Debug headers ...... 34 SPI Real-Time Clock...... 35 SD card reader...... 35 Home/NanoBoard Reset button...... 36 Board ID memory...... 36 Resources accessible from an FPGA design ...... 38 Accessing resources from an FPGA design ...... 38 System Clocks ...... 39 Serial SPI Flash memory ...... 40

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RS-232 Serial Port...... 41 CAN Port...... 42 PS/2 Mouse and Keyboard Ports ...... 44 ADC/DAC/I2C ...... 44 TFT LCD panel (with touch screen)...... 46 User DIP-switch ...... 48 User LEDs...... 49 User I/O headers...... 50 Daughter board Test / Reset button ...... 50 Generic user switches...... 51 Buzzer signal ...... 52 Soft JTAG chain...... 52 Using multiple SPI/I2C devices in a design ...... 53

Daughter Boards 54 Daughter board resources ...... 54 Accessing Desktop NanoBoard NB2DSK01 resources...... 54 Hard JTAG signals...... 54 Soft JTAG signals ...... 55 Daughter board identification signals...... 55 SPI bus interface...... 55 1-Wire® bus interface ...... 55 Daughter board power signals...... 55 Daughter board FPGA control signals ...... 56 Accessing peripheral board resources...... 56 A word about changing daughter boards...... 56

Peripheral Boards 57 Accessing board resources...... 57 JTAG signals...... 57 Peripheral board identification signal...... 57 Audio signals...... 58 I2C interface...... 58 SPI bus interface...... 58 1-Wire® bus interface ...... 58 Clocking ...... 58 Power signals...... 58 A word about changing peripheral boards ...... 59

Direct interaction with the Desktop NanoBoard NB2DSK01 60 Driving the GUI ...... 60 GUI options ...... 61 A shared panel...... 61 Bootstrapping the daughter board FPGA...... 62 Booting from an SD card...... 62 Booting from SPI Flash memory...... 62 Downloading example designs stored on an SD card ...... 65 Browsing Flash memory and SD card content...... 66 A word about storage...... 66 Bypassing JTAG devices...... 67 Changing system clock frequency ...... 67 Real Time Clock (RTC)...... 68 Test Routines...... 68

Desktop NanoBoard NB2DSK01 Constraint system 69 Constraint system overview...... 69 Configuring an FPGA project automatically...... 70 ii TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Identifying system hardware ...... 70 Configuring the project...... 72

Power Monitoring on the Desktop NanoBoard NB2DSK01 75 Functionality at the Hardware-Level ...... 76 Accessing and Using Power Monitoring ...... 77 Graphical Display of Monitored Information...... 78

Updating the NanoBoard firmware 82 Pre-update preparation...... 82 Downloading the new firmware...... 83 Downloading program code...... 83 Testing the NB2DSK01...... 84

Index 86

Revision History 91

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About this manual This document describes the board level operations of Altium's Desktop NanoBoard NB2DSK01. The Desktop NanoBoard, together with Altium Designer, constitute Altium's Innovation Station. This pairing of reconfigurable hardware platform and unified electronics design software, provides you with a design environment that places embedded intelligence at the center of the design process. The NB2DSK01 provides a general purpose platform with a range of commonly used peripherals. The basic system components are: • NB2DSK01 motherboard – providing development infrastructure and application specific hardware. • Plug-in peripheral boards – providing further peripheral resources, which, when plugged-in, behave as though they were inherent to the NB2DSK01 motherboard itself. • Plug-in daughter boards – providing the target field-programmable devices. • NB2DSK-SPK01 speaker board – catering for enhanced audio output through provision of high-quality speakers. The NB2DSK01 is initially supplied with three plug-in peripheral boards. The single daughter board chosen at the time of purchase is shipped separately. For more information on what gets shipped as part of your Desktop NanoBoard NB2DSK01 purchase, see the section What's in the box, later in this document.

Notational conventions This document uses the following conventions. • Altium's Desktop NanoBoard NB2DSK01 may be referred to using the following terminology: - NanoBoard - Desktop NanoBoard - Desktop NanoBoard NB2DSK01 - NB2DSK01 • The FPGA device on the NB2DSK01 motherboard may be referred to as the NanoTalk Controller or NanoBoard Controller. • Interactive instructions are shown in a bold typeface, for example: Continue View » Devices View • Program listings, program examples and filenames are shown in a mono-spaced typeface, for example: NB2DSK01.SchDoc • Reference to notations on printed circuit boards are shown in a mono-spaced typeface and encapsulated in single quotes, for example: ‘SYSTEM JTAG’

Information about cautions This manual may contain cautions.

Caution statements look like this.

A caution statement describes a situation that could potentially damage your software, or hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully.

Document referencing Where references are made to Altium Designer documents, such as articles, tutorials and application notes, such documents can be found in the \Help folder of your Altium Designer software installation. Additional information relating to any part of the software can be found using the Knowledge Center panel (Help » Knowledge Center), which incorporates a PDF-based search facility.

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Introduction to the Desktop NanoBoard NB2DSK01

Altium's Desktop NanoBoard NB2DSK01 is a unique, reconfigurable hardware platform that harnesses the power of today's high-capacity, low-cost programmable devices to allow rapid and interactive implementation and debugging of your digital designs. The Desktop NanoBoard NB2DSK01 takes the nano-level breadboarding concept introduced with the NanoBoard-NB1 to a whole new level, enhancing your ability to design, implement and debug an entire design before moving to the production PCB. Swappable daughter boards now support a much larger number of I/O connections from the target FPGA to the connected peripherals. With the Desktop NanoBoard NB2DSK01, peripherals available for the daughter board FPGA are delivered on removable peripheral boards, providing a simple and cost-effective method for rapid prototyping of hardware concepts. The Desktop NanoBoard NB2DSK01 is designed to be a perfect complement to Altium Designer, the unified electronic product development system that transforms your desktop into a complete and interactive electronics design laboratory that uses LiveDesign. LiveDesign is a unified electronics system design methodology that is based on 'live' engineering inside a programmable physical hardware design space. Altium Designer, the NanoBoard and LiveDesign, provide real-time communication and 'hands-on' interaction between you and your design during the development process. Unlike conventional electronics design flows, a unified design flow and LiveDesign eliminates the need to work in simulated environments, allowing you to run software on hardware in real time, right from the start of the design cycle through to final production! You begin developing your system by implementing it on a reconfigurable hardware platform – the Desktop NanoBoard NB2DSK01. Your circuit can then be probed, analyzed and debugged interactively using an array of virtual instruments and JTAG-based monitoring features. As the implementation is performed within a programmable hardware realm, you can update the design quickly and many times over without incurring cost or time penalties. This allows the device intelligence you are designing to be moved between different NanoBoard platforms, or even to custom hardware – greatly accelerating the process of bringing your products to market. Some architectural highlights of the Desktop NanoBoard NB2DSK01, explored in greater detail in this technical reference, include: • Application-specific plug-in peripheral boards for complete system flexibility • Plug-in daughter boards that allow you to target a wide range of FPGA and processor devices • High-speed PC interconnection through USB 2.0 that allows faster download and debugging • Built-in, high-quality speakers for enhanced audio output • Integrated color TFT touch screen that facilitates dynamic application interaction. Additionally, a wide variety of FPGA-ready schematic components (ranging from processors to peripheral components and generic logic), and a complete set of tools for development and debugging, are included with Altium Designer. So as you can see, when combined with Altium Designer, a LiveDesign-enabled Desktop NanoBoard NB2DSK01 transforms your PC desktop into an interactive reprogrammable hardware development system – an Innovation Station!

Figure 1. Altium's Desktop NanoBoard NB2DSK01.

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Board communications Communications between the various devices within the system makes extensive use of the technology defined by IEEE Standard 1149.1 – commonly referred to as JTAG. The Desktop NanoBoard NB2DSK01 is connected to your PC using either a parallel or USB connection. When you start Altium Designer, a driver is loaded that configures the relevant port (parallel or USB) to run as a single multiplexed JTAG link between the NB2DSK01 and the PC. Local to the NB2DSK01 itself, there are in fact multiple JTAG 'chains' present. These chains provide the communications paths between the various devices in the system. Within Altium Designer, interaction with these chains is performed through the Devices view (Figure 2), accessed by choosing View » Devices View from the main menus.

Figure 2. Various JTAG chains presented in Altium Designer's Devices view. The Devices view presents three JTAG chains, which collectively show all JTAG-compliant devices attached to the system. Each device in each chain is represented by its appropriate icon. Controls for a device can be accessed through interaction (double-click, right-click) with its icon, giving full control over all JTAG devices in the system. The following sections take a closer look at the three chains presented in the Devices view, giving you a foundation upon which further sections in this reference either build upon or relate to. The NanoBoard chain The NanoBoard chain (Figure 3) includes an icon for each powered-up NanoBoard detected by the system. This chain essentially detects the presence of each NanoBoard's controller device, or NanoTalk Controller. As a result it is often referred to as the NanoBoard Controllers chain. Controls associated with each icon allow you to communicate and control various on-board SPI-based devices, such as the programmable clock and the SPI Flash memory.

Figure 3. The NanoBoard chain.

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The Hard Devices chain The Hard Devices chain (Figure 4) shows all target programmable devices detected by the system. This includes FPGAs resident on daughter board plug-ins, as well as all JTAG devices found on any user boards connected to a NanoBoard in the configuration. Any discrete processors will also be presented in this chain. The NanoTalk Controller automatically detects and configures appropriate devices so that they form a continuous chain using their physical TDI and TDO JTAG lines. If a physical device (typically on a user board) is not supported by the system, it will appear in the chain as a Generic JTAG device. To ensure continuity of the Hard JTAG chain, a corresponding Boundary Scan Description Language (BSDL) file must be attached to the device, the contents of which are used by the system to correctly configure the JTAG chain. For more information on Generic JTAG devices, including how to attach a BSDL file, see the section Generic JTAG device support, a sub-section of the User Board headers resource later in this document. Each physical device in the chain that is programmable from Altium Designer will have a Process Flow associated to it. The stages in this flow are used to interactively compile, synthesize, build and ultimately program the device, all from within the Devices view.

Figure 4. The Hard Devices chain. The Soft Devices chain The Soft Devices chain (Figure 5) shows all Nexus-enabled devices, such as 'soft' processors and virtual instruments, found in each FPGA design project targeting a programmable device in the Hard Devices chain. When you use Nexus components in your design at the schematic level, the system automatically connects the TDI and TDO lines of each component's JTAG port, to form a continuous JTAG chain.

Figure 5. The Soft Devices chain. Note: The Soft Devices chain only becomes populated with the Nexus-enabled devices for a design, once that design has been programmed into the target device. For more information on communications between the Desktop NanoBoard NB2DSK01 and the PC, including an in-depth look at the JTAG Standard, refer to the article AR0130 PC to NanoBoard Communications. For more information on the Devices view, including access of device controls, refer to the application note AP0103 Processing the Captured FPGA Design.

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NanoTalk The NB2DSK01 includes Altium's proprietary communications protocol, referred to as NanoTalk. This protocol defines and provides a communication path between a PC running Altium Designer and one or more NanoBoards. NanoTalk is implemented as part of the firmware running in a Xilinx Spartan-3 1500 FPGA device (XC3S1500-4FG676C) on the motherboard. This device is commonly referred to as the NanoTalk (or NanoBoard) Controller. The NanoTalk Controller manages the routing of the multiple JTAG chains that communicate with both the physical devices on the board and the soft devices contained within your design running on the target daughter board FPGA. It also handles the multiplexing of these various chains for transmission to the software running on the PC, over the parallel or USB link. NanoTalk has been designed to be plug-and-play, in the sense that all NanoTalk communications paths automatically configure when multiple NanoBoards are daisy-chained together, or user boards are attached to a NanoBoard. Altium Designer scans the NanoTalk system and automatically maintains a map of all Hard JTAG and Soft JTAG devices.

NanoTalk installation NanoTalk is field-upgradeable, by using Altium Designer to install configuration data – the NanoBoard firmware – into a Xilinx serial Flash configuration PROM (XCF08PFS48C). Upon power-up, the firmware is loaded into the NanoTalk Controller. The NB2DSK01 is shipped with the firmware already pre-installed, but future revisions can be installed at any time using a dedicated 'SYSTEM JTAG' port on the NB2DSK01 motherboard. This port provides Altium Designer with Hard JTAG access only to the NanoTalk Controller and the associated configuration PROM. All other resources are invisible to the software. The configuration PROM can then be reprogrammed with the new firmware. This process is described in detail in the section Updating the NanoBoard firmware later in this document. Chaining multiple Desktop NanoBoards Each Desktop NanoBoard NB2DSK01 contains NanoTalk Master and Slave connectors that allow multiple NanoBoards to be daisy-chained together. The Hard and Soft JTAG chains are passed between boards using a 10-way IDC cable – from the Slave connector on the first board to the Master connector on the next. Under the management of the NanoTalk Controller, these chains are kept continuous, with both chains sent out from and received back by, the Master NB2DSK01 in the configuration – the one connected to the PC and ultimately the Altium Designer software. Altium Designer allows you to target different FPGA design projects to each Desktop NanoBoard in the chain, allowing the development of complex systems that contain multiple FPGAs, that may be implemented across several PCBs. For more information on the NanoTalk connectors, see the section NanoTalk Master-Slave headers, under System resources, later in this document.

Figure 6. Two NB2DSK01s chained together.

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Connecting Production PCBs As well as chaining multiple Desktop NanoBoards together, you can also attach your own board to the NB2DSK01, through a JTAG connection, for inclusion into the system. Up to two user boards can be connected to each NanoBoard in the system. This enables you to extend Altium's LiveDesign methodology to the design and debugging of your production PCB! No special control circuitry is required on a connected user board. Simply chain the JTAG ports of the compliant devices on your board – both the physical ports and the 'soft' ports established to connect with the Nexus-enabled devices inside a device (processors, virtual instruments) – and connect both chains to a 10-way header for connection to the NB2DSK01. When a user board is present, the NanoTalk Controller routes the appropriate TDO and TDI signals to form part of the overall Hard and Soft device chains for the NB2DSK01. Icons for all devices on the user board will be presented in the Altium Designer software, allowing you to interact with these devices. For more information on the connectors used to attach user boards to the NB2DSK01, see the section User Board headers, under System resources, later in this document.

Figure 7. Attaching a production PCB to an NB2DSK01. Key Features of the Desktop NanoBoard NB2DSK01 Altium's Desktop NanoBoard NB2DSK01 has the following features: • Altium NanoTalk parallel PC interface • Altium NanoTalk USB 2.0 PC interface • NanoTalk Master and Slave connectors, 10-way • Host status LEDs • Xilinx Spartan-3 (XC3S1500-4FG676C) NanoTalk Controller with JTAG-accessible Flash configuration PROM • Dedicated System JTAG programming port • Dual User Board JTAG headers, 10-way • Three 100-way FPGA daughter board connectors ('NANOCONNECT' interfaces) • Three 100-way peripheral board connectors ('NANOCONNECT' interfaces) – Peripheral Board A, Peripheral Board B, Peripheral Board C • Programmable clock 6 to 200 MHz, accessible by Altium Designer, firmware (through the interactive GUI), or by a daughter board FPGA design • Fixed 20MHz reference clock • SPI Real-Time Clock with 3V battery backup • Dual 5V DC power daisy-chain connectors with power switch

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• 5V DC power output connector, for supply of power to a user board • Power supply test points for all supply levels available on the board, including four GND points • Current sense circuits on all power lines to the peripheral board, daughter board and User Board connectors • RS-232 Serial Port – DB9M • CAN Port – DB9M • PS/2 Mini-DIN Mouse Port • PS/2 Mini-DIN PC Keyboard Port • 240 x 320 TFT LCD with touch screen - 50-pin TFT connector - 12-bit SPI touch screen digitizer - Shared use between NB2DSK01 firmware (interactive GUI) and a design running in a daughter board FPGA • 8-way DIP-switch • LED array, 8 LEDS • Serial SPI Flash memory • On-board memories used for firmware: - 256K x 32-bit common-bus SRAM (1MByte) - 16M x 32-bit common-bus SDRAM (64MByte) - 16M x 16-bit common-bus 3.0V Page Mode Flash memory (32MByte) - 256K x 32-bit independent SRAM (1MByte) ® • 1-Wire memory device used to store board ID and related information • Dual 18-way (20 pin) I/O expansion headers with power supply selection links • Four channel 8-bit ADC, I2C-compatible • Four channel 10-bit DAC, I2C-compatible • Screw terminal header for ADC and DAC • ADC/DAC/I2C 14 pin expansion header • Stereo 2W audio power amplifier with 3.5mm test input jack and DC volume control • Audio mixer (L and R) for combining audio sources: - Line Out from NanoTalk Controller (Delta-Sigma DAC output, driven by FPGA) - Line Out signal wired from peripheral board socket A - Line Out signal wired from peripheral board socket B - Line Out signal wired from peripheral board socket C - Buzzer output from daughter board FPGA design • Stereo audio jacks (3.5mm): - Line In / Line Out - Mic In - Headphone Out • Speaker socket for direct connection of Desktop Stereo Speaker Assembly NB2DSK-SPK01: - provides audio and power signals - provides two SPI buses for control of RGB LED drivers on NB2DSK-SPK01 - provides 1-Wire bus for interrogation of 1-Wire ID device on the NB2DSK-SPK01 • SD (Secure Digital) card reader, with 512MB SD card supplied • Dual debug headers, 10-way • 5 generic push-button switches made available to NanoTalk Controller and daughter board FPGA • Dedicated ESD pad • Home button – enables firmware to take control of TFT panel and also provides NanoBoard reset functionality • Daughter board test/reset button

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Functional overview of the Desktop NanoBoard NB2DSK01

PC Parallel Interface PC USB Interface

NanoTalk Master NanoTalk Slave

1-Wire Memory SD Reader System JTAG

User Board NanoTalk Host Status LEDs Headers Controller

Memories RTC (SRAM, SDRAM, Flash)

Debug Headers

TFT LCD Panel NanoBoard Reset System PB Switches Daughter Board Clock Reset

User I/O Headers

Peripheral Board A

CAN Port

RS-232 Port

Peripheral Board B FPGA PS/2 Keyboard Daughter Board Port

PS/2 Mouse Port

Peripheral Board C

ADC/DAC/I2C

User DIP-switch User LEDs

Delta-Sigma DAC output

Buzzer Power Supplies

Desktop Stereo Speaker Assembly 1.2V VCCX Stereo Audio 1.8V -7.5V Line In NB2DSK-SPK01 2.5V 9V 3.3V 16.5V Mic In 5V 0V 5V Jack 5V Jack 5V Jack (IN) (IN) (OUT)

Line Out Headphones

Figure 8. Desktop NanoBoard NB2DSK01 block diagram.

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Compatibility with the NanoBoard-NB1 Altium's Desktop NanoBoard NB2DSK01 has been designed with compatibility – with the NanoBoard-NB1 – in mind. All of the daughter boards available from Altium can be readily used with either the NB2DSK01 or the NB1. Note: With no HDR_L connector, 2-connector daughter boards can only address one of the three peripheral boards on the NB2DSK01 – more precisely, the peripheral board attached to the motherboard's 'PERIPHERAL BOARD C' connector. Also, 2- connector daughter boards do not possess a 1-Wire memory device and so will not be detected when using the auto- configuration feature. In addition, the NanoTalk communications protocol and related JTAG chain implementation and management are identical between boards, allowing you to easily link an NB1 to your NB2DSK01 as part of a daisy-chained configuration.

Figure 9. Chaining an NB2DSK01 and an NB1 together. A word about ESD... The NB2DSK01 contains many digital devices that are highly sensitive to electrostatic discharge (ESD). To provide a level of protection against such discharge, the NB2DSK01 incorporates shielding for the following metallic-based components that are routinely handled: • RS-232 port • CAN port • USB port • PS/2 Keyboard and Mouse ports • Power toggle switch • SD Card reader. Each of these components is connected to a common SHIELD point. When the NB2DSK01 is connected to a PC using the USB connection, the component SHIELD is essentially tied to the PC's chassis ground, and it is through this ground that any build-up of electrostatic charge will be dissipated (discharged). If the NB2DSK01 is not connected via USB, then the electrostatic charge is coupled via a 10M resistor and 470pf capacitor to logic ground (GND). In addition, ESD, RFI/EMI and aggressive earth management requirements are achieved through protective shield nets – made available to the motherboard, daughter board and peripheral boards via the mechanical standoffs. This not only ensures the protection of the NB2DSK01 against damage arising from ESD events, but also prevents spurious resets due to 'ground bounce'. A dedicated ESD pad is also provided on the motherboard – below the User LEDs. The ESD pad is also connected directly to the board's component SHIELD and should ideally be touched prior to touching another point on the board, and before removing/attaching a peripheral board or daughter board. As such, it is labeled 'TOUCH HERE FIRST'. Figure 10. Dedicated ESD pad.

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Common ESD prevention techniques Of course, as with all boards/devices susceptible to ESD, it is important to follow standard antistatic handling procedures. As the ESD generally involved with the NB2DSK01 will be the result of contact with the human body, the following are often considered when creating an electrostatic protection area (EPA) in which to work: • Common Point Ground – this is a common ground point to which all elements of the work area (work surface, floor surface, equipment, people) are connected, bringing all to the same electrical potential. Auxiliary grounding (pipes, building frame, etc) must also be connected to this common ground point. • Wrist Strap – connected through to the Common Point Ground, it essentially keeps the person wearing it at near-ground potential. • ESD-Protective Work Surface – a surface that typically offers a resistance of greater than 1MΩ to ground, and which is connected to the Common Point Ground. Such a surface provides controlled dissipation of static charge built-up on any materials that come into contact with it. • ESD-Protective Floor Surface – a protective flooring surface, such as a floor mat or vinyl tiling, connected to the Common Point Ground. Similar to the work surface, it provides a path of dissipation for charge built-up on personnel or equipment in contact with it. • Antistatic Chair – a chair with metal casters and a metal footplate, with which to conduct static charge away from a user's body. Ideally, such a chair will be positioned on a an ESD-protective floor surface. • Foot Strap – also referred to as a 'soul grounder', it is typically worn over a non-conductive item of footwear. It provides contact with an ESD-protective floor surface, for dissipation of static charge away from the body of the wearer. • Conductive Shoes – used in conjunction with an ESD-protective floor surface, such shoes provide electrical contact for dissipation of charge away from the body of the wearer. • Antistatic Clothing – clothing itself is typically isolated from the body. As such, electrostatic charge may build up on a person's clothes, even though they are wearing a wrist strap. Static control garments, which are grounded, can be used to minimize the effects of clothing charge. • Air Ionization – use of an ionizer, to charge molecules in the air, can be an effective complement to a sound grounding system. Static charge built-up on insulated or isolated objects can be effectively neutralized as the opposite polarity charges are attracted from the air.

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Setting up the Desktop NanoBoard NB2DSK01

This section gives step-by-step instructions on connecting Altium's Desktop NanoBoard NB2DSK01 to your PC, and testing the connectivity between the two. We suggest you read this section thoroughly before beginning the installation and setup process.

CAUTION: Utilize standard antistatic procedures when handling or using the NB2DSK01 and associated daughter boards, peripheral boards and plug-ins. Always power the NB2DSK01 down when making changes to the configuration, for example when removing or inserting daughter boards and peripheral boards, or adding or removing plug in devices to the NB2DSK01's expansion headers. What’s in the box

Figure 11 – Desktop NanoBoard NB2DSK01 package contents

A - NB2DSK01 complete with Desktop Stereo Speaker Assembly NB2DSK-SPK01, stand, three peripheral boards (not shown), TFT LCD panel and 3V lithium battery all affixed. A 512MB SD card is also included (not shown). B - Mains power cord C - Power supply module D - Power supply daisy-chain connector – used with multiple NanoBoards E - Stylus for use with the TFT LCD panel F - USB cable G - JTAG ribbon cable (long 10-way IDC – 10-way IDC) H - 2 x NanoBoard daisy-chain cable – for connecting multiple NanoBoards I - Parallel cable (26-way IDC – DB25) J - JTAG flying-lead cable (10-way IDC – 10 flying leads) K - Audio loop-back cable L - 2 x User I/O connector cable M - JTAG ribbon cable (short 10-way IDC – 10-way IDC) If any components of the system are missing or appear damaged, please contact your nearest Altium representative.

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Note that the following components come as standard with the Altium Designer software: • Universal JTAG Interface • Parallel cable (26-way IDC – DB25 • JTAG ribbon cables – both short and long (10-way IDC – 10-way IDC) • JTAG flying-lead cable (10-way IDC – 10 flying leads) The Universal JTAG Interface is required when updating the NanoBoard firmware via the dedicated 'SYSTEM JTAG' header. System requirements To fully experience the power of Altium's Innovation Station, using Altium Designer in conjunction with the Desktop NanoBoard NB2DSK01, please ensure that your computer meets the minimum system requirements listed below, prior to installing the Altium Designer software. Recommended system for optimal performance ~ • Windows XP Professional SP2 (or later) ® • Intel Core™2 Duo/Quad 2.66GHz (or faster) processor or equivalent • 2GByte RAM • 10GByte hard disk space (Install + User Files) • Dual monitors with at least 1680x1050 (widescreen) or 1600x1200 (4:3) screen resolution ® ® # • NVIDIA GeForce 8000 series, 256MB (or more) graphics card* or equivalent † • Parallel port and free USB 2.0 port • DVD-Drive, Adobe Reader 8 (or above), Internet Connection (to receive updates and online technical support). Minimum system requirements for acceptable performance $ • Windows XP Professional SP2 (or later) ® • Intel Pentium™ 1.8GHz processor or equivalent • 1GByte RAM • 3.5GByte hard disk space (Install + User Files) • Main monitor 1280x1024 screen resolution - Strongly recommended: second monitor with minimum 1024x768 screen resolution ® ® • NVIDIA GeForce 6000/7000 series, 128MB graphics card* or equivalent † • Parallel port and free USB 2.0 port • DVD-Drive, Adobe Reader 8 (or above). ~ Testing also performed on Windows Vista for the recommended system. $ Functionality testing has been performed on Windows 2000 for the minimum system, however optimum performance cannot be guaranteed. # Graphics for the recommended system tested using an 8500 GT (256MB). * To take advantage of the accelerated graphics engine, including 3D visualization, your graphics card must support DirectX 9.0c and Shader model 3. On-board based graphics cards are not recommended. † Connection to the Desktop NanoBoard NB2DSK01 can be made from a Parallel port or USB 2.0 port. Connection to the NanoBoard-NB1 can be made only from a Parallel port. Altium Designer software To install Altium Designer you will need a minimum 3.5GBytes of free disk space. To begin the install process simply insert the product CD into your computer’s CD ROM drive. The Installation Wizard will automatically start and guide you through the installation process. If the Installation Wizard does not start automatically, please run Setup.exe located in the \Setup directory of the software CD. The first time you run the software you will be required to activate it. Use the Activate License options on the License Management page that appears in the software to do this. Once the installation of the software is complete, you should install the necessary FPGA vendor tools – if not already present – and then connect the Desktop NanoBoard NB2DSK01 to your PC before starting the design system.

12 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Important note on FPGA vendor tools Before you can download a design to the NB2DSK01 – or rather the physical device resident on a daughter board plug-in – you must have the appropriate vendor tools installed on your computer. These tools are used to place and route the FPGA design for the target device. The FPGA vendor tools ARE NOT supplied with the system and must be sourced independently. A range of daughter boards are available for use with the NB2DSK01, one of which is chosen and shipped at the time of purchase. The FPGA devices on these daughter boards are supported by the respective vendor’s downloadable tools available on the web, as well as by the commercial versions of these tools. In order to use your chosen daughter board (and any subsequently purchased daughter boards), you will need to install the relevant tools. More information on the vendor tools can be found on the respective FPGA vendor’s web site: ® ® • Actel Designer or Libero IDE from www.actel.com. The software can be downloaded but does require a license. Check the website for licensing options. ® ® • Altera Quartus II from www.altera.com. The Altera Quartus II Web Edition Software can be freely downloaded and does not require a license. ® ® • Lattice ispLever from www.latticesemi.com. The ispLever Starter software can be downloaded but does require a license. Check the website for licensing options. ® • Xilinx ISE™ from www.xilinx.com. The Xilinx ISE WebPACK can be freely downloaded and does not require a license. Links to each vendor's downloadable tools can be found in the Vendor Resources area of the Altium website (www.altium.com/Community/VendorResources). This page can be accessed directly from within Altium Designer. With the Devices view active (View » Devices View), simply choose the Vendor Tool Support entry on the main Tools menu. Note: Altium does not provide technical support for FPGA vendor tools. For information on installing these tools, please refer to the information provided by the FPGA vendors. Connecting the Desktop NanoBoard NB2DSK01 Before you can communicate with (and download a design to) the Desktop NanoBoard NB2DSK01, the board needs to first be prepared. This involves connecting it to your PC, installing your daughter board and supplying power to the system. To set up the NB2DSK01, complete the following steps: 1. Connect the NB2DSK01 to your PC. The NB2DSK01 can be connected to your PC via Figure 12. Parallel connection. the computer’s parallel port or a spare USB 2.0 port: Parallel port connection – Connect the supplied parallel cable to the parallel port of your PC. Connect the header plug of the parallel cable to the parallel port header at the top left of the NB2DSK01, as shown in Figure 12. USB connection – Connect the supplied USB cable from a spare USB 2.0 port on your PC, to the USB port on the NB2DSK01, as shown in Figure 13. Note: If you connect using both parallel and USB connections, you will be able to select which connection to use from within the Altium Designer software. For more information, see the section Choosing the JTAG connection. 2. Install a daughter board by gently positioning it so that its connectors are aligned with the Figure 13. USB corresponding connectors on the NB2DSK01 – connection. the posts of which slot through the holes in the daughter board. Once located, press the daughter board firmly onto the NB2DSK01 (Figure 14). Use the threaded standoffs to secure the daughter board to the motherboard. 3. Connect the plug of the power supply module to either of the power connectors on the top-right edge of the NB2DSK01 (Figure 15). 4. Connect the mains power cord to the Figure 15. Daughter board plugged-in. power supply module and plug it in to a standard power socket. Figure 14. Insert power cable and flick switch down.

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5. Turn on the power to the NB2DSK01, by flicking the toggle switch to the downward position. Six LEDs located on the underside of the attached Desktop Stereo Speaker Assembly NB2DSK-SPK01 will become illuminated to reflect that power is available. In addition, the TFT LCD panel will display an intro screen, welcoming you to the Desktop NanoBoard. Testing the PC to NanoBoard connection Once you have connected the NB2DSK01 to your PC, you should check that the system software can also connect to the NanoBoard. To do this, first start the Altium Designer application software (if not started already). The first time Altium Designer is run, a dialog will appear asking whether or not you wish to install the latest USB JTAG driver (Figure 16). This driver is required for JTAG communications between the PC and the NB2DSK01, using a USB 2.0 connection. You should therefore click Yes. It is recommended that you leave the option to Figure 16. USB JTAG driver installation. check for future driver updates enabled. Also when you launch the software for the first time, you will be required to activate it. Use the Activate License options on the License Management page that appears in the software to do this. For more information on license activation, consult the Installing Your Software Quickstart Guide that comes with the software. Once your license is activated, use the View » Home menu entry to access the Home view (Figure 17), which provides a launch point to many of the features offered by the system.

Figure 17. Home Page within Altium Designer, offering a menu of common tasks.

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Click on the Device Management and Connections link to access the Devices view (Figure 18). Alternatively, access this view by using the Devices View entry on the main View menu.

Figure 18. Accessing the Devices view. Detecting the NanoBoard Enable the Live option at the top-left of the Devices view. Altium Designer will scan the various multiplexed JTAG chains over the PC's JTAG link to the NB2DSK01. A connection indicator will appear above the Live option, reflecting the status of the connection:

- the system is connected and communicating with the NB2DSK01.

- the system could not detect the presence of an NB2DSK01. A successful connection will also result in an icon for the connected NanoBoard appearing in the top chain of the Devices view (the NanoBoard chain), and an icon for the daughter board FPGA device appearing in the middle chain of the view (the Hard Devices chain). Figure 19 illustrates this for a connected NB2DSK01 whose plug-in daughter board (DB30) contains a Xilinx Spartan-3 device (XC3S1500-4FG676C). Note: Double-clicking on the icon for a device in a chain will give access to the associated front panel for that device, offering various controls used for development/debugging.

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Figure 19. An example of a successfully detected (and connected) Desktop NanoBoard NB2DSK01. If the Devices view does not show the NB2DSK01 status as connected, there is no NB2DSK01 icon, or no icon is visible for the physical FPGA device on the daughter board, refer to the section Troubleshooting Desktop NanoBoard NB2DSK01 connection problems later in this document. Choosing the JTAG connection The Desktop NanoBoard NB2DSK01 can be connected to the PC using a parallel or USB connection. It is quite feasible to have both parallel and USB connections in place. The Devices view provides the means to switch between the type of JTAG connection you use, through a dedicated drop-down field on its associated toolbar (Figure 20). Note: The USB JTAG option will appear in the drop-down only once the NB2DSK01 Figure 20. Choosing the JTAG connection – Parallel or USB. is powered-on. If connected to the PC using a single connection only, that connection will be automatically detected and the corresponding option selected. If connected to the PC using both parallel and USB connections, the Parallel Port option will be chosen by default. Downloading a test project to the Desktop NanoBoard NB2DSK01 To ensure that Altium Designer and the Desktop NanoBoard NB2DSK01 are installed and functioning correctly, follow the steps below to compile and synthesize an example project, from within Altium Designer, and download it to the FPGA resident on the currently plugged-in daughter board. For this test we will use the DSF_Mandelbrot.PrjFpg example project, found in the \Examples\NB2DSK1 Examples\DSF Mandelbrot folder of the installation. 1. From within Altium Designer, select File » Open Project. 2. Navigate to the \Examples\NB2DSK1 Examples\DSF Mandelbrot directory and open the file DSF_Mandelbrot.PrjFpg. When the project has loaded, the Projects panel on the left side of the workspace will display the files in this project. 3. If the Devices view is not active, select View » Devices View from the menus to display it. The open project will automatically be assigned to the FPGA device on the daughter board plug-in. Figure 21 illustrates this for an installed Xilinx Spartan-3 daughter board. This assignment takes place because a valid Configuration exists for the project, containing a constraint file that targets the daughter board device. For more information on configurations and constraints, refer to the article AR0124 Design Portability, Configurations and Constraints.

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Figure 21. Loading an example project – automatically targeted to the daughter board FPGA device. 4. The four stages displayed above the physical device are its Process Flow. To process the project and download it to the daughter board FPGA device, click the Program FPGA button – the final stage in this flow. The system will sequentially invoke each stage of the Process Flow. This involves: - compiling the source project files Figure 22. Starting the programming process. - synthesizing the design - calling the vendor place and route tools to process the design for the target FPGA, and - downloading the design to the daughter board FPGA. This process can take several minutes depending on the speed of your computer and which daughter board is installed. Note: If the system fails during the Build processes, shown by a magenta status indicator, Figure 23. Reaching the Place and Route stage of the overall Build process. this can be because the FPGA vendor tools are not correctly installed or have not been properly activated. Please refer to the information supplied with the FPGA vendor tools for information on installing and activating these tools. For more information on the Devices view and the Process Flow, refer to the application note AP0103 Processing the Captured FPGA Design. Once the design has been downloaded all of the stage indicators in the Process Flow will be green, the text underneath the physical device's icon will change from Reset to Programmed, and the Results Summary dialog will be shown (Figure 24). On the software side, this indicates that the project has been successfully processed and downloaded to the daughter board FPGA. Close this dialog.

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Figure 24. Physical device successfully programmed with the FPGA design.

On the hardware side, the 'Program' LED on the daughter board will be lit (Green), confirming that the design has been loaded into the physical device. For this example project, additional confirmation of successful programming comes in the form of a Mandelbrot pattern displayed on the TFT LCD panel. Use the supplied stylus to draw a frame around part of the pattern you wish to 'zoom into'. Press the 'DAUGHTER BD TEST/RESET' button at the bottom of the NB2DSK01 motherboard, to the left of 'User Header A', to restore the display to its original (full) size. Also notice that the lower chain in the Devices view – the Soft Devices chain – becomes populated with any soft (Nexus- enabled) devices detected in the design. This example project contains a single 32-bit processor (a TSK3000A). The icon representing the processor is shown as 'Running'. This reflects that the system is communicating with this processor, allowing you to interact and control the processor for development and debugging purposes. Double-clicking on the icon for any soft (Nexus-enabled) device in this chain (processors, virtual instruments) will give access to the front panel for that device.

Figure 25. Example of accessing the controls for a soft JTAG device (TSK3000A processor).

For more information on the various instrument panels associated with devices appearing on the various chains in the Devices view, and the controls they offer for interactive real-time debugging (LiveDesign), refer to the application note AP0103 Processing the Captured FPGA Design.

18 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Troubleshooting Desktop NanoBoard NB2DSK01 connection problems If, after completing the Desktop NanoBoard NB2DSK01 setup and installation procedures, the Devices view shows that the system cannot connect to the NB2DSK01 or cannot detect the presence of an FPGA on the plug-in daughter board, go through the following steps to try to correct the problem: 1. Ensure that the NB2DSK01 is switched on. 2. Ensure that the connecting cable (parallel or USB) between the NB2DSK01 and the PC is correctly plugged in at both ends. 3. Check that you have correctly installed an FPGA daughter board onto the NB2DSK01. 4. With the Devices view active (View » Devices View), ensure that the Live option is enabled, and select Tools » Refresh All from the menu (shortcut F5). 5. From the Devices view, select Tools » Scan NanoBoard Chain from the main menus. This forces a manual scan of the NanoBoard JTAG chain. A dialog will appear, listing all NanoBoards detected.

Figure 26. Manually interrogating the NanoBoard JTAG chain. 6. If the NanoBoard(s) are detected correctly, from the Devices view select Tools » Scan Hard Chain from the main menus. This forces a manual scan of the Hard Devices JTAG chain. A dialog will appear, listing all the physical devices detected (FPGAs and/or physical processors).

Figure 27. Manually interrogating the Hard Devices JTAG chain. If, after completing all the above steps, the system still cannot establish a connection with the NB2DSK01 and/or daughter board device, then please contact your nearest Altium Sales & Support representative. Note: When connecting the Desktop NanoBoard NB2DSK01 to a PC via a parallel port, the system requires the presence of a working, standard parallel port on the computer. The parallel port implementations on some computers do not strictly adhere to the standard, which may cause communications with the NB2DSK01 to fail. If possible, reinstall the system on a different computer to determine if this may be the problem, or switch to using USB for the connection. Where to go to from here Once you have completed the steps outlined in the previous sections, your system is installed and ready for use. To help become familiar with your design system and its features, we suggest you read over the following documents. These documents (and others referenced to elsewhere in this document) can be found in the \Help folder of the installation. You can either access them from there directly, or locate and launch them from the lower region of the Knowledge Center panel (Help » Knowledge Center). AR0137 Introduction to Altium Designer GU0112 Welcome to the Altium Designer Environment GU0123 An Introduction to Embedded Intelligence TU0116 Getting Started with FPGA Design TU0122 Getting Started with Embedded Software TU0128 Implementing a 32-bit Processor-based Design in an FPGA

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Desktop NanoBoard NB2DSK01 resources

Altium's Desktop NanoBoard NB2DSK01 is a 300 x 165mm (11.8” x 6.5”) eight layer printed circuit board (6 x signal, 2 x plane), powered by an external 5 Volt regulated supply. One of the plane layers is associated exclusively to GND. The other plane layer is used primarily for the 3.3V power supply, but incorporates a split region to accommodate the 5V supply. Both top and bottom of the board are used for component placement. Figure 28 indicates the layout of the NB2DSK01 motherboard.

Figure 28. Physical layout of the Desktop NanoBoard NB2DSK01. The NB2DSK01 motherboard features a variety of resources, many of which are made available to the target FPGA on the currently-fitted daughter board. There are also a number of system resources, that are not accessible from a daughter board device, but are available to the user in various situations – such as connectors for daisy-chaining NanoBoards, audio-related connectors, and resources for powering the board. Some system resources are only used by the NB2DSK01 itself, such as memory devices used by the firmware running in the board's Controller FPGA device. Additional resources are available to a daughter board device, located either on the daughter board itself (e.g. memories) or on dedicated satellite extension boards that also plug-in to the NB2DSK01 motherboard. The latter are referred to as peripheral boards. Further information on daughter and peripheral boards can be found in the sections Daughter Boards and Peripheral Boards respectively, later in this document. For information on the range of daughter boards and peripheral boards currently available and additional documentation specific to each, go to www.altium.com/nanoboard/resources. The following sections provide information on all of the resources on the NB2DSK01 motherboard – those not available to a target FPGA and those that are. Note: For each of the following resources, reference is made to the corresponding sheet(s) of the motherboard schematics on which the circuitry of interest can be found. A pdf document of these schematics – NB2DSK01 Desktop NanoBoard Schematics.pdf – can be found at www.altium.com/nanoboard/resources.

20 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

System resources The following sections detail those resources on the NB2DSK01 motherboard that can not be accessed from, and used within, a design targeted to a daughter board FPGA device. Power The NB2DSK01 is powered by a 5V regulated supply, the power module for which is supplied in the box. If the total power consumption of a given NanoBoard configuration – i.e. daisy-chained and/or with connected expansion devices/user boards – exceeds 4A, then a higher current capacity power supply may be required. Such a power source must provide a regulated 5V supply. Three power connector jacks are provided. Two of these are connected in parallel allowing one of the jacks to be used to supply power to the next NanoBoard in a series of daisy-chained NanoBoards. The third is used for outputting the board's 5V supply to an external user board. Figure 29. 5V power input connectors Power to the board is controlled through a power toggle switch. The board is powered and toggle switch. when the switch is in the downward position. This switch controls power to the NB2DSK01 and also power at the output power jack. It does not toggle the power to other NanoBoards in a daisy-chain configuration. The NB2DSK01 has on-board fixed-voltage regulators that provide 3.3V, 2.5V, 1.8V and 1.2V for the Xilinx Spartan-3 controller FPGA, and a programmable voltage regulator (1.25V to 3.3V) to provide an appropriate voltage (VCCX) for the FPGA device on a plug-in daughter board. Each daughter board module automatically programs the regulator (where applicable) to suit its own internal voltage requirements. Note: 3-connector daughter boards available with the Desktop NanoBoard NB2DSK01 and beyond do not make use of the VCCX voltage supply from the motherboard. Where the FPGA Figure 30. 5V power output device on such a board requires an additional voltage level, this level is supplied by a regulator connector. on board the daughter board itself, and powered from the daughter board's 5V supply rail. It is advised to use this approach when building your own daughter board. For the TFT LCD panel a further three voltage levels are produced by the NB2DSK01, based on the regulated 5V input. These are: -7.5V, 9V and 16.5V. The NB2DSK01 provides an array of test points for checking the integrity of each of the board's power supplies, including four dedicated GND points (0V). Power required for a daughter board (3.3V, 5V) and each peripheral board (1.2V, 1.8V, 2.5V, 3.3V, 5V) is routed to the corresponding docking connector(s) for those boards. Both the 3.3V and 5V supply buses can also be selected to power various expansion devices that can be connected to the NB2DSK01, via the 'User Header A' and 'User Header B' connectors. Current monitoring is in place for each of these power lines (19 in total) through use of a MAX4372T high-side current sense amplifier (from Maxim). Each power line is routed to its destination connector through a 47mΩ resistor, Figure 31. Test points are available for all power which serves as the external sense resistance for the associated MAX4372T supplies on the NB2DSK01, in the one convenient device. Powered by the NB2DSK01's 9V supply, this device provides a voltage location. output that is proportional to the voltage across this sense resistance, and has a fixed gain of 20. For current passing through the 47mΩ resistor, the voltage across the device's input is 47uV/mA. The output of the device is therefore 940uV/mA (applying the x20 gain). Two low-power, 12-channel, 12-bit ADC devices (MAX1229, from Maxim) collect together the analog voltage outputs from all current sense amplifiers, for transmission back to the NB2DSK01's Xilinx Spartan-3 Controller FPGA, over an SPI bus. The output of each ADC, which has an internal reference voltage of 2.5V is:

ADC output = (2.5V/4096) / 940uV = 0.64931mA/bit (=2.65957A full scale) Note: When the NB2DSK01 is powered, six LEDs located on the underside of the attached Desktop Stereo Speaker Assembly NB2DSK-SPK01 will become illuminated to reflect that power is available. These are RGB LEDs whose color is controlled by the NB2DSK01's NanoTalk Controller. Interaction with the LEDs is performed using the interactive GUI on the TFT LCD panel.

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Location on board The parallel-connected 5V power connectors (designated J1 and J3) and power toggle switch (designated SW6) are located on the component side of the board, towards the top-right corner. The 5V power output connector (designated J2) is located on the solder side, at the bottom-left edge of the board. The power supply test points (designated TP1, TP5-TP12, and TP15) and GND points (designated 0V) are also located on the component side of the board, directly below the parallel-connected power jacks. The MAX4372T devices for power routed to the 'PERIPHERAL BOARD A' connector (designated U31, U34, U37, U40, U43), 'PERIPHERAL BOARD B' connector (designated U29, U32, U35, U38, U41), 'PERIPHERAL BOARD C' connector (designated U30, U33, U36, U39, U42), the relevant daughter board connectors (designated U44, U46), and the User Board headers (designated U45, U47), are all located on the solder-side of the board. The MAX1229 devices (designated U48 and U49) are also located on the solder-side of the board.

Figure 32. Current sense circuitry on the NB2DSK01. Top – MAX4372T devices associated with peripheral board monitoring and the MAX1229 devices. Bottom-Left - MAX4372T devices associated with daughter board monitoring. Bottom-Right - MAX4372T devices associated with user board monitoring.

Schematic reference Power supply-related circuitry can be found on the following sheets of the motherboard schematics: • Sheet 2 (NB2_PSU.SchDoc, entitled NB2DSK01 POWER SUPPLIES) – top sheet for all power supplies on the NB2DSK01. • Sheet 3 (PSU_BZX84C7V5_-7V5.SchDoc, entitled PSU BZX84C7V5 -7V5) – TFT LCD panel's -7.5V supply. • Sheet 4 (PSU_MAX1831_1V2.SchDoc, entitled PSU MAX1831 1V2) – Primary 1.2V supply. • Sheet 5 (TPS75501_1V8.SchDoc, entitled PSU TPS75501 1V8) – Primary 1.8V supply. • Sheet 6 (TPS75501_2V5.SchDoc, entitled PSU TPS75501 2V5) – Primary 2.5V supply. • Sheet 7 (TPS75501_3V3.SchDoc, entitled PSU TPS75501 3V3) – Primary 3.3V supply. • Sheet 8 (PSU_LM317_9V0.SchDoc, entitled PSU LM317 9V0) – TFT LCD panel's 9V supply. • Sheet 9 (PSU_LM2704_16V5.SchDoc, entitled PSU LM2704 16V5) – TFT LCD panel's 16.5V supply. • Sheet 10 (PSU_LM1084_ADJ.SchDoc, entitled PSU LM1084 ADJ) – Daughter board VCCX supply. • Sheet 11 (PWJACK+SWITCH.SchDoc, entitled Power Jack & Switch) – 5V power jacks and toggle switch. • Sheet 12 (CURRENT_SENSE.SchDoc, entitled DB/PB Current Sense) – Current sense circuitry.

Further device information For more information on the MAX4372T and MAX1229 devices, refer to the datasheets (MAX4372-MAX4372T.pdf and MAX1227-MAX1231.pdf) available at www.maxim-ic.com.

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NanoTalk Controller The NB2DSK01 uses a Xilinx Spartan-3 device (XC3S1500- 4FG676C) as the controller for the board and the host for the NanoBoard firmware. This device is commonly referred to as the NanoTalk Controller. It is this device into which the 'smarts' of the system – the NanoBoard firmware – gets loaded upon power-up. The XC3S1500-4FG676C is a 456-pin device (333 User I/O) with 576K of embedded RAM and 29K logic cells. The NanoTalk Controller manages JTAG communications with: • Parallel PC and USB PC interfaces • System JTAG header • FPGA daughter board • Peripheral boards Figure 33. NanoTalk Controller, implemented using a Xilinx Spartan-3 • Master/Slave daisy-chain device. • User Board headers. The NanoTalk Controller also manages/communicates with the following areas of the board: • Host status LEDs • 1-Wire memory devices (used for identification) on motherboard, daughter board, peripheral boards and Desktop Stereo Speaker Assembly NB2DSK-SPK01 • TFT LCD panel. and the following SPI-based resources: • Touch Screen Digitizer • SPI Master clock • SPI Flash memory • Real-Time Clock (RTC) • SPI resources on peripheral boards • SPI-compatible LED drivers on the attached Desktop Stereo Speaker Assembly NB2DSK-SPK01. In addition to JTAG chain management and communications with board resources locally, the NanoTalk Controller multiplexes the various device chains (NanoBoard, Hard JTAG and Soft JTAG) to present a single JTAG link to the PC on which the Altium Designer software is installed. This single chain is then demultiplexed by the software (Figure 34).

Altium Designer NanoBoard NB2DSK01

SPI Devices NanoTalk Controller Daughter Board FPGA JTAG Link Hard

Soft Virtual Processor Inst.

Peripheral Peripheral Peripheral User Board User Board Board A Board B Board C A B

Figure 34. Accessing information for the multiplexed JTAG chains over a single JTAG link. The JTAG link between the NB2DSK01 and the PC can be implemented using either the parallel or USB 2.0 ports. For more information, see the sections NanoBoard-PC interface – Parallel port and NanoBoard-PC interface – USB port, respectively. For more information on communications between the Desktop NanoBoard NB2DSK01 and the PC, refer to the article AR0130 PC to NanoBoard Communications.

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Location on board The Xilinx Spartan-3 device (designated U5) is located on the component side of the board, within the real estate that falls beneath the TFT LCD panel.

Schematic reference The NanoTalk Controller can be found on Sheet 13 (Host_FPGA.SchDoc, entitled Host Controller – Spartan3-1500) of the motherboard schematics.

Further device information More information on the XC3S1500-4FG676C can be found through the Browse Physical Devices dialog. Access this dialog from the Devices view (View » Devices View) by choosing the Browse Physical Devices entry in the main Tools menu. Alternatively, refer to the datasheet (dso99.pdf) available at www.xilinx.com. Configuration PROM The NB2DSK01 uses a Xilinx Platform Flash Configuration PROM device (XCF08PFS48C) in which to store the system's firmware. The firmware gives the NB2DSK01 its 'smarts'. The XCF08PFS48C is a 48-pin device providing 8M of memory. On power-up, the firmware is automatically loaded into the NanoTalk Controller.

Location on board The configuration PROM (designated U7) is located on the component side of the board – to the top-right of the NanoTalk Controller.

Schematic reference Figure 35. Serial PROM device used to hold the NanoBoard firmware. The configuration PROM can be found on Sheet 19 (XCF08PFS48C_FLASH.SchDoc, entitled FPGA Config XCF08PFS48C) of the motherboard schematics.

Further device information More information on the XCF08PFS48C can be found through the Browse Physical Devices dialog. Access this dialog from the Devices view (View » Devices View) by choosing the Browse Physical Devices entry in the main Tools menu. Alternatively, refer to the datasheet (dso123.pdf) available at www.xilinx.com. System JTAG programming port The NB2DSK01 provides a dedicated host programming port, which is used to load updated NanoBoard firmware directly into the Xilinx Platform Flash Configuration PROM. The 10-pin male header caters for both Hard JTAG (pins 1-4) and Soft JTAG (pins 5-8) signals. Pin 9 of the header is tied to ground. Pin 10 is connected to the motherboard's 5V supply, via a 350mA fuse and 3A/40V Schottky diode. Connection to the port is made from the parallel port (or USB port) of the PC on which Altium Designer is installed. Altium's Universal JTAG Interface is used to convert the parallel (or USB) cabling to 10-way IDC JTAG cabling.

Location on board The header, labeled (and designated ) is located on the solder side of 'SYSTEM JTAG' HDR3 Figure 36. Update firmware using the board, at the left-hand edge and below the 'AUDIO TEST' jack. the dedicated Host Programming Port. The 350mA fuse (designated F5) and Schottky diode (designated D11) are also located on the solder-side of the board, to the bottom-left of the host programming port.

Schematic reference The circuitry relating to the host programming port can be found on the following sheets of the motherboard schematics: • Sheet 24 (JTAG_ALTIUM_HOST.SchDoc, entitled Host JTAG Header) • Sheet 25 (CON_HOSTJTAG_10WBOXHDRRAM.SchDoc, entitled Host JTAG Header)

24 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Common-Bus SRAM The NB2DSK01 includes Static RAM as part of the common-bus block of memory resources available to the NanoTalk Controller, or more specifically the firmware running within. The SRAM is provided in the form of two 4Mbit, high-speed CMOS SRAM devices. Each device is organized as 256K x 16 bits – combined together to give 256K x 32-bit storage (1MByte). Both devices are powered by the NB2DSK01's 3.3V supply.

Location on board The common-bus SRAM devices (designated U27 and U28) are located on the component side of the board, below the NanoTalk Controller (U5) and within the real estate that falls beneath the TFT LCD panel.

Schematic reference Figure 37. Common-bus SRAM used by the NB2DSK01's firmware. The common-bus SRAM devices can be found on Sheet 37 (SRAM_256Kx32_TSOP44_1.SchDoc, entitled 256K x 32 SRAM – TSOP44 x 2) of the motherboard schematics. The common-bus memory block and interface wiring can be found on Sheet 36 (NB2_CommonMemory.SchDoc, entitled Common-Bus Memory Block). Common-Bus SDRAM The NB2DSK01 includes Synchronous Dynamic RAM as part of the common-bus block of memory resources available to the NanoTalk Controller, or more specifically the firmware running within. The SDRAM is provided in the form of two MT48LC16M16A2TG devices (from Micron Technology). Each device is a 256Mbit, high-speed CMOS SDRAM, organized as 16M x 16 bits (4M x 16 bits x 4 banks) – combined together to give 16M x 32-bit storage (64MByte). Both devices are powered by the NB2DSK01's 3.3V supply.

Location on board The common-bus SDRAM devices (designated U25 and U26) are located on the component side of the board, to the right of the common-bus SRAM and within the real estate that falls beneath the TFT LCD panel. Figure 38. Common-bus SDRAM used by the NB2DSK01's firmware. Schematic reference The common-bus SDRAM devices can be found on Sheet 39 (SDRAM_MT48LC16M16A2TG_16Mx32.SchDoc, entitled 16M x 32 SDRAM TSOP54 x 2) of the motherboard schematics. The common-bus memory block and interface wiring can be found on Sheet 36 (NB2_CommonMemory.SchDoc, entitled Common-Bus Memory Block).

Further device information For more information on the MT48LC16M16A2TG device, refer to the datasheet (256MSDRAM.pdf) available at www.micron.com. Common-Bus Flash memory The NB2DSK01 includes Flash memory as part of the common-bus block of memory resources available to the NanoTalk Controller, or more specifically the firmware running within. The Flash memory is provided in the form of an S29GL256N11FFIV10 device (from Spansion). This Page Mode 256Mbit device is manufactured using 110nm MirrorBit™ technology and is organized as 16M x 16 bits (32MByte). It is powered by the NB2DSK01's 3.3V supply and offers a 110ns access time.

Location on board The common-bus Flash memory device (designated U24) is located on the component side of the board, to the right of the common-bus SDRAM and within the real estate that falls beneath the TFT LCD panel. Figure 39. Common-bus Flash memory used by the NB2DSK01's firmware.

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Schematic reference The common-bus Flash memory device can be found on Sheet 38 (FLASH_S29GL256N11FFIV10_16Mx16.SchDoc, entitled 16M x 16 Flash Memory (BGA)) of the motherboard schematics. The common-bus memory block and interface wiring can be found on Sheet 36 (NB2_CommonMemory.SchDoc, entitled Common-Bus Memory Block).

Further device information For more information on the S29GL256N11FFIV10 device, refer to the datasheet (s29gl-n_00_b3_e.pdf) available at www.spansion.com. Independent SRAM The NB2DSK01 also includes independent Static RAM as part of the memory resources available to the NanoTalk Controller, or more specifically the firmware running within. The term 'independent' is used in this case to distinguish this SRAM – which is interfaced using dedicated address and data lines – from the SRAM that is accessed over a common bus (also used to access on-board SDRAM and Flash memory). The SRAM is provided in the form of two 4Mbit, high-speed CMOS SRAM devices. Each device is organized as 256K x 16 bits – combined together to give 256K x 32-bit storage (1MByte). Both devices are powered by the NB2DSK01's 3.3V supply.

Location on board The independent SRAM devices (designated U22 and U23) are located on the component side of the board, to the right of the NanoTalk Controller (U5) and within the real estate that falls beneath the TFT LCD panel. Figure 40. Independent SRAM used by Schematic reference the NB2DSK01's firmware. The independent SRAM devices can be found on Sheet 41 (SRAM_256Kx32__TSOP44_2.SchDoc, entitled 256K x 32 SRAM – TSOP44 x 2) of the motherboard schematics. Host status LEDs The Host status LEDs (labeled 'SL1'..'SL8') are used to indicate the state of the NanoTalk Controller and the various communications links that interface with it, such as Hard JTAG, Soft JTAG and SPI. For more detailed information on these LEDs and what each represents, go to www.altium.com/nanoboard/resources.

Location on board The Host status LEDs (designated LED1 – LED8) are located on the component side of the board, to the left of the daughter board connector HDR_L1 and above the 'DAUGHTER BD TEST/RESET' button.

Schematic reference The LED circuitry can be found on Sheet 34 (LED_RED_0603x8.SchDoc, entitled 8-Way 0603 Red LED Array) of the motherboard schematics. Figure 41. Host status LEDs.

26 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

FPGA daughter board connectors The plug-in daughter boards are mounted onto the NB2DSK01 motherboard using three 100-way Female docking connectors – designated HDR_T1, HDR_L1 and HDR_B1. These are individually referred to as 'NANOCONNECT' interfaces, and collectively as the daughter board connectors. The daughter boards allow the NB2DSK01 to be used with a variety of target FPGAs. Daughter boards may be constructed with any configuration that matches the pinout requirements of HDR_T1, HDR_L1 and HDR_B1. Note: HDR_T1 and HDR_B1 are wired such that all Altium daughter boards are compatible with both the NanoBoard- NB1 and the Desktop NanoBoard NB2DSK01. The NB2DSK01 daughter board connectors map I/O resources on the NB2DSK01 motherboard directly to the pins of the daughter board FPGA device, as if that device were mounted directly on the NB2DSK01. Figure 42. Daughter board connectors ('NANOCONNECT' interfaces) – the docking point for a satellite daughter board. For more information on daughter boards, see the section Daughter Boards, later in this document. For more information on the NB2DSK01 motherboard resources made available to a daughter board FPGA device, see the section Resources accessible from an FPGA design. Resources on the plug-in peripheral boards are also made available to the daughter board FPGA device, with the corresponding I/O pins from each peripheral board connector wired directly to pins of the daughter board connectors. For more information, see the section Peripheral Boards later in this document.

Location on board The daughter board connectors (HDR_T1, HDR_L1, HDR_B1) are located on the component side of the board, to the left of the TFT LCD panel and above the two 20-pin user headers – 'User Header A' (UH1) and 'User Header B' (UH2).

Schematic reference The daughter board connectors can be found on Sheet 45 (NB2_DBCON.SchDoc, entitled 3-Way Daughter-Board Socket) of the motherboard schematics. Peripheral board connectors The plug-in peripheral boards are each mounted onto the NB2DSK01 motherboard using a single 100-way Female docking connector. Provision is made for the connection of up to three such boards, with the corresponding connectors labeled 'PERIPHERAL BOARD A', 'PERIPHERAL BOARD B' and 'PERIPHERAL BOARD C' respectively. These are individually referred to as 'NANOCONNECT' interfaces, and collectively as the peripheral board connectors. Resources on the peripheral boards are made available to the daughter board FPGA device. Figure 43. Peripheral board connectors ('NANOCONNECT' interfaces). The corresponding I/O pins from each peripheral board connector – 50 each – are wired directly to pins of the daughter board connectors: • Peripheral Board A and B connector signals are wired to daughter board connector HDR_L1 • Peripheral Board C connector signals are wired to daughter board connector HDR_T1. For more information on peripheral boards, see the section Peripheral Boards, later in this document.

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Location on board The peripheral board connectors – 'PERIPHERAL BOARD A' (designated EXTHDR1), 'PERIPHERAL BOARD B' (designated EXTHDR2) and 'PERIPHERAL BOARD C' (designated EXTHDR3) – are located on the component side of the board, on the left- hand side.

Schematic reference The generic peripheral board connector can be found on Sheet 46 (NB2_PBCON.SchDoc, entitled Peripheral Board Connector) of the motherboard schematics. NanoBoard-PC interface – Parallel port The NB2DSK01 can be connected to your PC via the computer's standard parallel port. The NB2DSK01 provides a corresponding parallel port through use of a 26-pin Male header. When you launch Altium Designer, the system loads a driver that configures the parallel port to run as a single multiplexed JTAG link between the NB2DSK01 and the PC. Three distinct JTAG chains present on the NB2DSK01 constitute this multiplexed link (NanoBoard JTAG chain, Hard devices JTAG chain, Soft (Nexus) devices JTAG chain), the multiplexing being handled by the NanoTalk Controller. Demultiplexing of the link is performed at the PC end, by the Altium Designer software. For more information on the JTAG communications, refer to the Figure 44. Parallel port interface for connection to PC. article AR0130 PC to NanoBoard Communications. Pin 26 of the header provides a 1-Wire bus connected to the DATA line of the DS2406 device used to provide board identification for the NB2DSK01. This is a spare pin of the header and is separate from the parallel port communications. This 1- Wire bus is used for production programming purposes only – allowing the ID device to be programmed externally through the parallel port. As such, it is not available for general use. For more information on board identification, see the section Board ID memory.

Location on board The parallel port header (designated HDR6) is located on the solder side of the board, towards the top-left corner.

Schematic reference The parallel port interface circuitry can be found on the following sheets of the motherboard schematics: • Sheet 32 (PC_ParallelPort.SchDoc, entitled PC Parallel Port Interface) • Sheet 33 (CON_PCPPORT_26WBOXHDRRAM.SchDoc, entitled PC Parallel Port + 1-Wire). NanoBoard-PC interface – USB port The NB2DSK01 can also be connected to your PC via one of the computer's standard USB 2.0 ports. The NB2DSK01 provides a corresponding port through use of a USB B-type connector. Providing the high-speed interface between the NanoTalk Controller and the USB bus is an EZ-USB SX2™ device (CY7C68001-56LFC, from Cypress Semiconductor). This device has a built-in USB transceiver and a Serial Interface Engine (SIE), which automatically manages the USB protocol. The device is powered by the NB2DSK01's 3.3V supply and is configured to provide a 16-bit bidirectional data bus to/from the NanoTalk Controller. Reset of the USB interface device is provided through use of a supervisory reset circuit device – a MAX6315US26D1, from Maxim. This device will assert the reset signal to the CY7C68001 (active Low) if its 3.3V supply voltage dips below 2.3V, or if it receives an external reset signal from the NanoTalk Controller. The reset signal will remain asserted for a Figure 45. USB interface port for minimum of 1ms (typically 1.4ms) after the supply voltage rises above this threshold, and/or connection to a PC. the NanoTalk Controller deasserts its reset signal. The USB power and data lines (VBUS, D+, D-) are protected against high transient voltages through the use of a low-capacitance transient voltage Although the USB interface device supports operation at Full (12Mbps) or High (480Mbps) speed, on the suppressor device – a NUP2201MR6, from ON Semiconductor. NB2DSK01, it is set to operate at High-speed only. When you launch Altium Designer, the system loads a driver that configures the

28 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

USB port to run as a single multiplexed JTAG link between the NB2DSK01 and the PC. Three distinct JTAG chains present on the NB2DSK01 constitute this multiplexed link (NanoBoard JTAG chain, Hard devices JTAG chain, Soft (Nexus) devices JTAG chain), the multiplexing being handled by the NanoTalk Controller. Demultiplexing of the link is performed at the PC end, by the Altium Designer software.

Location on board The USB connector (designated J4) is located on the component side of the board, to the right of the CAN port. The CY7C68001 device (designated U52) and the NUP2201MR6 device (designated U51) are also located on the component side of the board, directly below the USB port itself. The MAX6315 device (designated U50) is located on the solder side of the board.

Schematic reference The USB circuitry can be found on the following sheets of the motherboard schematics: • Sheet 22 (USB_CY7C68001-56LFC.SchDoc, entitled High-Speed USB 2.0 Controller) Figure 46. USB high-speed interface device (U52) and voltage suppressor (U51). • Sheet 23 (CON_USBB_RA.SchDoc, entitled USB 2.0 Type B Connector).

Further device information For more information on the CY7C68001 device, refer to the datasheet (CY7C68001.pdf) available at www.cypress.com. For more information on the MAX6315 device, refer to the datasheet (MAX6315.pdf) available at www.maxim-ic.com. For more information on the NUP2201MR6 device, refer to the datasheet (NUP2201MR6-D.pdf) available at www.onsemi.com. NanoTalk Master-Slave headers To allow multiple NanoBoards to be connected in a daisy- chain configuration, two 10-pin headers are provided – designated HDR4 ('NANOTALK IN') and HDR5 ('NANOTALK OUT'). To add an additional NanoBoard (e.g. an NB1 or an NB2DSK01) into the chain, simply connect a 10-way IDC ribbon cable from header HDR5 on the first board (labeled on the component side of the board as 'NANOTALK TO SLAVE'), to header HDR4 on the additional board (labeled on the component side of the board as 'NANOTALK FROM MASTER'). The presence of a NanoBoard is determined by the signal level on pin 10 of a header. If this is Low the NanoBoard Controller will route both the Hard and Soft JTAG chains via the header. Figure 47. NanoTalk Master and Slave connectors, used for daisy- chaining NanoBoards. Location on board The two headers are located on the solder side of the board, at the top-left and top-right edges respectively.

Schematic reference The NanoTalk Master and Slave circuitry can be found on the following sheets of the motherboard schematics: • Sheet 28 (JTAG_ALTIUM_NANOTALK.SchDoc, entitled NanoTalk JTAG Header) • Sheet 29 (CON_NANOTALK_10WHDRRAMx2.SchDoc, entitled NanoTalk JTAG Headers).

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Stereo Audio The NB2DSK01 provides a powerful stereo audio system, complete with analog mixer, power amplifier and various sound output methods. The following sections take a closer look at the various stages involved in the implementation of this system.

Sound input The NB2DSK01 provides 3.5mm stereo audio jacks for connection of an external audio device ('LINE IN') and a microphone ('MICROPHONE'). The signals derived from these inputs – LineInR, LineInL and MicIn – are wired through to each of the peripheral board connectors. The connectors are generic with respect to their pin assignments. In this way, a peripheral board containing an audio-based resource can be placed in any of the three connector positions, and the audio input Figure 48. Audio input jacks and mixer signals are made available. channel test points.

Figure 49. Audio test Note: Prior to being sent to the peripheral board connectors, the input. MicIn signal is fed through a MAX9812L low-power microphone amplifier (from Maxim). Powered by the NB2DSK01's 3.3V supply and permanently enabled, the amplifier delivers a fixed gain of 20dB. An analog mixer is used to mix the following audio sources together (one stage each for Left and Right channels):

LineOut from Host - this is the output from a Delta-Sigma DAC, driven by the host (NanoTalk Controller) FPGA. LineOut from peripheral board A - output from an audio resource on a peripheral board plugged-in to the socket corresponding to 'PERIPHERAL BOARD A'. LineOut from peripheral board B - output from an audio resource on a peripheral board plugged-in to the socket corresponding to 'PERIPHERAL BOARD B'. LineOut from peripheral board C - output from an audio resource on a peripheral board plugged-in to the socket corresponding to 'PERIPHERAL BOARD C'. Buzzer signal - this is the legacy NB1-style mono buzzer signal from the daughter board FPGA. Audio Test signal - this signal is supplied courtesy of an additional 3.5mm audio jack. Used as a test input to the amplifier, it essentially gives you a direct Line In from an audio source external to the NB2DSK01. Two test points are provided to monitor the output of the mixer, one for each channel.

Audio amplification At the heart of the audio system is a stereo audio power ® amplifier – an LM4849MH Boomer device, from National Semiconductor. This device incorporates stereo bridged audio power amplifiers capable of producing 2W output power, with DC volume control. It is powered by the NB2DSK01's 5V power supply. The device supports two stereo input signals, with an internal multiplexer to choose between them. For the NB2DSK01, the multiplexer control signal has been tied to ground, ensuring that only stereo input 1 is used. This input is sourced from the analog mixer discussed in the previous section. The LM4849 also provides shutdown and mute features. Figure 50. Stereo audio power amplifier and related circuitry. Both of these are disabled for its operation on the NB2DSK01, with the relevant control signals tied to ground.

30 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

The stereo amplifier in the output stage of the device is formed by wiring two pairs of operational amplifiers into a 'bridged' configuration. The result is stereo differential output – Left Out +/- and Right Out +/-. If headphones are connected to the NB2DSK01 (see next section) the LM4849's headphone sense input is driven High, causing the bridged output to effectively be muted – turning off the amplifiers driving the positive signals of the Left and Right channel differential outputs. In this case, the device is placed into single-ended output mode. Both bridged and single-ended outputs can be adjusted in terms of volume – the DC volume control stage of the LM4849 implemented prior to the output amplifier stage. Volume control is made possible through a dual gang (2x5K) potentiometer. Dual gang has been used to enhance mechanical stability on the board. Left and Right line output signals are also provided. These are the outputs of the input operational amplifiers of the device, which in turn provide the inputs to the device's internal volume control Figure 51. DC volume control. stage. As such, these line output signals are not volume-adjustable.

Sound output The line outputs (LLOUT, RLOUT) are made available at a 3.5mm stereo audio jack. This allows you to connect, for example, your own powered speakers (the line out signals are the outputs of the LM4849's input operational amplifiers, which can drive loads greater than 1kΩ). The negative signals of the stereo differential outputs (LOUT-, ROUT-) are wired to an additional 3.5mm jack, used for connecting headphones to the NB2DSK01 motherboard.

Desktop Stereo Speaker Assembly The differential stereo outputs (LOUT-, LOUT+ / ROUT-, ROUT+) and the DC Figure 52. Audio output jacks. volume control signal are wired to a 16-pin connector, on the solder side of the motherboard. The Desktop NanoBoard NB2DSK01 comes with a separate stereo speaker board – the Desktop Stereo Speaker Assembly NB2DSK-SPK01. This board features 4Ω speakers and comes already affixed to the motherboard by way of this 16-pin Figure 53. Connector socket for Desktop Stereo speaker board connector. Speaker Assembly. In addition to the audio-based signals, the connector provides two SPI buses (the associated signals of which are: LED_DIN1, LED_SCK1, LED_CS1 and LED_DIN2, LED_SCK2, LED_CS2) to the speaker assembly, used to control RGB LED drivers. A 1-Wire bus signal is also provided – AUD_1WIRE – which is routed from the NanoTalk Controller to pin 14 of the connector. This provides a path with which to interrogate the 1-Wire ID device located on the speaker board. This connector also provides 3.3V, 5V, audio ground and power ground signals.

Figure 54. Desktop Stereo Speaker Assembly NB2DSK-SPK01. Note: Should you wish to connect your own external speakers via the 'LINE OUT' jack, you will need to turn the volume control pot all the way down, to effectively mute the sound from the NB2DSK-SPK01's stereo speakers. For more information on the Desktop Stereo Speaker Assembly, refer to the document TR0172 Technical Reference for Altium's Desktop Stereo Speaker Assembly NB2DSK-SPK01.

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Location on board The following audio jack connectors are located on the solder side of the board, between the parallel port connector and the RS- 232 port: • 'MICROPHONE' jack – designated J11 and colored Pink. • 'LINE IN' jack – designated J10 and colored Black. • 'LINE OUT' jack – designated J12 and colored Green. • 'HEADPHONES' jack – designated J13 and colored Blue. The LM4849 device (designated U17) and analog mixer circuitry are located on the solder side of the board, directly below these four audio jacks. The MAX9812L device (designated U18) is located on the solder side of the board, below the 'MICROPHONE' jack. The 'AUDIO TEST' jack (designated J14 and colored Black) is also on the solder side of the board, directly above the 'SYSTEM JTAG' header. The 16-pin socket for connection of the Desktop Stereo Speaker Assembly (designated J15 and labeled 'TO NB2DSK-SPK01') is located on the solder side of the board. The DC volume control (designated VR2) is also located on the solder side of the board, next to the SD Card reader. The test points made available for the Left (TP13) and Right (TP14) stages of the analog mixer are located on the component side of the board, below the labeling for the 'MICROPHONE' audio jack. Figure 55. Low-power microphone amplifier (U18). Schematic reference The audio circuitry can be found on the following sheets of the motherboard schematics: • Sheet 65 (AUDIO_AMP_NB2A.SchDoc, entitled AUDIO SUB-SYSTEM) • Sheet 66 (AUDIO_AMP_LM4849.SchDoc, entitled AUDIO AMP & MIXER LM4849) • Sheet 67 (AUDIO_AMP_MAX9812L.SchDoc, entitled Microphone Pre-Amplifier) • Sheet 68 (CON_AUDIO_AC99.SchDoc, entitled AUDIO AC99 Interface) • Sheet 69 (NB2_EXTEND_A.SchDoc, entitled NB2-Extender A Interface) • Sheet 70 (CON_NB2_EXTEND_A16.SchDoc, entitled NB2-Extender A 16-Pin Header).

Further device information For more information on the LM4849 device, refer to the datasheet (LM4849.pdf) available at www.national.com. For more information on the MAX9812L device, refer to the datasheet (MAX9812-MAX9813L.pdf) available at www.maxim- ic.com. User Board headers The NB2DSK01 includes two JTAG extender headers for connection of user boards, such as third party development boards or production prototype boards. These 10-pin headers – designated HDR1 and HDR2 – facilitate the inclusion of user boards into the Hard and Soft JTAG chains, for design download and debugging from within the Altium Designer software. The presence of a user board is determined by the signal level on pin 10 of a header. If this is Low the NanoTalk Controller will route both Figure 56. User Board headers. the Hard and Soft JTAG chains via the header. Note: If the user board does not support the Soft JTAG chain then connect pin 5 (TDI_SOFT) to pin 6 (TDO_SOFT). If this is not done, the Soft JTAG chain will effectively be broken at the header and no soft devices (processors, virtual instruments) will be 'seen' by the system. Alternatively, either header can be excluded from the Soft JTAG chain directly from the firmware-driven GUI on the TFT LCD panel. For more information, see the section Bypassing JTAG devices, later in this document.

32 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Location on board The two headers, labeled 'User Board A' (HDR1) and 'User Board B' (HDR2) respectively, are located on the solder side of the board, to the left of the SD card reader.

Schematic Reference The User Board JTAG circuitry can be found on the following sheets of the motherboard schematics: • Sheet 26 (JTAG_ALTIUM_AUTO.SchDoc, entitled Auto-Detect JTAG Circuit) • Sheet 27 (CON_USERJTAG_10WBOXHDRRAM.SchDoc, entitled User-Board JTAG Header).

Generic JTAG device support If a user board contains a physical device that is not supported by the system, the device will appear in the Hard Devices chain of the Devices view (View » Devices View) as a Generic JTAG Device. In this case no specific Nexus driver exists for the device (no .NEX file in the \System folder of the installation). To get the system to drive the Hard JTAG chain containing such a device, you will need to attach a Boundary Scan Description Language (BSDL) file for the specific device you are using. Such files can be obtained from the relevant Vendor website. Once attached, the system will Figure 57. Generic JTAG use the information in the file – including the device's ID Code and Instruction Register Length – to device detected in the Hard Devices chain. correctly configure the Hard JTAG chain. A BSDL file is attached to a Generic JTAG Device by right-clicking on the icon for the device, in the Hard Devices chain of the Devices view, and choosing the Configure JTAG ID Mapping command. The Generic JTAG Device dialog will appear (Figure 58).

Figure 58. Attaching a BSDL file to a generic JTAG device. Simply click the Add button in the BSDL File Links region of the dialog – the entry 'enter BSDL filename' will appear in the list. Either type the filename directly or click the folder icon at the right of the field to navigate to the required file. By default, the path is set to the \Library\BSDL\Generic folder of the installation. BSDL files should be placed in this folder. By including the standard BSDL file supplied with each JTAG-compliant device, you have access to the pins on every JTAG device in your design, through the real-time JTAG Viewer panel. Access to this panel is made via the Instrument Rack – Hard Devices panel (double-click on the icon for the device in the Hard Devices chain of the Devices view to bring up this panel). Simply click on the JTAG Viewer Panel button and then enable the Live Update option once the JTAG Viewer panel appears (Figure 59).

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Figure 59. Monitoring device pins in real time using the JTAG Viewer panel. Where high-density component packaging makes physical probing of device pins impossible, the JTAG Viewer panel facilitates physical design debugging, 'virtual style'. The system can even handle the situation where a BSDL file is not available for a device. Simply set the correct instruction length for such a device (in the Generic JTAG Device dialog) and the JTAG system can continue to communicate to other devices in the chain. Without a BSDL file you will, however, not be able to interrogate the state of pins for the device using the JTAG Viewer panel. For more information on the JTAG Viewer panel, or any other panel in Altium Designer, press F1 when the cursor is over the (focused) panel. Debug headers A total of 16 spare I/O pins on the NanoTalk Controller FPGA are brought out to two 10-pin headers, 8 wired to each (pins 1-8). Pin 9 of each header is tied to ground. Pin 10 is connected to the motherboard's 5V supply, via a 350mA fuse and 3A/40V Schottky diode. These headers – and the I/O signals they convey – are reserved and not available for general use.

Location on board The two headers (designated DH1 and DH2 respectively) are located on the solder side, at the left- hand edge of the board. The 350mA fuse (designated F3) and Schottky diode (designated D9) associated with debug header DH1 are located to the right of the header itself. The 350mA fuse (designated F4) and Schottky diode (designated D10) associated with debug header DH2 are located above the header itself.

Schematic reference The debug header circuitry can be found on Sheet 43 (CON_DEBUG_10WBOXHDRRAM.SchDoc, entitled 8-Way Debug Header) of the motherboard schematics.

Figure 60. Reserved debug headers.

34 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

SPI Real-Time Clock The current date and time are made available to the NanoTalk Controller through the provision of a low-voltage, SPI Real-Time Clock (RTC) device – a DS1391U- 33, from Maxim. The device provides information in terms of: Year, month, day, hours, minutes, and seconds. The calendar automatically adjusts for months with fewer than 31 days and includes leap-year correction. The device operates from the NB2DSK01's 3.3V power supply, but also has a battery backup, courtesy of a 3V lithium cell (CR2032). An associated test point (labeled 'VBAT' and designated TP15) allows the cell's voltage level to be Figure 61. RTC (U2), external crystal (Y1) and verified. related circuitry. The primary power supply (3.3V) is internally monitored. Should the supply fail and fall below a threshold level – typically 2.88V – the device will switch to using the battery backup. Failure of the primary power supply results in the (active Low) Reset output being asserted, to flag the condition to the NanoTalk Controller. This signal will remain asserted until the primary power is restored, becoming deasserted after a delay of typically 160ms. The device uses an external 32.768kHz crystal to provide the input to its internal oscillator circuitry. A test point (TP2) is supplied for verification of the generated frequency. The NanoTalk Controller communicates with the RTC device over the SPI bus, with the RTC being a slave SPI device.

Location on board The DS1391 device (designated U2) and the 32.768kHz crystal (designated Y1) are both located on the solder side of the board. The 3V lithium battery is located in a cell holder (designated BT1), which is located on the component side of the board, directly below the 6-way mini- DIN connector used to provide the PS/2 Mouse port. The test point for the 3V supply (TP15) is located as part of the array of test points covering power supply voltages on the board, directly below the power connectors. The test point for the 32.768kHz crystal ( ) is located to the left of the TP2 Figure 62. Lithium backup power cell (3V). battery cell holder.

Schematic reference The RTC circuitry can be found on the following sheets of the motherboard schematics: • Sheet 20 (CLK_DS1391U_RTC.SchDoc, entitled SPI Real Time Clock) • Sheet 21 (CON_BATT_COIN.SchDoc, entitled Lithium Battery Holder – CR2032).

Further device information For more information on the DS1391, refer to the datasheet (DS1390-DS1393.pdf) available at www.maxim-ic.com. SD card reader The Secure Digital (SD) memory card is among a host of such cards available in today's world of storage-hungry devices, such as PDAs and digital cameras. The NB2DSK01 provides a reader for this type of memory card, by way of a DM1B- DSF-PEJ connector (HRS6090003-5), from Hirose. The connector features a push-in/push-out ejection mechanism, locking the SD card firmly in place. The connector provides Card Detection and Write Protection switches, to flag whether a card has been inserted, and the write status of that card. Both switches are commoned to the NB2DSK01's 3.3V power supply. Both switches are normally open (when no card is inserted). When a card is inserted: • The Card Detection switch will close.

• The Write Protection switch will close only if the SD card is enabled for writing Figure 63. Secure Digital (SD) memory card to. If the card's write protect tab is in the 'Locked' position (typically down) the reader. card is Read Only and the Write Protection switch will remain open.

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Switch closure will result in a logical '1' being sent to the NanoTalk Controller. The NanoTalk Controller provides clock and command signals to the SD card, as well as reading/writing data. From a user perspective, an SD card inserted into the motherboard's reader can be used to effectively 'boot' the daughter board FPGA device with a programming file stored on the card. Navigation of card contents and selection/download of a programming file is carried out through interaction with the TFT LCD panel. For more information, see the section Direct interaction with the Desktop NanoBoard NB2DSK01, later in this document.

Location on board The SD card reader, labeled 'SD/Multimedia Card' and designated J8 is located on the solder side of the board, next to the DC volume control for the board's audio system.

Schematic reference The SD card reader circuitry can be found on Sheet 42 (CON_SD_HIROSE_609_0003_5.SchDoc, entitled SD-CARD HIROSE 609_0003_5) of the motherboard schematics.

Further device information For more information on the DM1B-DSF-PEJ connector, refer to the datasheet (e60900048.pdf) available at www.hirose- connectors.com. Home/NanoBoard Reset button The NB2DSK01 provides a push button switch that is wired to an I/O pin of the NanoTalk Controller FPGA device. Its purpose is three-fold: • Press and release quickly to take control of the TFT LCD panel from the daughter board FPGA and present the Home screen of the firmware-driven GUI. • Press & hold for more than 5 seconds to provide a reset signal to the NanoTalk Controller, used to reset the TSK3000A processor on which the firmware is running. • While the firmware has control of the TFT LCD panel, press & hold for more than 5 seconds while also holding generic user switches SW1, SW3 and SW5, to access a screen to reset GUI Figure 64. NanoBoard Reset options to default settings. button. The switch is of type SPNO – Single Pole Normally Open. In the open position, it provides a logical High signal to the NanoTalk Controller, changing to logical Low when pressed. For more information on the TFT LCD panel and the firmware-driven GUI, see the section Direct interaction with the Desktop NanoBoard NB2DSK01, later in this document.

Location on board The switch (designated SW9) is located on the component side of the board, to the top-right of the TFT LCD panel.

Schematic reference The switch circuitry can be found on Sheet 57 (HOST_RESET_SPNO.SchDoc, entitled Push Button SPNO Switch) of the motherboard schematics. Board ID memory Board identification is handled courtesy of a DS2406 device (from Maxim). The DS2406 is a 1-Wire compatible device, primarily used to contain a code with which to identify the motherboard. It is also used to contain additional information such as revision, release date, and so on. The NanoTalk Controller interrogates this device over a single wire, the associated signal of which is ONE_WIRE_NBID. The DS2406 supports half-duplex communication at a rate of up to 16.3kbits/s. Although power for the device is sourced over the same single wire as the data itself – courtesy of a Figure 65. 1-Wire memory used to parasitic capacitor which charges when the 1-Wire bus signal line is High – the device is also contain the ident code for the fed from the NB2DSK01's 3.3V supply, to ensure continuous power. board. Similar devices on all peripheral boards, 3-connector daughter boards and the Desktop Speaker Board Assembly NB2DSK-SPK01, allow the NanoTalk Controller to detect which specific boards are available to the system.

36 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Location on board The DS2406 device (designated U19) is located on the solder side of the board, to the left of the 16-pin connector socket for the Desktop Stereo Speaker Assembly.

Schematic reference The 1-Wire memory device can be found on Sheet 71 (1WB_DS2406_PROTECTED.SchDoc, entitled Protected 1-Wire EEPROM) of the motherboard schematics.

Further device information For more information on the DS2406 device, refer to the datasheet (DS2406.pdf) available at www.maxim-ic.com.

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Resources accessible from an FPGA design The NB2DSK01 motherboard has a variety of resources individually wired to target daughter board FPGA I/O pins. These allow a wide variety of embedded examples to be executed on the NB2DSK01, in addition to providing a base for developing new applications. The following sections detail these resources. Bear in mind that additional resources – resident on plug-in peripheral boards or the daughter board itself – are also available for use in a design. In the case of peripheral boards, the relevant I/O and control signals are wired from the resource (via the peripheral board connector on the NB2DSK01 motherboard) to pins of the daughter board connector(s), and ultimately on to I/O pins of the FPGA device itself. For more information on the range of peripheral boards and daughter boards available and the resources they offer, go to www.altium.com/nanoboard/resources. Accessing resources from an FPGA design Before diving into the wealth of FPGA-accessible resources on the NB2DSK01 motherboard, it is worth taking time to look at how this access is made possible. Normally you would use ports to connect from the nets in a design to the pins on the FPGA. However, since the connectivity from the FPGA to the components on the NB2DSK01 is fixed by the routing, there is no need to place ports and then define the net-to-pin mapping. Instead, Altium Designer provides special components that can be placed – allowing the NB2DSK01 resources to be easily incorporated in designs. These components, which can be thought of as design interface components and are commonly referred to as port components, are available in the FPGA NB2DSK01 Port-Plugin integrated library (\Library\Fpga\FPGA NB2DSK01 Port-Plugin.IntLib). The port components automatically establish connectivity between the resource and FPGA IO pins, allowing the same design to be built for different FPGA devices from different manufacturers. They are placed on the top sheet of the FPGA design project (*.PrjFpg), instead of ports. They are recognized as being external to the FPGA design by the presence of the parameter: Figure 66. Accessing port components. PortComponent = True They are automatically converted to ports during synthesis.

The library contains design interface components for all design-accessible resources located on the NB2DSK01 motherboard.

Figure 67. Example port components.

Converting a port component to standard ports It can often be clearer to represent the signal lines to the physical pins of the FPGA device using standard ports, rather than the port components. Altium Designer provides a conversion command to quickly change a port component to standard ports. From the schematic document, this command can be accessed by: • Choosing Tools » Convert » Convert Part To Ports from the main menus and clicking on the required port component you wish to convert. • Right-clicking over the required port component and choosing Part Actions » Convert Part To Ports from the menu. After launching the command (and choosing the port component if applicable), the component will be converted into electrically equivalent ports. Figure 68. Converted port components.

38 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

System Clocks The NB2DSK01 has an SPI-based system clock generator (an ICS307-02 device) that provides a fixed 20MHz clock and a user-programmable clock providing frequencies from 6 to 200 MHz. Both clocks are made available to the NanoTalk Controller (Xilinx Spartan-3 FPGA) and the daughter board FPGA, connected to FPGA GCLK pins. The user-programmable clock has a default frequency of 50 MHz. It can be programmed in one of three ways: • From a PC with Altium Designer using the Instrument panel for the NanoTalk Controller. This allows frequency presets to common values, as well as any frequency possible with the ICS clock device. • Directly from the TFT LCD panel, through the firmware-driven GUI. • By the daughter board FPGA application at run time, via the NanoTalk Controller-to- Figure 69. NanoBoard clock circuitry daughter board SPI interconnect. (fixed and programmable clocks).

Location on board The ICS307-02 device (designated U3) is located on the solder side of the board, along with the 20MHz surface mount crystal (designated Y2) which is used to provide the fixed reference frequency. In addition, two test points are made available on the component side of the board for verification of the programmable clock frequency (labeled 'FPGA CLK' and designated TP4) and fixed 20MHz frequency (labeled 'REF CLK' and designated TP3) respectively. These are located beneath the 20K trim pot (VR1) used to provide contrast control for the TFT LCD panel.

Schematic reference The system clock circuitry can be found on Sheet 35 (CLK_ICS307-02_PLL.SchDoc, entitled Programmable SPI Clock) of the motherboard schematics.

Design interface component Figure 70. Fixed and programmable Table 1 summarizes the available design interface components that can be placed from the FPGA clock test points. NB2DSK01 Port-Plugin.IntLib, to access these resources.

Table 1. System clock port-plugin components.

Component Symbol Component Name Description

CLOCK_BOARD Place this component to bring the NB2DSK01's programmable system clock signal into your FPGA design.

CLOCK_REFERENCE Place this component to bring the NB2DSK01's fixed 20MHz system clock signal into your FPGA design.

CLOCK_SUPPLY Place this component to bring both fixed and programmable system clock signals into your FPGA design, using a single port component. The programmable clock signal (CLK_BOARD) will typically be used as the CLK_I input to devices in a design. Some peripheral devices used within a design may require input clocks of a particular frequency. This frequency is typically achieved by passing one of the system clocks through one or more clock divider devices. For more information on the available fixed and programmable clock divider components available for use in an FPGA design, refer to the Functional Classes – Clock Divider section of the CR0118 FPGA Generic Library Guide.

Further device information For more information on the programmable ICS307-02 device, refer to the datasheet (ics3070102[1].pdf) available at www.idt.com.

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Serial SPI Flash memory The NB2DSK01 provides serial Flash memory in the form of two M25P80 8-Mbit devices (from STMicroelectronics). These devices support a serial data rate of 25MHz. The M25P80 is an SPI-compatible device, with both devices accessed through the NB2DSK01's SPI Controller, which itself resides within the Xilinx Spartan-3 NanoTalk Controller. The function of the two devices (designated U20 and U21) can be summarized as follows: • U20 – used as Embedded memory. This device is used to provide embedded memory functionality within an FPGA design, enabling you to load and store an embedded software file that will be used when the target design is running. Figure 71. Serial Flash memory. • U21 – used as either Embedded memory or Boot memory. This device can be used from within an FPGA design, as described above. It can also be used to store the programming file required for implementing a design within the daughter board FPGA. This gives you the ability to 'bootstrap' the FPGA device upon powering-up the NB2DSK01. The SPI Flash memory devices can be erased and programmed from within Altium Designer, using the Instrument panel for the NanoTalk Controller. For more information on using an SPI Flash memory device for embedded purposes, refer to the application note AP0162 Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01. For more information on bootstrapping the daughter board FPGA with a programming file stored in serial Flash memory, see the section Booting from SPI Flash memory, later in this document.

Location on board The two M25P80 devices (U20 and U21) are located on the component side of the board, above the Xilinx Spartan-3 NanoTalk Controller device (U5). These devices, along with all other NB2DSK01 memories, the NanoTalk Controller and the configuration PROM, are covered by the TFT LCD panel.

Schematic reference The SPI Flash memory devices can be found on Sheet 40 (FLASHSPI_M25PX0.SchDoc, entitled Dual Serial Flash Memory) of the motherboard schematics.

Design interface component Table 2 summarizes the available design interface component that can be placed from the FPGA NB2DSK01 Port- Plugin.IntLib, to access and use the SPI Flash memory devices.

Table 2. SPI Flash memory port-plugin component.

Component Symbol Component Name Description

SERIALFMEMORY Place this component to access the signals relating to the SPI Flash memory device used to facilitate embedded memory.

For information on available peripheral devices – used to provide the control interface between a processor in the design and the NB2DSK01 resource – go to www.altium.com/nanoboard/resources. If your design involves communications with multiple SPI-based devices, you will need to place the generic SPI_BUS device. For more information, see the section Using multiple SPI/I2C devices in a design, later in this document.

Further device information For more information on the M25P80 device, refer to the datasheet (m25p80.pdf) available at www.st.com.

40 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

RS-232 Serial Port The NB2DSK01 provides a PC-style RS-232 serial interface. A DB-9 Male connector is used to provide a serial port, wired as a DCE (Data Communication Equipment), in accordance with the EIA-574 standard. Connection to a host PC (wired as a DTE (Data Terminal Equipment)) can be achieved using a null modem serial cable. Signal level translation – CMOS to RS-232 and vice-versa – is provided using a MAX3232EUE RS-232 Transceiver device (from Maxim). This device has 2 receivers and 2 drivers, the use of which is summarized as follows: • Receivers – used for the RXD (pin 2) and CTS (pin 8) signals, received from the host PC over the RS-232 interface and subsequently wired to pins of the daughter board FPGA. • Drivers – used for the TXD (pin 3) and RTS (pin 7) signals, sourced from the Figure 72. RS-232 serial interface port. design running in the daughter board FPGA device for transmission to the PC over the RS-232 interface. The MAX3232 is powered from the NB2DSK01's 3.3V supply and incorporates a dual charge The MAX3232 is compatible, both pump, requiring four 0.1uF external charge pump capacitors. RS-232 output levels are in terms of pinout and functionality, maintained at a guaranteed data rate of 120kbps. with the industry standard MAX232 device. Note: The incoming Data Terminal Ready signal (DTR) – which arrives on pin 4 of the connector – is wired, on the motherboard, directly to the outgoing pins for the Data Set Ready (DSR) and Data Carrier Detect (DCD) signals (pins 6 and 1 respectively). The Ring Indicator signal (RI) arriving on pin 9 of the connector, is not used.

Location on board The MAX3232 device (designated U13) and associated external capacitors are located on the solder side of the board. The DB9M (Male) connector (designated J9) is located on the component side of the board, to the immediate left of the CAN interface port.

Schematic reference The RS-232 interface circuitry can be found on the following sheets of the motherboard schematics: • Sheet 50 (RS232_MAX3232.SchDoc, entitled RS232COMMS_1) • Sheet 51 (CON_RS232DCE_DB9.SchDoc, entitled RS232-DCE DB9).

Design interface component Figure 73. MAX3232 device and related circuitry. Table 3 summarizes the available design interface component that can be placed from the FPGA NB2DSK01 Port-Plugin.IntLib, to access and use the RS-232 interface.

Table 3. RS-232 port-plugin component.

Component Symbol Component Name Description

RS232CNTR Place this component to interface to the MAX3232 device and subsequent RS-232 serial port.

For information on available peripheral devices – used to provide the control interface between a processor in the design and the NB2DSK01 resource – go to www.altium.com/nanoboard/resources.

Further device information For more information on the MAX3232 device, refer to the associated datasheet (MAX3222-MAX3241.pdf) available at www.maxim-ic.com.

TR0143 (v2.0) May 26, 2008 41 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

CAN Port The NB2DSK01 provides a standard CAN (Controller Area Network) interface. The interface provides the ability to send and receive data over a bus conforming to the CAN 2.0B specification. A DB9M connector is used to provide the connection to the external CAN bus. Providing the interface between a CAN Controller – which is placed within the FPGA design – and the physical CAN bus itself, is a high-speed MAX3051EKA-T CAN Transceiver device (from Maxim). This device essentially provides signal translation – from digital to differential voltage (suitable for transmission over the CAN bus) and vice-versa. Figure 74. CAN interface port. On the design side, transmit (TXD) and receive (RXD) signals are wired between the MAX3051 and two pins of the daughter board FPGA device. On the CAN bus side, the differential signals CANH and CANL are wired to the DB9M connector. CANH and CANL reflect the state of the TXD input to the MAX3051 and hence dictate the state of the CAN bus (from the NB2DSK01's perspective): • Dominant – the differential voltage (CANH - CANL) is greater than an internal threshold voltage (0.75V). This corresponds to the TXD input being Low. • Recessive - the differential voltage (CANH - CANL) is lower than an internal threshold voltage (0.75V). This corresponds to the TXD input being High. The RXD output signal sent back to the daughter board FPGA is simply the converse – a reflection of the current state of the CAN bus. RXD will be Low if the bus is in a Dominant state and High if in a Recessive state. The MAX3051 is powered from the NB2DSK01's 3.3V supply and can operate at speeds up to 1Mbps. Normal operation of the device, as used on the NB2DSK01, runs between two modes: • Slope Control (default) – the slope of the signal transitions on the CANH and CANL lines are controlled (limited) by an external 15kΩ resistor, helping to further reduce electromagnetic interference (EMI). The maximum operating speed in this mode is 800kbps. Unshielded twisted-pair cabling can be used for the CAN Bus when operating in this mode. • High Speed – the slope of the signal transitions on the CANH and CANL lines are not limited by an external resistor, giving faster output rise and fall times to support high speed CAN bus data rates (up to 1Mbps). In this mode, EMI problems can be avoided by use of shielded twisted-pair cable for the CAN Bus. Two configurable jumper headers – designated JP2 and JP3 – are provided to enable further configuration of the CAN interface, such as enabling 'High Speed' mode, in accordance with design requirements. Tables 4 and 5 summarize the effect of jumper placement on these headers.

Table 4. JP3 header jumper placement.

Jumper Position Description

1-2 Put a jumper on these pins to configure the DB9M connector in accordance with the CAN in Automation Draft Standard 102 (CiA DS102) for two-wire differential transmission. The action of the jumper is to connect pin 9 of the connector to +5V, via a 350mA fuse. All other pins of the connector are already connected as required: • pin 2 to CANL • pin 7 to CANH • pins 3 and 6 connected to GND • pins 10 and 11 connected to SHIELD • pins 1, 4, 5 and 8 unconnected.

2-4 and 1-3 Put jumpers on these pins to configure the DB9M connector to operate in the same way as the CAN port for the NanoBoard-NB1. The action of the jumper on pins 2-4 is to connect pin 4 of the connector to +5V, via a 350mA fuse. The action of the jumper on pins 1-3 is to connect pin 9 of the connector to GND. All other pins of the connector on the NB2DSK01 are as per the NB1, with the exception of the following: • pins 3 and 6 – unconnected on the NB1 and connected to GND on the NB2DSK01 • pins 10 and 11 – connected to GND on the NB1 and SHIELD on the NB2DSK01.

42 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Table 5. JP2 header jumper placement.

Jumper Position Description

1-2 Put a jumper on these pins to place the MAX3051 CAN Transceiver device in 'High Speed' mode. With the jumper in place, slope control is essentially disabled, as the external 15kΩ resistor providing the control is by-passed.

3-4 Put a jumper on these pins to apply a load of 120Ω across the CANH and CANL differential output lines. This resistance is used to unload the open-collector transceiver drivers, as well as to prevent signal reflections (other nodes on the CAN bus will have similar load resistances across their differential output lines). This jumper is inserted by default.

Location on board The MAX3051 device (designated U8) and related resistors/capacitors are located on the solder side of the board. The DB9M (Male) connector (designated J7) is located on the component side of the board, to the immediate right of the RS-232 interface port. The two configurable jumper headers (JP2 and JP3) are also located on the component side, directly below the DB9M connector. The 350mA fuse (designated F2) is located on the solder side of the board, to the bottom- right of the MAX3051 device.

Schematic reference The CAN interface circuitry can be found on the following sheets of the motherboard schematics: • Sheet 48 (CAN_MAX3051.SchDoc, entitled CAN Transceiver MAX3051) Figure 75. MAX3051 device and related circuitry. • Sheet 49 (CON_CAN_DB9M.SchDoc, entitled CAN Connector DB9 Male).

Design interface component Table 6 summarizes the available design interface component that can be placed from the FPGA NB2DSK01 Port- Plugin.IntLib, to access and use the CAN interface.

Table 6. CAN port-plugin component.

Component Symbol Component Name Description

CANCNTR Place this component to interface to the MAX3051 device and subsequent CAN port.

For information on available peripheral devices – used to provide the control interface between a processor in the design and the NB2DSK01 resource – go to www.altium.com/nanoboard/resources.

Further device information For more information on the MAX3051 device, refer to the datasheet (MAX3051.pdf) available at www.maxim-ic.com.

TR0143 (v2.0) May 26, 2008 43 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

PS/2 Mouse and Keyboard Ports The NB2DSK01 provides two standard PS/2 interfaces, for connection of an IBM PS/2-compatible mouse and keyboard. Each port is implemented using a 6-way mini-DIN (Female) connector and is directly connected to two daughter board FPGA I/O pins, providing CLOCK and bidirectional DATA lines respectively.

Location on board The 6-way mini-DIN connectors used to provide the PS/2 Mouse port (designated with green colored jack) and the PS/2 Keyboard port J6 Figure 76. PS/2 interface ports (Keyboard and Mouse). (designated J5 with purple colored jack) are located on the component side of the board, between the USB interface and the 5V power connectors.

Schematic reference The PS/2 interface circuitry can be found on the following sheets of the motherboard schematics: • Sheet 52 (PC_PS2.SchDoc, entitled PC PS2) • Sheet 53 (CON_PS2KEYBOARD_MINIDIN6F.SchDoc, entitled PS2 Keyboard Connector) • Sheet 54 (CON_PS2MOUSE_MINIDIN6F.SchDoc, entitled PS2 Mouse Connector).

Design interface component Table 7 summarizes the available design interface components that can be placed from the FPGA NB2DSK01 Port- Plugin.IntLib, to access and use the on-board PS/2 Mouse and PS/2 Keyboard ports, respectively.

Table 7. PS/2 port-plugin components.

Component Symbol Component Name Description

PS2A Place this component to interface to the PS/2 Mouse port.

PS2B Place this component to interface to the PS/2 Keyboard port.

For information on available peripheral devices – used to provide the control interface between a processor in the design and the NB2DSK01 resource – go to www.altium.com/nanoboard/resources. ADC/DAC/I2C The NB2DSK01 is equipped with general purpose analog-to-digital and digital-to-analog converters, both interfaced to the daughter board FPGA using the I2C bus protocol. Analog-to-digital conversion is provided by a 4-channel, 8-bit MAX1037EKA-T ADC device (from Maxim). Digital-to-analog conversion is provided by a 4-channel, 10-bit MAX5841MEUB DAC device (also from Maxim). Both devices are powered from an analog 3.3V power supply and provide a 400kHz I2C-compatible 2-wire serial interface. Figure 77. ADC/DAC and I2C interface. External analog signals destined for the daughter board FPGA are delivered to the NB2DSK01 through a 10-way screw terminal block. This terminal block also provides the four converted analog output signals, as well as the filtered 3.3V analog supply (VCCA) and analog ground (ADC_GND). These signals are summarized in Figure 78.

VCCA AIN3/ Analog AOUT0 AOUT1 AOUT2 AOUT3 AIN0 AIN1 AIN2 (3.3V) REF GND Figure 78. ADC/DAC-related screw terminal header.

44 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Note: The fourth analog input pin to the MAX1037 device has dual functionality. This pin can be programmed either to receive a fourth analog channel input (AIN3) or to output a reference voltage (REF) of 2.048V. These same analog signals are also made available from a 14-pin extension header. In addition, this header provides the I2C interface signals, SDA and SCL, as well as the NB2DSK01's 5V power supply and power ground. Table 8 summarizes the addresses that must be used to write and read the ADC and DAC devices (I2C slaves) over the I2C bus. Each address is made up of a 7-bit actual address (A6..A0) for the device and an additional bit (LSB) to distinguish whether the I2C master (an I2C Controller within the FPGA design) is writing to ('0'), or reading from ('1') that device.

Table 8. ADC/DAC addressing.

Device I2C Write Address I2C Read Address

MAX1037 ADC C8h (11001000) C9h (11001001)

MAX5841 DAC BAh (10111010) BBh (10111011)

Note: For the MAX1037 device, the actual 7-bit address is factory programmed to always be 1100100. For the MAX5841 device, bits A6..A1 are factory programmed to always be 101110. Bit A0 is determined by an additional input – ADD. This input has been tied to VCCA, thereby giving a logical '1' for this bit. The four analog input channels of the MAX1037 ADC (and similarly the 4 digital input channels of the MAX5841 DAC) are multiplexed – selectable by application software via the I2C connection. Refer to the respective datasheets for the devices (see Further device information) for details of the Configuration/Setup byte (MAX1037) and Command byte (MAX5841) definitions. Digital-to-analog conversion in the MAX5841 device is achieved using 10-bit resistor string DACs. The input supply reference to the device, used for each channel's DAC, is user-selectable via a configurable jumper header – designated JP1. Table 9 summarizes the effect of jumper placement on this header.

Table 9. JP1 header jumper placement.

Jumper Position Description

1-2 Put a jumper on these pins to provide a precision 2.048V supply voltage as the input to the MAX5841 device's REF input. This voltage is sourced from the MAX1037 device's AIN3/REF pin. The reference voltage and state of this pin is configured using the select bits S2..S0 of the Setup byte – written when configuring the ADC. To configure this pin as a reference output (outputting the device's internal reference voltage), these bits must be set to 11X respectively.

3-4 Put a jumper on these pins to provide the analog 3.3V supply voltage as the input to the MAX5841 device's REF input.

Location on board The MAX5841 device (designated U4) and the MAX1037 device (designated U1) are both located on the solder side of the board. The screw terminal block (designated TS1), the I2C/Analog extension header (designated HDR7) and the voltage reference configurable jumper header (JP1), are all located on the component side of the board – to the left of the User LEDs.

Schematic reference The ADC/DAC circuitry can be found on the following sheets of the Figure 79. MAX5841 (U4) and MAX1037 (U1) devices. motherboard schematics: • Sheet 60 (DAC+ADC_MAX5841+MAX1037.SchDoc, entitled 4-Ch I2C 10-Bit DAC & 8-Bit ADC) • Sheet 61 (ADC_MAX1037.SchDoc, entitled MAX1037 ADC) • Sheet 62 (DAC_MAX5841.SchDoc, entitled MAX5841 DAC) • Sheet 63 (CON_ADCDAC_SCRSTR10F.SchDoc, entitled ADC/DAC Screw Header) • Sheet 64 (CON_ADCDAC_HDR14M.SchDoc, entitled ADC/DAC Header).

Design interface component Table 10 summarizes the available design interface component that can be placed from the FPGA NB2DSK01 Port- Plugin.IntLib, to access and use the on-board ADC and DAC devices over an I2C bus.

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Table 10. ADC/DAC port-plugin component.

Component Symbol Component Name Description

ADCDAC_I2C Place this component to interface to the MAX5841 and MAX1037 devices.

For information on available peripheral devices – used to provide the control interface between a processor in the design and the NB2DSK01 resource – go to www.altium.com/nanoboard/resources. If your design involves communications with multiple I2C-compatible devices, you will need to place the generic I2C_BUS device. For more information, see the section Using multiple SPI/I2C devices in a design, later in this document.

Further device information For more information on the MAX5841 and MAX1037 devices, refer to the datasheets (MAX5841.pdf and MAX1036- MAX1039M.pdf respectively) available at www.maxim-ic.com. TFT LCD panel (with touch screen) The NB2DSK01 provides high quality color display through a Hitachi TX09D50VM1CAA TFT (Thin Film Transistor) LCD panel. The panel also features an analog resistive touch screen. From a user perspective, you can either output straightforward graphics to the panel, or provide a more sophisticated level of interaction involving input to your FPGA design from the touch screen. The NB2DSK01 motherboard utilizes the power of this display module to provide an interactive GUI with which to perform various board set-up functions – in essence a direct (and interactive) link with the firmware running within the NanoTalk Controller. For more information, see the section Direct interaction with the Desktop NanoBoard NB2DSK01, later in this document.

LCD display The 3.5" panel features a Transmissive Color TFT LCD, with a resolution of 240(W) by 320(H). The display is based on an active matrix and backlight for the panel is provided through six LEDs. Although capable of supporting 262144 colors (RGB, 6-bits parallel), the panel is fixed to use 16bpp display on the NB2DSK01, with bit 0 for both Red and Blue intensity inputs tied to GND. This results in a total of 65536 colors being available for display. Figure 80. TFT LCD panel with touch screen. The panel requires various power supply levels. In addition to the on-board 3.3V level used for internal logic, a further three voltage levels are produced by the NB2DSK01 (using voltage step-up converter and regulator devices) based on the board's regulated 5V input. These levels are -7.5V, 9V and 16.5V, and are used for purposes including Gate and Source Driver power, contrast control and generation of Gray-scale voltage levels. The panel connects to the NB2DSK01 motherboard through a 50-pin header. All display- based signals from I/O pins of the daughter board FPGA are routed through to this header, in addition to the required power supplies. A 20K linear trimming potentiometer is used to provide contrast control, fed from the 9V power supply.

Touch Screen control Control for the TFT LCD panel's touch screen is provided through an AD7843ARU Touch Screen Digitizer (from Analog Devices). This device is essentially a programmable 8-/12-bit ADC. Powered by the NB2DSK01's 3.3V supply, it is capable of throughput rates of 125kSPS when clocked at 2MHz. Input to the Digitizer is the four-wire analog output from the touch screen, which relates to the position touched on the screen. The reference voltage used for the device is the same as the power supply, i.e. 3.3V. This determines the analog input range to the converter. Figure 81. TFT LCD panel connection header (center), Touch Screen Digitizer (top) and contrast control pot (bottom).

46 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Communication between the daughter board FPGA/NanoTalk Controller and the Digitizer is performed over the SPI bus. From an FPGA design perspective, the following lists how the SPI interface signals from the daughter board FPGA are used: • The SPI_SEL line selects the Digitizer for access. The serial input/output registers are enabled and the ADC conversion process is started upon this signal being received by the Digitizer (active Low). • The SPI_DIN line is used to write to the Digitizer's control register. • The SPI_DOUT line is used to transmit the converted data to the daughter board FPGA device. • The SPI_CLK signal not only provides the clock source for the ADC conversion process, but also the serial clock for accessing the converted data. The Digitizer provides an interrupt signal, wired to an I/O pin of the daughter board FPGA. This The Desktop NanoBoard signal – TFT_IRQ – is sourced from the device's \PENIRQ output. This signal is kept normally High NB2DSK01 comes with a through use of an external pull-up resistance to the 3.3V power supply. When the touch screen is stylus for use with the TFT touched, the signal will be taken Low. The interrupt signal is used to alert a processor within the LCD panel. Use the stylus to FPGA design that the panel has been touched. The embedded code running on the processor can more efficiently interact with then enter a routine to send a control word to the Digitizer, and hence initiate conversion. the panel's touch screen. Two further signals are provided by the daughter board FPGA: • DAU_TFT_MUX – this signal is used to allow the daughter board to take 'control' of the TFT LCD panel. Tie this signal High so that your FPGA design has communication access to the panel. • DAU_TFT_BLIGHT – this signal is used to control the TFT LCD panel's backlight, from within the FPGA design. Tie this signal High to keep the panel's backlight lit.

Location on board The TFT LCD panel comes already affixed to the right-hand side of the NB2DSK01 motherboard. The 50-pin header (designated LCD1), into which it is connected, is located on the component side of the board, to the right of the FPGA daughter board connectors. The AD7843 device (designated U6) and 20K trim pot (designated VR1) are also located on the component side of the board, directly above and below the 50-pin header respectively. The power-related circuitry for the TFT LCD panel, including voltage regulator (designated U9) and step-up DC/DC converter (designated U11), is located on the solder side of the board.

Figure 82. TFT LCD panel power circuitry.

Schematic reference The TFT LCD panel interface circuitry can be found on the following sheets of the motherboard schematics: • Sheet 30 (TSC_AD7843.SchDoc, entitled TFT Touchscreen Interface) • Sheet 31 (CON_LCD_TX09D50VM1CAA.SchDoc, entitled TFT LCD Header). The additional power supplies generated for use by the TFT LCD panel can be found on the following sheets: • Sheet 3 (PSU_BZX84C7V5_-7V5.SchDoc, entitled PSU BZX84C7V5 -7V5) • Sheet 8 (PSU_LM317_9V0.SchDoc, entitled PSU LM317 9V0) • Sheet 9 (PSU_LM2704_16V5.SchDoc, entitled PSU LM2704 16V5).

Design interface component Table 11 summarizes the available design interface component that can be placed from the FPGA NB2DSK01 Port- Plugin.IntLib, to access and use the TFT LCD panel for purely graphical display purposes.

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Table 11. TFT LCD panel port-plugin component.

Component Symbol Component Name Description

TFT_LCD Place this component to interface to the TFT LCD panel, via the 50-pin interface header (LCD1).

Should you wish to utilize the panel's touch screen, you will need to place the relevant design interface component that allows access to, and communications with, the Touch Screen Digitizer, as summarized in Table 12.

Table 12. Touch Screen Digitizer port-plugin component.

Component Symbol Component Name Description

TOUCH_SCREEN_DIGITIZER Place this component to interface to the AD7843 device, over the SPI bus.

For information on available peripheral devices – used to provide the control interface between a processor in the design and the NB2DSK01 resource – go to www.altium.com/nanoboard/resources. If your design involves communications with multiple SPI-based devices, you will need to place the generic SPI_BUS device. For more information, see the section Using multiple SPI/I2C devices in a design, later in this document.

Further device information For more information on the TX09D50VM1CAA TFT LCD panel, refer to the datasheet (TX09D50VM1CAA[1].pdf) available at www.hitachi-displays-eu.com. For more information on the AD7843 device, refer to the datasheet (AD7843.pdf) available at www.analog.com. User DIP-switch The NB2DSK01 provides an 8-way DIP-switch, with each switch wired to a separate I/O pin of the daughter board FPGA device. This provides you with eight generic switchable signals for use in an FPGA design. The DIP-switch is wired as an active low device, which means setting a switch to the ON position generates a corresponding Low signal.

Location on board The DIP-switch (designated SW7) is located on the component side of the board, to the Figure 83. Switchable inputs provided immediate right of the User LEDs. courtesy of the 8-way DIP-switch. The eight switch signals arrive at the daughter board FPGA as signals DIP0 to DIP7. On the physical device, DIP7 is the signal associated with switch number 1, in the left-most position.

Schematic reference The DIP-switch circuitry can be found on Sheet 59 (SW_DIP8.SchDoc, entitled 8-Way DIP Switch) of the motherboard schematics.

Design interface component Table 13 summarizes the available design interface component that can be placed from the FPGA NB2DSK01 Port- Plugin.IntLib, to access and use the DIP-switch.

48 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Table 13. DIP-switch port-plugin component.

Component Symbol Component Name Description

DIPSWITCH Place this component to interface to the NB2DSK01's DIP-switch.

Although the eight signals arrive at the daughter board FPGA device on separate pins, the interface component provides an 8- bit bus input. Connection to the component's bus port depends on where in the design these signals are destined. If, for example, you wish to control port input to an 8-bit wide port peripheral, you would wire directly from the DIPSWITCH interface component to that port input. If, for example, you wanted to control 8 bits of a 32-bit data input, or if you wanted to use single switch signals for different device inputs, you would need to use an appropriate bus joiner device. For more information on the available bus joiner components available for use in an FPGA design, refer to the Functional Classes – Bus Joiner section of the CR0118 FPGA Generic Library Guide. User LEDs The NB2DSK01 provides a bank of eight Green LEDs, labeled 'USER LEDS'. Each LED is wired to, and driven from, a separate I/O pin of the daughter board FPGA device. The LEDs provide a visual output for signals in an FPGA design. The LED signals are active High – outputting a '1' on one of these lines will illuminate the corresponding LED.

Location on board The LEDs (designated LED9-LED16 and labeled '0' to '7' respectively) are located on the component side of the board, to the immediate left of the 8-way DIP-switch. Figure 84. Visual output through a bank of LED16 (labeled '7') is in the left-most position. eight user LEDs.

Schematic reference The LED circuitry can be found on Sheet 55 (LED_GREEN_0603x8.SchDoc, entitled 8-Way 0603 Green LED Array) of the motherboard schematics.

Design interface component Table 14 summarizes the available design interface component that can be placed from the FPGA NB2DSK01 Port- Plugin.IntLib, to access the User LEDs.

Table 14. User LEDs port-plugin component.

Component Symbol Component Name Description

LED Place this component to interface to the user LEDs.

Although the eight signals leave the daughter board FPGA device on separate pins, the interface component requires an 8-bit bus input. Connection to the component's bus port depends on where in the design these signals are sourced. If, for example, you wish to monitor port output from an 8-bit wide port peripheral, you would wire directly from that port output to the LED interface component. If, for example, you wanted to monitor 8 bits from a 32-bit data output, or if you wanted to bring single signals together from various device outputs, you would need to use an appropriate bus joiner device. For more information on the available bus joiner components available for use in an FPGA design, refer to the Functional Classes – Bus Joiner section of the CR0118 FPGA Generic Library Guide.

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User I/O headers The NB2DSK01 includes two I/O headers that allow user-defined hardware to be interfaced to the daughter board FPGA. These 20-pin headers – designated UH1 and UH2 – cater for a total of 36 daughter board FPGA I/O signals, 18 wired to each. Each header also supplies power and ground signals. The power supply level is user-selectable via an associated configurable Figure 85. Connect to off-board hardware through use of the jumper header – designated JP4 and JP5 respectively. Table 15 NB2DSK01's dedicated User I/O headers. summarizes the effect of jumper placement on these headers.

Table 15. JP4/JP5 header jumper placement.

Jumper Position Description

1-2 Put a jumper on these pins to provide the NB2DSK01's 5V supply.

3-4 Put a jumper on these pins to provide the NB2DSK01's 3.3V supply.

Take care to place only a single jumper on each of headers JP4 and JP5 – to select either 3.3V or 5V in each case. DO NOT put jumpers in both positions for a header simultaneously. The result will be elevation of the 3.3V line to 5V, causing damage to devices expecting a 3.3V supply. Current monitoring is also in place for the power lines selected.

Location on board The two headers, labeled 'User Header A' (UH1) and 'User Header B' (UH2) respectively, are located on the component side of the board, between the 'DAUGHTER BD TEST/RESET' button and the ADC/DAC. The two configurable jumper headers (JP4 and JP5) are also located on the component side, directly to the left of their respective user headers (UH1 and UH2).

Schematic reference The User I/O headers can be found on Sheet 47 (CON_USER_20WBOXHDRRAMx2.SchDoc, entitled 36-Way User I/O Headers) of the motherboard schematics.

Design interface component Since the headers can be configured as either input or output, they are not provided as a design interface component (available from the NB2DSK01 Port-Plugin integrated library). Daughter board Test / Reset button The NB2DSK01 provides a push button switch that is wired to an I/O pin of the daughter board FPGA. The button has no intrinsic function – it is simply a switch made available for FPGA design purposes. It is typically used to provide the external reset signal (RST_I) for the FPGA design. As such, it is labeled on the board as 'DAUGHTER BD TEST/RESET'. The switch is of type SPNO – Single Pole Normally Open. In the open position, it provides a logical High signal to the daughter board FPGA, changing to logical Low when pressed.

Location on board

The switch (designated SW8) is located on the component side of the board, to the left of 'User Figure 86. Provide an external Header A'. reset to your design using this dedicated Test/Reset button. Schematic reference The switch circuitry can be found on Sheet 56 (SW_RESET_SPNO.SchDoc, entitled Push Button SPNO Switch) of the motherboard schematics.

Design interface component Table 16 summarizes the available design interface component that can be placed from the FPGA NB2DSK01 Port- Plugin.IntLib, to access and use the push button switch, SW8.

50 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Table 16. Test/Reset switch port-plugin component.

Component Symbol Component Name Description

TEST_BUTTON Place this component to interface to, and use, the push button

switch (SW7) in your FPGA design.

As the signal is normally High (switch open) and the RST_I signal is active High, an inverter is typically placed directly in front of the interface component (within the FPGA design), therefore preventing a permanent reset signal. For more information on the inverter and other generic components available for use in an FPGA design, refer to the CR0118 FPGA Generic Library Guide. Generic user switches The NB2DSK01 provides a further five push button style switches that are wired to separate I/O pins of both the NanoTalk Controller (Xilinx Spartan-3 FPGA) and the daughter board FPGA. From the NanoTalk Controller's perspective, these switches are used for navigation/control of the GUI on the TFT LCD panel. From a daughter board FPGA perspective, they can be used as generic switch inputs to a design.

Each switch is of type DPNO – Double Pole Normally Open. In Figure 87. PDA-style push buttons. the open position, it provides a logical High signal to the destination FPGA device, changing to logical Low when pressed.

Location on the board The switches (designated SW1 – SW5) are located on the component side of the board, below the area populated by the TFT LCD panel. The five switch signals arrive at the daughter board FPGA as signals SW0 to SW4. On the NB2DSK01, SW0 is the signal associated with switch number 1, in the left-most position.

Schematic reference The switches can be found on Sheet 58 (SW_PDA_DPNOx5.SchDoc, entitled PDA-Style 5 x DPNO Switch) of the motherboard schematics.

Design interface component Table 17 summarizes the available design interface components that can be placed from the FPGA NB2DSK01 Port- Plugin.IntLib, to access and use the push button switches, SW1 – SW5.

Table 17. User switches port-plugin components.

Component Symbol Component Name Description

USER_BUTTONS Place this component to use all five push button switches (SW1 – SW5) in your FPGA design.

USER_BUTTON0 Place this component to use push button switch SW1 in your FPGA design.

USER_BUTTON1 Place this component to use push button switch SW2 in your FPGA design.

USER_BUTTON2 Place this component to use push button switch SW3 in your FPGA design.

USER_BUTTON3 Place this component to use push button switch SW4 in your FPGA design.

USER_BUTTON4 Place this component to use push button switch SW5 in your FPGA design.

Although the five signals arrive at the daughter board FPGA device on separate pins, the USER_BUTTONS interface component provides a 5-bit bus input. Connection to the component's bus port depends on where in the design these signals are destined.

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If, for example, you wanted to use single switch signals in different areas of the design, you would need to use an appropriate bus joiner device. Remember that each switch provides a Low signal when pressed. If you require a signal that goes High when the corresponding switch is pressed, you will need to place an inverter component within your design accordingly. For more information on the available bus joiner and inverter components available for use in an FPGA design, refer to the Functional Classes – Bus Joiner and Functional Classes – Inverter sections of the CR0118 FPGA Generic Library Guide, respectively. Buzzer signal As part of its audio capabilities, the NB2DSK01 provides a hardwired path for a mono-based audio signal from the daughter board FPGA. This signal – a legacy NB1-style Buzzer signal – can be incorporated as input to the NB2DSK01's analog audio mixer. Note: The Buzzer signal is input to only the right channel of the NB2DSK01's audio power amplifier. By using only the right channel, the digital noise generated by the FPGA in a sigma-delta configuration is reduced, as there is one less speaker emitting noise. When using the NB2DSK01's audio system with just this signal, output is relayed to only the right-channel speaker of the attached Desktop Stereo Speaker Assembly NB2DSK-SPK01.

Schematic reference The Buzzer signal input to the analog mixer can be found on Sheet 65 (AUDIO_AMP_NB2A.SchDoc, entitled AUDIO SUB- SYSTEM) of the motherboard schematics.

Design interface component Table 18 summarizes the available design interface component that can be placed from the FPGA NB2DSK01 Port- Plugin.IntLib, to provide a mono audio signal from the FPGA design, using the NB2DSK01's hardwired Buzzer signal.

Table 18. Buzzer signal port-plugin component.

Component Symbol Component Name Description

SPEAKER Place this component to send a mono-based audio signal from your FPGA design, to the NB2DSK01's audio system.

Soft JTAG chain Communications from the Altium Designer software environment to embedded processors and virtual instruments in an FPGA design, is carried out over a JTAG communications link. This is referred to on the NB2DSK01 as the Soft JTAG (or Nexus) chain. Within Altium Designer, such devices included in the chain are presented in the Devices view as part of the Soft Devices chain. Figure 88. Nexus JTAG Connector. The Soft JTAG chain signals (NEXUS_TMS, NEXUS_TCK, NEXUS_TDI and NEXUS_TDO) are derived in the NB2DSK01's NanoTalk Controller (Xilinx Spartan-3). As part of the communications chain, these signals are wired to four pins of the daughter board FPGA. To interface to these pins, you need to place the NEXUS_JTAG_CONNECTOR design interface component (Figure 88). This can be found in the FPGA NB2DSK01 Port-Plugin integrated library (\Library\Fpga\FPGA NB2DSK01 Port-Plugin.IntLib). This component 'brings' the Soft JTAG chain into the design. In order to wire all relevant Nexus-enabled devices (processors, virtual instruments) into this chain, you need to also place a NEXUS_JTAG_PORT component (Figure 89), and connect this directly to the NEXUS_JTAG_CONNECTOR (Figure 90). This component can be found in the FPGA Generic integrated library (\Library\Fpga\FPGA Generic.IntLib). Figure 89. Nexus The presence of the NEXUS_JTAG_PORT JTAG Port. component instructs the software to wire all components that possess the parameter NEXUS_JTAG_DEVICE=True into the Soft JTAG chain.

Figure 90. Connecting JTAG devices into the Soft JTAG chain.

52 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Working with multiple FPGAs The FPGA design environment supports the simultaneous development of FPGAs on multiple NanoBoards or connected user boards. If you have multiple FPGA devices present in the Devices view, you must have a valid design downloaded into each device in order to use the Soft JTAG chain. If one FPGA in this chain includes soft (Nexus-enabled) devices and others do not, each design that does not include soft devices must include the two Soft JTAG implementation components, as described in the previous section. This is because the Soft JTAG chain must route through all target FPGAs, even if an FPGA does not make use of it. Using multiple SPI/I2C devices in a design When interfacing to a single SPI (or I2C) device from an FPGA design, access to the device is straightforward – simply place the specific port component representing the interface to that device, and wire to it (typically from an interface controller in the design). For example, if you want to access and use the SPI Flash memory on the NB2DSK01 motherboard, you would place the SERIALFMEMORY port component, from the FPGA NB2DSK01 Port-Plugin integrated library. If your design is to communicate with multiple SPI (or I2C) devices, you can not simply place the corresponding specific port component for each device. To do so would result in multiple port components with the same pin names being used (e.g. SDA, SCL for I2C devices). This duplication of names will lead to errors when the design is processed for the target FPGA device. The solution is to place, and wire to, a single SPI- or I2C-based port component. To use a specific port component can make the design hard to read, especially if the device represented graphically by that component is not even targeted by that design! To avoid this situation, generic SPI- and I2C-based port components are provided. Table 19 summarizes these components, which can be placed from the FPGA NB2DSK01 Port-Plugin.IntLib. Note: Your design may need to communicate with multiple SPI- and/or I2C-based resources, but remember that communications can only be carried out with one such resource of each type at a time. Access to more than one device, in turn, would be achieved through the embedded software for your design.

Table 19. Generic port-plugin components.

Component Symbol Component Name Description

SPI_BUS Place this component to include a generic interface to the NB2DSK01 motherboard's SPI bus within your FPGA design.

I2C_BUS Place this component to include a generic interface to the NB2DSK01 motherboard's I2C bus within your FPGA design.

For information on available peripheral devices – used to provide the control interface between a processor in the design and the NB2DSK01 resource – go to www.altium.com/nanoboard/resources.

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Daughter Boards

The target FPGA devices to which a design can be downloaded, reside on separate satellite boards, All daughter boards available referred to as daughter boards. These boards plug-in to the NB2DSK01 motherboard. By keeping from Altium may be plugged each programmable device on its own daughter board, engineers can easily change the target into either the Desktop project architecture, while keeping the NB2DSK01 a truly FPGA vendor-independent development NanoBoard NB2DSK01 or the board. NanoBoard-NB1. Daughter board resources Various daughter boards are available, each offering a different FPGA device. Resources on a daughter board can vary, such as the available memory (SRAM, SDRAM, Flash). Some future daughter boards may well include a physical processor, for use by the design running in the main FPGA device. The following is a list of generic features, common to all daughter boards: • Protective casing – all daughter boards have a protective casing that helps protect the topside of the board. • 100-way connectors – these 100-way Male docking connectors are used to connect the daughter board to the NB2DSK01 motherboard, which has corresponding 100-way Female docking connectors ('NANOCONNECT' interfaces). Daughter boards available with the Desktop NanoBoard NB2DSK01 and beyond each have three connectors (top, bottom and left). Those available previously for the NanoBoard-NB1 have two such connectors (top and bottom). • Power LED – this will light (RED) when the daughter board is correctly plugged into the NB2DSK01 motherboard and the NB2DSK01's power is switched on. • Program LED – this will light (GREEN) when the target device on the daughter board has been successfully programmed with an FPGA design. 3-connector daughter boards also have three holes that align with threaded standoffs on the NB2DSK01. These can be used to affix the board securely to the motherboard. Figure 91. Example 3-connector daughter board, featuring an Altera Cyclone 2 FPGA device. Note: If using a 2-connector daughter board, it will have three locator 'legs' on its underside. These legs are used to ensure correct alignment between the daughter board's connectors and those of the motherboard. The NB2DSK01 has corresponding holes to receive these 'legs'. For more information on the range of daughter boards currently available and additional documentation specific to each, go to www.altium.com/nanoboard/resources. Accessing Desktop NanoBoard NB2DSK01 resources A daughter board is mounted onto the NB2DSK01 motherboard by plugging its three 100-way Male connectors into the motherboard's three 100-way Female connectors – designated HDR_T1, HDR_L1 and HDR_B1. The board can be securely fixed in place using the available threaded standoffs (3-connector daughter boards only). The NB2DSK01 daughter board connectors map I/O resources on the NB2DSK01 directly to the pins of the daughter board FPGA device, as if that device were mounted directly on the motherboard. For more information on the NB2DSK01 motherboard resources made available to a daughter board FPGA device, see the section Resources accessible from an FPGA design, earlier in this document. In addition to the user-available IO, the daughter board connectors provide pins for a series of other functions, including implementation of the NanoTalk communications protocol, power, and programming of the FPGA device. The following sections detail these additional signals, in relation to the daughter board connectors on the motherboard. Hard JTAG signals All daughter board devices that are JTAG-equipped are connected to signals FPGA_TMS, FPGA_TCK, FPGA_TDI and FPGA_TDO. This allows the NB2DSK01 and Altium Designer to address the daughter board hardware using the JTAG protocol.

54 TR0143 (v2.0) May 26, 2008 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01

Soft JTAG signals Four FPGA I/O pins are reserved for JTAG signals that are utilized by the FPGA design. Altium Designer uses JTAG IP to communicate directly with the FPGA fabric, allowing applications to be debugged live. These signals (NEXUS_TMS, NEXUS_TCK, NEXUS_TDI and NEXUS_TDO) are derived in the NB2DSK01's NanoTalk Controller, which is implemented in a Xilinx Spartan-3 on the motherboard. For more information on the JTAG communications, refer to the article AR0130 PC to NanoBoard Communications. Daughter board identification signals FPGA devices from different manufacturers and families require differing auto-configuration processes, so it is necessary for the NanoTalk Controller to be able to identify the device family. For 2-connector daughter boards, four signals (FPGA_ID0..FPGA_ID3) are hardwired on the daughter board to provide the required identification to the NanoTalk Controller. These four signals are also used on 3-connector daughter boards, to satisfy compatibility requirements when plugging such a daughter board into a NanoBoard-NB1 motherboard. ® Enhanced identification is available on 3-connector daughter boards, courtesy of a 1-Wire compatible slave memory device. This device carries more than enough storage capacity to hold information such as Board ID, physical Device ID, board revision, and so on. The NanoTalk Controller interrogates this device over a single wire, the associated signal of which is ONE_WIRE_DBID. SPI bus interface The NB2DSK01 SPI system involves a variety of SPI-compatible slave resources, located across the hardware system – on the NB2DSK01 motherboard itself and also on certain peripheral boards that plug in to the motherboard. These SPI resources are accessible by three distinct SPI masters: • Altium Designer (via the parallel or USB connection) • The firmware – more specifically a TSK3000A processor therein – loaded onto the motherboard's Spartan-3 FPGA device (the NanoTalk Controller) • The design loaded onto the currently plugged-in daughter board FPGA device. Providing the required SPI bus arbitration between the masters, and access to the SPI devices, is the NB2DSK01's SPI Controller. The Controller, which is part of the NanoBoard firmware, plays the role of multiplexer/router – determining which master has access to the SPI bus and which SPI slave device is selected for communications. From an FPGA design perspective, the NB2DSK01's SPI Controller provides an SPI path from the daughter board to each of the SPI slave resources resident in the system. Daughter board connector signals DAU_SPI_DIN, DAU_SPI_DOUT, DAU_SPI_CLK, DAU_SPI_SEL and DAU_SPI_MODE provide this connectivity. During operation, the daughter board FPGA design communicates with the NB2DSK01's SPI Controller to establish a path between the design and a specific motherboard/peripheral board SPI device. For detailed information on the Desktop NanoBoard's SPI communications system, refer to the document AP0163 SPI Communications on the Desktop NanoBoard NB2DSK01.

1-Wire® bus interface A 1-Wire serial bus interface signal is provided (ONE_WIRE_DB_PB) which is connected through to each of the NB2DSK01's peripheral board connectors. This provides the ability to communicate directly from a processor in an FPGA design, with one or more slave 1-Wire compatible devices located across plugged-in peripheral boards (where such devices exist). As the 1-Wire bus is made available to all three peripheral board sites it allows development of a dedicated network of 1-Wire devices – a micro-LAN if you will. Daughter board power signals Daughter board connectors HDR_T1 and HDR_B1 provide three power supplies to the daughter board, as well as ground signals. The power supply voltages are 5V, 3.3V and a third programmable supply, VCCX, providing an internal voltage for the target FPGA. The programmable voltage signal is daughter board dependent. It is supplied by a voltage regulator (designated U10), which is controlled by a reference voltage, VCCX_REF, supplied by the FPGA. Current monitoring is in place on both the 5V and 3.3V power lines. Note: 3-connector daughter boards available with the Desktop NanoBoard NB2DSK01 and beyond do not make use of the VCCX voltage supply from the motherboard. Where the FPGA device on such a board requires an additional voltage level, this level is supplied by an on-board regulator, powered from the daughter board's 5V supply rail. It is advised to use this approach when building your own daughter board.

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Note: The maximum current available to the daughter board will depend upon the number and type of peripheral boards attached to the motherboard, as well as the power requirements of each individual rail. In any case, the total connector contact rating of 2.0A for both the 3.3V and 5V rails is not to be exceeded. The maximum return ground current for all rails should not exceed 3A. Daughter board FPGA control signals Daughter board connector HDR_T1 handles various signals between the NanoTalk Controller and the daughter board FPGA device, that are used to control that device. Such signals include detection of an FPGA device when a daughter board is plugged-in to the motherboard, as well as signals used to actually program the device with an FPGA design. Accessing peripheral board resources Resources on the plug-in peripheral boards are also made available to the daughter board FPGA device. The corresponding I/O pins from each peripheral board connector – 50 each – are wired directly to pins of the daughter board connectors: • Peripheral Board A and B connector signals are wired to daughter board connector HDR_L1 • Peripheral Board C connector signals are wired to daughter board connector HDR_T1 These signals are subsequently wired to I/O pins of the daughter board's FPGA device. By keeping the signals generic – based on the peripheral board connector position and not on the resources – the peripheral boards can be attached to the NB2DSK01 in any of the three peripheral board positions. Note: Some peripheral boards (e.g. PB01 – the Audio / Video Peripheral Board) are twice the width of other available peripheral boards and, as such, can only be connected to the NB2DSK01 using the 'PERIPHERAL BOARD A' or 'PERIPHERAL BOARD C' connectors. For more information on peripheral boards, see the section Peripheral Boards, later in this document. A word about changing daughter boards When changing FPGA daughter boards, please take care not to damage the connectors that attach the daughter board to the NB2DSK01. The following procedure is recommended: 1. Ensure that the NB2DSK01's power is switched off. 2. If using a 3-connector daughter board, ensure that any screws affixing it to the motherboard are removed. 3. Grip the two sides of the daughter board between your thumb and fingers and gently pull the daughter board upwards. Gently rocking the daughter board from side to side can help loosen the connectors. 4. As the daughter board disengages, ensure that you keep the board parallel to the motherboard and pull it straight up until all connectors are fully disengaged. 5. Install a different daughter board by gently positioning it so that its connectors are aligned with the corresponding connectors on the motherboard – the posts of which slot through the holes in the Figure 92. Switch daughter boards to change the target daughter board. architecture. If using a 2-connector daughter board, place its locator 'legs' into the corresponding holes in the motherboard. Once located, press the daughter board firmly onto the NanoBoard. If using a 3-connector daughter board, you can secure it to the motherboard using the available threaded standoffs. 6. Switch the NB2DSK01's power on. The system software interrogates the NB2DSK01 at regular intervals to determine the FPGA device installed. If you change daughter boards, the system will automatically detect the change and show the correct device in the Devices view. When the Devices view is active you can force the system to poll the NB2DSK01 by pressing the F5 key.

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Peripheral Boards

With the Desktop NanoBoard NB2DSK01, peripherals available to the daughter board FPGA are delivered on removable peripheral boards, providing a simple and cost-effective method for rapid prototyping of your hardware concepts. Peripheral boards reduce congestion on the NB2DSK01 motherboard, while allowing additional resources to be made available to the daughter board for expansion of your designs. Application-specific plug-in peripheral boards give you further flexibility and greatly accelerate the process of exploring your design flows in real time. Additionally, peripheral boards continue to be developed by Altium, making it easy to evaluate new and alternate technology options, such as wireless networking. The Desktop NanoBoard NB2DSK01 caters for the use of up to three peripheral boards, and is delivered with three such boards as standard. You can also build your own peripheral board for your specific production applications, giving you ultimate control to develop, implement and debug your designs. Considered an extension to the Desktop NanoBoard NB2DSK01, resources on a peripheral board appear as though they are physically located on the motherboard itself. It's worth noting that peripheral boards may be constructed with any required resources, provided the pinout requirements of the motherboard's generic peripheral board docking connector are met. Figure 93. Example peripheral board, providing For more information on the range of peripheral boards currently available USB, IrDA and Ethernet resources. and additional documentation specific to each, go to www.altium.com/nanoboard/resources. Accessing board resources Each peripheral board is mounted onto the NB2DSK01 motherboard by plugging its 100-way Male docking connector into one of the motherboard's corresponding 100-way Female docking connectors (each referred to as a 'NANOCONNECT' interface). The board can be securely fixed in place using the available threaded standoffs. The three peripheral board connectors on the NB2DSK01 motherboard (labeled 'PERIPHERAL BOARD A', 'PERIPHERAL BOARD B' and 'PERIPHERAL BOARD C') are identical in their pinouts, providing generic docking platforms that allow for a peripheral board to be affixed to the motherboard in any of the three locations. Note: Some peripheral boards (e.g. PB01 – the Audio / Video Peripheral Board) are twice the width of other available peripheral boards and, as such, can only be connected to the NB2DSK01 using the 'PERIPHERAL BOARD A' or 'PERIPHERAL BOARD C' connectors. 50 pins from each connector are wired directly to the NB2DSK01's daughter board connectors, making the I/O resources on a plugged-in peripheral board available to the daughter board FPGA once plugged in. In addition to these IO pins, each connector provides pins for the following common services: JTAG signals Both Hard and Soft JTAG signals are wired to the peripheral board connectors, in the same way as for the user board headers – 'User Board A' (HDR1) and 'User Board B' (HDR2). This allows for communications with future peripheral boards that might include JTAG-equipped physical devices (e.g. an FPGA) featuring designs that include Nexus-enabled (Soft) devices. The NanoTalk Controller will only route the Hard and Soft JTAG chains via a peripheral board connector if the signal level on pin 23 of the connector (signal JTAG.DETECT on the motherboard) is Low. Any of the peripheral board connectors can be excluded from the Soft JTAG chain directly from the firmware-driven GUI on the TFT LCD panel. See Bypassing JTAG devices later in this document for more information. Peripheral board identification signal ® The NanoTalk Controller uses dedicated ID lines, based on the 1-Wire serial bus protocol, to verify which peripheral board it is communicating with: • ONE_WIRE_PB_ID_A – to identify the peripheral board plugged in to the 'PERIPHERAL BOARD A' connector. • ONE_WIRE_PB_ID_B – to identify the peripheral board plugged in to the 'PERIPHERAL BOARD B' connector.

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• ONE_WIRE_PB_ID_C – to identify the peripheral board plugged in to the 'PERIPHERAL BOARD C' connector. Board identification is achieved through use of a 1-Wire compatible slave memory device located on each peripheral board. Audio signals Line In and Mic In signals from the NB2DSK01's audio input jacks are routed to the peripheral board connectors on the motherboard, appearing as AIN.L, AIN.R and AIN.MIC inputs. These signals provide the audio input to any audio resource (e.g. audio codec) on a plugged-in peripheral board. Line output signals – AOUT.L and AOUT.R – are wired from each peripheral board connector, through to the NB2DSK01's analog mixer circuitry, to be used as input to the motherboard's stereo audio power amplifier. The signals from each connector arrive at the mixer and are distinguished by the connector's position: • AOUT_PBA.L and AOUT_PBA.R – from the 'PERIPHERAL BOARD A' connector. • AOUT_PBB.L and AOUT_PBB.R – from the 'PERIPHERAL BOARD B' connector. • AOUT_PBC.L and AOUT_PBC.R – from the 'PERIPHERAL BOARD C' connector. I2C interface I2C bus signals are provided to each peripheral board connector (I2C.SDA and I2C.SCL) for use with resources possessing an I2C-compatible interface. SPI bus interface The NanoTalk Controller provides an SPI path to each peripheral board connector, enabling a daughter board FPGA to communicate with/control an SPI based resource resident on a plugged-in peripheral board. Connector signals SPI.DOUT, SPI.DIN, SPI.SCLK, SPI_CS_N0 and SPI_CS_N1 provide this connectivity. The NanoTalk Controller uses dedicated Chip Select lines to distinguish communication between multiple SPI devices: • EXTSPI_CSA_N[1..0] – to access devices on a board plugged in to the 'PERIPHERAL BOARD A' connector. • EXTSPI_CSB_N[1..0] – to access devices on a board plugged in to the 'PERIPHERAL BOARD B' connector. • EXTSPI_CSC_N[1..0] – to access devices on a board plugged in to the 'PERIPHERAL BOARD C' connector. For detailed information on the Desktop NanoBoard's SPI communications system, refer to the document AP0163 SPI Communications on the Desktop NanoBoard NB2DSK01.

1-Wire® bus interface A 1-Wire serial bus interface signal is provided (ONE_WIRE_DB_PB) for use with one or more slave 1-Wire compatible devices located on the peripheral board. Clocking Four pins are made available to receive gated clock signals from the NanoTalk Controller. These signals arrive at each connector as three actual clock signals (CLOCKS.CLK0, CLOCKS.CLK1, CLOCKS.CLK2) and a clock enable signal (CLOCKS.EN). The NanoTalk Controller uses dedicated clock signals for each peripheral board, as follows: • CLK_EXTA[2..0] and CLK_ENA – for a board plugged in to the 'PERIPHERAL BOARD A' connector. • CLK_EXTB[2..0] and CLK_ENB – for a board plugged in to the 'PERIPHERAL BOARD B' connector. • CLK_EXTC[2..0] and CLK_ENC – for a board plugged in to the 'PERIPHERAL BOARD C' connector. Power signals Each peripheral board connector provides five power supplies to the docked peripheral board, as well as ground signals. The power supply voltages are 5V, 3.3V, 2.5V, 1.8V and 1.2V. Current monitoring is in place on all power lines. Note: The maximum current consumption will depend upon the number and type of peripheral boards attached to the motherboard, and the type of daughter board used, as well as the power requirements of each individual rail. In any case, the connector contact rating of 1.0A for each individual power rail (1.5A for the 5V rail) is not to be exceeded.

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A word about changing peripheral boards When changing peripheral boards, please take care not to damage the connector that attaches the peripheral board to the NB2DSK01. The following procedure is recommended: 1. Ensure that the NB2DSK01's power is switched off. 2. Ensure that all screws affixing the peripheral board to the motherboard are removed. 3. Grip the two sides of the peripheral board between your thumb and fingers and gently pull the board upwards. Gently rocking the peripheral board from side to side can help loosen the connector. 4. As the peripheral board disengages, ensure that you keep the board parallel to the motherboard and pull it straight up until the connector is fully disengaged. 5. Install a different peripheral board by gently positioning it so that its connector is aligned with the corresponding connector Figure 94. Attaching a peripheral board to the NB2DSK01 on the motherboard – the posts of which slot through the holes motherboard. in the peripheral board. Once located, press the peripheral board firmly onto the NanoBoard. You can secure it to the motherboard using the available threaded standoffs. 6. Switch the NB2DSK01's power on.

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Direct interaction with the Desktop NanoBoard NB2DSK01

When the Desktop NanoBoard NB2DSK01 is powered on, the TFT LCD panel will present a graphical user interface, the Home screen of which is shown in Figure 95. This GUI is driven by the firmware running on the board's Spartan-3 FPGA device (NanoTalk Controller). Through its touch screen, the panel becomes a portal to the firmware, allowing direct interaction with various NB2DSK01 resources.

Programmable Clock Frequency NanoBoard-to-PC Connection Current Time (Parallel Port or USB2.0) (Output from Real Time Clock)

Icons giving access to sub-screens

Icon for handing TFT LCD Icon for manual panel control from activation of screen firmware GUI to daughter saver board FPGA design

Detected daughter board Detected peripheral boards (Board.Revision) attached to (Board.Revision) attached to Detected NanoBoard motherboard motherboard connectors: (Board.Revision) and currently ‘PERIPHERAL BOARD A’ loaded version of firmware ‘PERIPHERAL BOARD B’ ‘PERIPHERAL BOARD C’ Figure 95. TFT LCD panel GUI – allowing direct interaction with the NB2DSK01. Driving the GUI Navigation and selection on the TFT LCD panel is simply a case of touch-and-go. This facility is provided courtesy of the panel's touch screen layer. Use your finger, or the supplied stylus, to touch icons and descend into sub-screens of the GUI, which collectively provide access to a myriad of features. The GUI itself is very intuitive – a few taps on the screen and you will quickly become familiarized with the controls and options available. The following list offers a few pointers when using the GUI – some obvious, some more subtle, but all aimed at making your experience with the GUI a more productive one. More detail on specific features offered by the GUI can be found in subsequent sections. • The panel's touch screen should already be calibrated correctly upon first use. However, recalibration can be performed at any time. From the Home screen of the GUI, touch the icon, followed by the icon. Calibration involves touching at four prompted locations – top-left, top-right, bottom-right and bottom-left. • If a screen presents radio-button style options, simply touch the radio button for the option that you wish to make use of. If a screen presents check box style options, simply touch on the check box area to toggle the state of that option. • If a screen allows you to change a setting, there will typically be two icons at the bottom of the screen with which to commit the change or cancel and return back to the parent GUI screen .

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• The icon at the bottom-right of a screen may change depending on the context of the screen and the action permitted. For example, if you have selected an example design on the Examples screen, or an FPGA programming file on the Browse screen, the icon will appear as , meaning the design/file will be downloaded to the daughter board FPGA if touched. • Settings modified through the GUI can be reset to their default values. This can be achieved in one of two ways: In both cases, ensure that you keep - Press and hold generic user switches SW1, SW3 and SW5 (located below the TFT LCD the three generic user switches panel) and keep the Home button (designated SW9 and located to the top-right of the pressed until the reset screen panel) pressed for more than 5 seconds. appears. Otherwise you will simply be performing a reset of the NanoTalk - Press an d hold generic user switches SW1, SW3 and SW5 and cycle the NB2DSK01's Controller. power. In both cases, a screen will appear on the TFT LCD panel asking for confirmation to proceed with the reset. Press generic user switch SW4 to load the defaults (Yes) or SW2 to decline (No) and keep your current settings. • Certain sub-screens or options of the GUI will be disabled if they can not be used or accessed at that time. The Examples screen, for example, will only become enabled if an SD card with applicable content is inserted into the motherboard's SD card reader. Another example is the GUI to daughter board icon, , which will be disabled unless an FPGA design is running on the daughter board FPGA, and which utilizes the TFT LCD panel. • The image at the top-left of the screen reflects the current JTAG connection between the NB2DSK01 and the PC. denotes a parallel port connection, while denotes a USB2.0 connection. The image will flicker momentarily, and periodically, in accordance with the chosen polling interval, defined on the FPGA – Devices View page of the Preferences dialog (DXP » Preferences). • The version of firmware currently installed and running on the NanoTalk Controller is reflected at the bottom of the GUI's Home screen. If there is a later version of firmware available, you will need to follow the procedure for updating to the new firmware. For detailed information on how to do this, see the section Updating the NanoBoard firmware, later in this document. GUI options To access options for the GUI, from the Home screen of the GUI touch on the icon, followed by the icon on the sub- screen that appears. The following options are available: • Enable Screen Saver – use this option to enable the automatic screen saver. Screen saving will be applied after the TFT panel's touch screen has not been The screen saver can also be activated manually, and immediately, by clicking on the available icon on touched for a period of 10 minutes. The automatic screen saver functionality the Home screen of the GUI. Manual activation does simply displays Bitmap or JPEG images in a loop, with each image displayed not depend on the Enable Screen Saver setting. for 10 seconds. Images are sourced from two places – within the ScreenSaver folder stored in the NB2DSK01's common-bus Flash memory, and within a ScreenSaver folder resident on an SD card currently inserted If no images can be found – in either Flash memory into the motherboard's SD card reader. All images found within the Flash or an SD card – a simple screen saver will be used, location will be used first, followed by those found on the SD card. with the Altium logo cycling through different locations on the screen. To return back to the GUI while the screen saver is running, simply touch the panel. • Enable Sounds – enable this option to have action-based sounds played during the course of using the GUI, for example when you touch on the accept/confirm icon . Use the NB2DSK01's volume control to adjust the sound level as required. • Enable RGB LEDs – use this option to control the ON/OFF state of the RGB LEDs on the attached Desktop Stereo Speaker Assembly NB2DSK-SPK01. • Fade Screens – Use this option to enable a 'fade' effect when transitioning between screens of the GUI. • Show intro at startup – With this option enabled, introductory screens will be presented on the panel whenever the NB2DSK01 is powered on, or after a reset of the NanoTalk Controller. These screens are in fact JPEG images, stored within the Welcome folder in the NB2DSK01's common-bus Flash memory. This option is also presented while the introductory screens are being viewed, so that you can opt to disable these screens directly. There is also an option to skip the intro screens. A shared panel... The TFT LCD panel on the NB2DSK01 is used by the firmware, to present the interactive GUI, but it can also be used by a design running on the daughter board FPGA. When you program the FPGA with a design that utilizes the panel, it will automatically assume control (provided the DAU_TFT_MUX line is tied High in the design).

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To pass ownership of the panel back to the firmware running on the NanoTalk Controller, you simply need to press the NB2DSK01's 'Home' button (designated SW9 and located to the top-right of the panel). This button actually serves multiple purposes: • By pressing and releasing quickly, the firmware is given the driving seat for the panel – presenting the Home screen of the GUI. • If pressed and held for more than 5 seconds, the NanoTalk Controller is reset. • If pressed and held for more than 5 seconds while also holding generic user switches SW1, SW3 and SW5, a screen is accessed from which to reset GUI options to default settings. (Note: The generic switches must be kept pressed until the reset screen actually appears). If you need to give control of the panel back to the daughter board FPGA again, simply touch the icon on the Home screen of the GUI. Whatever was displayed on the panel prior to handing control to the firmware will reappear on the panel. Bootstrapping the daughter board FPGA The Desktop NanoBoard NB2DSK01 provides the ability to bootstrap the physical FPGA device, on the currently inserted daughter board, at power-up. To access boot controls (Figure 96), from the Home screen of the GUI touch the icon, followed by the icon. The GUI allows you to choose whether or not you wish to enable use of the boot feature and, if so, from where the programming file(s) for the design will be sourced for the boot process – either from an SD memory card inserted into the NB2DSK01 motherboard's SD card reader, or from dedicated on-board SPI Flash memory. Booting from an SD card To boot from an SD memory card on power-up, simply use the GUI to select the option First example found on SD-card, and ensure the SD memory card carrying the design is inserted into the motherboard's SD card reader (designated J8 on the board). Note: The required FPGA programming file and HEX file (for the code if applicable) must reside on the card, and be pointed to by an associated EXAMPLE file (*.example), also on the card, and in the same location. For more information on EXAMPLE files, see the Figure 96. Controls related to section Examples screen, later in this document. bootstrapping of the FPGA device. Once the NB2DSK01's power is cycled, the first EXAMPLE file found will be used (EXAMPLE files are sorted alphabetically). This will also depend on the file structure in-place on the card. The FPGA programming file referenced in the EXAMPLE file will be downloaded to the daughter board FPGA. Any HEX file referenced will be downloaded to the M25P80 SPI Flash memory device that is solely used for embedded storage purposes (designated U20 on the motherboard). Booting from SPI Flash memory To boot using a design stored in serial Flash memory, simply use the GUI to select the Serial Flash option and ensure that the FPGA programming file for the design is loaded into the M25P80 SPI Flash memory device that is used for boot purposes (designated U21 on the motherboard). Once the NB2DSK01's power is cycled, the FPGA programming file stored in the SPI Flash memory will be downloaded to the daughter board FPGA. The procedure for loading an FPGA programming file into the Flash memory can be carried out at any time – with or without an FPGA project open and irrespective of whether a design is currently programmed into the target FPGA device (on the daughter board). Controls for downloading to, and erasing, the Flash memory, can be found in the Flash RAM Controller For FPGA Boot dialog. Access to and use of this dialog, is detailed in the following sections.

Accessing Flash memory controls The Flash RAM Controller For FPGA Boot dialog is accessed directly from the instrument panel for the NB2DSK01's NanoTalk Controller. From the Devices view (View » Devices View), simply double-click on the icon for the NanoBoard (in the NanoBoard Controllers chain) whose FPGA Boot Flash memory you wish to load. The Instrument Rack – NanoBoard Controllers panel will appear. Click on the FPGA Boot Flash button to access the dialog (Figure 97).

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Figure 97. Accessing controls for the FPGA Boot Flash memory. The Device ID region of the dialog reflects the communications link between the NanoTalk Controller and the Flash memory device. If communications are successful, upon accessing the dialog a value of $13 will be entered into the far right field and the confirmatory message "Device Found: M25P80 (8M-Bit Serial Flash RAM)" will be displayed. If this is not the case, try to manually interrogate the communications link by pressing the Read Electronic Signature button.

Erasing the Flash memory Before loading the required programming file into the Flash memory device, the memory must first be cleared. To erase the entire 8Mbit of Flash memory, press the Erase Entire Device button, in the Erase region of the Flash RAM Controller For FPGA Boot dialog. The erasing process will take approximately five to eight seconds, after which a confirmation dialog will appear (Figure 98). Controls are also available for erasing a particular sector of memory. Each M25P80 device is organized into 16 sectors. Each sector contains 256 pages, and each page is 256 bytes Figure 98. Confirming full erasure. wide. Therefore each sector is 65536 bytes or 512Kbits. Simply use the available drop-down to select the sector you wish to erase (or enter the sector number directly) and then click the Erase Sector button. Erasure time is typically less than a second, after which time you will receive a dialog to confirm completion of the erase (Figure 99). To verify that the device has been successfully erased, press the Blank Check button. The verification process Figure 99. Sector erasure. will take approximately sixty seconds, after which time Figure 100. Verification of memory you will receive another confirmation dialog (Figure erasure. 100).

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Downloading to Flash memory Once the Flash memory has been erased, the programming file can be downloaded. From the Download region of the Flash RAM Controller For FPGA Boot dialog, press the ... button to the right of the File Name field. The Choose FPGA Programming File For Download dialog will appear. Use this dialog to browse to, and open, the required file. The programming file used depends on the target device: • *.bit file for a Xilinx device • *.rbf file for an Altera device • *.rbt (ASCII) or *.bit (binary) file for a Lattice device • *.stp file for an Actel device. Note: When using Xilinx FPGA devices, the programming file used will be different for JTAG programming and Slave-Serial programming. The SPI Flash memory on the NB2DSK01 uses the latter when loading the FPGA device on the daughter board. Therefore, when choosing the programming file, the _cclk.bit version of the file should be used. For a design that has been compiled, synthesized and built using Altium Designer, the programming file will be located in the {OutputPath}\ConfigurationName sub-folder defined for the project. The {OutputPath} is project-specific and is defined on the Options tab of the Options for FPGA Project dialog (Project » Project Options). ConfigurationName is the configuration containing a constraint file that targets the physical FPGA device on the daughter board, into which the design will be programmed. For example NB2DSK01_08_DB30_06, which targets the Xilinx Spartan-3 device on the DB30. After choosing the file and clicking Open, you will be returned to the Flash RAM Controller For FPGA Boot dialog. The chosen file (including path) will be displayed in the File Name field (Figure Figure 101. FPGA programming file chosen and ready for download. 101). To download this file to the Flash memory device, simply click the Save File To Flash button. If you want to download to a specific area of memory, enter the required address in the Memory Address field. The download process will proceed, with progress shown in Altium Designer's Status bar. At the end of the download an information dialog will appear, confirming the end of the process (Figure 102).

Figure 102. Confirmation of file download to the Flash memory device.

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Verifying the download After you have downloaded the FPGA programming file to the Flash memory device, a check should be made to ensure the integrity of the file. To do this, simply click on the Verify against File button, in the Download region of the Flash RAM Controller For FPGA Boot dialog. The contents of the Flash memory are read back and compared against the original programming file. Progress is again reflected in Altium Designer's Status bar. An information dialog will appear at the end of the process, providing details of the verification Figure 103. Successful verification of results (Figure 103). downloaded file. If the download process is shown to have failed, the dialog will report an error count. A large number of errors typically indicates that the Flash memory device was not successfully erased prior to downloading the programming file. In this case, try erasing the device again – using the Erase Entire Device button – and then using the Blank Check button to verify that the device's memory has indeed been successfully erased. The programming file can then be downloaded again. Downloading example designs stored on an SD card When an SD memory card is inserted into the NB2DSK01 motherboard's SD card reader, the icon becomes enabled on the Home screen of the GUI. Touch this icon to access the Examples sub-screen. This screen of the GUI lists all EXAMPLE files (*.example) found on the SD card. The upper region of the screen provides a short description of each example. Touch an entry to populate the lower region of the screen with a more detailed description. Examples appearing in the list can be downloaded directly to the FPGA device on the daughter board. Simply select an example and then touch the icon that appears at the bottom-right corner of the screen. The EXAMPLE file itself is simply a list of constraint records. Two additional (non- constraint) records are used to store the text for the short and long descriptions that get displayed on TFT LCD panel, for example: Record=ShortDescription | Text="Ethernet Analyser" Record=LongDescription | Text="The Ethernet Analyser example provides capture and filter functionality of packets seen on the PB03 Ethernet connection" Figure 104. Example designs. A set of constraint records are used to declare the hardware configuration – the boards required within the NanoBoard system for the design to run. Board revision must be included when specifying the constraint for the daughter board or a peripheral board (e.g. PB03.06 for revision 6 of the peripheral board PB03). Revision of the NanoBoard is not necessary – as it is assumed that the design is to run on a daughter board plugged into the NB2DSK01, and so the revision of the motherboard is not checked. For example, to run the Ethernet Analyser design on a Xilinx Spartan-3 device, which also involves use of peripheral board PB03, the following constraint entries would be made: Record=Constraint | TargetKind=Board | TargetId=NB | Id="NB2DSK01" Record=Constraint | TargetKind=Board | TargetId=DAUGHTERBOARD | Id="DB30.06" Record=Constraint | TargetKind=Board | TargetId=PERIPHERALBOARD_B | Id="PB03.06" A single constraint is used to define the clock speed to be used for the design, for example: Record=Constraint | TargetKind=Clock | TargetId=CLK_BRD | FPGA_CLOCK_FREQUENCY=49.5 Mhz Finally, constraint records are used to declare which files to use when programming the daughter board FPGA device with the design. This will include the FPGA programming file and typically a program code file (*.hex) – the latter loaded into the motherboard's M25P80 SPI Flash memory device that is solely used for embedded storage purposes (designated U20 on the board). The following entries point to files to be used for a design targeting the Xilinx Spartan-3 on the DB30: Record=Constraint | TargetKind=FPGA_FILE | Filename="dsf_ethernet_analyser_cclk.bit" If using a folder structure on the SD card, the download files are expected to reside in Record=Constraint | TargetKind=SERIAL_FLASH_FILE | the same folder as the EXAMPLE file itself. Filename="ethernet_analyser_system_XROM.hex"

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Note: Before the list of examples is populated, a check is made between the required hardware system configuration (specifically the daughter board and peripheral board(s) defined in each EXAMPLE file) and the actual hardware system configuration (daughter board and peripheral board(s) detected using the 1-Wire ID devices resident on each board). If a design example cannot run on the current hardware system, it will not appear in the list. Browsing Flash memory and SD card content The GUI provides a screen for browsing the file content of both the NB2DSK01's common-bus Flash memory and also an SD card currently inserted into the motherboard's SD card reader. To access this screen, simply touch the icon on the GUI's Home screen. The screen will present the two storage locations in drive-style fashion: A: NB2FLASH B: SD Card Touch on one of the entries – if files are stored in a folder structure, each folder will be listed. Simply touch on a folder and then touch the icon at the bottom-right of the screen, to expand the folder and browse its contents. FPGA programming files can be downloaded directly to the daughter board FPGA from this screen. Simply select the required programming file and then touch the icon that appears at the bottom-right corner of the screen.

Note: Program code files (*.hex) can not currently be downloaded from the Browse Figure 105. Browsing file content. screen. To download a design fully, an EXAMPLE file should be made, stored on the SD card, and the download performed from the Examples screen If there are any image files (*.bmp or *.jpg), these can be opened directly within the TFT LCD panel. Once opened, simply touch the screen again to return to the GUI. Similarly, if there are any audio files (*.wav), you can open these for listening, directly from the panel. Doing so will open the GUI's Audio Player, the screen for which is illustrated in Figure 106. Initially, controls are available to start playback and choose which of the speakers on the attached Desktop Stereo Speaker Assembly NB2DSK- SPK01 are enabled – Left channel, Right channel, or both. Simply touch on a speaker icon to toggle its state between enabled and disabled . During playback, pause and stop controls become available and a progress bar is used to represent Figure 106. Playback music (wav) files Figure 107. Screen appearance during using the GUI's Audio Player. playback time (Figure 107). Use the NB2DSK01's playback. volume control to crank-up the sound as required! A word about storage... Both the NB2DSK01 common-bus Flash memory and the inserted SD card appear as additional drives within Windows Explorer, allowing you to quickly add file content to either storage location, or copy or move content between them. The common-bus Flash memory offers just under 30MB of storage space. Content written to this memory will remain until deleted – it does not expire upon power down of the Desktop NanoBoard. The following should be considered when using these two file storage facilities: You must perform a reset of the • EXAMPLE files can be stored in both locations, but the Examples screen of the GUI will NanoTalk Controller in order to only list those examples found on the SD card. refresh the displayed list of contents • If you wish to use the GUI's screen saver facility, the image files (.bmp and/or .jpg) must for both SD card and Flash memory. be stored within a folder named ScreenSaver in either storage location. • Only those default introductory screens resident in the Flash memory's Welcome folder (welc1.jpg to welc6.jpg) are expected and displayed by the GUI when the option to show intro screens is enabled. Any additional Bitmap or JPEG files added to this folder will not be displayed as part of the intro-cycle.

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Bypassing JTAG devices With the NanoBoard-NB1, if a user board connected to the NanoBoard did not make use of, or support, the Soft JTAG chain, the TDI_SOFT and TDO_SOFT pins had to be connected at the header, in order for the chain not to be broken. With the Desktop NanoBoard NB2DSK01, there is no manual looping of such signals. You can selectively control which boards are included or excluded from the Soft JTAG chain, literally with a tap of the GUI screen. To access JTAG chain-related controls (Figure 108), from the Home screen of the GUI touch the icon, followed by the icon. You can choose to include/exclude any of the following boards – or more specifically, their associated header/connector: • User Header A • User Header B • Peripheral Board A • Peripheral Board B

• Peripheral Board C Figure 108. Controls related to inclusion By default, all boards will be included in the chain. of boards into the Soft JTAG chain. Changing system clock frequency The NB2DSK01 motherboard provides an on-board system clock generator in the form of the SPI-compatible ICS307-02 device. The frequency of the programmable clock output from this device can be changed directly through the GUI. To access clock frequency-related controls (Figure 109), from the Home screen of the GUI touch the icon, followed by the icon. Simply touch the frequency required – the supported frequencies in the range 6 to 200MHz are listed – and then touch the icon to commit your selection. The requested clock frequency is written, over the SPI bus, to the ICS307-02 device. It is also stored in the motherboard's common-bus Flash memory. The new frequency is read back from the Flash memory and reflected at the top-center of the panel display. As the frequency is stored in Flash memory, it is persistent across design and hardware sessions. Cycling the NB2DSK01's power for example will result in the last set clock frequency, stored in the Flash memory, to be used at startup – regardless of whether that frequency was set by the firmware (through the GUI) or by Altium Designer. The user-programmable clock has a default frequency of 50MHz. Figure 109. Controls to change the Note: Only predefined frequencies for the programmable clock, based on the 20MHz frequency of the motherboard's fixed reference frequency, are available for selection. Should you wish to use a different programmable system clock. frequency, this can be achieved via the Instrument Rack – NanoBoard Controllers panel, from within Altium Designer. Access this panel by double-clicking on the icon for the NB2DSK01, in the NanoBoard chain of the Devices view (View » Devices View).

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Real Time Clock (RTC) The GUI contains a screen for viewing/modifying the current date and time. This information is sourced from the NB2DSK01 motherboard's DS1391U-33 device – an SPI-compatible real- time clock (RTC). To access clock controls (Figure 110), from the Home screen of the GUI touch the icon, followed by the icon. Time is always displayed using the 24-hour format (e.g. 14:22). The date is always displayed in the format yyyy - mm - dd (e.g. 2007 - 12 - 04). Simply touch the relevant field to expose controls for incrementing/decrementing the value of that field. Commit any changes by touching the icon. Once the DS1391U-33 device is setup with the correct time and date, it will always reflect the correct time and date, even after a reset to default values, providing power to the device is not lost (i.e. NB2DSK01 motherboard powered off and the 3V Lithium battery is depleted).

Test Routines Figure 110. Display and modification of time and date. A variety of test routines can be performed from the TFT LCD panel, specifically testing the integrity of key elements of the NB2DSK01 motherboard, including the host LEDs and the generic user switches. Test routines (Figure 111) are accessed by pressing the icon on the Home screen of the GUI.

Figure 111. Accessing routines to test functionality of key motherboard resources. Simply select the test you wish to perform and follow the instructions on the panel. Navigation and selection is performed using the generic user switches, located directly below the panel. Note: When the daughter board FPGA has been programmed with a design, access to the Test Routines screen will be unavailable, with the icon put into a disabled state – .

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Desktop NanoBoard NB2DSK01 Constraint system

The process of mapping or constraining a design to its physical implementation is done by creating constraint files – files that specify implementation detail such as the target device, the port-to-pin mapping, pin IO standards and so on. The minimum information required to synthesize a design is the device specification. Sets of constraint files are targeted to a design by creating a configuration, which is simply a named list of constraint files. Setting up to implement a design on the NB2DSK01 is simplified through provision of constraint files as part of the installation. These can be found in the \Library\Fpga\NB2 Constraint Files folder of the installation. For more information on the concept of configurations and constraints, and their role in design portability, refer to the article AR0124 Design Portability, Configurations and Constraints. Constraint system overview The constraint system in place for the Desktop NanoBoard NB2DSK01 utilizes various constraint files covering: • Resources and pin-mapping local to the NB2DSK01 motherboard and satellite peripheral and daughter boards • Connection of a satellite board (peripheral boards and daughter boards) to the NB2DSK01 motherboard. Figure 112 indicates the base set of constraint files used for a design targeting a daughter board FPGA device – plugged into the NB2DSK01 motherboard – and where that design utilizes additional peripherals located across all three plug-in peripheral boards.

E

HDR1 HDR_T

C HDR_L B A HDR_B Peripheral Board F PBxxPeripheral Board PBxxPeripheral Board Daughter Board PBxx F DBxx

D

EXTHDR3 HDR_T1

HDR_L1 EXTHDR1 EXTHDR2 HDR_B1

NB2DSK01 Motherboard

Figure 112. Constraint files used for a design targeted to the NB2DSK01. Table 20 summarizes these base constraint files. Together, they ultimately map the resources available (on motherboard, daughter board and peripheral boards) to the physical pins of the daughter board FPGA.

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Table 20. Constraint file descriptions.

Constraint Targets Description File

A Peripheral board PBxx Defines the peripheral board and its connector, as well as the mapping of all resources on that board to pins of that connector. B Peripheral board PBxx

C Peripheral board PBxx

D NB2DSK01 motherboard Defines the NB2DSK01 motherboard and its connectors (daughter board, peripheral board and user board); the mapping of pins between peripheral board connectors and daughter board connectors; and the mapping of all NB2DSK01 motherboard resources to pins of the daughter board connectors.

E Daughter board DBxx Defines the daughter board and FPGA device, the connectors available on that board, and the pin mapping between those connectors and pins of the physical device. The mapping of any other resources on the daughter board, available for use by the FPGA design (e.g. memories), is also specified in this file.

F Peripheral board-to- Declares the following: motherboard and daughter • NanoBoard instance board-to-motherboard • Daughter board instance interfaces • Peripheral board instance(s) • Daughter board-to-motherboard connector mapping • Peripheral board-to-motherboard connector mapping.

Notes: 1. Additional constraint files may be included/used, such as a file for timing-related constraints. 2. Constraint file F in Figure 112 and Table 20 is commonly referred to as the 'Board Mapping constraint file'. It does not exist as part of the installation, but rather is created on-the-fly, in accordance with the hardware in the system. 3. Depending on the resources being used by your design and the number of peripheral boards plugged into the NB2DSK01 motherboard, your FPGA project may contain up to three peripheral board-related constraint files, one per board. 4. If your FPGA project has multiple configurations – targeting different daughter board FPGA devices – there will be a daughter board-related constraint file for each different device. The different configurations will contain these different constraint files. A different mapping constraint file will also be generated for, and assigned to, each unique configuration. Configuring an FPGA project automatically Although an FPGA design project targeting the Desktop NanoBoard NB2DSK01 can be configured manually – by adding a configuration, assigning the required board constraint files and creating a board mapping constraint file by hand – the process is greatly simplified through use of an auto-configuration feature. Using this feature, a target configuration for the FPGA design project is automatically created. The required board-level constraint files are then automatically determined and added to this configuration, based on the hardware (motherboard, daughter board and peripheral boards) detected in your system. An additional board mapping constraint file is also generated and added to the configuration, which handles connection of satellite boards detected in the system – daughter board and any peripheral boards – to the motherboard. Identifying system hardware Before taking a closer look at the auto-configuration procedure itself, it is a good idea to understand the technology by which such automatic configuration of the system is made possible. The key to being able to configure an FPGA design project automatically, is the ability of Altium Designer to identify the specific hardware you are currently using in your system. Identification is made possible through the use of memory devices, located on: • the NB2DSK01 motherboard • the daughter board • each peripheral board • the Desktop Stereo Speaker Assembly NB2DSK-SPK01 (though not used for auto-configuration purposes).

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The device used on each board – a DS2406 from Maxim – is a 1-Wire compatible device. The NanoTalk Controller interrogates the DS2406 on each board over a single wire, resulting in the presence of six 1-Wire buses used for system identification purposes. For more information on the DS2406 device on the NB2DSK01, refer back to the section Board ID memory, earlier in this document. Figure 113 illustrates the 1-Wire board identification system in place for the Desktop NanoBoard NB2DSK01.

Peripheral Board A ID Motherboard ID

PBxx.nn NB2DSKxx.nn

1-Wire Memory 1-Wire Memory

Peripheral Board B ID Speaker Board ID

PBxx.nn FIRMWARE NB2DSK-SPKxx.nn

1-Wire Memory 1-Wire Memory

NanoTalk Controller

Peripheral Board C ID Daughter Board ID

PBxx.nn DBxx.nn

1-Wire Memory 1-Wire Memory

Figure 113. 1-Wire board identification system for the NB2DSK01. Each 1-Wire memory device is pre-programmed with an Altium Board Identifier string. This string is 32 bytes long and can be represented as:

The four components of the string are defined in the following sections.

UniqueID is an 8 byte code programmed by the manufacturer to guarantee a unique device. The 64 bits of this code are made up of three distinct parts. The first 8 bits provide the 1-Wire family code, the next 48 bits provide the serial number which is unique to each device. The last 8 bits provide a cyclic-redundancy-check of the first 56 bits. The full 64-bit code is stored in, and accessed from, a separate ROM within the device.

ClassID is a 16 byte (hex-coded ASCII) ident for the board upon which the 1-Wire memory device resides. The string consists of the board code and the board revision, separated by a full stop. Right-padding using space characters (20h) ensures the length is kept to 16 bytes. These 16 bytes are stored in, and accessed from, Page 0 of the DS2406's data memory (EPROM) in the address range 0000h – 000Fh. Table 21 illustrates example coding for the motherboard, a daughter board and a peripheral board.

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Table 21. Example strings.

Board Format Example Resulting 16 Bytes entered into DS2406's EPROM Information

Motherboard NB2DSKxx.nn NB2DSK01.08 4E 42 32 44 53 4B 30 31 2E 30 38 20 20 20 20 20

Daughter Board DBxx.nn DB30.06 44 42 33 30 2E 30 36 20 20 20 20 20 20 20 20 20

Peripheral Board PBxx.nn PB01.07 50 42 30 31 2E 30 37 20 20 20 20 20 20 20 20 20

Speaker Board NB2DSK-SPKxx.nn NB2DSK-SPK01.07 4E 42 32 44 53 4B 2D 53 50 4B 30 31 2E 30 37 20

BatchID is a 4 byte ident for the production run. These four bytes are stored in, and accessed from, Page 0 of the DS2406's data memory in the address range 0010h – 0013h.

VendorID is a 4 byte ident for who made the board. This value is 00000001h for all Altium manufactured boards. These four bytes are stored in, and accessed from, Page 0 of the DS2406's data memory in the address range 0014h – 0017h. Note: The remaining 8 bytes in Page 0 of the device's data memory (address range 0018h - 001Fh) are left blank (contain FFh) For more information on the DS2406 device, refer to the datasheet (DS2406.pdf) available at www.maxim-ic.com. For a high-level overview of the 1-Wire bus protocol, refer to the application note (AN3989.pdf) available at www.maxim- ic.com. In terms of auto-configuration, it is the portion of the string that empowers the feature, as it is this string that determines the constraint file required in relation to a board. Information on how these IDs are used in populating a configuration with the necessary constraint files is covered in the next section. Configuring the project Prior to using the auto-configuration feature, ensure the following: • The particular daughter board carrying the FPGA device to which the design is to be targeted is plugged into the NB2DSK01 motherboard. • Any peripheral boards carrying resources used by the FPGA design are also plugged into the NB2DSK01 motherboard. Peripheral boards whose resources are not actually used can be left attached to the motherboard, or removed, as required. • The NB2DSK01 is connected to the PC (via parallel or USB connection) and is powered-on. The auto-configuration feature can be used to create the configuration for any chosen FPGA project that is currently open (in the Projects panel). Alternatively, it can be used to create the configuration and add it to a newly-created FPGA project. Access to the feature can be made in two ways: • Right-click on the icon for the NB2DSK01, in the NanoBoard chain of the Devices view (View » Devices View). Use the Configure FPGA Project sub-menu to choose the specific FPGA design project to be configured, or choose New FPGA Project. In the latter case, a dialog will appear from which you can determine where, and under what name, the new project will be saved. Figure 114. Auto-configure direct from Devices view. • From the NanoBoard Configuration dialog (Figure 115 on the following page). To access this dialog, double-click on the icon for the NB2DSK01 to access its corresponding instrumentation in the Instrument Rack – NanoBoard Controllers panel. Then click on the Board View button. Alternatively, right-click on the NB2DSK01 icon and choose View Configuration from the menu. By using the dialog, you are presented with a visual summary of your current Desktop NanoBoard NB2DSK01 system. The image in the dialog displays the specific peripheral board(s) and daughter board that are physically plugged in to the NB2DSK01 motherboard. The dialog is dynamic – refreshed on access. So if you remove the daughter board, or switch positions of peripheral boards, the new physical setup will be displayed when you next access the dialog. The dialog also provides information relating to the Altium Board Identifier string for:

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• The NB2DSK01 motherboard (located over the TFT LCD panel) • The daughter board (if plugged in) • The peripheral board plugged in to the 'PERIPHERAL BOARD A' connector (if present) • The peripheral board plugged in to the 'PERIPHERAL BOARD B' connector (if present) • The peripheral board plugged in to the 'PERIPHERAL BOARD C' connector (if present)

Figure 115. Accessing the NanoBoard Configuration dialog and its visual summary of the physical hardware present in the system. Use the Auto Configure FPGA Project drop-down at the bottom-left of the dialog to choose the existing (open) project to configure, or to create a new project to which the configuration will be added. Whichever method of access is used, the auto-configuration process proceeds in exactly the same way. First, a configuration is created and named using the format: Figure 116. Auto-configure from the motherboard code_revision_daughter board code_revision NanoBoard Configuration dialog. For example, with a Desktop NanoBoard NB2DSK01 (revision 8), and a Xilinx Spartan-3

TR0143 (v2.0) May 26, 2008 73 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01 daughter board DB30 (revision 6), the configuration will be named NB2DSK01_08_DB30_06. Constraint files will then be added to the configuration for each of the detected boards in the system (motherboard, daughter board and peripheral board(s)). These are sourced from the \Library\Fpga\NB2 Constraint Files folder of the installation. In each case, the file used will be determined by the component of the board's Altium Board Identifier string. So if you are using peripheral board PB02 (revision 6), with = PB02.06, then the constraint file retrieved and added to the configuration will be PB02.06.Constraint. The constraint file that defines the mapping of daughter board and peripheral board(s) to the motherboard is also created, on- the-fly, and added to the configuration. This corresponds to constraint file F in Figure 112 and Table 20. The name of this file will simply be that of the configuration itself, with the additional suffix '_BoardMapping' (e.g. NB2DSK01_08_DB30_07_BoardMapping.Constraint). The file will be saved to the same location as the project file (*.PrjFpg) itself. Note: _BoardMapping.Constraint files do not exist in the \Library\Fpga\NB2 Constraint Files folder of the installation. To manually create such files would be time-consuming, in addition to manually identifying which boards are present in the system and sourcing the relevant constraint files by hand. The auto-configuration feature delivers these files, and configuration, in literally a 'blink-of-an-eye', freeing you to concentrate on other important aspects of your design. The configuration and assigned constraint files are listed in the subsequent Configuration Manager dialog that appears for the project (Figure 117).

Figure 117. Resulting configuration and constituent constraint files (auto-configuration-related files will be automatically assigned). Use the dialog to add any other constraint files for the project as required, and assign them to the configuration. If you already had constraint files added to the project – for example to handle timing constraints – these will appear listed in the Configuration Manager dialog, but will not automatically be assigned to the configuration generated by the auto-configuration process.

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Power Monitoring on the Desktop NanoBoard NB2DSK01

As the number of daughter boards and peripheral boards continues to grow – both those designed by Altium and those made externally – the number of different hardware configurations possible for a Desktop NanoBoard NB2DSK01 becomes considerable. Add to this, the ability to connect expansion devices to the NB2DSK01's User Headers, again changing the configuration of the system. While developing embedded intelligence, the ability to monitor and compare the power consumption of different Desktop NanoBoard configurations would be an invaluable tool. The Innovation Station offers exactly this ability. Current monitoring hardware is provided on the Desktop NanoBoard, while access to the resulting power, current and voltage information is facilitated through instrumentation within Altium Designer.

Altium Designer

Power Supplies Peripheral Board A NanoTalk 1.2V 1.8V 2.5V 3.3V 5V Controller

Peripheral Board B Current-Sensing Daughter Board Circuitry

Peripheral Board C Desktop NanoBoard NB2DSK01

Board connected to Board connected to User Header A User Header B

Figure 118. Simplified diagram showing the power monitoring concept for Altium's Innovation Station.

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Functionality at the Hardware-Level Before looking at how the power monitoring functionality is accessed within the software, it is worth revisiting the underlying hardware, by which such power monitoring of the system is made possible. On the NB2DSK01 motherboard, current monitoring is in place for each of the following power lines: • 1.2V, 1.8V, 2.5V, 3.3V and 5V lines routed to the 'PERIPHERAL BOARD A' connector • 1.2V, 1.8V, 2.5V, 3.3V and 5V lines routed to the 'PERIPHERAL BOARD B' connector • 1.2V, 1.8V, 2.5V, 3.3V and 5V lines routed to the 'PERIPHERAL BOARD C' connector • 3.3V and 5V lines routed to the corresponding connectors for the daughter board • 3.3V or 5V line selected for use with 'User Header A' connector • 3.3V or 5V line selected for use with 'User Header B' connector. A total of 19 monitored power lines. In terms of hardware, this monitoring is achieved through use of a MAX4372T high- side current sense amplifier (from Maxim). Each power line is routed to its destination connector through a 47mΩ resistor, which serves as the external sense resistance for the associated MAX4372T device. Powered by the NB2DSK01's 9V supply, this device provides a voltage output that is proportional to the voltage across this sense resistance, and has a fixed gain of 20. For current passing through the 47mΩ resistor, the voltage across the device's input Figure 119. Schematic fragment showing the current-sensing circuitry in place for the is 47uV/mA. The output of the device is daughter board power rails on the NB2DSK01. therefore 940uV/mA (applying the x20 gain). Two low-power, 12-channel, 12-bit ADC devices (MAX1229, from Maxim) collect together the analog voltage outputs from all current sense amplifiers, for transmission back to the NB2DSK01's Xilinx Spartan-3 Controller FPGA (the NanoTalk Controller), over an SPI bus.

Figure 120. Schematic fragment showing the two ADC devices, which pass the subsequently converted data to the NanoTalk Controller over the SPI bus, and subsequent processing by the firmware. The output of each ADC, which has an internal reference voltage of 2.5V is:

ADC output = (2.5V/4096) / 940uV = 0.64931mA/bit (=2.65957A full scale) For more information on the MAX4372T and MAX1229 devices, refer to the datasheets (MAX4372-MAX4372T.pdf and MAX1227-MAX1231.pdf) available at www.maxim-ic.com.

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Accessing and Using Power Monitoring Prior to accessing the power monitoring in Altium Designer, ensure that the Desktop NanoBoard is connected to the PC (via USB or Parallel connection) and is powered-on. 'Command Central' for power monitoring can be found on the instrument panel for the NanoBoard. Simply double-click on the icon for the NB2DSK01 in the Devices view (View » Devices View) to access the Instrument Rack – NanoBoard Controllers panel (Figure 121).

Figure 121. Power monitoring is an integral part of the Desktop NanoBoard's instrument panel. The controls are located in the bottom-right region of the panel, labeled 'POWER MONITOR'. Use the Polling LED to essentially turn power monitoring ON or OFF with respect to the panel. With polling enabled, the window to the right presents the total power usage across all 19 monitored power rails on the NB2DSK01, as well as its temperature (in Degrees Celsius). Fo each satellite board (daughter board and peripheral boards) currently plugged into the NB2DSK01 motherboard (and presented in the 'PLUGINS' region of the panel), the total power usage across all monitored power rails (routed to the corresponding docking connector) is shown. For a more detailed look at the power monitoring landscape, click on the Show Panel button to access the Power Monitor panel (Figure 122). Note: The panel can be accessed directly from the Devices view by right-clicking on the icon for the NB2DSK01 and choosing Show Power Monitor Panel from the context menu. The panel gives you a breakdown of current and power values for each monitored power line, grouped by destination (daughter board, peripheral board, User Header). The total power usage in each group is also given. In addition to the total power usage across all monitored power lines for the entire system, the panel also gives a breakdown of: • Total power usage, per power supply

• Total voltage, per power supply Figure 122. Use the Power Monitor panel to get a detailed view of • Total current drawn, per power supply. the currents drawn and the power used across all monitored lines. As with the instrument panel, the option to enable/disable polling is

TR0143 (v2.0) May 26, 2008 77 Legacy documentation refer to the Altium Wiki for current information Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01 provided, as well as the ability to define the polling interval – the period between accessing current measurements from the NanoBoard itself (more specifically, the firmware on the NanoTalk Controller). By default, this value is set to be 1000ms. Unlike the instrument panel however, if polling is disabled, you can still manually update the monitored information displayed within the Power Monitor panel. Remember that polling is simply the automatic retrieval and update of monitored values. The power monitoring itself – the hardware on the motherboard – is permanently functional! Further options are available in the Power Monitor Options dialog (Figure 123). This dialog can be accessed from both the instrument panel and the Power Monitor panel, by clicking the Options button. The dialog provides another place in which to define the polling interval. It also allows you to specify the voltage that is applied to the User Headers. This is required if you have not selected either 3.3V or 5V on the NB2DSK01 itself, through use of jumper placement on the associated configurable jumper headers for 'User Header A' (JP4) and 'User Header B' (JP5), respectively. If you have placed a jumper to select the voltage, the setting in the dialog should match that selection, in order to gain accurate power calculations for these lines. The dialog also offers graphing options. This relates to the graphical display of power monitoring information, which is considered in the next section. Figure 123. Setup power monitoring options as required. Graphical Display of Monitored Information Display of power monitoring information in tabular format is good, but a visual representation of the values over time is far more engaging and readable. To this end, the power monitoring facility offers the ability to display the monitored information graphically. All information available in the Power Monitor panel can be enabled for display in a number of charts within Altium Designer's Sim Data Editor. Use the Graphing Options region of the Power Monitor Options dialog (refer back to Figure 123) to enable the charts required. Graphing itself is only possible provided polling is enabled. Graphing can be started/stopped in a number of ways: • From the NanoBoard's Instrument panel – either use the Start Graphing button (which changes to Stop Graphing button) or the Graphing LED, to toggle graphing ON/OFF. • From the Power Monitor panel – use the Enable Graphing option to toggle graphing ON/OFF. Once enabled, the monitored data and resulting waveforms will be written to a Simulation Data File (*.sdf) and displayed within a multi-tabbed waveform analysis window – presented in the Sim Data Editor. Figure 124. Start graphing the data for the monitored power lines. Figure 125, on the next page, illustrates graphing of results for a Desktop NanoBoard that has three peripheral boards and a daughter board attached. As can be seen, each chart is available on a separate tab. The active chart in this case is the Summary chart, which contains two plots. The first plot – entitled Power Summary – contains waveforms for: • The total power usage for the Desktop NanoBoard system (all 19 monitored power lines), labeled Total • The total power usage for the daughter board • The total power usage for Peripheral Board A • The total power usage for Peripheral Board B • The total power usage for Peripheral Board C • The total power usage for the two User Headers The second plot – entitled Temperature – contains a single waveform for the temperature of the system.

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Figure 125. Charts, wave plots and waveforms, all displayed in the integrated Sim Data Editor. Using the power monitoring facility, you can quickly compare power usages for different hardware configurations on the Desktop NanoBoard. Figures 126 and 127 compare two configurations – with and without peripheral boards attached. In each case, the graphical results focus on the total power consumption across the system, as well as the power consumption and current drawn for each main power rail (1.2V, 1.8V, 2.5V, 3.3V and 5V).

Figure 126. System power and current waveforms – NB2DSK01 with daughter board (DB30) attached only.

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Figure 127. System power and current waveforms – NB2DSK01 with daughter board (DB30) and three peripheral boards (PB01, PB02, PB03) attached. Looking at Figures 126 and 127, we can see that addition of the peripheral boards to the system has increased the total power consumption and that this is due to increased power on the 3.3V and 5V rails. If we had looked across the individual peripheral board waveforms, we would have found that the board plugged into the 'PERIPHERAL BOARD C' connector was indeed responsible for much of the power increase. The board was in fact the PB01 Audio/Video Peripheral Board which, when considering its size and larger number of on-board devices, easily explains the result! The comparison can be extended to see the effect on power consumption when the physical FPGA device on the daughter board is programmed with a design (Figure 128).

Figure 128. System power and current waveforms – NB2DSK01 with daughter board (DB30) and three peripheral boards (PB01, PB02, PB03) attached. A design has been downloaded into the FPGA device on the daughter board.

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The total power consumption for the system has, as expected, increased. This increase is from the extra power consumed by the 3.3V power rail (by the daughter board). Figure 129 shows the jump in daughter board 3.3V power usage at the point where the design is downloaded into the FPGA device.

Figure 129. Increase in 3.3V power consumption at the point where the physical FPGA device on the daughter board is programmed with the design. The Sim Data Editor provides a wealth of features for waveform manipulation. For example, you can change the display by moving waveforms between plots and between charts. You can change X and Y axes, change the appearance of waveforms, and take measurements – either for a single waveform or between waveforms. For more information on the workings of the Sim Data Editor and the feature-rich analysis environment it has to offer, refer to the document AP0106 Working with the Sim Data Editor.

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Updating the NanoBoard firmware

The Desktop NanoBoard NB2DSK01 uses a Xilinx Spartan-3 device (XC3S1500-4FG676C) as the controller for the board. Referred to as the NanoTalk Controller, this device (designated U5) communicates with the host PC using Altium's NanoTalk communications protocol. It is responsible for managing JTAG communications with the following: • Parallel PC interface • USB PC interface • System JTAG header • FPGA daughter board • Peripheral boards • Master/Slave daisy-chain • User Board headers The NanoTalk Controller also manages/communicates with the following areas of the board: • Host status LEDs • 1-Wire memory devices (used for identification) on motherboard, daughter board, peripheral boards and Desktop Stereo Speaker Assembly NB2DSK-SPK01 • TFT LCD panel and the following SPI-based resources: • Touch Screen Digitizer • SPI Master clock • SPI Flash memory • Real-Time Clock (RTC) • SPI resources on peripheral boards • SPI-compatible LED drivers on the attached Desktop Stereo Speaker Assembly NB2DSK-SPK01 It is the NanoTalk Controller into which the intelligence of the system – the NanoBoard firmware - is programmed. This upgradeable firmware is stored in a Xilinx Platform Flash Configuration PROM device (XCF08PFS48C), designated U7 on the board. On power-up, the firmware is automatically loaded from the Configuration PROM into the NanoTalk Controller. Note: The version of firmware currently loaded into the Configuration PROM can be identified in two places. Firstly, underneath the icon for the NanoBoard in the NanoBoard chain of the Devices view (View » Devices View). Secondly, from the TFT LCD panel on the NB2DSK01 motherboard itself. Pre-update preparation Before the new version of firmware can be downloaded to the Configuration PROM, the Desktop NanoBoard NB2DSK01 must first be prepared as follows: 1. Turn off the NB2DSK01. 2. Connect from the PC to the 'SYSTEM JTAG' header on the NB2DSK01 (at the left-hand edge of the board). This is a fixed function header which, when used, switches control of the NB2DSK01 from the NanoTalk Controller to a simple hardware chain, which involves the NanoTalk Controller and the Configuration PROM. Connection to the 'SYSTEM JTAG' header involves the use of Altium's Universal JTAG Interface, to convert from parallel or USB cabling to 10-way IDC JTAG cabling. This interface device, along with various connection cables, is shipped with the Altium Designer software. If you do not have this interface, or it appears damaged, Figure 130. The Universal JTAG Interface facilitates please contact your nearest Altium Sales & Support representative. connection to the 'SYSTEM JTAG' header. Note: The selector switch on the Universal JTAG Interface is used only when programming a JTAG device from Altera Quartus II or Xilinx ISE tools directly, and via their associated parallel cabling. The switch position has no relevance when programming the Configuration PROM from Altium Designer. 3. Power-up the NB2DSK01.

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Downloading the new firmware Within Altium Designer, open the Devices view (View » Devices View), if not already open. Ensure that the Live option is enabled as this activates the auto-board-recognition system. With the connection to the 'SYSTEM JTAG' header in place, the Configuration PROM device will appear in the Hard Devices chain, as shown in Figure 131 .

Figure 131. Accessing the Configuration PROM device. The configuration for the device is stored in a PROM file, using the Intel MCS-86 format. This is an ASCII hex file with extension .mcs. To download the new configuration: 4. Right-click on the icon for the Configuration PROM in the Hard Devices chain of the Devices view and select Choose File and Download from the pop-up menu. 5. The Choose Programming File For Xilinx XCF XCF08PFS48C dialog appears. Use this dialog to navigate to the required programming file ( *.mcs) and click Open. By default, this file is located in the \System folder of the Altium Designer installation. The download will proceed, with progress shown in Altium Designer's Status bar. The process actually consists of device erasure, device programming, and then verification of programming. At the end of the cycle, an information dialog will appear with the result of the download. Successful programming is reflected in the text beneath the device's icon changing to Programmed. If any errors occur during the download, a warning dialog will appear. If this happens, power-down the NB2DSK01 for a few seconds and then run the download process again. Downloading program code The .mcs file downloaded to the Configuration PROM contains the FPGA design destined to reside on the NB2DSK01 motherboard's Spartan-3 FPGA device (the NanoTalk Controller). Within that design is a TSK3000A processor, the embedded code for which also needs to be downloaded as part of the overall process of updating the firmware on the NanoBoard. The .mcs file contains the portion of embedded code that is to reside in Block RAM within the NanoTalk Controller. The remainder of the embedded code must be saved into the common-bus Flash memory resident on the motherboard. To do this, perform the following: 6. Cycle the power for the NB2DSK01. The TFT LCD panel will show the current version of firmware loaded into the Configuration PROM. As the embedded code in the Flash memory will not be the same version the message ' Program code is not present in flash or is out of date ' will be displayed. In addition, the text underneath the icon for the Configuration PROM will change to Read Protected. 7. From the Devices view, access the Program NB2 Firmware command from the main Tools menu. 8. From the subsequent Choose NB2 firmware hex file dialog that appears, locate the required embedded object file (*.hex) and click Save. By default, this file is also located in the \System folder and will typically have the same name as the .mcs file.

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9. After a short delay, text will appear on the TFT LCD panel, showing first that the Flash memory is being erased, and then that the embedded code is being downloaded. Once the download has finished, the total number of bytes downloaded will be displayed. 10. Press any of the NB2DSK01's generic user switches, located below the TFT LCD panel. The firmware will be rebooted and the embedded code stored in the Flash memory will be loaded into SRAM on the motherboard. Testing the NB2DSK01 Once the Configuration PROM device has been successfully programmed and the corresponding Hex file has been loaded into the Flash memory, the new firmware can be tested as follows: 1. Power-down the NB2DSK01. 2. Remove the cable from the 'SYSTEM JTAG' header. 3. Re-connect the NB2DSK01 to the PC, using either the parallel port or the USB port. 4. Power-up the NB2DSK01. 5. Ensure that the Live option (in the Devices view) is enabled, to activate the auto-board-recognition system. 6. In the Devices view, press F5 (Refresh). This forces a scan of the hardware to detect which devices are currently connected. The NanoTalk Controller for the connected NB2DSK01 should automatically be detected and an icon for the board appear in the NanoBoard chain (the top chain in the Devices view). The FPGA device on the daughter board should be automatically detected and appear in the Hard Devices chain (the middle chain in the Devices view). Figure 132 illustrates detection of an NB2DSK01 which has a Xilinx Spartan-3 daughter board (DB30) attached.

Figure 132. Successful detection of Desktop NanoBoard NB2DSK01 and target FPGA device. 7. Open an FPGA project that includes one or more Nexus-enabled devices (e.g. processors, counters, logic analyzers) and that is appropriately configured to target the FPGA device on the DB30 daughter board. Go ahead and program the FPGA on the daughter board. This will test that the Soft Devices JTAG chain is functioning correctly (presented as the bottom chain in the Devices view, once the design is downloaded into the target physical device).

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Figure 133. Successful communications with a Nexus-enabled device in the Soft Devices JTAG chain. 8. With the chosen design running in the FPGA, double-click on the icon for the NB2DSK01 (in the NanoBoard chain of the Devices view). The Instrument Rack – NanoBoard Controllers panel will appear. Use the instrument panel to change the system clock frequency. This will write the new clock frequency to the system clock, which, being an SPI device, will test that communication to SPI devices is working correctly.

Figure 134. Reprogramming the SPI-based programmable system clock. As well as writing the new frequency to the clock, the value will also be stored in the common-bus Flash memory and read back by the NanoTalk Controller to verify the change. As the new frequency is stored in the Flash memory, it is persistent across both design sessions and hardware sessions. Therefore, closing Altium Designer, relaunching and opening an FPGA project (or cycling the NB2DSK01'S power) will result in the last clock frequency entered being used.

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Index

1 audio power amplifier ...... 30 1-Wire ...... 31, 36, 55, 57 Audio Test ...... 32 1-Wire board identification system...... 71 auto-configuration...... 70, 72, 74 A B Actel...... 13 battery ...... 11, 35 Activate License...... 12, 14 battery backup...... 35 ADC/DAC/I2C ...... 44 Board communications...... 3 Altera ...... 13 Boot memory ...... 40 Altium Board Identifier ...... 71 Booting from an SD card ...... 62 ...... 72 Booting from SPI Flash memory...... 62 ...... 71 Accessing Flash memory controls ...... 62 ...... 71 Downloading to Flash memory ...... 64 ...... 72 Erasing the Flash memory ...... 63 Altium Designer ...... 3, 14, 23, 28, 82 Verifying the download...... 65 Devices view ...... 15 Boundary Scan Description Language ...... 4, 33 Home view ...... 14 BSDL...... 4, 33 Altium Designer panels bus joiner...... 49 Instrument Rack – Hard Devices...... 33 Buzzer signal...... 52 Instrument Rack – NanoBoard Controllers...... 85 C JTAG Viewer ...... 33 cable Knowledge Center...... 1 audio loop ...... 11 Projects ...... 16 JTAG flying-lead ...... 11 analog mixer ...... 30, 32 JTAG ribbon...... 11 analog-to-digital ...... 44 NanoBoard daisy-chain...... 11 audio parallel ...... 11, 13 analog mixer...... 30 USB ...... 11, 13 bridged ...... 31 User I/O ...... 11 daughter board FPGA Buzzer signal...... 30 CAN...... 42 DC volume control...... 31 Dominant state...... 42 headphones ...... 31 High Speed ...... 42 Line In ...... 30 Recessive state ...... 42 Line Out...... 31 Slope Control ...... 42 Mic In...... 30 CAN bus ...... 42 mixer test points ...... 30 CAN in Automation Draft Standard...... 42 NanoTalk Controller Line Out...... 30 CAN port...... 42 peripheral board connector Line Out...... 30 CAN Transceiver ...... 42 single-ended...... 31 changing daughter boards...... 56 stereo audio power amplifier ...... 30 changing peripheral boards ...... 59 stereo speakers...... 31 Choosing the JTAG connection...... 16 test signal ...... 30, 32 CiA DS102...... 42 Audio amplification...... 30 clock audio jacks...... 30 programmable...... 39 Audio loop cable ...... 11 system ...... 39 Audio Player ...... 66 Common-Bus Flash memory...... 25

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Common-Bus SDRAM...... 25 Desktop NanoBoard NB2DSK01...... 1, 70 Common-Bus SRAM ...... 25 Desktop NanoBoard NB2DSK01 resources ...... 20 compatibility...... 9 Desktop Stereo Speaker Assembly NB2DSK-SPK01 ...... 14 configuration ...... 69 Devices view ...... 3, 15, 16, 33, 83, 84 Configuration ...... 16 compiling...... 17 Configuration Manager ...... 74 downloading...... 17 configuration PROM ...... 5 place and route ...... 17 Configuration PROM...... 24, 82 Process Flow ...... 17 Configuring the project...... 72 Results Summary...... 17 Connecting synthesizing ...... 17 multiple Desktop NanoBoards...... 5 digital-to-analog...... 44 NB2DSK01 and NB1...... 9 direct interaction ...... 60 production PCBs ...... 6 Downloading a test project to the Desktop NanoBoard connection problems...... 19 NB2DSK01 ...... 16 connector DPNO...... 51 daughter board...... 54 E peripheral board ...... 27 EIA-574 standard ...... 41 constraint files...... 69 electrostatic discharge...... 9 Constraint files electrostatic protection...... 10 Daughter board ...... 70 Embedded memory ...... 40 Daughter board-to-motherboard interface...... 70 ESD...... 9 NB2DSK01 motherboard...... 70 ESD pad...... 9 Peripheral board...... 70 ESD prevention Peripheral board-to-motherboard interface ...... 70 Air Ionization ...... 10 Controller Area Network...... 42 Antistatic Chair...... 10 crystal ...... 35 Antistatic Clothing ...... 10 Current monitoring ...... 21, 75, 76 Common Point Ground ...... 10 current sense amplifiers...... 21, 76 Conductive Shoes...... 10 D Foot Strap ...... 10 daisy-chain...... 11, 29 Protective Floor Surface ...... 10 daisy-chain connector...... 11 Protective Work Surface ...... 10 daughter board ...... 1, 13, 17, 21, 38, 54, 70 Wrist Strap ...... 10 1-Wire bus interface ...... 55 ESD prevention techniques ...... 10 FPGA control signals...... 56 EXAMPLE file...... 62, 65 Hard JTAG signals ...... 54 F identification signals ...... 55 firmware...... 5, 24, 60, 82 Power LED ...... 54 downloading...... 83 power signals ...... 55 program code...... 83 Program LED ...... 54 testing ...... 84 Soft JTAG signals ...... 55 Firmware GUI SPI bus interface...... 55 Bootstrapping the daughter board FPGA...... 62 daughter board connectors ...... 27, 54 Browsing Flash memory and SD card content...... 66 DC volume control ...... 30, 32 Bypassing JTAG devices ...... 67 Debug headers ...... 34 Changing system clock frequency ...... 67 Delta-Sigma DAC ...... 30 Downloading example designs stored on an SD card...65 design interface components...... 38 Driving the GUI ...... 60 GUI options...... 61

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introductory screens...... 61 Soft Devices...... 84 Real Time Clock (RTC) ...... 68 JTAG communications ...... 82 Screen Saver ...... 61 JTAG extender headers ...... 32 Sounds...... 61 JTAG flying-lead cable ...... 11 Test Routines ...... 68 JTAG ID Mapping...... 33 FPGA...... 38 JTAG ribbon cable...... 11 FPGA I/O ...... 38 JTAG Viewer panel ...... 33, 34 FPGA vendor tools ...... 13, 17 K G Knowledge Center panel ...... 1 Generic JTAG device...... 4, 33 L generic port component ...... 53 Lattice...... 13 generic switch inputs ...... 51 LCD ...... 46 Generic user switches...... 51 LEDs graphical user interface...... 60 Host status...... 26 GUI ...... 60 License Management ...... 12, 14 H Line In...... 32 Hard Devices chain...... 4, 33, 83 Line Out...... 32 Hard Devices JTAG chain...... 19, 84 Live option...... 15 Hard JTAG...... 23, 32, 33 Live Update ...... 33 header M Debug...... 34 mains power ...... 11 I2C extension ...... 45 manual scan ...... 19 NanoTalk Master...... 29 Mapping constraint file...... 70 NanoTalk Slave...... 29 memory card ...... 35 TFT LCD panel...... 46 microphone...... 30, 32 User board ...... 32 microphone amplifier ...... 30 User I/O...... 50 motherboard ...... 1, 20, 38, 54 headphones ...... 31, 32 multiple SPI/I2C devices...... 53 Home screen ...... 60 multiplexed JTAG link...... 28 Home view...... 14 N I NanoBoard chain...... 3 I2C ...... 44, 53 NanoBoard Configuration dialog ...... 72 I2C bus ...... 44 NanoBoard daisy-chain cable...... 11 ID Code...... 33 NanoBoard JTAG chain...... 19, 84 Identifying system hardware ...... 70 NanoBoard Reset...... 36 IEEE Standard 1149.1 ...... 3 NanoBoard-NB1 ...... 9, 42 image files...... 66 NanoBoard-PC interface Independent SRAM ...... 26 Parallel port...... 28 Instruction Register Length...... 33 USB port ...... 28 Instrument Rack – Hard Devices panel ...... 33 NANOCONNECT ...... 27, 54, 57 Instrument Rack – NanoBoard Controllers panel...... 85 NanoTalk...... 5, 6, 82 J NanoTalk Controller...... 5, 25, 35, 82 JTAG...... 3 NanoTalk Master ...... 29 JTAG chains NanoTalk Slave ...... 29 Hard Devices...... 84 NB2DSK01 ...... 1, 70 NanoBoard ...... 84 NB2DSK01 block diagram...... 8

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NB2DSK01 Constraint system...... 69 SPI_BUS...... 53 NB2DSK-SPK01 ...... 21, 31, 70 TEST_BUTTON...... 51 Nexus...... 4, 18, 52 TFT_LCD ...... 48 Nexus driver...... 33 TOUCH_SCREEN_DIGITIZER ...... 48 NEXUS_JTAG_PORT ...... 52 USER_BUTTON0 ...... 51 O USER_BUTTON1 ...... 51 overview...... 8 USER_BUTTON2 ...... 51 P USER_BUTTON3 ...... 51 Parallel cable ...... 11, 13 USER_BUTTON4 ...... 51 Parallel port connection ...... 13 USER_BUTTONS...... 51 parallel port header...... 28 port components...... 38 PC to NanoBoard connection ...... 14 Power ...... 21 peripheral board...... 1, 56, 57, 70 power connectors ...... 13 1-Wire bus interface ...... 58 power consumption ...... 79 Audio signals...... 58 Power Monitor panel ...... 77 Clocking ...... 58 Power Monitoring ...... 75 I2C interface...... 58 Access ...... 77 Identification signal...... 57 Graphical Display...... 78 JTAG signals...... 57 Options ...... 78 Power signals...... 58 Sim Data Editor...... 78 SPI bus interface...... 58 Power supply module ...... 11 Peripheral board connectors...... 27 power supply test points...... 22 Platform Flash...... 24, 82 processors...... 18 port programmable clock ...... 39 CAN...... 42 Projects panel...... 16 parallel...... 28 PROM...... 5 PS/2 Keyboard ...... 44 PS/2...... 44 PS/2 Mouse...... 44 PS/2 Keyboard port ...... 44 RS-232...... 41 PS/2 Mouse port...... 44 System JTAG ...... 24 R USB...... 28 regulated supply ...... 21 Port component Resources accessible from an FPGA design ...... 38 ADCDAC_I2C ...... 46 RGB LEDs...... 21, 31 CANCNTR...... 43 RS-232 ...... 41 CLOCK_BOARD ...... 39 RS-232 serial interface...... 41 CLOCK_REFERENCE...... 39 RS-232 Transceiver ...... 41 CLOCK_SUPPLY...... 39 RTC...... 35 DIPSWITCH ...... 49 S I2C_BUS ...... 53 SD ...... 35 LED ...... 49 SD card reader ...... 35 NEXUS_JTAG_CONNECTOR...... 52 SD memory card ...... 62 PS2A...... 44 Secure Digital ...... 35 PS2B...... 44 Setting up the Desktop NanoBoard NB2DSK01...... 11 RS232CNTR ...... 41 Soft Devices chain...... 4, 18, 52 SERIALFMEMORY ...... 40 Soft JTAG...... 23, 32 SPEAKER ...... 52 Sound input ...... 30

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Sound output ...... 31 touch screen...... 46 Spartan-3...... 24 Touch Screen Digitizer ...... 46 SPI...... 3, 23, 39, 53, 85 Transmissive Color...... 46 SPI Flash memory ...... 62 Troubleshooting...... 19 SPI Flash memory ...... 40 TSK3000A ...... 36 SPI Real-Time Clock ...... 35 U SPNO...... 36, 50 Universal JTAG Interface ...... 24, 82 Stereo Audio ...... 30 Updating the NanoBoard firmware ...... 82 Stereo Speaker Assembly ...... 31 USB stylus...... 18 supervisory reset circuit ...... 28 switch transient voltage suppressor...... 28 daughter board Test/Reset...... 50 USB transceiver...... 28 DIP-switch ...... 48 USB cable ...... 11, 13 generic ...... 51 USB connection...... 13 NanoBoard Reset...... 36 user board ...... 33 System Clocks ...... 39 User Board headers ...... 32 SYSTEM JTAG...... 83 User DIP-switch...... 48 System JTAG programming port ...... 24 User I/O connector cable...... 11 System requirements...... 12 User I/O headers ...... 50 T User LEDs ...... 49 TDI...... 4 V TDO ...... 4 Vendor Resources...... 13 Test / Reset ...... 50 Vendor tools TFT LCD panel ...... 18, 21, 46 Actel Designer ...... 13 contrast control...... 46 Actel Libero IDE...... 13 Digitizer interrupt ...... 47 Altera Quartus II...... 13 power supplies ...... 46 Altera Quartus II Web Edition ...... 13 SPI interface signals ...... 47 Lattice ispLever...... 13 touch screen...... 46 Xilinx ISE ...... 13 Touch Screen Digitizer...... 46 Xilinx ISE WebPACK ...... 13 TFT touch screen calibration ...... 60 virtual instruments ...... 18 The Hard Devices chain...... 4 W The NanoBoard chain...... 3 Working with multiple FPGAs ...... 53 The Soft Devices chain...... 4 X Thin Film Transistor ...... 46 Xilinx...... 13

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Revision History

Date Version No. Revision

01-Nov-2007 1.0 Initial release.

30-Jan-2008 1.1 Updated for Altium Designer 6.9

26-May-2008 2.0 Updated for Altium Designer Summer 08

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