Environmental Challenges for 45-Nm and 32-Nm Node CMOS Logic

Environmental Challenges for 45-nm and 32-nm node CMOS Logic

Sarah Boyd, David Dornfeld Nikhil Krishnan, Mehran Moalem Dept. ofMechanical Engineering Applied Materials University of California, Berkeley Santa Clara, CA, USA Berkeley, CA, USA sboyd @ me.berkeley.edu

Abstract- The objective of this work is to understand the the 1980's grew to include tungsten, titanium, copper and materials and energy requirements, and emissions associated tantalum in the 1990's. In the past few years, however, dozens with new semiconductor manufacturing technology nodes. of new elements as well as a broad array of highly tailored Current and near-future CMOS technologies (for the 45-nm and compounds have been integrated into the process flow or are 32-nm nodes) are investigated using an inventory based on being considered as tools to overcome the challenges of current bottom-up process data. The process flow of the CMOS chip is leakage and tunneling, or to build novel geometrical modeled by updating an existing inventory analysis (for 130 nm arrangements, in order to achieve ever smaller devices. node devices) to include strained Si channels, metal gates, 10 layers of interconnect and high-k gate dielectrics used in 45-nm and 32-nm CMOS nodes. Conclusions are made concerning emissions of new materials and trends in life cycle energy consumption of logic devices. Keywords - Life Cycle Inventory, Life Cycle Assessment, * Environmental Management

I. INTRODUCTION The semiconductor industry is a large and growing segment of the global economy which, throughout its history, has been...... challenged by the impacts of its operations on human and environmental health. These challenges have included the hazards of process gases (silane, phosphine, diborane), the release of ozone depleting chloro-fluorocarbons, dumping of untreated fluorine wastes, poisoning of groundwater with mercury, the under-forecasting of facility water demands resulting in serious water shortages (e.g. in Taiwan) and more Figure 1: Rapid expansion ofelements used in semiconductor manufacture. recently the release of potent global warming perfluorinated Blue elements represent elements first used in the 1980s. Elements in green, gases into the atmosphere. The industry has repeatedly had to the 1990s, and those in red came into use in the 2000s. Credit: F. Robertson make costly changes in the form of process changes and equipment retrofits, materials substitutions, installation of The result ofthis material-dependent technology progress is abatement systems or remediation due to these unforeseen that a larger number, as well as entirely new classes of problems. Looking into the future, several new environmental materials will be emitted into the environment by questions emerge for the industry, as the range of chemicals semiconductor fabs. It is therefore more important than ever to used in production expands. Potential environmental impacts assess the environmental impact of process technologies before associated with novel semiconductor process technologies they are ramped up into full scale production. should be investigated, so that costly manufacturing setbacks can be averted, and to bring quantitative measures of II. METHODS prospective future environmental damages into current This paper gives selected results from the 45-nm and 32-nm manufacturing decision-making. node technology update to an existing detailed life cycle Maintaining and improving device performance while inventory model of the process flow of a CMOS device [7]. reducing size and scale of critical device features (in line with Data are taken from emissions characterization studies and Moore's Law) requires an increasingly broader palette of power measurement reports performed at Applied Materials. materials. Historically, the range of process materials has Emissions characterization is performed using FT-JR and QMS expanded only slightly: a short list of only about 12 elements in Sponsored by the Environmental Protection Agency

1-4244-0861-X/07/$25.O0 2007 IEEE 102 measurement providing data with an upper bound error of+±- deposition results in emissions of NH3, DMA and petra- 10%. Power measurement data has an upper bound error of±/- dimethyl amine tantalum (PDMAT). Tungsten deposition 2.5%. processes emit quantities of SiH4, WF6, SiF4, CF4, HF and F2 which may be abated using bum-and-scrub systems. Emissions III. NEW PROCESSES associated with Ru deposition include bis(2,4 dimethyl The 45-nm and 32-nm process flows are a composite of the pentadienyl) ruthenium (DMRu), CH3, CO2 and CO. technology choices of several leading manufacturers [8, 9, 10] D. Sea/in Interconnects ALD ofBarrier as well as industry expectations for near future device scaling g [11]. Some logic manufacturers are meeting the 45-nm node The thickness offththeirinterconnect barrier layer plays a part through strain engineering alone [10][12], while others are in determininginterconnectresistivity atagiven scale Atomic introducing high-k gate dielectrics and metal gates in this layer deposition (ALD) of the TiN barrier layer may be generation [15]. Interconnect scaling will proceed at either introduced to achieve thinner barriers, decreasing line node with the incorporation of barrier ALD. New process resistance. Material inputs would be about the same between technologies specific to the 45-nm and 32-nm node which PVD and ALD, but step duration is lengthened for ALD, with a involve environmentally significant materials are described as resultant increased electricity demand. follows. E. Additional Metal Layers A. Strained Silicon A typical high performance logic chip at the 45 nm node is Strained Si technology is the enhancement of carrier designed with 12 layers of interconnect, versus 6 or 8 metal mobility in the MOS channels through straining of the Si layers of 130 nm and 90 nm devices, and 10 layers for 65 nm lattice. For PMOS, a layer of Si is epitxially grown on top of a devices. Adding each additional 2 metal layers adds 34 steps to SiGe layer, to compressively strain the Si channel. The the process flow and 82 kWh per wafer in production discrepancy in lattice constants between crystalline SiGe and Si electricity, as well as 37 kg oftotal chemical inputs. causes the epitaxial Si to become axially distorted, enhancing hole mobility in the PMOS channels. Similarly, for NMOS, Si F. Shift to Low-k Dielectric may be subjected to tensile strain through the use of SiN at the In order to control circuit delay and cross-talk, advanced channel edge to enhance electron mobility. Higher directional low-k dielectrics are taking the place of undoped and fluoro- carrier mobility overcomes the limitations of high dose silicate glass as intra-layer and inter-metal dielectrics. Etching implantation and short channel effects of scaling. these organo-silicates requires fluorinated precursors and Germane (GeH4), tetra-chloro-silane (TCS), di-chloro- results in substantial global warming PFC emissions. Even with silane (DCS) and HC1 are used in epitaxial growth of SiGe the use of lower-emission remote plasma NF3 clean, the shift to film; Chamber cleaning for silicon and germanium compounds low-k, combined with the increase in the number of metal may be achieved using HC1. Emissions from epitaxial SiGe layers, results in a significant increase in PFC emissions at the deposition include GeH4, SiH4ETCS DCS,includeHCl and Cl2. 45 and 32 nm nodes. This ongoing trend has been studied in deposition GeH4' S4TCSDCSHCIanprevious literature [16, 17]. PFC emissions from dielectric etch can be abated bum-and-scrub B. High-kgate Dielectric technologies.effectivelyUsing the currentusinglifepoint-of-usecycle inventory model, the Several options exist for high-k gate dielectrics, with two additional two layers of interconnect will produce 33 leading options being HfO2 and HfSiOx. Deposition of HfO2 kgCE/wafer in direct global warming emissions, or 6.7 results in emissions of tetrakis (diethylamido) hafnium kg/wafer using combustion and water scrubbing point-of-use (TDEAH), di-ethyl amine (DEA), quartemary ammonium salt abatement. (H2NEt2+OH-) and 02. HfSiOX deposition emits TDEAH, tetrakis (dimethylamido) silane (TDMAS), DEA, di-methyl IV. NEW MATERIALS amine (DMA), C2H4, C2H2, CO and CO2. TDEAH, TDMAS, DEA, DMA, PDMAT, HfCl4, and Etching of HfO2 and HfSiOX is performed using chlorine DMRu would all be new to semiconductor fab emissions. A chemistries similar to those used for Si etch and these steps hypothetical fab producing 300mm, 32 nm node wafers with produce chlorinated gaseous emissions that are not new to HfSiOx gate dielectric, TaN NMOS and Ru PMOS electrodes, semiconductor facilities. Solid compounds are also produced, operating at 7,500 wafer starts per week, would, without including HfCl4, which accumulate in pump and abatement abatement, emit totals of each compound as given in Tables I lines and which may become suspended in wafer clean and II. It is important to note that this process flow is wastewater or water waste from point-of-use abatement. h ande has imp lemteat this time. upper bound for these solid emissions, assuming that all chlorine not accounted for in gaseous emissions is converted to HfCl4, is 103 kg/year. C. Metal Gate Electrodes Gate electrode materials which are potentially compatible with HfO2 gate oxides include TaN, W and Ru. TaN

1-4244-0861-X/07/$25.O0 2007 IEEE 103 TABLE I. SELECTED GASEOUS EMISSIONS FOR 32 NM PROCESS FLOW achievable standby power and potential decreased electricity throughout the lifetime of the though high Mass of GaseousEmuse device, performance chips with higher operational frequency will Compound Per wafer (g) Per annum (kg) demand roughly the same use phase power as previous TDEAH 3.3 x 10-4 0.13 generations. TDMAS l.Ox 104 0.04 A full cradle-to-gate inventory of material and energy demands, as well as emissions will follow in future work. DEA 4.2 x 10-3 1.6 DMA 1.5 x 10-2 5.9 ACKNOWLEDGMENT DMRu 27 1.0x 104 Special thanks to Sebastien Raoux of Transcarbon International Corp. This project is supported by Applied Materials and the Environmental Protection Agency (EPA) under grant #RD-83 145601. TABLE II. SELECTED SOLID EMISSIONS FOR 32 NM PROCESS FLOW

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