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RC Snubber Networks For Thyristor Power Control and Transient Suppression http://onsemi.com

By George Templeton APPLICATION NOTE Thyristor Applications Engineer

INTRODUCTION

Edited and Updated

RC networks are used to control voltage transients that ǒdVǓ DEVICE PHYSICS could falsely turn-on a thyristor. These networks are called dt s snubbers. Static dV turn-on is a consequence of the Miller effect The simple snubber consists of a series resistor and dt capacitor placed around the thyristor. These components and regeneration (Figure 1). A change in voltage across the along with the load inductance form a series CRL circuit. junction capacitance induces a current through it. This cur- Snubber theory follows from the solution of the circuit’s rent is proportional to the rate of voltage change ǒdVǓ . It differential equation. dt Many RC combinations are capable of providing accept- triggers the device on when it becomes large enough to able performance. However, improperly used snubbers can raise the sum of the NPN and PNP transistor alphas to unity. cause unreliable circuit operation and damage to the semi- conductor device. A Both turn-on and turn-off protection may be necessary A for reliability. Sometimes the thyristor must function with a I IA BP PE range of load values. The type of thyristors used, circuit V PNP configuration, and load characteristics are influential. I CJ I I 1 P J CP NB CJ Snubber design involves compromises. They include N C C I J CN I2 dv I G P cost, voltage rate, peak voltage, and turn-on stress. Practi- J dt B cal solutions depend on device and circuit physics. NPN G t IB N NE IK dV CJ dV K + dt STATIC IA * a ) a dt 1 ( N p) K TWO TRANSISTOR MODEL CJ OF C + INTEGRATED dV EFF 1*(aN)ap) WHAT IS STATIC ? SCR STRUCTURE dt Static dV is a measure of the ability of a thyristor to dt retain a blocking state under the influence of a voltage dV Figure 6.1. ǒ Ǔ Model transient. dt s

© Semiconductor Components Industries, LLC, 2008 1 Publication Order Number: June, 2008 − Rev. 3 AN1048/D AN1048/D

170 CONDITIONS INFLUENCING ǒdVǓ dt s 150 Transients occurring at line crossing or when there is no MAC 228A10 130 initial voltage across the thyristor are worst case. The col- VPK = 800 V lector junction capacitance is greatest then because the μ 110 depletion layer widens at higher voltage. dt

dV 90 Small transients are incapable of charging the self- capacitance of the gate layer to its forward biased threshold 70 STATIC (V/ s) STATIC voltage (Figure 2). Capacitance voltage divider action 50 between the collector and gate-cathode junctions and built- in resistors that shunt current away from the cathode emit- 30 ter are responsible for this effect. 10 25 40 55 70 85 100 115 130 145

TJ, JUNCTION TEMPERATURE (°C) 180 dV Figure 6.3. Exponential ǒ Ǔ versus Temperature 160 dt s MAC 228A10 TRIAC 140 TJ = 110°C ǒdVǓ FAILURE MODE μ 120 dt s 100 Occasional unwanted turn-on by a transient may be dt dV acceptable in a heater circuit but isn’t in a fire prevention 80 sprinkler system or for the control of a large motor. Turn-on STATIC (V/ s) STATIC 60 is destructive when the follow-on current amplitude or rate 40 is excessive. If the thyristor shorts the power line or a charged capacitor, it will be damaged. 20 0 100 200 300 400 500 600 700 800 Static dV turn-on is non-destructive when series imped- dt PEAK MAIN TERMINAL VOLTAGE (VOLTS) ance limits the surge. The thyristor turns off after a half- dV dV Figure 6.2. Exponential ǒ Ǔ versus Peak Voltage cycle of conduction. High aids current spreading in the dt s dt thyristor, improving its ability to withstand dI. Breakdown dt turn-on does not have this benefit and should be prevented. Static dV does not depend strongly on voltage for opera- dt tion below the maximum voltage and temperature rating. 140 Avalanche multiplication will increase leakage current and 120 reduce dV capability if a transient is within roughly 50 volts MAC 228A10 dt 100 800 V 110°C of the actual device breakover voltage. μ A higher rated voltage device guarantees increased dV at 80 dt dt dV lower voltage. This is a consequence of the exponential rat- 60 ing method where a 400 V device rated at 50 V/μs has a

STATIC (V/ s) STATIC 40 RINTERNAL = 600 Ω higher dV to 200 V than a 200 V device with an identical dt rating. However, the same diffusion recipe usually applies 20 for all voltages. So actual capabilities of the product are not 0 much different. 10100 1000 10,000 Heat increases current gain and leakage, lowering GATE‐MT1 RESISTANCE (OHMS) ǒdVǓ , the gate trigger voltage and noise immunity ǒdVǓ dt s Figure 6.4. Exponential dt s versus (Figure 3). Gate to MT1 Resistance

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ǒdVǓ 10 IMPROVING MEG MCR22‐006 dt s TA = 65°C dV Static can be improved by adding an external resistor A dt 10 from the gate to MT1 (Figure 4). The resistor provides a 1 V G K path for leakage and dV induced currents that originate in MEG dt the drive circuit or the thyristor itself. Non-sensitive devices (Figure 5) have internal shorting resistors dispersed throughout the chip’s cathode area. This 100 design feature improves noise immunity and high tempera- K ture blocking stability at the expense of increased trigger and holding current. External resistors are optional for non- (OHMS) RESISTANCE GATE‐CATHODE sensitive SCRs and TRIACs. They should be comparable in 10K size to the internal shorting resistance of the device (20 to 0.001 0.010.1 1 10 100 100 ohms) to provide maximum improvement. The internal STATIC dV (Vńms) dt resistance of the thyristor should be measured with an ohm- ǒdVǓ meter that does not forward bias a diode junction. Figure 6.6. Exponential versus dt s Gate-Cathode Resistance A gate-cathode capacitor (Figure 7) provides a shunt 2200 path for transient currents in the same manner as the resis- tor. It also filters noise currents from the drive circuit and 2000 enhances the built-in gate-cathode capacitance voltage MAC 15‐8 1800 divider effect. The gate drive circuit needs to be able to VPK = 600 V μ 1600 charge the capacitor without excessive delay, but it does not need to supply continuous current as it would for a dt dV 1400 resistor that increases dV the same amount. However, the 1200 dt capacitor does not enhance static thermal stability. STATIC (V/ s) STATIC 1000 130 800 120 600 MAC 228A10 50 60 70 80 90 100 110 120 130 110 800 V 110°C TJ, JUNCTION TEMPERATURE (°C) μ ǒdVǓ 100 Figure 6.5. Exponential versus dt dt s dV Junction Temperature 90

STATIC (V/ s) STATIC 80

70

Sensitive gate TRIACs run 100 to 1000 ohms. With an 60 0.001 0.01 0.1 1 dV external resistor, their capability remains inferior to μ dt GATE TO MT1 CAPACITANCE ( F) non-sensitive devices because lateral resistance within the ǒdVǓ Figure 6.7. Exponential versus Gate gate layer reduces its benefit. dt s Sensitive gate SCRs (IGT t 200 μA) have no built-in to MT1 Capacitance resistor. They should be used with an external resistor. The The maximum ǒdVǓ improvement occurs with a short. recommended value of the resistor is 1000 ohms. Higher dt s Actual improvement stops before this because of spreading values reduce maximum operating temperature and ǒdVǓ dt s resistance in the thyristor. An external capacitor of about (Figure 6). The capability of these parts varies by more than 0.1 μF allows the maximum enhancement at a higher value 100 to 1 depending on gate-cathode termination. of RGK.

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for sinusoidal currents is given by the slope of the secant One should keep the thyristor cool for the highest ǒdVǓ . dt s line between the 50% and 0% levels as: Also devices should be tested in the application circuit at 6fITM the highest possible temperature using thyristors with the ǒdIǓ + Ańms dt 1000 lowest measured trigger current. c where f = line frequency and ITM = maximum on-state cur- TRIAC COMMUTATING dV rent in the TRIAC. dt Turn-off depends on both the Miller effect displacement dV WHAT IS COMMUTATING dV ? current generated by across the collector capacitance dt dt and the currents resulting from internal charge storage The commutating dV rating applies when a TRIAC has dt within the volume of the device (Figure 10). If the reverse been conducting and attempts to turn-off with an inductive recovery current resulting from both these components is load. The current and voltage are out of phase (Figure 8). high, the lateral IR drop within the TRIAC base layer will The TRIAC attempts to turn-off as the current drops below forward bias the emitter and turn the TRIAC on. Commu- the holding value. Now the line voltage is high and in the tating dV capability is lower when turning off from the pos- opposite polarity to the direction of conduction. Successful dt itive direction of current conduction because of device turn-off requires the voltage across the TRIAC to rise to the geometry. The gate is on the top of the die and obstructs instantaneous line voltage at a rate slow enough to prevent current flow. retriggering of the device. Recombination takes place throughout the conduction period and along the back side of the current wave as it R L declines to zero. Turn-off capability depends on its shape. If i 2 dI VLINE G VMT2‐1 the current amplitude is small and its zero crossing ǒ Ǔ is 1 dt c low, there is little volume charge storage and turn-off ǒdIǓ dV PHASE ǒ Ǔ VOLTAGE/CURRENT becomes limited by . At moderate current amplitudes, dt c MT2‐1 ANGLE V dt s Φ the volume charge begins to influence turn-off, requiring a TIME TIME larger snubber. When the current is large or has rapid zero ǒdVǓ crossing, ǒdVǓ has little influence. Commutating dI and i VLINE dt c dt c dt delay time to voltage reapplication determine whether turn- dV off will be successful or not (Figures 11, 12). Figure 6.8. TRIAC Inductive Load Turn-Off ǒ Ǔ dt c

GMT1 dV ǒ Ǔ DEVICE PHYSICS TOP dt c A TRIAC functions like two SCRs connected in inverse- N NNN parallel. So, a transient of either polarity turns it on. P

There is charge within the crystal’s volume because of Previously prior conduction (Figure 9). The charge at the boundaries Conducting Side N of the collector junction depletion layer responsible for ǒdVǓ is also present. TRIACs have lower ǒdVǓ than +- dt s dt c NN N ǒdVǓ because of this additional charge. dt s The volume charge storage within the TRIAC depends REVERSE RECOVERY MT2 STORED CHARGE on the peak current before turn-off and its rate of zero CURRENT PATH LATERAL VOLTAGE FROM POSITIVE DROP CONDUCTION crossing ǒdIǓ . In the classic circuit, the load impedance dt c Figure 6.9. TRIAC Structure and Current Flow and line frequency determine ǒdIǓ . The rate of crossing dt c at Commutation

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CONDITIONS INFLUENCING ǒdVǓ dt c dV ǒdiǓ Commutating depends on charge storage and recov- dt dt c ery dynamics in addition to the variables influencing static ǒdVǓ dt dV. High temperatures increase minority carrier life-time c dt

VOLTAGE/CURRENT TIME and the size of recovery currents, making turn-off more dif- 0 ficult. Loads that slow the rate of current zero-crossing aid turn-off. Those with harmonic content hinder turn-off. VMT2‐1 CHARGE DUE TO Circuit Examples VOLUME dV/dt IRRM STORAGE Figure 13 shows a TRIAC controlling an inductive load CHARGE in a bridge. The inductive load has a time constant longer than the line period. This causes the load current to remain constant and the TRIAC current to switch rapidly as the line Figure 6.10. TRIAC Current and Voltage at Commutation voltage reverses. This application is notorious for causing TRIAC turn-off difficulty because of high ǒdIǓ . dt c

RS C

E i V LS ǒdIǓ dt c DC MOTOR - + i L VOLTAGE (V) VOLTAGE 60 Hz R t

E ǒL u8.3 msǓ R MAIN TERMINAL MAIN TERMINAL Figure 6.13. Phase Controlling a Motor in a Bridge VT High currents lead to high junction temperatures and 0 t d TIME rates of current crossing. Motors can have 5 to 6 times the normal current amplitude at start-up. This increases both Figure 6.11. Snubber Delay Time junction temperature and the rate of current crossing, lead- ing to turn-off problems. The line frequency causes high rates of current crossing in 400 Hz applications. Resonant transformer circuits are doubly periodic and have current harmonics at both the pri- 0.5 mary and secondary resonance. Non-sinusoidal currents 0.2 can lead to turn-off difficulty even if the current amplitude 0.2 0.1 is low before zero-crossing. ) d t 0.05 0.1 ǒdVǓ FAILURE MODE dt d0 d0 c (t * = W 0.05 0.02 RL = 0 ǒdVǓ 0.03 0.01 failure causes a loss of phase control. Temporary NORMALIZED DELAY TIME NORMALIZED DELAY M = 1 dt c 0.02 IRRM = 0 V turn-on or total turn-off failure is possible. This can be T 0.005 E destructive if the TRIAC conducts asymmetrically causing a 0.001 0.002 0.005 0.01 0.020.05 0.1 0.2 0.3 0.5 1 dc current component and magnetic saturation. The winding DAMPING FACTOR resistance limits the current. Failure results because of Figure 6.12. Delay Time To Normalized Voltage excessive surge current and junction temperature.

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ǒdVǓ Hs ML IMPROVING I + where : dt c s 0.4 p N

Hs = MMF to saturate = 0.5 Oersted The same steps that improve ǒdVǓ aid ǒdVǓ except dt s dt c ML = mean magnetic path length = 4.99 cm. when stored charge dominates turn-off. Steps that reduce (.5) (4.99) I + + 60 mA. the stored charge or soften the commutation are necessary s .4 p 33 then. Larger TRIACs have better turn-off capability than SNUBBER PHYSICS smaller ones with a given load. The current density is lower in the larger device allowing recombination to claim a UNDAMPED NATURAL RESONANCE greater proportion of the internal charge. Also junction I w0 + Radiansńsecond temperatures are lower. ǸLC TRIACs with high gate trigger currents have greater Resonance determines dV and boosts the peak capacitor turn-off ability because of lower spreading resistance in the dt gate layer, reduced Miller effect, or shorter lifetime. voltage when the snubber resistor is small. C and L are The rate of current crossing can be adjusted by adding a 2 dV related to one another by ω0 . scales linearly with ω0 commutation softening inductor in series with the load. dt when the damping factor is held constant. A ten to one Small high permeability “square loop” inductors saturate reduction in dV requires a 100 to 1 increase in either causing no significant disturbance to the load current. The dt inductor resets as the current crosses zero introducing a component. large inductance into the snubber circuit at that time. This slows the current crossing and delays the reapplication of DAMPING FACTOR blocking voltage aiding turn-off. The commutation inductor is a circuit element that ρ + R ǸC 2 L introduces time delay, as opposed to inductance, into the The damping factor is proportional to the ratio of the circuit. It will have little influence on observed dV at the dt circuit loss and its surge impedance. It determines the trade device. The following example illustrates the improvement off between dV and peak voltage. Damping factors between resulting from the addition of an inductor constructed by dt winding 33 turns of number 18 wire on a tape wound core 0.01 and 1.0 are recommended. (52000-1A). This core is very small having an outside The Snubber Resistor diameter of 3/4 inch and a thickness of 1/8 inch. The delay time can be calculated from: Damping and dV dt ρ t dV * When 0.5, the snubber resistor is small, and (NAB10 8) dt t + where: s E depends mostly on resonance. There is little improvement in dV for damping factors less than 0.3, but peak voltage t = time delay to saturation in seconds. dt s and snubber discharge current increase. The voltage wave B = saturating flux density in Gauss has a 1-COS (θ) shape with overshoot and ringing. Maxi- A = effective core cross sectional area in cm2 mum dV occurs at a time later than t = 0. There is a time N = number of turns. dt delay before the voltage rise, and the peak voltage almost For the described inductor: doubles. When ρ u 0.5, the voltage wave is nearly exponential in dV + 2 shape. The maximum instantaneous occurs at t = 0. ts (33 turns) (0.076 cm ) (28000 Gauss) dt (1 10−8) ń (175 V) + 4.0 ms. There is little time delay and moderate voltage overshoot. When ρ u 1.0, the snubber resistor is large and dV dt The saturation current of the inductor does not need to be depends mostly on its value. There is some overshoot even much larger than the TRIAC trigger current. Turn-off fail- through the circuit is overdamped. ure will result before recovery currents become greater than High load inductance requires large snubber resistors and this value. This criterion allows sizing the inductor with the small snubber capacitors. Low inductances imply small following equation: resistors and large capacitors.

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Damping and Transient Voltages Table 1 shows suggested minimum resistor values esti- Figure 14 shows a series inductor and filter capacitor mated (Appendix A) by testing a 20 piece sample from the connected across the ac main line. The peak to peak voltage four different TRIAC die sizes. of a transient disturbance increases by nearly four times. Also the duration of the disturbance spreads because of Table 1. Minimum Non-inductive Snubber Resistor ringing, increasing the chance of malfunction or damage to for Four Quadrant Triggering. the voltage sensitive circuit. Closing a switch causes this dI behavior. The problem can be reduced by adding a damping Peak VC Rs dt resistor in series with the capacitor. TRIAC Type Volts Ohms A/μs Non-Sensitive Gate 200 3.3 170 u (IGT 10 mA) 300 6.8 250 100 μH 0.05 8 to 40 A(RMS) 400 11 308 600 39 400 340 V 0.1 VOLTAGE 800 51 400 0 μ μF V SENSITIVE 10 s CIRCUIT Reducing dI + 700 dt TRIAC dI can be improved by avoiding quadrant 4 dt 0 triggering. Most optocoupler circuits operate the TRIAC in V (VOLTS) quadrants 1 and 3. Integrated circuit drivers use quadrants 2 - 700 and 3. Zero crossing trigger devices are helpful because 02010 they prohibit triggering when the voltage is high. μ TIME ( s) Driving the gate with a high amplitude fast rise pulse increases dI capability. The gate ratings section defines the dt Figure 6.14. Undamped LC Filter Magnifies and maximum allowed current. Lengthens a Transient Inductance in series with the snubber capacitor reduces dI. It should not be more than five percent of the load dI dt dt inductance to prevent degradation of the snubber’s dV dt Non-Inductive Resistor suppression capability. Wirewound snubber resistors The snubber resistor limits the capacitor discharge sometimes serve this purpose. Alternatively, a separate current and reduces dI stress. High dI destroys the thyristor inductor can be added in series with the snubber capacitor. dt dt It can be small because it does not need to carry the load even though the pulse duration is very short. current. For example, 18 turns of AWG No. 20 wire on a The rate of current rise is directly proportional to circuit T50-3 (1/2 inch) powdered iron core creates a non-saturat- voltage and inversely proportional to series inductance. ing 6.0 μH inductor. The snubber is often the major offender because of its low A 10 ohm, 0.33 μF snubber charged to 650 volts resulted inductance and close proximity to the thyristor. in a 1000 A/μs dI. Replacement of the non-inductive snub- With no transient suppressor, breakdown of the thyristor dt sets the maximum voltage on the capacitor. It is possible to ber resistor with a 20 watt wirewound unit lowered the rate exceed the highest rated voltage in the device series of rise to a non-destructive 170 A/μs at 800 V. The inductor because high voltage devices are often used to supply low gave an 80 A/μs rise at 800 V with the non−inductive voltage specifications. resistor. The minimum value of the snubber resistor depends on the type of thyristor, triggering quadrants, gate current The Snubber Capacitor amplitude, voltage, repetitive or non-repetitive operation, A damping factor of 0.3 minimizes the size of the snub- and required life expectancy. There is no simple way to pre- ber capacitor for a given value of dV. This reduces the cost dict the rate of current rise because it depends on turn-on dt speed of the thyristor, circuit layout, type and size of snub- and physical dimensions of the capacitor. However, it raises ber capacitor, and inductance in the snubber resistor. The voltage causing a counter balancing cost increase. equations in Appendix D describe the circuit. However, the Snubber operation relies on the charging of the snubber values required for the model are not easily obtained except capacitor. Turn-off snubbers need a minimum conduction by testing. Therefore, reliability should be verified in the angle long enough to discharge the capacitor. It should be at actual application circuit. least several time constants (RS CS).

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STORED ENERGY snubber inductor and limits the rate of inrush current if the Inductive Switching Transients device does turn on. Resistance in the load lowers dV and dt E + 1 LI 2 Watt−seconds or Joules VPK (Figure 16). 2 0 I0 = current in Amperes flowing in the 1.4 2.2 inductor at t = 0. E Resonant charging cannot boost the supply voltage at dV 2.1 dt turn-off by more than 2. If there is an initial current flowing 1.2 2 VPK in the load inductance at turn-off, much higher voltages are 1.9 possible. Energy storage is negligible when a TRIAC turns 1 1.8 off because of its low holding or recovery current. M = 1 M = 0.75 The presence of an additional switch such as a relay, ther- 1.7 dt mostat or breaker allows the interruption of load current and dV 0.8 1.6 0 the generation of high spike voltages at switch opening. The 1.5 / (E W ) M = 0.5 PK energy in the inductance transfers into the circuit capacitance V /E

dt 0.6 1.4 dV NORMALIZED

and determines the peak voltage (Figure 15). ( ) M = 0.25 1.3

0.4 1.2 NORMALIZED PEAK VOLTAGE L I M = 0 1.1 R 0.2 1 OPTIONAL VPK M = RS / (RL + RS) 0.9 C FAST 0 0 0.2 0.4 0.6 0.8 1 SLOW DAMPING FACTOR R ǒ + + S Ǔ M RESISTIVE DIVISION RATIO ) RL RS dV + I V + I ǸL I + 0 dt C PK C RRM Figure 6.16. 0 To 63% dV (a.) Protected Circuit (b.) Unprotected Circuit dt

Figure 6.15. Interrupting Inductive Load Current CHARACTERISTIC VOLTAGE WAVES

Capacitor Discharge Damping factor and reverse recovery current determine The energy stored in the snubber capacitor the shape of the voltage wave. It is not exponential when the snubber damping factor is less than 0.5 (Figure 17) or ǒE + 1 CV2Ǔ transfers to the snubber resistor and c 2 when significant recovery currents are present. thyristor every time it turns on. The power loss is propor- tional to frequency (P = 120 E @ 60 Hz). AV c ρ = 0 ρ = 0.1 500 CURRENT DIVERSION 400 The current flowing in the load inductor cannot change 300 0.1 200 0.3 ρ ρ instantly. This current diverts through the snubber resistor 2‐1 1 = 0.3 = 1

MT 100 causing a spike of theoretically infinite dV with magnitude V (VOLTS) 0 dt 0 0 0.7 1.42.12.8 3.5 4.2 4.9 5.6 6.3 7 equal to (IRRM R) or (IH R). TIME (μs) LOAD PHASE ANGLE Highly inductive loads cause increased voltage and ƪ 0*63% ǒdVǓ + 100 Vńms, E + 250 V,ƫ dt s ǒdVǓ R + 0, I + 0 at turn-off. However, they help to protect the L RRM dt c ǒdVǓ Figure 6.17. Voltage Waves For Different thyristor from transients and . The load serves as the Damping Factors dt s

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2.8 COMPLEX LOADS 2.6 E Many real-world inductances are non-linear. Their core 2.4 0-63% dV materials are not gapped causing inductance to vary with dt dV 2.2 dt ǒdVǓ MAX current amplitude. Small signal measurements poorly char- 2 dt acterize them. For modeling purposes, it is best to measure 1.8 10-63% them in the actual application. 1.6 Complex load circuits should be checked for transient 1.4 voltages and currents at turn-on and off. With a capacitive 10-63 V 1.2 PK dV% load, turn-on at peak input voltage causes the maximum 1 dt surge current. Motor starting current runs 4 to 6 times the 0.8 steady state value. Generator action can boost voltages 0.6 above the line value. Incandescent lamps have cold start NORMALIZED PEAK VOLTAGE AND 0.4 ǒdVǓ currents 10 to 20 times the steady state value. Transformers 0.2 dt o generate voltage spikes when they are energized. Power 0 factor correction circuits and switching devices create 0 0.20.4 0.6 0.8 1 1.21.4 1.6 1.8 2 DAMPING FACTOR (ρ) complex loads. In most cases, the simple CRL model + + + ) allows an approximate snubber design. However, there is (RL 0, M 1, IRRM 0 no substitute for testing and measuring the worst case load dV dVńdt VPK NORMALIZED + NORMALIZED V + conditions. dt E w0 PK E dV SURGE CURRENTS IN INDUCTIVE CIRCUITS Figure 6.18. Trade-Off Between VPK and dt Inductive loads with long L/R time constants cause asymmetric multi-cycle surges at start up (Figure 20). Trig- A variety of wave parameters (Figure 18) describe dV dt gering at zero voltage crossing is the worst case condition. Some are easy to solve for and assist understanding. These The surge can be eliminated by triggering at the zero cur- include the initial dV, the maximum instantaneous dV, and rent crossing angle. dt dt the average dV to the peak reapplied voltage. The 0 to 63% dt 20 MHY dV dV ǒ Ǔ and 10 to 63% ǒ Ǔ definitions on device data i dt dt 240 0.1 s c VAC Ω sheets are easy to measure but difficult to compute.

NON-IDEAL BEHAVIORS CORE LOSSES 90 The magnetic core materials in typical 60 Hz loads introduce losses at the snubber natural frequency. They appear as a resistance in series with the load inductance and 0 i (AMPERES) dV winding dc resistance (Figure 19). This causes actual to ZERO VOLTAGE TRIGGERING, IRMS = 30 A dt be less than the theoretical value. 40 80120 160 200 TIME (MILLISECONDS) LR

Figure 6.20. Start-Up Surge For Inductive Circuit Core remanence and saturation cause surge currents. C They depend on trigger angle, line impedance, core charac- L DEPENDS ON CURRENT AMPLITUDE, CORE teristics, and direction of the residual magnetization. For SATURATION example, a 2.8 kVA 120 V 1:1 transformer with a 1.0 R INCLUDES CORE LOSS, WINDING R. INCREASES ampere load produced 160 ampere currents at start-up. Soft WITH FREQUENCY starting the circuit at a small conduction angle reduces this current. C WINDING CAPACITANCE. DEPENDS ON INSULATION, WIRE SIZE, GEOMETRY Transformer cores are usually not gapped and saturate easily. A small asymmetry in the conduction angle causes Figure 6.19. Inductor Model magnetic saturation and multi-cycle current surges.

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Steps to achieve reliable operation include: resistor. The non-inductive snubber circuit is useful when 1. Supply sufficient trigger current amplitude. TRIACs the load resistance is much larger than the snubber resistor. have different trigger currents depending on their quadrant of operation. Marginal gate current or RL optocoupler LED current causes halfwave operation. R 2. Supply sufficient gate current duration to achieve E e S latching. Inductive loads slow down the main terminal C current rise. The gate current must remain above the S specified I until the main terminal current exceeds e GT τ = (R + R ) C the latching value. Both a resistive bleeder around the E L S S R load and the snubber discharge current help latching. V + E S step R ) R ǒdVǓ S L 3. Use a snubber to prevent TRIAC failure. TIME dt c t = 0 4. Minimize designed-in trigger asymmetry. Triggering R must be correct every half-cycle including the first. Use + ƪǒ S Ǔ *tńt ) * *tńt ƫ e(t + o)) E ) e (1 e ) a storage scope to investigate circuit behavior during the RS RL first few cycles of turn-on. Alternatively, get the gate RESISTOR CAPACITOR circuit up and running before energizing the load. COMPONENT COMPONENT 5. Derive the trigger synchronization from the line instead Figure 6.21. Non-Inductive Snubber Circuit of the TRIAC main terminal voltage. This avoids regenerative interaction between the core hysteresis Opto-TRIAC Examples and the triggering angle preventing trigger runaway, Single Snubber, Time Constant Design halfwave operation, and core saturation. Figure 22 illustrates the use of the RC time constant 6. Avoid high surge currents at start-up. Use a current design method. The optocoupler sees only the voltage probe to determine surge amplitude. Use a soft start across the snubber capacitor. The resistor R1 supplies the circuit to reduce inrush current. trigger current of the power TRIAC. A worst case design DISTRIBUTED WINDING CAPACITANCE procedure assumes that the voltage across the power There are small capacitances between the turns and lay- TRIAC changes instantly. The capacitor voltage rises to ers of a coil. Lumped together, they model as a single shunt 63% of the maximum in one time constant. Then: capacitance. The load inductor behaves like a capacitor at + t + 0.63 E ǒdVǓ dV R1 CS where is the rated static frequencies above its self-resonance. It becomes ineffective ǒdVǓ dt s dt in controlling dV and V when a fast transient such as that dt s dt PK resulting from the closing of a switch occurs. This problem for the optocoupler. can be solved by adding a small snubber across the line. 1 A, 60 Hz SELF-CAPACITANCE L = 318 MHY 10 V/μs A thyristor has self-capacitance which limits dV when the dt Rin 1 6180 2.4 k 170 V VCC 2N6073A load inductance is large. Large load inductances, high power 2 MOC 0.1 μF C1 1 V/μs factors, and low voltages may allow snubberless operation. 3021 4

φ CNTL SNUBBER EXAMPLES 0.63 (170) (0.63) (170) DESIGN dV + + 0.45 Vńms WITHOUT INDUCTANCE dt (2400) (0.1 mF) Power TRIAC Example TIME 240 μs Figure 21 shows a transient voltage applied to a TRIAC dV controlling a resistive load. Theoretically there will be an (Vńms) dt instantaneous step of voltage across the TRIAC. The only Power TRIAC Optocoupler elements slowing this rate are the inductance of the wiring 0.99 0.35 and the self-capacitance of the thyristor. There is an expo- nential capacitor charging component added along with a Figure 6.22. Single Snubber For Sensitive Gate TRIAC decaying component because of the IR drop in the snubber and Phase Controllable Optocoupler (ρ = 0.67)

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The optocoupler conducts current only long enough to However a power TRIAC along with the optocoupler trigger the power device. When it turns on, the voltage should be used for higher load currents. between MT2 and the gate drops below the forward thresh- old voltage of the opto-TRIAC causing turn-off. The opto- 80 coupler sees ǒdVǓ when the power TRIAC turns off later 70 dt s in the conduction cycle at zero current crossing. Therefore, 60 CS = 0.01 it is not necessary to design for the lower optocoupler 50 ǒdVǓ rating. In this example, a single snubber designed 40 dt c for the optocoupler protects both devices. 30 CS = 0.001 20 LOAD CURRENT (mA RMS) (mA LOAD CURRENT 1 MHY NO SNUBBER 10 100 VCC 0 430 120 V 20 30 40 50 60 70 80 90 100 1 4 1N4001 MCR265-4 400 Hz TA, AMBIENT TEMPERATURE (°C) 2 5 (RS = 100 Ω, VRMS = 220 V, POWER FACTOR = 0.5) 3 MOC3031 6 51 MCR265-4 0.022 μF Figure 6.24. MOC3062 Inductive Load Current versus TA 100 1N4001

(50 V/μs SNUBBER, ρ = 1.0) A phase controllable optocoupler is recommended with a power device. When the load current is small, a MAC97A TRIAC is suitable. Figure 6.23. Anti-Parallel SCR Driver Unusual circuit conditions sometimes lead to unwanted operation of an optocoupler in ǒdVǓ mode. Very large cur- dt Optocouplers with SCRs c rents in the power device cause increased voltages between Anti-parallel SCR circuits result in the same dV across MT2 and the gate that hold the optocoupler on. Use of a dt the optocoupler and SCR (Figure 23). Phase controllable larger TRIAC or other measures that limit inrush current opto-couplers require the SCRs to be snubbed to their lower solve this problem. Very short conduction times leave residual charge in the dV rating. Anti-parallel SCR circuits are free from the dt optocoupler. A minimum conduction angle allows recovery charge storage behaviors that reduce the turn-off capability before voltage reapplication. of TRIACs. Each SCR conducts for a half-cycle and has the next half cycle of the ac line in which to recover. The turn- THE SNUBBER WITH INDUCTANCE off dV of the conducting SCR becomes a static forward Consider an overdamped snubber using a large capacitor dt whose voltage changes insignificantly during the time blocking dV for the other device. Use the SCR data sheet dt under consideration. The circuit reduces to an equivalent L/R series charging circuit. ǒdVǓ rating in the snubber design. dt s The current through the snubber resistor is: A SCR used inside a rectifier bridge to control an ac load *t i + V ǒ1 * e tǓ , will not have a half cycle in which to recover. The available Rt time decreases with increasing line voltage. This makes the circuit less attractive. Inductive transients can be sup- and the voltage across the TRIAC is: + pressed by a snubber at the input to the bridge or across the e iRS. SCR. However, the time limitation still applies. The voltage wave across the TRIAC has an exponential rise with maximum rate at t = 0. Taking its derivative gives ǒdVǓ OPTO its value as: dt c Zero-crossing optocouplers can be used to switch VRS ǒdVǓ + . inductive loads at currents less than 100 mA (Figure 24). dt 0 L

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Highly overdamped snubber circuits are not practical φ = measured phase angle between line V and load I designs. The example illustrates several properties: RL = measured dc resistance of the load. 1. The initial voltage appears completely across the circuit Then inductance. Thus, it determines the rate of change of V + RMS Ǹ 2 ) 2 + Ǹ 2 * 2 current through the snubber resistor and the initial dV. Z RL XL XL Z RL and dt IRMS This result does not change when there is resistance in X the load and holds true for all damping factors. + L L p . 2. The snubber works because the inductor controls the 2 fLine rate of current change through the resistor and the rate If only the load current is known, assume a pure inductance. of capacitor charging. Snubber design cannot ignore This gives a conservative design. Then: the inductance. This approach suggests that the snubber V capacitance is not important but that is only true for + RMS + Ǹ L p where E 2 VRMS. this hypothetical condition. The snubber resistor shunts 2 fLine IRMS the thyristor causing unacceptable leakage when the For example: capacitor is not present. If the power loss is tolerable, Ǹ E + 2 120 + 170 V; L + 120 + 39.8 mH. dV can be controlled without the capacitor. An (8 A) (377 rps) dt example is the soft-start circuit used to limit inrush Read from the graph at ρ = 0.6, VPK = (1.25) 170 = 213 V. current in switching power supplies (Figure 25). Use 400 V TRIAC. Read dV + 1.0. dt (ρ+0.6) 2. Apply the resonance criterion: ǒ dVǓ ǒdV Ǔ Snubber With No C w0 + spec ń E . dt dt(P) RS E 5 106 VńS w + + 29.4 103 rps. RECTIFIER 0 (1) (170 V) AC LINE SNUBBER BRIDGE C1 L G C + 1 + 0.029 mF ERS 2 ǒdVǓ + w0 L dt f L 3. Apply the damping criterion: RS E *3 RECTIFIER + ρ ǸL + Ǹ 39.8 10 + AC LINE SNUBBER R 2 2(0.6) 1400ohms. BRIDGE C1 S C *6 L G 0.029 10

ǒdVǓ SAFE AREA CURVE dt c Figure 6.25. Surge Current Limiting For a Switching Power Supply Figure 26 shows a MAC15 TRIAC turn-off safe operating area curve. Turn-off occurs without problem ǒdVǓ under the curve. The region is bounded by static dV at low TRIAC DESIGN PROCEDURE dt dt c 1. Refer to Figure 18 and select a particular damping values of ǒdIǓ and delay time at high currents. Reduction dt c factor (ρ) giving a suitable trade-off between V and dV. PK dt of the peak current permits operation at higher line frequency. This TRIAC operated at f = 400 Hz, T = 125°C, Determine the normalized dV corresponding to the chosen J dt and ITM = 6.0 amperes using a 30 ohm and 0.068 μF damping factor. snubber. Low damping factors extend operation to higher The voltage E depends on the load phase angle: ǒdIǓ , but capacitor sizes increase. The addition of a small, dt X c + Ǹ f f + *1ǒ LǓ saturable commutation inductor extends the allowed E 2 VRMS Sin ( )where tan where RL current rate by introducing recovery delay time.

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One hundred μH is a suggested value for starting the design. Plug the assumed inductance into the equation for - ITM = 15 A C. Larger values of inductance result in higher snubber resistance and reduced dI. For example: 100 dt Ǹ ǒdIǓ + 6 f ITM 10*3 Ańms Given E = 240 2 + 340 V. dt c Pick ρ = 0.3. 10 μ Then from Figure 18, VPK = 1.42 (340) = 483 V.

(V/ s) Thus, it will be necessary to use a 600 V device. Using the c ) previously stated formulas for ω0, C and R we find: dt dV WITH COMMUTATION L ( 50 106 VńS 1 w + + 201450 rps 0 (0.73) (340 V)

+ 1 + m C * 0.2464 F (201450)2 (100 10 6) 0.1 10 14 18 22 2630 34 38 42 46 50 *6 ǒdIǓ ń + Ǹ 100 10 + AMPERES MILLISECOND R 2(0.3) * 12 ohms dt c 0.2464 10 6 MAC 16-8, COMMUTATIONAL L + 33 TURNS # 18, ǒ ń Ǔ 52000-1A TAPE WOUND CORE 3 4 INCH OD VARIABLE LOADS dV dI The snubber should be designed for the smallest load Figure 6.26. ǒ Ǔ versus ǒ Ǔ T = 125°C dt dt J c c inductance because dV will then be highest because of its dt dependence on ω0. This requires a higher voltage device for operation with the largest inductance because of the corre- STATIC dV DESIGN dt sponding low damping factor. Figure 28 describes dV for an 8.0 ampere load at various There is usually some inductance in the ac main and dt power wiring. The inductance may be more than 100 μH if power factors. The minimum inductance is a component there is a transformer in the circuit or nearly zero when a added to prevent static dV firing with a resistive load. shunt power factor correction capacitor is present. Usually dt the line inductance is roughly several μH. The minimum inductance must be known or defined by adding a series 8 A LOAD inductor to insure reliable operation (Figure 27). R L BTA08-800CW3G 68 Ω 120 V 60 Hz μ μ 10 0.33 F 0.033 F

100 μH t 50 V/μs 20 A ǒdVǓ + 100 Vńms ǒdVǓ + 5Vńms dt dt L s c S1

340 R L V V dv 12 Ω ρ step PK V dt HEATER Ω MHY V V V/μs 0.75 15 0.1 170 191 86 0.03 0 39.8 170 325 4.0 0.04 10.6 28.1 120 225 3.3 0.06 13.5 17.3 74 136 2.6

Figure 6.27. Snubbing For a Resistive Load Figure 6.28. Snubber For a Variable Load

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EXAMPLES OF SNUBBER DESIGNS 1 Table 2 describes snubber RC values for ǒdVǓ . dt s 80 A RMS Figures 31 and 32 show possible R and C values for a 5.0 μ ǒdVǓ V/ s assuming a pure inductive load. 40 A dt c 0.1 dV 20 A Table 2. Static Designs dt (E = 340 V, V = 500 V, ρ = 0.3) 10 A peak μ

μ μ μ S

5.0 V/ s 50 V/ s 100 V/ s C ( F) 5 A L C R C R C R μ μ μ μ H F Ohm F Ohm F Ohm 0.01 2.5 A 47 0.15 10 100 0.33 10 0.1 20 220 0.15 22 0.033 47 500 0.068 51 0.015 110 0.6 A 1000 3.0 11 0.033 100 0.001 TRANSIENT AND NOISE SUPPRESSION 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 DAMPING FACTOR Transients arise internally from normal circuit operation ǒPURE INDUCTIVE LOAD, V + 120 V ,Ǔ or externally from the environment. The latter is partic- RMS I + 0 ularly frustrating because the transient characteristics are RRM Figure 6.30. Snubber Capacitor For ǒ dV Ǔ = 5.0 V/μs undefined. A statistical description applies. Greater or dt c smaller stresses are possible. Long duration high voltage The natural frequencies and impedances of indoor ac transients are much less probable than those of lower wiring result in damped oscillatory surges with typical fre- amplitude and higher frequency. Environments with infre- quencies ranging from 30 kHz to 1.5 MHz. Surge ampli- quent lightning and load switching see transient voltages tude depends on both the wiring and the source of surge below 3.0 kV. energy. Disturbances tend to die out at locations far away

10K from the source. Spark-over (6.0 kV in indoor ac wiring) sets the maximum voltage when transient suppressors are not present. Transients closer to the service entrance or in 0.6 A RMS 2.5 A heavy wiring have higher amplitudes, longer durations, and more damping because of the lower inductance at those 5 A locations. The simple CRL snubber is a low pass filter attenuating 1000 10 A frequencies above its natural resonance. A steady state 20 A sinusoidal input voltage results in a sine wave output at the same frequency. With no snubber resistor, the rate of roll 40 A

S off approaches 12 dB per octave. The corner frequency is at R (OHMS) the snubber’s natural resonance. If the damping factor is 80 A 100 low, the response peaks at this frequency. The snubber resistor degrades filter characteristics introducing an up-turn at ω = 1 / (RC). The roll-off approaches 6.0 dB/octave at frequencies above this. Inductance in the snubber resistor further reduces the roll-off rate. Figure 32 describes the frequency response of the circuit 10 in Figure 27. Figure 31 gives the theoretical response to a 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 3.0 kV 100 kHz ring-wave. The snubber reduces the peak DAMPING FACTOR voltage across the thyristor. However, the fast rise input + ǒPURE INDUCTIVE LOAD, V 120 VRMS,Ǔ causes a high dV step when series inductance is added to the + IRRM 0 dt snubber resistor. Limiting the input voltage with a transient Figure 6.29. Snubber Resistor For ǒ dV Ǔ = 5.0 V/μs dt c suppressor reduces the step.

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400 In Figure 32, there is a separate suppressor across each WITHOUT 5 μHY WITH 5 μHY AND thyristor. The load impedance limits the surge energy deliv- 450 V MOV ered from the line. This allows the use of a smaller device AT AC INPUT but omits load protection. This arrangement protects each 0

2‐1 thyristor when its load is a possible transient source. MT V (VOLTS) WITH 5 μHY

- 400 0 1 2 3 4 5 6 TIME (μs)

Figure 6.31. Theoretical Response of Figure 33 Circuit VMAX Ω to 3.0 kV IEEE 587 Ring Wave (RSC = 27.5 )

+ 10 Figure 6.33. Limiting Line Voltage 0

- 10 100 μH WITH 5 μHY - 20 5 μH

VOLTAGE GAIN (dB) VOLTAGE Vin 10 Vout - 30 0.33 μF 12 WITHOUT 5μHY

- 40 10K 100K 1M FREQUENCY (Hz) Vout Figure 6.32. Snubber Frequency Response ǒ Ǔ Vin Figure 6.34. Limiting Thyristor Voltage

It is desirable to place the suppression device directly The noise induced into a circuit is proportional to dV across the source of transient energy to prevent the induc- dt tion of energy into other circuits. However, there is no when coupling is by stray capacitance, and dI when the dt protection for energy injected between the load and its con- coupling is by mutual inductance. Best suppression trolling thyristor. Placing the suppressor directly across requires the use of a voltage limiting device along with a each thyristor positively limits maximum voltage and snub- rate limiting CRL snubber. ber discharge dI . The thyristor is best protected by preventing turn-on dt from dV or breakover. The circuit should be designed for dt EXAMPLES OF SNUBBER APPLICATIONS what can happen instead of what normally occurs. In Figure 30, a MOV connected across the line protects In Figure 35, TRIACs switch a 3 phase motor on and off many parallel circuit branches and their loads. The MOV and reverse its rotation. Each TRIAC pair functions as a SPDT switch. The turn-on of one TRIAC applies the differ- defines the maximum input voltage and dI through the load. dt ential voltage between line phases across the blocking With the snubber, it sets the maximum dV and peak voltage device without the benefit of the motor impedance to dt constrain the rate of voltage rise. The inductors are added to across the thyristor. The MOV must be large because there prevent static dV firing and a line-to-line short. is little surge limiting impedance to prevent its burn-out. dt

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SNUBBER φ 1 2 1 22 Ω 100 μH 2 W G 300 WIREWOUND 4 MOC 6 91 3081 0.15 μ FWD F SNUBBER

2 1 SNUBBER ALL MOV’S ARE 275 G 300 VRMS ALL TRIACS ARE 4 6 91 MOC BTA08−8003W3G 3081 1/3 HP REV 208 V 91 SNUBBER 3 PHASE φ 2 2 1 G 1 100 μH 6 G MOC SNUBBER 300 2 3081 4 MOC 6 91 3081 4 FWD SNUBBER 43

2 1

G 300 6 MOC 4 91 3081 φ 3 REV

N

Figure 6.35. 3 Phase Reversing Motor

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Figure 36 shows a split phase capacitor-run motor with less dV capability than similar non-sensitive devices. A reversing accomplished by switching the capacitor in series dt with one or the other winding. The forward and reverse non-sensitive thyristor should be used for high dV . dt TRIACs function as a SPDT switch. Reversing the motor TRIAC commutating dV ratings are 5 to 20 times less applies the voltage on the capacitor abruptly across the dt blocking thyristor. Again, the inductor L is added to prevent than static dV ratings. dt ǒdVǓ firing of the blocking TRIAC. If turn-on occurs, the dt s forward and reverse TRIACs short the capacitors (C ) s SNUBBER INDUCTOR resulting in damage to them. It is wise to add the resistor RS to limit the discharge current. D1 D2 + C 120 VAC 1 - D OR 3 D REV 240 VAC 4 91 0.1 RL 46 V/μs 3.75 LS 330 V 240 V MAX 0 G + μ 5.6 C FWD 500 H 120 V 2 - 91 0.1 MOTOR 1/70 HP R C R C S S S S 0.26 A 115

2N6073 Figure 6.37. Tap Changer For Dual Voltage Switching Power Supply

Phase controllable optocouplers have lower dV ratings dt Figure 6.36. Split Phase Reversing Motor than zero crossing optocouplers and power TRIACs. These should be used when a dc voltage component is present, or Figure 37 shows a “tap changer.” This circuit allows the to prevent turn-on delay. operation of switching power supplies from a 120 or 240 Zero crossing optocouplers have more dV capability than dt vac line. When the TRIAC is on, the circuit functions as a power thyristors; and they should be used in place of phase conventional voltage doubler with diodes D1 and D2 con- controllable devices in static switching applications. ducting on alternate half-cycles. In this mode of operation, inrush current and dI are hazards to TRIAC reliability. APPENDIX A dt Series impedance is necessary to prevent damage to the MEASURING ǒdVǓ TRIAC. dt s The TRIAC is off when the circuit is not doubling. In this Figure 38 shows a test circuit for measuring the static dV state, the TRIAC sees the difference between the line volt- dt of power thyristors. A 1000 volt FET switch insures that the age and the voltage at the intersection of C1 and C2. Tran- voltage across the device under test (D.U.T.) rises rapidly sients on the line cause ǒdVǓ firing of the TRIAC. High dt from zero. A differential preamp allows the use of a s N-channel device while keeping the storage scope chassis inrush current, dI, and overvoltage damage to the filter dt at ground for safety purposes. The rate of voltage rise is capacitor are possibilities. Prevention requires the addition adjusted by a variable RC time constant. The charging of a RC snubber across the TRIAC and an inductor in series resistance is low to avoid waveform distortion because of with the line. the thyristor’s self-capacitance but is large enough to pre- vent damage to the D.U.T. from turn-on dI. Mounting the THYRISTOR TYPES dt miniature range switches, capacitors, and G-K network Sensitive gate thyristors are easy to turn-on because of close to the device under test reduces stray inductance and their low trigger current requirements. However, they have allows testing at more than 10 kV/μs.

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27 V /V SELECT DRM RRM 2 W 1000 10 WATT WIREWOUND X100 PROBE 2 DIFFERENTIAL DUT 20 k 2 W 0.33 1000 V PREAMP 0.047 X100 PROBE G 1 1000 V

RGK 470 pF dV MOUNT DUT ON dt 100 0.001 TEMPERATURE CONTROLLED VERNIER 2 W Cμ PLATE 0.005 1 MEG 2 W EACH 1.2 MEG 82 0.01 2 W 2 W POWER TEST 0.047

1N914 0.1

MTP1N100 20 V 0.47 0-1000 V 10 mA 56 1000 2 W 1N967A f = 10 Hz 1/4 W 18 V PW = 100 μs 50 Ω PULSE GENERATOR

ALL COMPONENTS ARE NON‐INDUCTIVE UNLESS OTHERWISE SHOWN

Figure 6.38. Circuit For Static dV Measurement of Power Thyristors dt

APPENDIX B Commercial chokes simplify the construction of the nec- essary inductors. Their inductance should be adjusted by MEASURING ǒdVǓ dt c increasing the air gap in the core. Removal of the magnetic pole piece reduces inductance by 4 to 6 but extends the cur- A test fixture to measure commutating dV is shown in dt rent without saturation. Figure 39. It is a capacitor discharge circuit with the load The load capacitor consists of a parallel bank of 1500 series resonant. The single pulse test aids temperature con- Vdc non-polar units, with individual bleeders mounted at trol and allows the use of lower power components. The each capacitor for safety purposes. limited energy in the load capacitor reduces burn and shock An optional adjustable voltage clamp prevents TRIAC hazards. The conventional load and snubber circuit pro- breakdown. vides recovery and damping behaviors like those in the To measure ǒdVǓ , synchronize the storage scope on the application. dt c The voltage across the load capacitor triggers the D.U.T. current waveform and verify the proper current amplitude It terminates the gate current when the load capacitor volt- and period. Increase the initial voltage on the capacitor to age crosses zero and the TRIAC current is at its peak. compensate for losses within the coil if necessary. Adjust Each VDRM, ITM combination requires different compo- the snubber until the device fails to turn off after the first nents. Calculate their values using the equations given in half-cycle. Inspect the rate of voltage rise at the fastest Figure 39. passing condition.

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HG = W AT LOW LD10‐1000‐1000 NON‐INDUCTIVE + CLAMP - CLAMP LL RL RESISTOR DECADE 0-10 k, 1 Ω STEP TRIAD C30X 51 k 50 H, 3500 Ω 2 W 910 k

2.2 M, 2W 2.2 M, 2W Q Q MR760 2 W 3 1 51 k 2 W 2.2 M 2.2 M

μ 910 k R S 2 W + 1.5 kV 2N3904 2N3906 62 μF 6.2 MEG 2 W 1 kV L + C (NON‐POLAR) - 70 mA 0.01 120 1/2 W 0.01 - 6.2 MEG 2 W 2.2 M 2.2 M MR760 MR760 1/2 W 120 0‐1 kV 20 mA 150 k μ 2N3906 2N3904

Q3 Q1 2N3906 2N3904 - 5 + 5

μ 0.1 0.1 PEARSON 301 X 360 1/2 W 360 1/2 W 2N3904 2N3906 1 k 1 k 2 CASE CONTROLLED 2N3904 HEATSINK 1 -+ 51 2 W C 2N3906 S + 5 51 2 W - 5 G 56 2 WATT Q3 Q1 TRIAC 0.22 0.22

CAPACITOR DECADE 1-10 F, 0.01-1 F, 100 pF- 0.01 F 0.01-1 F, DECADE 1-10 F, CAPACITOR dV 270 k 1N5343 2.2 k UNDER dt TEST 7.5 V 270 k SYNC 1/2

I Ip T V 2 ǒ + PK + + Ci + T + I ǒdIǓ + *6Ǔ CL p LL W0 6f IPK 10 W0 V 2 V W0 I 4 p 2C ǸL dt c Ci Ci PK L L Ańms

dV Figure 6.39. ǒ Ǔ Test Circuit For Power TRIACs dt c

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APPENDIX C CONSTANTS (depending on the damping factor): dV DERIVATIONS 2.1 No Damping (ρ + 0) dt w + w0 + a + ρ + DEFINITIONS RT 0 + ) + 1.0 RT RL RS Total Resistance 2.2 Underdamped (0 t ρ t 1) Ǹ 2 2 Ǹ 2 w + w0 * a + w0 1 * ρ RS 1.1 M + + Snubber Divider Ratio R T 2.3 Critical Damped (ρ + 1) a + w w + + ǸL + 2 1.2 w + 1 + Undamped Natural Frequency 0, 0, R 2 ,C a 0 Ǹ C RT LCS w + Damped Natural Frequency 2.4 Overdamped (ρ u 1) Ǹ 2 2 Ǹ 2 w + a * w0 + w0 ρ * 1 RT 1.3 a + + Wave Decrement Factor 2L Laplace transforms for the current and voltage in Figure 40 are: 1ń2LI2 Initial Energy In Inductor SV * c 1.4 χ2 + + ń ) 0L ń 2 Final Energy In Capacitor + E L SI +E * 1 2CV 3.0 i(S) ;e RT S RT S2)S ) 1 S2) S) 1 L LC L LC 1.5 χ + I ǸL + Initial Current Factor E C

R L RT a L 1.6 ρ + ǸC + + Damping Factor 2 L w0 t = 0 I RS 1.7 V + E * R I + Initial Voltage drop at t + 0 0L S e across the load CS

ER INITIAL CONDITIONS I L 1.8 c + * I + I C L RRM S V + 0 CS ǒdVǓ + Initial instantaneous dV at t + 0, ignoring dt 0 dt Figure 6.40. Equivalent Circuit for Load and Snubber any initial instantaneous voltage step at + t 0 because of IRRM The inverse laplace transform for each of the conditions gives:

RT UNDERDAMPED (Typical Snubber Design) 1.9 ǒdVǓ + V ) c. For all damping conditions dt OL L a * a 0 4.0 e + E * V ƪCos (wt) * sin (wt)ƫe t ) 0L w c ERS w *at 2.0 When I + 0, ǒdVǓ + w sin ( t) e dt 0 L dV dV ǒ Ǔ + Maximum instantaneous w2 * a2 dt dt de + ƪ a w ) ( ) w ƫ −at) max 4.1 V0 2 Cos ( t) w sin ( t) e dV dt L tmax + Time of maximum instantaneous dt ƪ a ƫ −at + c Cos (wt) * sin (wt) e tpeak Time of maximum instantaneous peak w voltage across thyristor ȱ ȳ dV + ń + Average VPK tPK Slope of the secant line 2a V ) c dt 1 *1 0L 4.2 t + w tan ȧ* ȧ from t + 0 through V PK ȧ caȧ PK ǒw2*a2Ǔ * + V0 w w VPK Maximum instantaneous voltage across the Ȳ L ȴ thyristor. + + + w + p When M 0, RS 0, I 0: tPK

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Ǹ 2 + * ƪ a c ƫ −a t a * a t w 2 V ) 2ac V ) c2 6.3 VPK E V0 (1− tPK)− tPK e PK 4.3 V + E ) PK 0 0L 0L L PK w0 When I + 0, R + 0, M + 1: L VPK 6.4 Average dV + dt tPK V PK * a + + + 4.4 + (1 ) e tPK) When I 0, R 0, M 0 E S dV VPK e(t) rises asymptotically to E. t and average Average dV + PK dt dt tPK do not exist.

w (2ac * V (w2 * 3a2)) 3aV ) 2c + 1 ƪ 0L ƫ + 0L 4.5 tmax w ATN 6.5 tmax V (a3 * 3aw2) ) c(a2 * w2) a2V ) ac 0L 0L When I + 0, tmax + 0 ǒdVǓ +Ǹ 2 w 2) ac ) c2 −at R 4.6 V0 0 2 V0 e max S y ń dt max L L For 3 4, RT NO DAMPING then dV + ǒdVǓ dt max dt 0 I 5.0 e + E(1* Cos (w0t)) ) sin (w0t) C w0 ǒdVǓ de I 6.6 5.1 + E w0 sin (w0t) ) Cos (w0t) dt max dt C a +ƪa V (2−a t ) ) c (1−a t ) ƫe− tmax 0L max max 5.2 ǒdVǓ + I + 0whenI+ 0 dt 0 C

* p * tan 1ǒ I Ǔ CE w0 + APPENDIX D 5.3 tPK w 0 SNUBBER DISCHARGE dI DERIVATIONS dt 2 5.4 V + E ) ǸE2 ) I PK OVERDAMPED w02C2 V CS a dV VPK 1.0 i + a− t sinh (wt) 5.5 ǒ Ǔ + w L dt AVG tPK S

w 1 *1ǒ 0 ECǓ 1 p CS a 5.6 tmax + ƪtan ƫ + when I + 0 1.1 i + V Ǹ e− t w I w 2 PK CS PK 0 0 LS

ǒdVǓ + I Ǹ 2w 2 2) 2 + w + 5.7 E 0 C I 0EwhenI 0 + 1 −1 ƪwƫ dt max C 1.2 tPK w tanh a

CRITICAL DAMPING CRITICAL DAMPED *a *a 6.0 e + E * V (1 * at)e t ) cte t 0L VC a 2.0 i + S te− t *a L 6.1 de + ƪa V (2 * at) ) c(1 * at)ƫe t S dt OL V c + CS 2 ) 2.1 iPK 0.736 2V RS + 0L 6.2 tPK c a ) 1 V 2.2 t + 0L PK a

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UNDERDAMPED NO DAMPING VC a V 3.0 i + S e− t sin (wt) + CS w w L 4.0 i w sin ( t) S LS

CS a 3.1 i + V Ǹ e− t CS PK CS PK 4.1 i + V Ǹ LS PK CS LS 1 ǒwǓ 3.2 t + w tan −1 a p PK 4.2 t + PK 2 w

RS LS

t = 0

V CS CS i

INITIAL CONDITIONS : i + 0, V + INITIAL VOLTAGE CS

Figure 6.41. Equivalent Circuit for Snubber Discharge

BIBLIOGRAPHY

Bird, B. M. and K. G. King. An Introduction To Power Kervin, Doug. “The MOC3011 and MOC3021,” EB-101, Electronics. John Wiley & Sons, 1983, pp. 250−281. Motorola Inc., 1982. Blicher, Adolph. Thyristor Physics. Springer-Verlag, 1976. McMurray, William. “Optimum Snubbers For Power Gempe, Horst. “Applications of Zero Voltage Crossing Semiconductors,” IEEE Transactions On Industry Applica- Optically Isolated TRIAC Drivers,” AN982, Motorola Inc., tions, Vol. IA-8, September/October 1972. 1987. “Guide for Surge Withstand Capability (SWC) Tests,” Rice, L. R. “Why R-C Networks And Which One For Your ANSI 337.90A-1974, IEEE Std 472−1974. Converter,” Westinghouse Tech Tips 5-2. “IEEE Guide for Surge Voltages in Low-Voltage AC Power “Saturable Reactor For Increasing Turn-On Switching Circuits,” ANSI/IEEE C62.41-1980, IEEE Std 587−1980. Capability,” SCR Manual Sixth Edition, General Electric, 1979. Ikeda, Shigeru and Tsuneo Araki. “The dI Capability of dt Thyristors,” Proceedings of the IEEE, Vol. 53, No. 8, Zell, H. P. “Design Chart For Capacitor-Discharge Pulse August 1967. Circuits,” EDN Magazine, June 10, 1968.

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