Europaisches Patentamt 19 European Patent Office

Office europeen des brevets © Publication number: 0 614 267 A1

12 EUROPEAN PATENT APPLICATION

(2j) Application number : 94301445.6 6i) Int. CI.5 : H02M 7/06

(22) Date of filing : 01.03.94

(§) Priority : 05.03.93 US 27031 @ Inventor : Tsai, Fu Sheng 105 Bartlett Street @ Date of publication of application : Northboro, Massachusetts 01532 (US) 07.09.94 Bulletin 94/36 Inventor : Dhaval, Dalai B. 70-9 Commons Drive Shrewsbury, Massachusetts 01545 (US) @ Designated Contracting States : DE FR GB IT (74) Representative : Goodman, Christopher et al Eric Potter & Clarkson © Applicant : DIGITAL EQUIPMENT St. Mary's Court CORPORATION St. Mary's Gate 146 Main Street Nottingham NG1 1LE (GB) Maynard, Massachusetts 01745 (US)

@) Lossless active snubber for half-bridge output .

(57) A bridge-type primary switching circuit (12) is represented by a pulsed source (VSW). The primary switched waveform is transformed to secondary circuit (14) using a transformer (T1) with the required turns ratio N and a cen- ter-tapped secondary winding (16). Half-bridge (18) formed by (DR1) and (DR2) rectifies the secondary waveform and feeds the waveform through a low-pass filter (LF) and (CF) to obtain the desired DC output voltage. The snubber circuit (20) is represented by -- combinations (SA- DS1-CS1) and (SB-DS2-CS2) across each rec- tifier (DR1) and (DR2). Capacitances (CS1) and (CS2) are selected large enough such that their remain essentially constant during a switching cycle. The controlled (SA) and (SB) are turned ON with a specific delay after the primary voltage reaches a magnitude close to the input voltage in order to allow the rectifier diodes (DR1) and (DR2) to be commu- tated. It is crucial that the switches (SA) and (SB) be turned OFF before the primary voltage collapses to zero to avoid current spikes through the switches.

S o Q_ LU Jouve, 18, rue Saint-Denis, 75001 PARIS 1 EP 0 614 267 A1 2

BACKGROUND OF THE INVENTION medium voltage power converters have adopted.

1. Field of the Invention SUMMARY OF THE INVENTION

The present invention relates generally to a cir- 5 These and related problems may be solved and cuit for controlling voltage spikes and ringing during features may be obtained through use of the novel turn-off of half-bridge rectifiers in bridge-type pulse lossless active snubber for half-bridge output rectifi- width modulated - direct current (PWM ers herein disclosed. The invention in its broad form DC-DC) converters. More particularly, it relates to resides in a pulse width modulated DC to DC current such a circuit for controlling voltage spikes and ring- 10 converter as recited in claim 1. ing which redirects energy in a leakage inductance of A lossless active snubber for a half bridge output a transformer to a load in a lossless manner using ac- rectifier as described herein includes a bridge-type tive switches. Most especially, it relates to such a cir- primary switching circuit having an input for a direct cuit for controlling voltage spikes and ringing which current at a first voltage and having an output supply- permits use of lower voltage rectifiers and signifi- 15 ing a chopped signal derived from cantly reduces conduction losses. the direct current. A transformer includes a primary winding connected to the output and a center-tapped 2. Description of the Prior Art secondary winding. A half-bridge rectifier includes first and second rectifier diodes connected to the two When output rectifiers of a PWM DC-DC conver- 20 end terminals of the center-tapped secondary wind- ter with transformer isolation turn off, voltage spikes ing. Asnubber circuit is connected across the first and and high-frequency ringing are induced across the second rectifier diodes. The snubber circuit includes rectifier terminals due to the presence of leakage in- a first snubber diode connected in a reverse direction ductances in the transformer. The voltage spikes im- to the first rectifier diode. A first snubber capacitor is pose severe stresses on the rectifiers and force one 25 serially connected to the first snubber diode. The first to use higher voltage rectifiers, resulting in higher snubber diode and first snubber capacitor are con- conduction losses. Traditionally, resistance - capaci- nected across the first rectifier diode. A first control- tance (R-C) or resistance - diode - capacitance (R-D- lable switch is connected across the first snubber di- C) snubber circuits are used across the rectifiers to ode. A second snubber diode is connected in a re- limit the voltage spikes. The capacitance chosen in an 30 verse direction to the second rectifier diode. A first R-C or R-D-C snubber is usually much larger than the control signal input is connected to the first controlla- junction capacitance of the rectifier, so that the ma- ble switch to turn the first controllable switch ON dur- jority of the leakage inductor current is diverted ing a maximum magnitude of a first sign in a pulse of through the snubber, resulting in a smaller voltage the chopped alternating current signal. overshoot. The provides necessary damping 35 to reduce ringing, but it dissipates energy. The energy BRIEF DESCRIPTION OF THE DRAWINGS stored in the has to be redirected to the load each cycle when the rectifier turns on. This in- A more detailed understanding of the invention troduces additional losses in the resistor unless a di- may be had from the following description of a prefer- ode is used across it (R-D-C). Tradeoffs are usually 40 red embodiment, given by way of example and to be necessary in the choice of R and C values, since a understood in conjunction with the accompanying large capacitance reduces voltage spikes while in- drawing wherein: creasing the power dissipation, and a smaller resis- Figure 1 is a previously proposed active snubber tance reduces losses while decreasing the damping for a full-bridge rectifier. effects. An optimum design is hard to achieve. 45 Figure 2 is a generalized circuit schematic of a Various clamping and snubbing circuits have lossless active snubber for half-bridge output rectifi- been proposed to limit or eliminate voltage spikes ers in accordance with a preferred embodiment of the across rectifiers. It is known to provide a R-D-C clamp invention. circuit for a full-bridge rectifier as shown in Figures 1 Figure 2A is a set of waveform diagrams for the and 1A in the present application. Although such a cir- 50 circuit of Figure 2. cuit can effectively limit the voltage across the recti- Figure 3 is a block diagram of one form of a con- fier, significant energies are lost in the discharging re- trol signal generator for the circuit of Figure 2. sistance. A known lossless active snubber circuit to- Figure 3A is a set of waveform diagrams for the tally eliminates voltage overshoot and ringing across control signal generator of Figure 3. a full-bridge rectifier. While this circuit appears to 55 Figure 4 is a block diagram of another form of a have many virtues and requires a few extra compo- control signal generator for the circuit of Figure 2. nents, it is not clear whether and how it can be imple- Figure 4A is a set of waveform diagrams for the mented in a half-bridge rectifier, which most low to control signal generator of Figure 4. 2 3 EP 0 614 267 A1 4

Figure 5 is a set of waveforms for a condition source and the drain to represent these MOSFET when SA and SB are not turned off before Vsw characteristics. Separate capacitors and diode ele- changes magnitude significantly. ments are not actually present in the circuit. Figure 6 is a circuit schematic of a second em- The detailed circuit operation is as follows. As the bodiment of a lossless active snubber for half-bridge 5 voltage pulse in the primary of the transformer T1 output rectifiers in accordance with an embodiment of goes positive, the dotted terminals in the secondary the invention. go positive. Rectifier diode DR1 turns ON and com- Figure 6A is a set of waveform diagrams for the mutation of DR2 starts. The current through DR2 is circuit of Figure 6. decreased to zero and begins to flow in the reverse Figure 7 is a circuit schematic of a third embodi- 10 direction (reverse recovery). After the reverse recov- ment of a lossless active snubber for half-bridge out- ery is completed, DR2 turns OFF and the current, put rectifiers in accordance with an embodiment the which can not instantaneously go to zero due to the invention. presence of LS2, flows through CS2 and DS2, as this Figure 7A is a set of waveform diagrams for the is the lowest impedance path. The voltage across circuit of Figure 7. 15 DR2 is clamped to the voltage of CS2. If CS2 is chos- en sufficiently high, its voltage will be held at a con- DETAILED DESCRIPTION OF THE INVENTION stant value, preventing any ringing or overshoot. The recovery current charges CS2 up, whose energy is Turning now to the drawings, more particularly to then discharged to the load when SB is turned ON. As Figures 2 and 2A, there is shown a simplified sche- 20 a result, a majority of the leakage energies are recov- matic of the proposed circuit 10 and several wave- ered and delivered to the load instead of being dissi- forms related thereto. A bridge-type primary switch- pated in the external resistances. Before the voltage ing circuit 12 is represented by a pulsed voltage in the primary starts decreasing, SB is turned OFF to source VSW. The primary topology can be a half- disengage CS2 from the rest of the circuit. This pre- bridge, a full bridge or any other configuration of 25 vents large current spikes from being generated switches which chops the DC input voltage into an AC through SB when the primary voltage decreases. The form at a given switching frequency. The primary circuit is then returned to conventional operation. As switched waveform VSW (Figure 2A) is transformed the primary voltage reaches zero, DR2 is turned ON to secondary circuit 14 using a transformer T1 with and the filter inductor current free-wheels through the required turns ratio N and a center-tapped sec- 30 both DR1 and DR2 until the primary voltage goes ondary winding 16. Transformer T1 primary leakage negative. At that instant, a similar process occurs with inductance and magnetizing inductance are repre- the roles of DR1, CS1, SA, DS1 and DR2, CS2, SB, sented by LP and LM, respectively, and its secondary DS2 interchanged, respectively. leakage inductances are represented by LS1 and The gate-drive signals for auxiliary switches SA LS2. Half-bridge rectifier 18 formed by diodes DR1 35 and SB are derived from the primary gate-drive sig- and DR2 rectifies the secondary waveform and feeds nals as illustrated in Figures 3-3B and Figures 4-4B. the waveform through a low-pass filter LF and CF to Certain conditions have to be metforthis snubber cir- obtain the desired DC output voltage. cuit to function properly. First, it is required that SA or The snubber circuit 20 is represented by switch- SB not be turned ON while DR1 or DR2 are conduct- diode-capacitor combinations SA-DS1-CS1 and SB- 40 ing, including the reverse recovery period. Hence, the DS2-CS2 across each rectifier DR1 and DR2. Capac- turn ON of SA or SB must be delayed by a fixed itances CS1 and CS2 are selected large enough such amount of time with respect to the turn ON of Q3 and that their voltages remain essentially constant during Q4 or Q1 and Q2 to allow proper commutation of DR1 a switching cycle. VCTAand VCTB are the control vol- or DR2. Also, it is essential that SA or SB be turned tages for switches SAand SB, respectively. The con- 45 OFF prior to the magnitude of the primary voltage de- trolled switches SAand SB are turned ON with a spe- creasing significantly. Otherwise, high current spikes cific delay after the primary voltage VSW reaches a will be generated through the leakage inductances, magnitude close to the input voltage in order to allow as shown in Figure 5, and significant losses intro- the rectifier diodes DR1 and DR2 to be commutated. duced in the auxiliary switches. It is crucial that the switches SA and SB be turned so Figures 3 and 3A illustrate the implementation of OFF before the voltage VSW collapses to zero to gate-drive signals for the active snubber in a conven- avoid current spikes through the switches (Figure 5). tional full-bridge PWM converter 22, where switches MOSFETS are used to represent the controlled Q1 , Q2 or Q3,Q4 are turned ON/OFF simultaneously. switches (SA and SB) in the active snubbers; how- Asimilarcircuitappliesfora half-bridge PWM conver- ever, any controlled switches, such as BJT, IGBT, and 55 ter. The logic signals GP1 and GP2 are generated by so forth may be used for this purpose. The MOSFET certain PWM control. A time delay td1 is introduced switches in the Figures are drawn with a phantom or in GP1 or GP2 to generate the gating signals G1, G2 dashed capacitor and diode in parallel between the or G3, G4 for the primary switches Q1 , Q2 or Q3, Q4. 3 5 EP 0 614 267 A1 6

Another front edge time delay td2 is introduced in rectifiers have lower forward drop leading to low- GP1 or GP2 to generate gating signals GB or GAfor er conduction losses. In a specific implementa- the auxiliary switch SB or SA. Both delays can be ac- tion providing a 48 volt output at 1 500 watts, vol- counted for by the propagation delays in the logic tage requirements for the rectifiers would have gates, the driver chips or the gate-drive circuits in- 5 been between 400 and 600 volts without the use cluding the gate-drive transformers. The delay td1 of the active snubber circuit. With the snubber cir- should allow SB or SA to turn OFF before Q1 , Q2 or cuit, it is possible to use 200 volt rectifiers and Q3, Q4, while the delay td2 should provide enough still maintain sufficient margin. The forward time for DR1 or DR2 to complete commutation before drops are approximately 0.95, 1 .3 and 1 .5 volts SA or SB is turned ON. In general, td2 need not be 10 for the 200, 400 and 600 volt rectifiers, respec- tightly controlled. tively. This means savings of 1 0-1 5 watts in con- Figures 4-4A illustrate the gating arrangement for duction losses alone. Another significant advan- implementing the lossless active snubbing in a tage of using lower voltage rectifiers lies in the re- phase-controlled PWM converter 24. In this circuit, all verse recovery characteristics of the rectifiers. the primary switches are operated with 50% duty cy- 15 Due to the limitations in current device technolo- cle, and the output is controlled by changing the gy, the reverse recovery current in rectifier di- phase delay between gating signals for Q1 and Q2 or odes become much higher when the devices are Q3 and Q4. In Figures 4-4A, four logic signals GP1- rated above 200 volts. Also, at higher di/dt condi- GP4 are generated from a phase controlled PWM cir- tions, the recovery behavior of the rectifiers can- cuit 26 with GP1 and GP3 or GP2 and GP4 being com- 20 not be well-controlled. On certain occasions, plementary pulses. Each pulse is almost at 50% duty- thermal runaway is observed when higher vol- cycle. As explained earlier, SB or SA should be trig- tage devices are used to sustain voltage spikes. gered only when DR2 or DR1 is OFF. This occurs Higher recovery current also makes the snubber when VSW is positive or negative, respectively. Thus, design more difficult. GB or GA is generated by ANDing GP1 and GP2 or 25 (b) Due to the lossless nature of this circuit, the GP3 and GP4 with proper front-edge delay intro- energies in the leakage inductances of the trans- duced as shown. The selection of the delays is similar former are redirected to the load without going to the case of the conventional full-bridge PWM con- through dissipative , as in the conven- verter. tional R-C or R-D-C snubbers. The measured im- The snubbing circuit as described above is opera- 30 provement in efficiency is about 2.5 to 3 percent tional from no load to full load. In otherwords, it is op- (35-40 watts) over a circuit using conventional R- erational in both continuous and discontinuous C snubbers. Reduced losses also lead to smaller modes of operation. heat sinks and thus, reduced cost. Lower thermal The snubber circuit can be simplified to reduce stresses improve the reliability of the rectifier. the number of components. By tying the sources of 35 Elimination of high-frequency ringing reduces MOSFETs SAand SB together as shown in Figures 6 radiated and conducted EMIs. The cost and com- and 6A, the capacitor CS2 (Figure 2) can be elimin- plexity of additional components (1 less capaci- ated. There is no detrimental effect when only one ca- tor, 2 more diodes, 2 less resistors, 1 or 2 more pacitor is used. Furthermore, one of the auxiliary controlled switches and additional related drive switches can also be eliminated, as shown in Figures 40 circuitry as compared to a conventional R-C 7 and 7A. In so doing, capacitor CSA is charged every snubber) are easily offset by the gains outlined half-cycle, but discharged every other half-cycle, above. which results in slightly higher voltage fluctuation It should be apparent to those skilled in the art across the capacitor and slight imbalance in circuit that various changes in form and details of the inven- operation. The impact, however, is minimal. It should ts tion as shown and described may be made. It is in- be noted that the anti-parallel diodes DS1, DS2 have tended that such changes be included within the to be present across each of the rectif ierdiodes DR1 , scope of the present invention. DR2 under all circumstances. A primary advantage of the active snubber circuit of this invention is that it totally eliminates snubbing so Claims losses and high-frequency ringing, which results in higher efficiency, smaller size, reduced cost, im- 1. A pulse width modulated direct current - direct proved reliability and reduced electromagnetic inter- current converter circuit, (10) which comprises a ference (EMI). Power losses are reduced for two rea- bridge-type primary switching circuit (12) having sons: 55 an input for a direct current at a first voltage and (a) The circuit enables the use of lower voltage having an output supplying a chopped alternating rectifiers because it eliminates voltage spikes current signal {Vsw} derived from the direct cur- and ringing across the rectifiers. Lower voltage rent, a transformer {TJ including a primary wind- 4 7 EP 0 614 267 A1 8

ing connected to the output of the primary circuit mary winding, fifth and sixth controllable and a center-tapped secondary winding (16), a switches connected between said inputforthedi- half-bridge rectifier (18), including first and sec- rect current and another end of said transformer ond rectifier diodes (DR1DR2, } connected to primary winding, a third and fourth control signal each of two end terminals of said center-tapped 5 input connected to said third and fourth control- secondary winding, and a snubber circuit (20) lable switches to turn said third and fourth con- connected across said first and second rectifier trollable switches ON during a maximum magni- diodes, said snubber circuit including a first snub- tude of a first sign in a pulse of the chopped al- ber diode (DSi) connected in a reverse direction ternating current signal. to said first rectifier diode, a first snubber capac- 10 itor (CSi) serially connected to said first snubber 5. The pulse width modulated direct current - direct diode (DSi), said first snubber diode and first current converter circuit of claim 4 in which said snubber capacitor being connected across said first, third, fourth, fifth and sixth controllable first rectifier diode (DR^, a first controllable switches comprise metal oxide semiconductor switch (SA) connected across said first snubber 15 field effect transistors. diode, a second snubber diode (DS2) connected in a reverse direction to said second rectifier di- 6. The pulse width modulated direct current - direct ode and a first control signal input, (VGA) connect- current converter circuit of claim 4 in which the ed to said first controllable switch to turn said first first control signal and the third control signal are controllable switch ON during a maximum mag- 20 generated from a common control signal by nitude of a first sign in a pulse of the chopped al- means of a first delay element for the first control ternating current signal. signal and a second delay element for the third control signal. 2. The pulse width modulated direct current - direct current converter circuit of claim 1 additionally 25 7. A pulse width modulated direct current - direct comprising a second controllable switch (SB) current converter circuit, which comprises a connected across said second snubber diode bridge-type primary switching circuit having an (DS2) and a second control signal input connect- input for a direct current at a first voltage and hav- ed to said second controllable switch to turn said ing an output supplying a chopped alternating second controllable switch ON during a maxi- 30 current signal derived from the direct current, a mum magnitude of a second sign opposite to the transformer including a primary winding connect- first sign in a pulse of the chopped alternating ed to the output of the primary circuit and a cen- current signal. ter-tapped secondary winding, a half-bridge rec- tifier including first and second rectifier diodes 3. The pulse width modulated direct current - direct 35 connected to each of two end terminals of said current converter circuit of claim 2 in which said center-tapped secondary winding, and a snubber first and second controllable switches each have circuit connected across said first and second current flow electrodes which are connected to- rectifier diodes, said snubber circuit including a gether and connected to said first snubber capac- first snubber diode connected in a reverse direc- itor, said converter additionally comprising a sec- 40 tion to said first rectifier diode, a first snubber ca- ond snubber capacitor (CS2) serially connected to pacitor serially connected to said first snubber di- said second snubber diode (DS2), said second ode, said first snubber diode and first snubber ca- snubber diode and second snubber capacitor be- pacitor being connected across said first rectifier ing connected across said second rectifier diode diode, a first controllable switch connected (DR2) and further comprising a low-pass filter 45 across said first snubber diode, a second snub- (LF, CF) connected to said first and second rec- ber diode connected in a reverse direction to said tifier diodes, an output of said low-pass filter pro- second rectifier diode, a first control signal input viding a direct current output (RL) at a second vol- connected to said first controllable switch to turn tage. said first controllable switch ON during a maxi- 50 mum magnitude of a first sign in a pulse of the 4. The pulse width modulated direct current - direct chopped alternating current signal and a second current converter circuit of claim 1 in which said controllable switch connected across said sec- bridge-type primary switching circuit is a full- ond snubberdiode and a second control signal in- bridge pulse width modulated switching circuit, put connected to said second controllable switch and wherein said bridge-type primary switching 55 to turn said second controllable switch ON during circuit comprises third and fourth controllable a maximum magnitude of a second sign opposite switches connected between said input for the di- to the first sign in a pulse of the chopped alternat- rect current and one end of said transformer pri- ing current signal. 5 EP 0 614 267 A1

6

EP 0 614 267 A1 G1, G2 DELAY td1 OUINVtlN I IUIMAL PWM G3, G4 DELAY td1

J FRONT-EDGE GB !4 I DELAY td2

h" usw — t FRONT-EDGE GB DELAY td2

FIG. 3

i s TS , 2 2

GP2_ 4*i V 11, G2_

□1 i3, G4_ 3d.

GB_ fir 32

GA_

■IG. 3A EP 0 614 267 A1

24 GP1 I G1 DELAY td1 PHASE- GP2 G2 DELAY td1 CONTROLLED GP3 G3 PWM DELAY td1 GP4 G4 DELAY td1 v. 26

FRONT-EDGE GB^ * DELAY td2

GA FIG. 4 FRONT-EDGE DELAY td2

TS ' 2 2

3W

GP1

GP3_

GP2

GP4.

3P1* GP2_

3P3* GP4_

GB _ tdZ GA ■ iii _ 3* tan Q1 Ll ■ i ten G3 — j]j 7i td1 - 32 — U; tan - 34 FIG. 4A _

lu tP U t>14Zb/ Al tP U t>14Zb/ Al J tP U t>14Zb/ Al

EP 0 614 267 A1

European Patent EUROPEAN SEARCH REPORT Application Number Office EP 94 30 1445

DOCUMENTS CONSIDERED TO BE RELEVANT Category Citation of document with indication, where appropriate, Relevant CLASSIFICATION OF THE of relevant passages to claim APPLICATION (lnt.CI.5) EP-A-0 443 342 (BONNET) 1,7 H02M7/06 * figure 1A *

WO-A-83 02370 (BECKMAN) 1,7 * figure 3 *

TECHNICAL FIELDS SEARCHED (lnt.CI.5) H02M

The present search report has been drawn up for all claims Place of search Date af coBftletioB of Ike search THE HAGUE 8 April 1994 Bertin, M CATEGORY OF CITED DOCUMENTS T : theory or principle underlying the invention E : earlier patent document, but published on, or X : particularly relevant if taken alone after the filing date V : particularly relevant if combined with another D : document cited in the application document Df the same category L : document cited for other reasons A : technological background O : non-written disclosure & : member of the same patent family, corresponding P : intermediate document document

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