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Area Array Packages with Known Reliably and Mitigation Risks, Allowing Greater Processing Power in a Smaller Board Footprint and Lower System Weight

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Area Array Packages with Known Reliably and Mitigation Risks, Allowing Greater Processing Power in a Smaller Board Footprint and Lower System Weight National Aeronautics and Space Administration Reliability of CGA/LGA/HDI Package Board/Assembly (Revision A) Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California Jet Propulsion Laboratory California Institute of Technology Pasadena, California JPL Publication 12-3 2/12 National Aeronautics and Space Administration Reliability of CGA/LGA/HDI Package Board/Assembly (Revision A) NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California NASA WBS: 724297.40.43 JPL Project Number: 104593 Task Number: 40.49.02.02 Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109 http://nepp.nasa.gov This research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, and was sponsored by the National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology. Copyright 2013. California Institute of Technology. Government sponsorship acknowledged. Acknowledgments The author would like to acknowledge many people from industry and the Jet Propulsion Laboratory (JPL) who were critical to the progress of this activity. The author extends his appreciation to program managers of the National Aeronautics and Space Administration Electronics Parts and Packaging (NEPP) Program, including Michael Sampson, Ken LaBel, Drs. Charles Barnes and Douglas Sheldon for their continuous support and encouragement. ii OBJECTIVES AND PRODUCTS Commercial-off-the-shelf column grid array (COTS CGA) packaging technologies in high-reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. The previous report on this subject presented test data and assembly information for CGA packages with 1752 and 1272 inputs/outputs (I/Os) and 1-mm pitch. Also presented were test results for a number of land grid arrays (LGAs) with 1517 I/Os that were converted to CGAs and subjected to column pull testing—first, as attached and, subsequently, at intervals during isothermal aging at 125°C. These CGAs were also successfully assembled onto PCBs for subsequent environmental reliability testing. This follow-up report presents reliability test results conducted by thermal cycling of five CGA assemblies evaluated under two extreme cycle profiles, representative of use for high-reliability applications. The thermal cycles ranged from a low temperature of −55°C to maximum temperatures of either 100°C or 125°C with slow ramp-up rate (3°C/min) and dwell times of about 15 minutes at the two extremes. Optical photomicrographs that illustrate key inspection findings of up to 200 thermal cycles are presented. Other information presented include an evaluation of the integrity of capacitors on CGA substrate after thermal cycling as well as process evaluation for direct assembly of an LGA onto PCB. The qualification guidelines, which are based on the test results for CGA/LGA/HDI packages and board assemblies, will facilitate NASA projects’ use of very dense and newly available FPGA area array packages with known reliably and mitigation risks, allowing greater processing power in a smaller board footprint and lower system weight. Key Words: CGA, CCGA, LGA, BME Capacitor, solder joint reliability, thermal cycle, column grid array, 2nd level reliability iii Table of Contents 1.0 Executive Summary .............................................................................................................................................. 1 2.0 GAs and Evaluation Approaches .......................................................................................................................... 4 2.1 Column Grid Array Packaging Technology Trend ........................................................................................ 4 2.2 Purpose of This 2nd Interim Report ............................................................................................................... 5 3.0 Experimental Approaches for CGA Packages ...................................................................................................... 6 3.1 CCGA Package Types ................................................................................................................................. 6 3.2 CGA Package Receiving, Inspection, and Evaluation .................................................................................. 6 3.2.1 CGA Package Characterization by X-ray .......................................................................................... 7 3.2.2 Chip Capacitor Characterization ........................................................................................................ 7 3.2.3 Chip Capacitor Characterization after Thermal Shock Cycles of Unattached CGA ........................... 9 3.2.4 Chip Capacitor Failure Analysis after Thermal Shock Cycles of CGA Assembly ............................ 10 3.2.5 BME Capacitor Grain Size Evaluation ............................................................................................. 14 3.3 Test Vehicle Design and Assembly Parameters for CGA1272/1752 ......................................................... 16 3.4 Solder Paste Volume Measurement ........................................................................................................... 17 3.5 Attachment Procedures .............................................................................................................................. 18 4.0 Test Results after TV Build ................................................................................................................................. 19 4.1 Daisy-Chain Resistance Results ................................................................................................................ 19 4.2 Inspection ................................................................................................................................................... 19 4.3 X-Ray Characterization .............................................................................................................................. 20 4.4 Optical Microscopy Characterization .......................................................................................................... 20 4.5 Thermal Cycle Test Profiles ....................................................................................................................... 21 4.5.1 Damage Progress with Thermal Cycling (–55°/100°C) ................................................................... 22 4.5.2 Damage Progress with Thermal Cycles (–55°/125°C) .................................................................... 24 5.0 Experimental Approaches for LGA Packages ..................................................................................................... 26 5.1 LGA Column Attach ................................................................................................................................... 26 5.2 Test Vehicle Design and Assembly Parameters for CGA1272/1509/1517 ................................................ 26 5.3 Optical Microscopy Characterization of LGA/CGA ..................................................................................... 27 5.3.1 After Assembly ................................................................................................................................ 27 5.4 Thermal Cycle Test Results (−55°/100°C) ................................................................................................ 28 5.5 Thermal Cycle Test Results (−55°/125°C) ................................................................................................ 30 5.6 Direct LGA Assembly on PCB .................................................................................................................... 32 6.0 Status Results ..................................................................................................................................................... 36 7.0 Acronyms and Abbreviations .............................................................................................................................. 38 8.0 References .......................................................................................................................................................... 39 iv 1.0 EXECUTIVE SUMMARY The overall objectives and approaches of the reliability evaluation of CGA/LGA/HDI package/board/assembly are summarized in Figure 1. Topics marked with smiley faces are investigated and either presented previously [1] or will be covered in this or follow-on reports when sufficient data become available. The overall goal is to develop qualification guidelines for advanced high input/output (I/O) column/land grid array (CGA/LGA) assembled onto both conventional and high density interconnect (HDI) printed circuit/wiring boards (PCB/PWB). This report will briefly address results for package evaluation and assembly optimization as well as detail results of thermal cycle testing and failure analyses. Figure 1. Test matrix
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