Simulating and Designing an RF Transmitter for Small Satellites

High Frequency Design From May 2007 High Frequency Electronics Copyright © Summit Technical Media, LLC SATELLITE TRANSMITTER Simulating and Designing An RF Transmitter for Small Satellites By Mohamed Kameche, CNTS, and Samir Kameche, University of Tlemcen, Algeria his paper discusses before detailed circuit implementation. Here is a case history the design and Today’s transmitter subsystems in earth describing the specifica- Tsimulation of an imaging microsatellite systems demand high- tions and design process RF transmitter for small er communication quality and higher data for an S-band telemetry satellites operating in the rates to transmit pictures or data with higher transmitter used in a commercial S-band (2.2- frequency operation and more channels per micro- or nanosatellite 2.29 GHz) with a data unit bandwidth. Low power consumption and rate of 8 Mbps. In such small size are required for this equipment. In systems, modeling frequency-dependent non- this module, modeling frequency-dependent linear characteristics of complex analog blocks nonlinear characteristics of complex analog and subsystems is critical for enabling effi- blocks and subsystems is critical for enabling cient verification of mixed-signal system efficient verification of mixed-signal system designs. In order to provide efficient and accu- designs. It’s well known that the mixer and rate simulation for the transmitter circuits, the power amplifier are considered, respec- simple macromodels for weakly nonlinear tively, as time-varying systems, because they mixer and power amplifier are used in the sys- involves frequency translation and can be tem simulation. Also, we introduce noise into affected by a large signal in an adjacent chan- several circuits (frequency synthesizer, crystal nel [1]. For the transmitter, simple macro- oscillator, power amplifier, mixer, etc.), and we models for weakly nonlinear mixer and power demonstrate their effect on the noise perfor- amplifier are used to achieve efficient and mance system. In the simulation we consider accurate system simulation [2, 3]. Also, this features of components and technologies com- system model includes noise in several blocks mercially available. and demonstrates its effect on the noise per- formance system. Introduction For the transmitter presented in this arti- The increasing demand for small satellite cle, the system model architecture follows that communication systems has greatly expanded which was used for the RF transmitter module the need for algorithms and system-level sim- integrated on the nanosatellite SNAP-1 ulation that are both efficient and accurate launched in 1999 [4, 5]. In the simulation, we when applied to RF communication circuits. consider the characteristics of commercially The technical specifications of future systems available components. requires further effort in integrated circuit technologies and RF circuits. The increasing Conception and Discussion number of electronic functions integrated in Figure 1 shows a simplified block diagram satellite RF systems is accompanied by of an S-band transmitter designed for a vari- increased power consumption and faster com- ety of low-cost nanosatellite, microsatellite putations. Circuit designers are very apprecia- and enhanced microsatellite applications. This tive of a design methodology that includes effi- transmitter module is also suitable for all cient exploration of system-level architectures classes of satellite missions. It provides a low 50 High Frequency Electronics High Frequency Design SATELLITE TRANSMITTER for different noise sources (crystal reference noise, phase detector noise and VCO phase noise) were used in the simulation [7]. Also, reference spurs can occur at the multiples of the com- parison frequency, and can be trans- lated by the mixer to the desired signal frequency and cause a modulation on the tuning line of the VCO, which appears as FM modulation. In the simulation, we use the characteristics of a National Semi- conductor model LMX2326 programmable frequency synthesizer Figure 1 · S-band transmitter module block diagram. capable of phase locking a VCO between 500 MHz and 3 GHz. The VCO is from Mini-Circuits (JTOS- power output, can be configured for a called an integer-N system. This 2700V), which utilizes a high perfor- wide range of data rates and sup- means the voltage controlled oscilla- mance transistor operating in the ports BPSK and QPSK modulation tor (VCO) frequency and the crystal fundamental, rather than the dou- schemes. The transmitter is com- reference are some integer multiple bling push-push mode, capable of prised of a data processing unit, a of the reference frequency. The PLL generating a power of +8 dBm into a Controller Area Network (CAN) for consists of a high stability crystal ref- 50 ohm load. Its linearity is relative- TT&C, a frequency synthesizer, an erence oscillator, a frequency synthe- ly good (46-56 MHz/V). This data is I/Q modulator and power amplifiers. sizer, a voltage controlled oscillator, very important in the loop filter cal- As shown in Figure 1, this transmit- and a passive loop filter. The frequen- culation. Also, this VCO presents a ter generates a very high, stable S- cy synthesizer includes a phase pulling of 5 MHz, a pushing of 1 MHz band signal with a frequency synthe- detector, a current mode charge and a phase noise of –114 dBc/Hz at sizer. It then translates the signal to pump, and programmable frequency an offset frequency of 100 kHz. In the conversion frequency by mixing it dividers. The passive filter is desir- practice, the PLL can be programmed with a temperature compensated able for its simplicity, low cost and via a laptop computer and parallel crystal oscillator. The resulting RF low phase noise. port cable. The frequency changes signal is directly converted to base- To achieve optimal circuit perfor- were done using software provided by band and amplified with a power mance, the phase noise should be National Semiconductor, where the amplifier. evaluated for proper loop design, and PLL serial-control data are controlled it will impact many critical operating by three inputs (data, LE and clock). Frequency Synthesizer characteristics of the synthesized The 21-bit data register pro- Figure 2 shows the PLL’s linear oscillator including adjacent channel grammed with the data stream is model with feedback. This PLL is power [6]. The simple approximations shifted into 14-bit R counter, 18-bit N Figure 2 · Block diagram of the frequency synthesizer. Figure 3 · PLL output spectrum. 52 High Frequency Electronics High Frequency Design SATELLITE TRANSMITTER counter, and 18-bit function latch according to control bits. In this work, the output frequency range of the synthesizer is (2.2-2.29 GHz) (FVCO) with a spacing channel of 1 MHz (Fcomparison). The reference frequency of the oscillator is 10 MHz (Fosc). To begin with, we choose a frequency within the operating range, and we determine the values of the N and R counters. In this case, the reference divider (R counter) equal to 10 and the N counter equal to 2005 (A counter = 21 and B counter = 62), the output frequency resulting ((32 × B+A) × reference frequency) is Figure 4 · Simplified diagram of the mixer with the equal to 2005 MHz. band-pass filter. In this work, the loop filter design is a very critical part of the PLL synthesizer. In general, a low loop filter cutoff Figure 5 · Output signal of the mixer. Figure 6 · Mixer output spectrum. 54 High Frequency Electronics input signals of the mixer are the S- band signal from frequency synthesizer and the 240 MHz offset frequency are generated by a TCXO. This signal is mixed with the S-band signal through a passive mixer and passed through a block filter to remove all but the desired channel. In system simulation, the mixer can be incorporated by a macromodel that consists of several transfer functions. These transfer functions are found by reducing the Figure 7 · Filtered output spectrum. large systems of equations that describe this circuit. The noise is char- acterized by using the noise figure of makes the PLL response slower and the block, because it is relatively sim- the setting time of frequency switch- ple to combine it with cascaded blocks ing (PLL lockup time) longer and the to determine the noise figure of the PLL spurious suppressed. Conversely, entire transmitter. increasing cutoff frequency provides While consulting companies cata- faster PLL response, shorter PLL logues, notably Mini-Circuits, we find lockup time. Also as a result, the PLL many models perfectly adapted. The output signal is frequency-modulated mixer selected is TUF-2500 MHSM and contains high level spurs. The specified up to 2.5 GHz with isolation output spectrum plot is displayed in more than 24 dB between RF and IF Figure 3 for a chosen loop filter ports and a conversion loss lower design. The results show a noise den- than 8.5 dB. The output spectrum and sity of –93 dBc/Hz at 10 kHz and –118 the form of signal plots of the mixer dBc/Hz at 100 kHz offset frequencies. are displayed in Figures 5 and 6, The results indicate that the PLL respectively. The filtered signal spec- gives an rms value of 0.008 radian and trum plot is illustrated in Figure 7. a signal-to-noise ratio of 35.74 dB. The output power level of the synthesizer I/Q Modulator is about 6.4 mW (+8 dBm), which is In addition to the S-band signal, I sufficient to feed the balanced mixer and Q channels from FPGA are fed of level 10 or level 13 series, generally through the I/Q modulator for direct used in transmit/ receive applications. upconversion to S-band. Today’s QPSK modulators, as those of Analog Mixer and Band pass Filter Devices, Sirenza Microdevices or In such systems, it was found opti- Mini-Circuits, are designed to take mal to offset the synthesizer to pre- RF inputs from S-band frequencies vent the modulated BPSK signal form and convert directly down to base- pre-modulating VCO output, only to band I and Q signals, thus providing be remodulated again [5].

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