Article Design of a 335 GHz Multiplier Source Based on Two Schemes

Jin Meng 1,*, Dehai Zhang 1, Guangyu Ji 1,2, Changfei Yao 3, Changhong Jiang 1 and Siyu Liu 1,2

1 Key Lab. of Remote Sensing, National Space Science Center, Chinese Academy of Sciences, Beijing 100190, China 2 School of Computer Science, University of Chinese Academy of Sciences, Beijing 100049, China 3 Lab. of Microwave, School of Electronic and Information Engineering, Nanjing University of Information Science and Technology, Nanjing 210044, China * Correspondence: [email protected]

 Received: 3 July 2019; Accepted: 25 August 2019; Published: 28 August 2019 

Abstract: Based on a W-band high-power source, two schemes are proposed to realize a 335 GHz frequency multiplier source. The first scheme involves producing a 335 GHz signal with a two-stage doubler. The first doubler adopts two-way power-combined technology and the second stage is a 335 GHz doubler using a balanced circuit to suppress the odd harmonics. The measured output power was about 17.9 and 1.5 dBm at 167.5 and 335 GHz, respectively. The other scheme involves producing a 335 GHz signal with a single-stage quadrupler built on 50 µm thick quartz circuit adopting an unbalanced structure. The advantage of the unbalanced structure is that it can provide bias to the without an on-chip capacitor, which is hard to realize with discrete devices. The measured output power was about 5.8 dBm at 337 GHz when driven with 22.9 dBm. Such 335 GHz frequency multiplier sources are widely used in terahertz imaging, radiometers, and so on.

Keywords: cascaded doubler; quadrupler; Schottky varactor; hybrid integrated circuit

1. Introduction In recent decades, terahertz technology has been used for a variety of applications such as radio astronomy, remote sensing of the Earth’s atmosphere, radar imaging, etc. [1–5]. Furthermore, advances in terahertz sources and detectors have facilitated the development of these terahertz applications. As for terahertz sources, the methods mainly include the extension of microwave electronics towards high on one side and the development of photonic devices from the optical region towards low frequencies. In general, the frequency multiplier chain is the typical electronic method that can work at room temperature. Some leading overseas research institutes such as the Jet Propulsion Laboratory (JPL) have been able to realize solid-state frequency multiplier sources above 1 THz, which can produce tens of microwatts of power [6,7]. Furthermore, several competing technologies have been proposed in the semiconductor frequency multiplier field. In comparison, domestic research on frequency multipliers has mainly focused on the hybrid integrated circuits with discrete Schottky diodes, with an operating frequency around 200 GHz [8–10]. Based on a W-band high-power source, detailed in our former research, two schemes are proposed to design a 335 GHz multiplier. The first solution consists of a W-band source, two cascaded 167.5 GHz doublers, and a 335 GHz doubler. Another solution is to replace the two-stage doubler with a single-stage quadrupler. The details of the modules mentioned above are discussed further in this paper.

Electronics 2019, 8, 948; doi:10.3390/electronics8090948 www.mdpi.com/journal/electronics Electronics 2019, 8, x FOR PEER REVIEW 2 of 11

Increasing the efficiency and power capability of the frequency multiplier is the common way to obtain high output power [11–13]. For the diodes used in this paper, the safe input power was 24 dBm for a single multiplier. Therefore, power-combined technology was adopted to increase the effective input power. Figure 1 shows the diagram of a 335 GHz solid-state source with different schemes. A frequency multiplier of order N converts the input sinusoidal signal of frequency F1 and power P1 to an output sinusoidal signal of frequency FN = N × F1 and power PN. Hence, the conversion efficiency of the frequency multiplier is defined as the ratio of PN to P1. For a chain (×N1×N2) of two cascaded multipliers of respective order N1 and N2, the conversion efficiency of the chain is η (N1,

ElectronicsN2). A high-order2019, 8, 948 frequency multiplier of order N3 = N1 × N2 usually has a conversion efficiency2 of 11η (N3) < η (N1, N2) and η (N1, N2) = η (N1) × η (N2). Therefore, in theory, the efficiency of scheme (a) in Figure 1 is higher than that of scheme (b). 2. GeneralFurthermore, Scheme the relation of η (N1, N2) = η(N1) × η(N2) is valid only when there is no reflected powerIncreasing by the thesecond efficiency multiplier. and power Besides, capability the mismatch of the frequency of the interface multiplier between is the common the cascaded way to obtainmultipliers high outputcaused power by dimension [11–13]. For error the diodesand assembly used in this error paper, could the safe lead input to powera loss wasof 24power. dBm forConsequently, a single multiplier. the efficiency Therefore, of the power-combined chain × N1×N2 is technology not necessarily was adoptedmore than to that increase of the the chain effective × N3 inputin practical power. application. Figure1 shows the diagram of a 335 GHz solid-state source with di fferent schemes.

(a)

(b)

Figure 1. (a(a) )Block Block diagram diagram of of the the 335 335 GHz GHz frequency frequency multiplier multiplier based based on ona two-stage a two-stage doubler. doubler. (b) (Blockb) Block diagram diagram of the of the335 335GHz GHz frequency frequency mult multiplieriplier based based on ona single-stage a single-stage quadrupler. quadrupler.

3. BasicA frequency Principle multiplier of Schottky of orderDiode N converts the input sinusoidal signal of frequency F1 and power P1 to an output sinusoidal signal of frequency FN = N F1 and power PN. Hence, the conversion The Schottky barrier is a two-port device× that is important to terahertz frequency efficiency of the frequency multiplier is defined as the ratio of PN to P1. For a chain ( N1 N2) of two multipliers. The diode can be divided into two modes based on operating principle:× varistor× and cascaded multipliers of respective order N1 and N2, the conversion efficiency of the chain is η (N1, varactor. In general, the structure of a Schottky varactor is qualitatively the same as that of a varistor N2). A high-order frequency multiplier of order N3 = N1 N2 usually has a conversion efficiency η diode. However, the epitaxial layer of the varactor is thicker× than that of the varistor, which could (N3) < η (N1,N2) and η (N1,N2) = η (N1) η (N2). Therefore, in theory, the efficiency of scheme (a) in increase the breakdown voltage to maximize× capacitance variation [14]. Figure 2 shows the cross- Figure1 is higher than that of scheme (b). sectional view of the Schottky diode. The varistor makes use of a nonlinear resistance characteristic Furthermore, the relation of η (N1,N2) = η(N1) η(N2) is valid only when there is no reflected for the mixer, and the varactor is used for frequency× multipliers by using a nonlinear capacitance power by the second multiplier. Besides, the mismatch of the interface between the cascaded multipliers characteristic. The upper part of Figure 2 shows the nonlinear curves of the varistor and varactor. caused by dimension error and assembly error could lead to a loss of power. Consequently, the efficiency The diode consists of intrinsic and parasitic parameters. When the frequency increases to the of the chain N1 N2 is not necessarily more than that of the chain N3 in practical application. terahertz range,× the× parasitic parameters of the diode cell caused ×by its physical structure play an 3.important Basic Principle role in affecting of Schottky the Diodeperformance of the frequency multiplier. Hence, the electromagnetic field around the diodes is calculated with full-wave simulation software. As for intrinsic parameters, The Schottky barrier diode is a two-port device that is important to terahertz frequency multipliers. The diode can be divided into two modes based on operating principle: varistor and varactor. In general, the structure of a Schottky varactor is qualitatively the same as that of a varistor diode. However, the epitaxial layer of the varactor is thicker than that of the varistor, which could increase the breakdown voltage to maximize capacitance variation [14]. Figure2 shows the cross-sectional view of the Schottky diode. The varistor makes use of a nonlinear resistance characteristic for the mixer, and the varactor is used for frequency multipliers by using a nonlinear capacitance characteristic. The upper part of Figure2 shows the nonlinear curves of the varistor and varactor. Electronics 2019, 8, x FOR PEER REVIEW 3 of 11

Electronicsthese primarily2019, 8, 948 include series resistance, zero bias junction capacitance, barrier voltage, and 3ideal of 11 factor. These parameters can be obtained from the IV or CV curve.

Electronics 2019, 8, x FOR PEER REVIEW 3 of 11 these primarily include series resistance, zero bias junction capacitance, barrier voltage, and ideal factor. These parameters can be obtained from the IV or CV curve.

Figure 2. StructuresStructures and operating principles of the Schottky varistor and varactor.

4. DesignThe diode of 335 consists GHz Source of intrinsic Based andon Two-Stage parasitic parameters. Doubler When the frequency increases to the terahertz range, the parasitic parameters of the diode cell caused by its physical structure play an The three-dimensional model of a 335 GHz source with cascaded balanced frequency doublers important role in affecting the performance of the frequency multiplier. Hence, the electromagnetic is presented in Figure 3. As shown in the graph, the frequency multiplier is a split-block waveguide field around the diodes is calculated with full-wave simulation software. As for intrinsic parameters, design, and a suspended microstrip circuit based on a 50 µm thick quartz substrate is mounted in the these primarily include series resistance, zero bias junction capacitance, barrier voltage, and ideal channel between the input and output waveguide. The varactor chips are mounted on the suspended factor. These parameters can be obtained from the IV (Intensity and voltage) or CV (Capacitance and microstrip circuit with silver epoxy. voltage) curve. Figure 2. Structures and operating principles of the Schottky varistor and varactor. 4. Design of 335 GHz Source Based on Two-Stage Doubler 4. Design of 335 GHz Source Based on Two-Stage Doubler The three-dimensional model of a 335 GHz source with cascaded balanced frequency doublers is presentedThe three-dimensional in Figure3. As shown model in of the a 335 graph, GHz the source frequency with cascaded multiplier balanced is a split-block frequency waveguide doublers isdesign, presented and ain suspended Figure 3. As microstrip shown in circuit the graph, based the on afrequency 50 µm thick multiplier quartz substrateis a split-block is mounted waveguide in the design,channel and between a suspended the input microstrip and output circuit waveguide. based on The a 50 varactor µm thick chips quartz are substrate mounted onis mounted the suspended in the channelmicrostrip between circuit the with input silver and epoxy. output waveguide. The varactor chips are mounted on the suspended microstrip circuit with silver epoxy.

Figure 3. The three-dimensional model of the 335 GHz source based on a two-stage doubler.

4.1. W-Band High-Power Source The W-band power source driven by the 167 GHz doubler, which mainly includes a sextupler, a power , and a four-way power-combining module. The composition block diagram is shown in Figure 4. The sextupler employs a commercially available GaAs MMIC chip HMC1110 fabricated by Analog Devices Company (Norwood, MA, USA), and the power amplifier uses an

MMIC chip MAAP-011106 fabricated by M/A-COM Technology Solutions Inc (Lowell, MA, USA). Finally, theFigureFigure measured 3. TheThe three-dimensional three-dimensional results indicate modelthat model the of of outputthe the 335 335 GHz GHzpower source is more based than on a25 two-stage dBm at doubler. 81–86 GHz, and that the output power is about 27.5 dBm at 83 GHz when driven by 3 dBm of input power. 4.1. W-Band High-Power Source 4.1. W-Band High-Power Source The W-band power source driven by the 167 GHz doubler, which mainly includes a sextupler, The W-band power source driven by the 167 GHz doubler, which mainly includes a sextupler, a power amplifier, and a four-way power-combining module. The composition block diagram is a power amplifier, and a four-way power-combining module. The composition block diagram is shown in Figure 4. The sextupler employs a commercially available GaAs MMIC chip HMC1110 fabricated by Analog Devices Company (Norwood, MA, USA), and the power amplifier uses an MMIC chip MAAP-011106 fabricated by M/A-COM Technology Solutions Inc (Lowell, MA, USA). Finally, the measured results indicate that the output power is more than 25 dBm at 81–86 GHz, and that the output power is about 27.5 dBm at 83 GHz when driven by 3 dBm of input power.

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shown in Figure4. The sextupler employs a commercially available GaAs MMIC chip HMC1110 fabricated by Analog Devices Company (Norwood, MA, USA), and the power amplifier uses an MMIC chip MAAP-011106 fabricated by M/A-COM Technology Solutions Inc (Lowell, MA, USA). Finally, the measured results indicate that the output power is more than 25 dBm at 81–86 GHz, and that the output power is about 27.5 dBm at 83 GHz when driven by 3 dBm of input power. Electronics 2019, 8, x FOR PEER REVIEW 4 of 11

Figure 4. The block diagram of the W-band source.

4.2. Two-Way Power-Combined 167 GHz Frequency MultiplyingMultiplying SourceSource Considering thethe technical technical requirements requirements and cost,and thecost, 167 the GHz 167 high-power GHz high-power frequency multiplyingfrequency source adopts a two-way power-combined scheme. As depicted in Figure5, the power source includes Electronicsmultiplying 2019, 8, xsource FOR PEER adopts REVIEW a two-way power-combined scheme. As depicted in Figure 5, the5 ofpower 11 asource power includes divider /acombiner power divider/combiner and two identical and doublers. two identical doublers. The power divider used in the 167 GHz high-power frequency multiplying source is a Y-type waveguide divider and the phase difference between the two output signals is zero. Furthermore, the second harmonic produced by the doublers has the same phase, and can be combined by using a Y-type waveguide combiner at the output ports. Figure 5 shows the phase relationship of each part in the two branches using the red arrow. Actually, the Y-type power combiner can be regarded as a combination of two-phase shifters and an E–T-type combiner, and the function of the phase shifter is to change the phase of the two-way signal from the same direction to the reverse direction for the T- type combiner. Generally, the frequency doubler is designed to convert a pump microwave signal to its second harmonic based on the nonlinear voltage-dependence of the diode junction capacitance of the Schottky varactor. To suppress the odd harmonics, the diode array adopted has an anti-series type configuration. The incident signal with the dominant mode of the input rectangular waveguide (TE10) feeds the anti-series diode array. In contrast, the second harmonic would propagate along the suspended microstrip line in an unbalanced mode (TEM). In the 167 GHz doubler design, a 5VA40- 13 diode chip provided by Advanced Compound Semiconductor Technologies (Hanau, Germany)

was selected,Figure 5. whichThe structure comprises of the a 167 line GHzar array doubler of basedthree onSchottky the two-way juncti power-combinedons. The dimension technology. of the chip is 240Figure × 60 5. µm The (length structure and of thewidth, 167 GHzrespectively) doubler based and theon the semi-insulating two-way power-combined GaAs substrate technology. is 35 µm thick. The equivalent power divider circuit used of the in thebalanced 167 GHz doubler high-power is described frequency at the multiplyingtop right of Figure source 5. is Based a Y-type on 4.3.waveguidethe 335. IV GHz characteristic Doubler divider Based andof the theon Schottky Discrete phase di Schottkydiode,fference the Varactor between output current the two i can output be expressed signals is as zero. [15]: Furthermore, the second harmonic produced by the doublers has the same phase, and can be combined by using a i=i +i =−ie −1 −i e −1 =−2icoshαV −1 (1) Y-typeConsidering waveguide the rise combiner of working at the frequency, output ports. the varactor Figure5 showsused in the the phase 335 GHz relationship doubler requires of each part a smaller zero bias junction capacitance, and therefore obtains higher cut-off frequency. At the same inwhere the twois represents branches the using reverse the red saturation arrow. Actually, current and the V Y-typein represents power combinerthe junction can voltage be regarded across asthe a time,combinationSchottky the dimension contact. of two-phase ofBy the using diode Fourier shifters chip mustexpansion, and anbe E–T-typeredu Formulaced to combiner, match (1) is decomposedthe and width the of function theas follows: waveguide of the phase channel. shifter Finally,is to changethe diode the chip phase 137C of the from two-way Virginia signal Diodes from Inc the (Charlottesville, same direction VA, to the USA). reverse with direction four anodes for the i=i2IαV −2 +4iIαVcos2ωt +IαVcos4ωt +∙∙∙ (2) in anti-seriesT-type combiner. configuration was applied in the design. To improve the performance of RF ground, the flip-chipwhere mountedIn (αVin) ismethod the Bessel was functionadopted. ofThe the diode first chipkind. was Similar glued to on the the computational ground points, method which ofare the twooutput gold belts current, on either the current side of in the the quartz loop can substrate. be expressed as: The design process of the 335 GHz balanced doubler is shown in Figure 6. First of all, the i =i −i =4iI αV cosω t +I αV cos3ω t +∙∙∙ impedances of the diode at fundamental and second harmonic are optimized by using source. and(3) load-pull under ideal conditions. The diode optimum impedance was found to be Zsource = 33 − j37 Ω From the calculated results, it can be seen that the odd harmonics are suppressed in the output and Zload = 16 − j23 Ω. To improve the accuracy of simulation, the field-circuit method is applied in circuit, and thus the second harmonic can be obtained at the output waveguide by using the matching the design process [16,17]. Hence, the doubler is divided into two parts: a linear network, which is circuit. analyzed using the finite element method in consideration of the parasitic effects, and the nonlinear behavior of the varactor solved by the harmonic balance method. To reduce the complexity of the problem, the linear part is broken up into three sections: input transition at fundamental and second frequency, output transition, and matching circuit. The signal is coupled through a waveguide- microstrip structure, and the locations of Schottky diodes junction are inserted based on the port impedances (at fundamental frequency) acquired from step 1. Generally, the length of the reduced- height waveguide and location of the input back-short are optimized to achieve a small return loss in the input port. The second harmonic passes through the region between the diodes and input back- short and then is coupled into the output line by matching circuit. Another probe located in the output circuit couples the second harmonic to the standard output waveguide. The abovementioned design process refers to steps 2–5. In the next step, the generated SNP files are imported to the Advanced Design System (ADS) circuit and the characteristic of the diode is added in the nonlinear circuit. Furthermore, the optimization procedure is achieved based on harmonic balance analysis. Finally, the three-dimensional model of the doubler is built according to the optimized results and the calculated S parameter of the complete circuit is exported to the ADS. Now, the doubler model is regarded as a 7-port network. The simulated result of a doubler working at 335 GHz is described at the right side of Figure 6. It clear that the odd harmonics are suppressed in simulation, and that the results coincide with those obtained by Equations (1)–(3).

Electronics 2019, 8, 948 5 of 11

Generally, the frequency doubler is designed to convert a pump microwave signal to its second harmonic based on the nonlinear voltage-dependence of the diode junction capacitance of the Schottky varactor. To suppress the odd harmonics, the diode array adopted has an anti-series type configuration. The incident signal with the dominant mode of the input rectangular waveguide (TE10) feeds the anti-series diode array. In contrast, the second harmonic would propagate along the suspended microstrip line in an unbalanced mode (TEM). In the 167 GHz doubler design, a 5VA40-13 diode chip provided by Advanced Compound Semiconductor Technologies (Hanau, Germany) was selected, which comprises a linear array of three Schottky junctions. The dimension of the chip is 240 60 µm × (length and width, respectively) and the semi-insulating GaAs substrate is 35 µm thick. The equivalent circuit of the balanced doubler is described at the top right of Figure5. Based on the IV characteristic of the Schottky diode, the output current i can be expressed as [15]:

αV αV i = i + i = is(e− in 1) is(e in 1) = 2is[cos h(αV ) 1] (1) 1 2 − − − − − in − where is represents the reverse saturation current and Vin represents the junction voltage across the Schottky contact. By using Fourier expansion, Formula (1) is decomposed as follows:

i = is[2I (αV ) 2] + 4is[I (αV ) cos (2ω t) + I (αV ) cos (4ω t) + ] (2) 0 in − 2 in 0 4 in 0 ··· where In (αVin) is the Bessel function of the first kind. Similar to the computational method of the output current, the current in the loop can be expressed as:

i = i i = 4is[I (αV ) cos (ω t) + I (αV ) cos (3ω t) + ]. (3) loop 1 − 2 1 in 0 3 in 0 ··· From the calculated results, it can be seen that the odd harmonics are suppressed in the output circuit, and thus the second harmonic can be obtained at the output waveguide by using the matching circuit.

4.3. 335 GHz Doubler Based on Discrete Schottky Varactor Considering the rise of working frequency, the varactor used in the 335 GHz doubler requires a smaller zero bias junction capacitance, and therefore obtains higher cut-off frequency. At the same time, the dimension of the diode chip must be reduced to match the width of the waveguide channel. Finally, the diode chip 137C from Virginia Diodes Inc (Charlottesville, VA, USA). with four anodes in anti-series configuration was applied in the design. To improve the performance of RF ground, the flip-chip mounted method was adopted. The diode chip was glued on the ground points, which are two gold belts on either side of the quartz substrate. The design process of the 335 GHz balanced doubler is shown in Figure6. First of all, the impedances of the diode at fundamental and second harmonic are optimized by using source and load-pull under ideal conditions. The diode optimum impedance was found to be Zsource = 33 j37 Ω − and Z = 16 j23 Ω. To improve the accuracy of simulation, the field-circuit method is applied in the load − design process [16,17]. Hence, the doubler is divided into two parts: a linear network, which is analyzed using the finite element method in consideration of the parasitic effects, and the nonlinear behavior of the varactor solved by the harmonic balance method. To reduce the complexity of the problem, the linear part is broken up into three sections: input transition at fundamental and second frequency, output transition, and matching circuit. The signal is coupled through a waveguide-microstrip structure, and the locations of Schottky diodes junction are inserted based on the port impedances (at fundamental frequency) acquired from step 1. Generally, the length of the reduced-height waveguide and location of the input back-short are optimized to achieve a small return loss in the input port. The second harmonic passes through the region between the diodes and input back-short and then is coupled into the output line by matching circuit. Another probe located in the output circuit couples the second harmonic to the standard output waveguide. The abovementioned design process refers to steps 2–5. Electronics 2019, 8, 948 6 of 11

In the next step, the generated SNP files are imported to the Advanced Design System (ADS) circuit and the characteristic of the diode is added in the nonlinear circuit. Furthermore, the optimization procedure is achieved based on harmonic balance analysis. Finally, the three-dimensional model of the doubler is built according to the optimized results and the calculated S parameter of the complete circuit is exported to the ADS. Now, the doubler model is regarded as a 7-port network. The simulated result of a doubler working at 335 GHz is described at the right side of Figure6. It clear that the odd harmonics are suppressed in simulation, and that the results coincide with those obtained by EquationsElectronics 2019 (1)–(3)., 8, x FOR PEER REVIEW 6 of 11

FigureFigure 6.6. DesignDesign processprocess ofof aa 335335 GHzGHz balancedbalanced doublerdoubler withwith thethe field-circuitfield-circuit method. method.

5.5. DesignDesign ofof 335335 GHzGHz SourceSource BasedBased onon Single-StageSingle-Stage QuadruplerQuadrupler IfIf varactor varactor currents currents are are allowed allowed only only at at the the input input and and output output frequencies, frequencies, a a Schottky Schottky diode diode with with idealideal CVCV characteristicscharacteristics cannotcannot generategenerate harmonicsharmonics higherhigher thanthan thethe secondsecond harmonic.harmonic. ToTo generategenerate higherhigher harmonics, harmonics, it isit necessaryis necessary to allow to allow idler idler currents currents to flow to in flow the varactor, in the varactor, which could which be produced could be byproduced frequency by doublingfrequency or doubling frequency or mixing.frequency mixing. For a quadrupler, one way to obtain higher harmonics is by doubling and then producing a fourth harmonic by doubling again. Another way is by mixing the second harmonic idler with the fundamental to produce the third harmonic idler first, and by continuing to mix to produce the fourth harmonic output. Actually, the high-order multipliers are most efficient when idler circuits are provided at all idler frequencies. Therefore, the use of idlers could increase the output power and efficiency of reactive frequency multipliers. The quadrupler has a suspended microstrip circuit based on a 50 µm thick quartz substrate mounted in the channel with silver epoxy. The input and output ports of the quadrupler are standard full-height WR-12 and WR-2.8 waveguides with waveguide dimensions of 3.1 × 1.65 mm2 and 0.71 × 0.355 mm2, respectively. As described in Figure 7, a compact suspended microstrip (CSMR) low-pass filter follows an input conversion structure (the simulated return loss is below −20 dB from 75 to 90 GHz), and hence the fourth harmonic produced by varactors could prevent leaking from the

Electronics 2019, 8, 948 7 of 11

For a quadrupler, one way to obtain higher harmonics is by doubling and then producing a fourth harmonic by doubling again. Another way is by mixing the second harmonic idler with the fundamental to produce the third harmonic idler first, and by continuing to mix to produce the fourth harmonic output. Actually, the high-order multipliers are most efficient when idler circuits are provided at all idler frequencies. Therefore, the use of idlers could increase the output power and efficiency of reactive frequency multipliers. The quadrupler has a suspended microstrip circuit based on a 50 µm thick quartz substrate mounted in the channel with silver epoxy. The input and output ports of the quadrupler are standard full-height WR-12 and WR-2.8 waveguides with waveguide dimensions of 3.1 1.65 mm2 and × 0.71 0.355 mm2, respectively. As described in Figure7, a compact suspended microstrip resonator × (CSMR) low-pass filter follows an input conversion structure (the simulated return loss is below 20 dB − Electronicsfrom 75 2019 to 90, 8,GHz), x FOR PEER and REVIEW hencethe fourth harmonic produced by varactors could prevent leaking7 of 11 from the input port. Compared with the step impedance filter, the CSMR filter has a compacted inputstructure port. and Compared wide stop with band the [18 step]. The impedance simulated filt resulter, the of CSMR the CSMR filter filter has a in compacted the band of structure 30–350 GHz and wideare shown stop band in Figure [18]. 7The. It simulated can be seen result from of the the graph CSMR that filter the in insert the band loss of is 30–350 lower thanGHz 0.3are dBshown in the in passFigure band, 7. It can while be theseen side from rejection the graph is better that the than insert 20 dB loss from is lower 160 tothan 350 0.3 GHz. dB in Finally, the pass another band, probewhile thelocated side inrejection the output is better circuit than couples 20 dB from the fourth 160 to harmonic 350 GHz. toFinally, the standard another outputprobe located waveguide, in the and output the circuitsimulated couples return the loss fourth is better harmonic than 15 to dB the in standard the frequency output range waveguide, of 320–360 and GHz. the simulated All passive return networks, loss issuch better as thethan low-pass 15 dB in filter, the frequency input and range output of waveguide-to-microstrip 320–360 GHz. All passive transition, networks, and such diode as the passive low- part,pass filter, are analyzed input and by output EM simulators. waveguide-to-microstrip When the sub-circuits transition, are optimized,and diode passive the complete part, are quadrupler analyzed bycircuit EM issimulators. simulated. When The ninethe sub-circuits port S-parameters are optimize of thisd, the simulation complete are quadrupler extracted andcircuit then is simulated. combined withThe nine a nonlinear port S-parameters diode to model of this the simulation multiply earefficiency extracted in the and circuit then combined simulator. with This a process nonlinear is usually diode torepeated model forthe the multiply further efficiency optimization in the ofthe circuit quadrupler simulator. multiply This process efficiency. is usually repeated for the further optimization of the quadrupler multiply efficiency.

Figure 7. Three-dimensional model of the 335 GHz source based on a single-stage quadrupler. Figure 7. Three-dimensional model of the 335 GHz source based on a single-stage quadrupler. 6. Measurements and Discussion 6. Measurements and Discussion The block diagram of the measurement setup is illustrated in Figure8. An Agilent analog signal generatorThe block E8257D diagram (Santa of Clara, the measurement CA, USA) is setup followed is illu bystrated the W-band in Figure power 8. An source Agilent to analog generate signal the generatorsignal in the E8257D 81–86 (Santa GHz band. Clara, The CA, output USA) poweris follow ofed the by frequency the W-band multipliers power source is measured to generate by a PM4 the powersignal in meter the 81–86 (Charlottesville, GHz band. The VA, output USA). Moreover,power of the a Sub-Miniature-Afrequency multipliers (SMA) is measured (type KFD55(Xi’an, by a PM4 powerChina)) meter is connected (Charlottesville, to the main VA, transmission USA). Moreover, circuit an using SMA gold (type wire KFD55(Xi’an, bonding and China)) an external is connected sliding torheostat the main connected transmission to the circuit SMA port using so gold as to wire bias thebonding varactor. and an external sliding rheostat connected to the SMA port so as to bias the varactor. Figure 9a shows the measured results of the W-band source. The measured output power is more than 310 mW from 81 GHz to 86 GHz, and the maximum power is about 560 mW at 83 GHz. In the measurement of the quadrupler, the input power is about 200 mW to make sure the diodes work safely, and hence an attenuator is added. The measured output power of the 167 GHz power- combined doubler is shown in Figure 9b. It was found that the power is more than 45 mW at 164–172 GHz, and the highest output power is 62 mW at 167.5 GHz. The measured results of the 335 GHz source based on two cascaded doublers are shown in Figure 9c. The measured output power of the 335 GHz doubler is more than 0.5 mW at 328–337 GHz and the maximum output power is about 1.4 mW at 333 GHz. The relation of the single-stage quadrupler 335 GHz source output versus pumping power is described in Figure 9d. The measured typical output power is 2.5 mW at 332–344 GHz, and the highest measured output power of 3.8 mW is measured at 337 GHz with an input power of 198 mW. Tables 1 and 2 illustrate a comparison of some reported multipliers. A recent development of terahertz solid circuits in China caused a regression in advanced semiconductor technology such as

Electronics 2019, 8, x FOR PEER REVIEW 8 of 11

Schottky diode technology, membrane technology, transferred substrate technology, and so on. The result is that an integrated circuit is difficult to realize and the design of the frequency multiplier needs to use a discrete circuit with a higher loss transmission line. The performance of the frequency multipliers presented in this paper reached the same level as that achieved by research institutions Electronics 2019, 8, x FOR PEER REVIEW 8 of 11 abroad, and has a leading position at home. Furthermore, the design using discrete diodes is easy to realizeSchottky and diode the cost technology, is relatively membrane low. technology, transferred substrate technology, and so on. The resultTo is ensure that an that integrated the 167 GHz circuit doubler is difficult is working to realize safely, and the theinput design power of produced the frequency by the multiplier W-band sourceneeds tois controlleduse a discrete below circuit 280 with mW aand higher the losstypical transmission output power line. ofThe the performance doubler is, ofaccordingly, the frequency 55 mW.multipliers Hence thepresented typical inefficiency this paper of thereached 167 GHz the same doubler level is asabout that 20%. achieved The typicalby research efficiency institutions of the 335abroad, GHz anddoubler has ais leading 2% with position typical atinput home. and Furthermore, output power the values design of using 55 and discrete 1.1 mW, diodes respectively. is easy to Torealize summarize, and the thecost efficiency is relatively of the low. frequency multiplier chain is about 0.4%. In contrast, the typical input Toand ensure output that power the 167 values GHz doublerof a single-stage is working quadrupler safely, the inputare 190 power mW produced and 2.8 mW, by the and W-band said quadrupler has a higher efficiency of about 1.5%. However, it is difficult to say whether it is better to Electronicssource is2019 controlled, 8, 948 below 280 mW and the typical output power of the doubler is, accordingly,8 of 1155 realizemW. Hence a high-order the typical multiplier efficiency via ofa single-stagethe 167 GHz process doubler or is by about a cascade 20%. The of two typical or more efficiency low-order of the multipliers.335 GHz doubler The decision is 2% with could typical be made input in accordanceand output withpower specific values conditions. of 55 and 1.1 mW, respectively. To summarize, the efficiency of the frequency multiplier chain is about 0.4%. In contrast, the typical input and output power values of a single-stage quadrupler are 190 mW and 2.8 mW, and said quadrupler has a higher efficiency of about 1.5%. However, it is difficult to say whether it is better to realize a high-order multiplier via a single-stage process or by a cascade of two or more low-order multipliers. The decision could be made in accordance with specific conditions.

(a) (b)

Figure 8. (a) Photo of the assembled 335 GHz source with two cascaded doublers. (b) Photo of the Figure 8. (a) Photo of the assembled 335 GHz source with two cascaded doublers. (b) Photo of the assembled 335 GHz source with a single-stage quadrupler. assembled 335 GHz source with a single-stage quadrupler. Figure9a shows the measured results of the W-band source. The measured output power is more than 310 mW from 81 GHz to(a 86) GHz, and the maximum power is about(b) 560 mW at 83 GHz. In the measurement of the quadrupler, the input power is about 200 mW to make sure the diodes work safely, and henceFigure an 8. attenuator(a) Photo of isthe added. assembled The 335 measured GHz source output with powertwo cascaded of the doublers. 167 GHz (b power-combined) Photo of the doublerassembled is shown 335 inGHz Figure source9b. with It was a single-stage found that quadrupler. the power is more than 45 mW at 164–172 GHz, and the highest output power is 62 mW at 167.5 GHz.

(a) (b)

Electronics 2019, 8, x FOR PEER REVIEW 9 of 11

(a) (b)

(c) (d)

FigureFigure 9. 9. (a()a Measured) Measured output output power power of ofthe the W-band W-band source. source. (b) Measured (b) Measured output output power power of the of 167 the GHz167 GHzhigh-power high-power source. source. (c) Measured (c) Measured input and input output and power output of power the 335 of GHz the source 335 GHz based source on a basedtwo- stageon a doubler. two-stage (d doubler.) Measured (d )input Measured and output input power and output of the power 335 GHz of thesource 335 based GHz sourceon a single-stage based on a quadrupler.single-stage quadrupler.

Table 1. Performance comparison of the doubler around 170 GHz.

Frequency Max Output Power Typical References Technology (GHz) (mW) Efficiency ×2 [19] from VDI 110–170 24 8% integrated [20] from ×2 discrete 176–196 40 12% NUIST This paper ×2 discrete 164–172 62 20%

Table 2. Performance comparison of the frequency multipliers above 300 GHz.

Frequency Max Output Power Typical References Technology (GHz) (mW) Efficiency ×2 [19] from VDI 220–330 3 6% integrated [21] from RAL ×2 discrete 330–336 1.2 2% [22] from ×3 discrete 320–342 0.149 0.3% UESTC

This paper ×2 discrete 328–337 1.4 2% ×4 discrete 332–344 3.8 1.5%

7. Conclusions A solid-state frequency multiplier chain based on two schemes has been designed and tested in this paper. For the first option, the measured highest output power was about 1.4 mW at 333 GHz and more than 0.5 mW at 328–337 GHz. For the second option, the measured typical output power was 2.5 mW at 332–344 GHz, and the highest measured output power was 3.8 mW at 337 GHz. The research content provides the means to generate a terahertz signal above 300 GHz. Our future work will aim at the design of a G-band, higher output power source, and at the increased efficiency of the frequency multiplier working in the sub-millimeter region.

Author Contributions: Conceptualization, methodology, software, and writing, J.M., D.Z., and G.J.; formal analysis, C.Y. and C.J.; visualization, J.M. and S.L.

Funding: This research received no external funding.

Electronics 2019, 8, 948 9 of 11

The measured results of the 335 GHz source based on two cascaded doublers are shown in Figure9c. The measured output power of the 335 GHz doubler is more than 0.5 mW at 328–337 GHz and the maximum output power is about 1.4 mW at 333 GHz. The relation of the single-stage quadrupler 335 GHz source output versus pumping power is described in Figure9d. The measured typical output power is 2.5 mW at 332–344 GHz, and the highest measured output power of 3.8 mW is measured at 337 GHz with an input power of 198 mW. Tables1 and2 illustrate a comparison of some reported multipliers. A recent development of terahertz solid circuits in China caused a regression in advanced semiconductor technology such as Schottky diode technology, membrane technology, transferred substrate technology, and so on. The result is that an integrated circuit is difficult to realize and the design of the frequency multiplier needs to use a discrete circuit with a higher loss transmission line. The performance of the frequency multipliers presented in this paper reached the same level as that achieved by research institutions abroad, and has a leading position at home. Furthermore, the design using discrete diodes is easy to realize and the cost is relatively low.

Table 1. Performance comparison of the doubler around 170 GHz.

Frequency Max Output Typical References Technology (GHz) Power (mW) Efficiency [19] from VDI (Virginia Diodes, Inc.) 2 integrated 110–170 24 8% × [20] from NUIST (Nanjing University of Information Science 2 discrete 176–196 40 12% × and Technology) This paper 2 discrete 164–172 62 20% ×

Table 2. Performance comparison of the frequency multipliers above 300 GHz.

Frequency Max Output Typical References Technology (GHz) Power (mW) Efficiency [19] from VDI 2 integrated 220–330 3 6% × [21] from RAL (Rutherford Appleton 2 discrete 330–336 1.2 2% Laboratory) × [22] from UESTC (University of Electronic 3 discrete 320–342 0.149 0.3% Science and Technology of China) × 2 discrete 328–337 1.4 2% This paper × 4 discrete 332–344 3.8 1.5% ×

To ensure that the 167 GHz doubler is working safely, the input power produced by the W-band source is controlled below 280 mW and the typical output power of the doubler is, accordingly, 55 mW. Hence the typical efficiency of the 167 GHz doubler is about 20%. The typical efficiency of the 335 GHz doubler is 2% with typical input and output power values of 55 and 1.1 mW, respectively. To summarize, the efficiency of the frequency multiplier chain is about 0.4%. In contrast, the typical input and output power values of a single-stage quadrupler are 190 mW and 2.8 mW, and said quadrupler has a higher efficiency of about 1.5%. However, it is difficult to say whether it is better to realize a high-order multiplier via a single-stage process or by a cascade of two or more low-order multipliers. The decision could be made in accordance with specific conditions.

7. Conclusions A solid-state frequency multiplier chain based on two schemes has been designed and tested in this paper. For the first option, the measured highest output power was about 1.4 mW at 333 GHz and more than 0.5 mW at 328–337 GHz. For the second option, the measured typical output power was 2.5 mW at 332–344 GHz, and the highest measured output power was 3.8 mW at 337 GHz. The research content provides the means to generate a terahertz signal above 300 GHz. Our future work will aim at Electronics 2019, 8, 948 10 of 11 the design of a G-band, higher output power source, and at the increased efficiency of the frequency multiplier working in the sub-millimeter region.

Author Contributions: Conceptualization, methodology, software, and writing, J.M., D.Z., and G.J.; formal analysis, C.Y. and C.J.; visualization, J.M. and S.L. Funding: This research received no external funding. Conflicts of Interest: The authors declare no conflict of interest.

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