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Layout of CMOS Circuits

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Layout of CMOS Circuits Layout of CMOS Circuits September, 2016 Kjell Jeppson Aim of the lecture • To give some basic understanding of layout trade-offs between wiring and active circuitry • To provide guidelines for systematic and structured design using standard cell templates • To discuss the influence of layout on performance • To use Euler paths to minimize parasitics and letting MOSFETs share common source/drain areas • To introduce methods for symbolic layout on virtual grids 2016 MCC092: Integrated Circuit Design 2 The inverter - - from schematic to layout Inverter schematic Well tie Power supply rails BodyActiveContactsMetalPoly gates ties wiringareas to polyactive gatesareas VDD Poly only vertically Metal mainly horizontally How do we get through IN IN OUT with metal wiring? VSS Substrate tie 2016 MCC092: Integrated Circuit Design 3 The inverter - - from schematic to layout Vertical poly straps Well tie VDD How do we get through IN OUT with metal wiring? VSS Substrate tie 2016 MCC092: Integrated Circuit Design 4 The inverter - - from schematic to layout Active supply straps Well tie VDD How do we get through IN OUT with metal wiring? VSS Substrate tie 2016 MCC092: Integrated Circuit Design 5 Standard cell architecture Fixed cell height: 2.6 um VDD Fixed supply rails Fixed n-well regions Fixed contact size and positions A 2.6 B VSS 2016 MCC092: Integrated Circuit Design 6 Standard cell architecture Fixed cell height: 2.6 um VDD How many wire tracks can fit Fixed supply rails the empty space between the Fixed well MOSFET source/drain contacts? Fixed contact size and positions Pitch 1 But MOSFET widths can be changed Pitch 2 within limits for different inverter A driving capability (or size X) 2.6 Pitch 3 B Pitch 4 Extra space A certain number of pitches are required, plus one extra space at bottom VSS 2016 MCC092: Integrated Circuit Design 7 Stick Diagrams • Stick diagrams help plan layout quickly – Need not be to scale – Draw with color pencils or dry-erase markers VDD VDD A A B C metal1 c poly ndiff pdiff Y Y contact GND GND INV NAND3 2016 MCC092: Integrated Circuit Design 8 The NAND2 gate VDD ina inb ina inb inc out out out inb ina NAND2 NAND3 VSS 2016 MCC092: Integrated Circuit Design 9 The NAND2NAND3 gate VDD out ina inb ina inb inc inc out out inb ina NAND2 NAND3 VSS 2016 MCC092: Integrated Circuit Design 10 The NOR2 gate VDD ina inb ina inb inc NOR2 out inb out ina NOR2 NOR3 VSS 2016 MCC092: Integrated Circuit Design 11 The NOR3 gate VDD NOR3 ina inb ina inb inc out inc out inb out ina NOR2 NOR3 VSS 2016 MCC092: Integrated Circuit Design 12 The AOI12 gate VDD ina inb ina inb inc out out ina inc inb AOI12 VSS 2016 MCC092: Integrated Circuit Design 13 The AO212 gate VDD A B C D A B C D E E Z A D E B C VSS 2016 MCC092: Integrated Circuit Design 14 Graph theory: Euler paths • The Seven Bridges of Königsberg is a historically notable problem in mathematics. Its negative resolution by Leonhard Euler in 1736 laid the foundations of graph theory and prefigured the idea of topology. • The city of Königsberg (now Kaliningrad) was set on both sides of the Pregel River, and included two large islands which were connected to each other and the mainland by seven bridges. The problem was to devise a walk through the city that would cross each bridge once and only once. The starting and ending points of the walk need not be the same. • Euler proved that the problem has no solution. The difficulty was the development of a technique of analysis and of subsequent tests that established this assertion with mathematical rigor. 2016 MCC092: Integrated Circuit Design 15 Graph theory: Euler paths → → Euler's argument shows that a necessary condition for the walk of the desired form is that the graph be connected and have exactly zero or two nodes of odd degree. This condition turns out also to be sufficient—a result stated by Euler and later proven by Carl Hierholzer. Such a walk is now called an Eulerian path or Euler walk in his honor. Further, if there are nodes of odd degree, then any Eulerian path will start at one of them and end at the other. (From Wikipedia) 2016 MCC092: Integrated Circuit Design 16 Graph theory: Euler paths The blue graph has V V DD DD only one node with odd number of A B edges. Not A X B OK! C D D C Z X X X VSS E Z A D The red graph has two E E nodes with B C odd number of edges. OK! VSS Z 2016 MCC092: Integrated Circuit Design 17 Gate Matrix Layout VDD P0 C in Cout=G3+P3(G2+P2(G1+P1(G0+P0Cin) P1 cout G0 P2 G1 a3 g3 P3 Set-up b3 cell p3 G2 block a2 g2 Set-up G3 b2 cell p2 carry - P a1 g1 3 Set-up G3 b cell p 1 1 ripple P2 a0 g0 bit G - 2 Set-up P 4 1 b0 cell p0 G1 P G0 0 Cin cin VSS 2016 MCC092: Integrated Circuit Design 18 Gate Matrix Layout Our task in this example: We have been given the seemingly impossible task to layout the 4- bit ripple-carry block using the layout template given below, with the given gate order!! Cin P1 G1 P2 G2 P3 G3 P4 G4 VDD CIN COUT VSS 2016 MCC092: Integrated Circuit Design 19 Gate Matrix Layout VDD G2 Cout=G3+P3(G2+P2(G1+P1(G0+P0Cin) G1 a3 g3 G Set-up P2 0 b cell P3 P1 3 p3 P0 block Cin a2 g2 Set-up b2 cell p2 G carry 3 - a1 g1 Set-up P3 b cell p 1 1 ripple G3 a0 g0 bit P - 2 Set-up 4 G2 b0 cell p0 P1 G1 G P0 0 cin Cin It seems impossible to pass all MOSFETs in the VSS given order without passing some MOSFETs twice! 2016 MCC092: Integrated Circuit Design 20 Gate Matrix Layout VDD G2 Cout=G3+P3(G2+P2(G1+P1(G0+P0Cin) P0 Cin P 1 a3 g3 G Set-up P2 0 b cell P3 3 p3 block G1 a2 g2 Set-up b2 cell p2 G carry 3 - a1 g1 Set-up P3 b cell p 1 1 ripple G3 a0 g0 bit P - 2 Set-up 4 G2 b0 cell p0 P1 G1 G P0 0 cin Cin However, there is a solution! MOSFET blocks can be VSS rearranged in the schematic with same functionality. 2016 MCC092: Integrated Circuit Design 21 Gate Matrix Layout VDD G2 Cout=G3+P3(G2+P2(G1+P1(G0+P0Cin) G0 P 1 a3 g3 P Set-up P2 0 Cin b cell P3 3 p3 block G1 a2 g2 Set-up b2 cell p2 G carry 3 - a1 g1 Set-up P3 b cell p 1 1 ripple G3 a0 g0 bit P - 2 Set-up 4 G2 b0 cell p0 P1 G1 G P0 0 cin Cin However, there is a solution! MOSFET blocks can be VSS rearranged in the schematic with same functionality. 2016 MCC092: Integrated Circuit Design 22 Gate Matrix Layout VDD G2 Cout=G3+P3(G2+P2(G1+P1(G0+P0Cin) G0 P 1 a3 g3 P Set-up P2 0 Cin b cell P3 3 p3 block G1 a2 g2 Set-up b2 cell p2 G carry 3 - a1 g1 Set-up P2 b cell p 1 1 ripple G3 G2 a0 g0 bit P0 Set-up - G1 4 b0 cell p0 G0 Cin P1 cin P3 However, there is a solution! MOSFET blocks can be VSS rearranged in the schematic with same functionality. 2016 MCC092: Integrated Circuit Design 23 Gate Matrix Layout Here is the resulting layout! Cin P1 G1 P2 G2 P3 G3 P4 G4 VDD CIN COUT VSS 2016 MCC092: Integrated Circuit Design 24 Gate Matrix Layout The layout again, a bit more refined! Cin P1 G1 P2 G2 P3 G3 P4 G4 VDD CIN COUT VSS NOTE: The layout is very compact and elegant, however, only post-layout circuit simulations with node capacitances extracted from the layout will reveal the exact performance of the cell. 2016 MCC092: Integrated Circuit Design 25 General Rules for CMOS Layout • Run supply lines for VDD and VSS along the upper and lower cell boundaries • Run a vertical poly wire for each input signal • Order the poly wires to obtain maximal connectivity between transistors through abutment of source/drain areas. Connected transistors then form transistor segments • Place n-transistor segments close to the bottom VSS supply rail and p-transistors close to the top VDD supply rail • Wires necessary to complete the design are drawn in metal, poly, or, if necessary in diffusion (for instance when connecting segments to the supply rails • Remember to keep internal node capacitances at a minimum 2016 MCC092: Integrated Circuit Design 26.
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