Synchronous Sequential Circuits

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

SYNCHRONOUS COMPONENTS

ASYNCHRONOUS CIRCUITS: LATCHES

SR LATCH: R S R Qt+1 Qt+1 Q 0 0 Qt Qt 0 1 0 1

1 0 1 0 S Q restricted 1 1 0 0

S SR Latch R S Q

Q R Q Q

SR LATCH WITH ENABLE: E S R R Qt+1 Qt+1 R' 0 x x Qt Qt Q

1 0 0 Qt Qt

E 1 0 1 0 1

S' Q 1 1 0 1 0 S 1 1 1 0 0

D LATCH WITH ENABLE:

. This is essentially an SR Latch, where 푅 = 푛표푡(퐷), 푆 = 퐷

D R' E D Q t+1 Q 0 x Q t E 1 0 0

1 1 1 S' Q

1 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

SYNCHRONOUS CIRCUITS: FLIP FLOPS

. Flip flops are made out of: o A Latch with an enable input. o An Edge detector circuit.

. The figure depicts an SR Latch, where the enable is connected to the output of an Edge Detector Circuit. The input to the Edge Detector is a signal called 'clock'. A clock signal is a square wave with a fixed frequency.

clock

T Frequency = 1/T Period SR Flip Flop R R'

clock Edge E Detector

S' Q S or

. The edge detector circuit generates short-duration pulses during rising (or falling) edges. These pulses act as short-time enables of the Latch. . The behavior of the flip flops can be described as that of a Latch that is only enabled during rising (or falling edges).

. Depending on what type of edge we are detecting, flip flops can be classified as: o Positive-edge triggered flip flop: The edge detector circuit generates pulses during rising edges. o Negative-edge triggered flip flop: The edge detector circuit generates pulses during falling edges. o Dual-edge triggered flip flop: The edge detector circuit generates pulses during both rising and falling edges. Current FPGA technology does not support dual-edge triggered flip flops.

S Q S Q

clock clock

R Q R Q

Positive Negative edge-triggered edge-triggered

FLIP FLOP TYPES

SR Flip Flop

clock S R Qt+1 Qt+1

0 0 Qt Qt S Q

0 1 0 1 clock

Q 1 0 1 0 R

1 1 0 0

Excitation Equation:

푄푡+1 = 푆푅̅ + 푄푡푆̅푅̅ = 푅̅(푆 + 푄푡푆̅) = 푅̅(푆 + 푆̅)(푆 + 푄푡) = 푅̅푆 + 푅̅푄푡 (on the edge)

2 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

D Flip Flop

clock D Qt+1 D Q 0 0

clock Q 1 1 D Flip Flop

clock Edge E Detector

Excitation Equation: 푄푡+1 = 퐷 (on the edge)

T Flip Flop

clock T Q T D Q T Q t+1

0 Q t clock clock Q Q 1 Qt

Excitation Equation: 푄푡+1 = 푇푄푡 (on the edge)

JK Flip Flop

clock J K Qt+1 J

J Q 0 0 Qt K D Q clock 0 1 0

clock K Q 1 0 1 Q

1 1 Qt

Excitation Equation: 푄푡+1 = 퐽푄̅̅̅푡 + 퐾̅푄푡 (on the edge)

SYNCHRONOUS AND ASYNCHRONOUS INPUTS

Synchronous Inputs . Typically, flip flops only change their outputs on the rising (or falling edge). Usually, a change on the inputs forces a change on the outputs. These inputs are known as synchronous inputs, as the inputs' state is only checked on the rising (or falling) edges. Example: Input D of a D flip flop, Inputs J, K of a JK flip flop.

Asynchronous Inputs prn . However, in many instances, it is useful to have inputs that force the outputs to a value immediately, disregarding the rising (or falling edges). These inputs are known as asynchronous D D Q inputs. Common asynchronous inputs are 푝푟푛 and 푐푙푟푛 (they can be active-low or active high) . The figure depicts a D Flip Flop with two asynchronous inputs: o 푝푟푛: Preset (active low). When 푝푟푛 = 0 → 푄 = 1. clock Q o 푐푙푟푛 (sometimes called 푟푒푠푒푡푛): Clear (active low). When 푐푙푟푛 = 0 → 푄 = 0. o If 푝푟푛 and 푐푙푟푛 are both 0, usually 푐푙푟푛 is given priority. clrn . A Flip flop can have more than one asynchronous inputs, or none.

3 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

PRACTICE EXERCISES

1. Complete the timing diagram of the circuit shown below:

clk

clrn 0 D Q D Q 1 D E E clk Q

clrn Q

2. Complete the VHDL description of the circuit shown below:

library ieee; use ieee.std_logic_1164.all; a 0 D Q entity circ is b Q port ( a, b, s, clk, clrn: in std_logic; 1 q: out std_logic); end circ; s

architecture a of circ is clk Q

begin clrn -- ???

end a;

3. Complete the timing diagram of the circuit shown below. If the frequency of the signal clock is 25 MHz, what is the frequency (in MHz) of the signal Q?

clrn clock '1' T Q clrn

clock Q Q

4. Complete the timing diagram of the circuit whose VHDL description is shown below:

library ieee; elsif (clk’event and clk = ‘1’) then use ieee.std_logic_1164.all; if x = ‘1’ then qt <= not (qt); entity circ is end if; port ( clrn, x, clk: in std_logic; end if; q: out std_logic); end process; end circ; q <= qt end a; architecture a of circ is signal qt: std_logic; clk begin process (clrn, clk, x) begin clrn if clrn = ‘0’ then qt <= ‘0’; x

4 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

5. Complete the timing diagram of the circuit shown below:

a Full Adder s x s clk b y FA cin cout clrn D Q

clk a Q b clrn s

6. Complete the VHDL description of the synchronous sequential circuit whose truth table is shown below:

library ieee; use ieee.std_logic_1164.all; clrn clk A B Qt+1

entity circ is 1 0 0 1 port ( A, B, C: in std_logic; clrn, clk: in std_logic; 1 0 1 C q: out std_logic); end circ; 1 1 0 Qt architecture a of circ is begin 1 1 1 Qt -- ???

end a; 0 X X X 0

7. Complete the timing diagram of the circuit shown below:

clk

Q J Q clrn clk

K Q x clrn y

y x Q

8. Complete the timing diagram of the circuit shown below:

clrn clock D Q D Q clrn clk Q D Latch Q Q L D Q

Q L E Q

5 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

SYNCHRONOUS CIRCUITS: REGISTERS resetn n-bit Register: This is a collection of 'n' D-type flip flops, D D Q Q where each flip flop independently stores one bit. The flip n-1 n-1 flops are connected in parallel. They also share the same resetn and clock signals. resetn Dn-2 D Q Qn-2 n n D D Q Q

...... clk

D D Q Q 0 0

clk n-bit shift registers: This is a collection of 'n' D-type flip flops, connected serially. The flip flops share the same resetn and clock signals. The serial input is called 'din', and the serial output is called 'dout'. The flip flop outputs (also called the parallel output) are called 푄 = 푄푛−1푄푛−2 ⋯ 푄0. Depending on how we label the bits, we can have: . Right shift register: The input bit moves from the MSB to the LSB, and . Left shift register: The input bit moves from the LSB to the MSB.

RIGHT SHIFT REGISTER: Qn-1 Qn-2 Qn-3 Q0 resetn resetn

din din dout dout din D Q D Q D Q ... D Q dout clk

1 2 3

- -

n n

n ... clk

Q Q Q

LEFT SHIFT REGISTER: Q0 Q1 Q2 Qn-1 resetn resetn din din dout dout din D Q D Q D Q ... D Q dout clk

0 1 2

n clk

Q Q Q

... Q

Timing Diagram example: Q Q Q Q 3 2 1 0 resetn

x D Q D Q D Q D Q

clk

resetn x

Q 0000 0000 0000 1000 0100 0010 1001 0100 1010 1101 1110 0111 0011 0001

6 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

PARALLEL ACCESS SHIFT REGISTER . This is a shift register in which we can write data on the flip flops in parallel. 푠_푙 = 0  shifting operation, 푠_푙 = 1  parallel load. The figure shows a 4-bit parallel access right shift register. Q3 Q2 Q1 Q0

resetn

D Q D Q D Q D Q

clk

0 1 0 1 0 1 0 1

din D3 s_l D2 D1 D0

clk

resetn

s_l

din

D 0000 1101 1001 1100

Q 0000 0000 1000 1100 0110 0011 1001 1101 1110 0111 1011 1100 0110 0011 1100 1110 0111 0011

ADDING AN ENABLE INPUT TO FLIP FLOPS . In many instances, it is very useful to have a signal that controls whether the flip flop works. The following circuit represents a D flip flop with synchronous enable. When E = ‘0’, the flip flop does not work, i.e., the flip flop keeps its value. When E = ‘1’, the flip flop works, i.e., Q=D on the rising edge. . We can thus create n-bit registers and n-bit shift registers with enable. Here, all the flip flops share the same enable input.

clk

resetn 0 D Q D 1 Q D E clk E resetn Q

REGISTER: RIGHT SHIFT REGISTER: LEFT SHIFT REGISTER: resetn resetn resetn n n D D Q Q din din dout dout din din dout dout E E E E E clk clk

clk

1 2 3

0 1 2

- - -

n n n

Q Q Q

...... Q

Q Q Q

7 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

Parallel access shift register with enable . All the flip flops share the same enable input. Q3 Q2 Q1 Q0

resetn

D Q D Q D Q D Q

E E E E E

clk

0 1 0 1 0 1 0 1

din D3 s_l D2 D1 D0

clk

resetn

s_l

din

D 0000 1101 1001 1100

Q 0000 0000 1000 1100 0110 1011 1101 1101 0110 1101 0110 1100 0110 0011 1001 1100 0110 0011

ADDING A SYNCHRONOUS CLEAR INPUT TO FLIP FLOPS . In many instances, it is very useful to have a signal that can clear the value of the flip flop but only on the rising (or falling edges): synchronous clear (푠푐푙푟). Typically, all synchronous signals are validated by enable. For example, for a D flip flop, the table show how the output state 푄 changes (on the rising edge):

퐸 푠푐푙푟 푄 (output state) sclr 0 0 X 푄 ← 푄 D 0 D Q Q 1 0 푄 ← 퐷 1 1 1 1 푄 ← 0 0 E clk resetn

. We can thus create 푛-bit registers and 푛-bit shift registers with enable and 푠푐푙푟. Here, all the flip flops share the same enable and 푠푐푙푟 inputs.

din din din din D D Q Q dout dout dout dout E E E E E sclr sclr sclr sclr sclr clk clk

clk

3 1 2

- - -

0 1 2

n n n

...... n

Q Q Q

Q Q Q Q

8 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

SYNCHRONOUS COUNTERS . Counters are useful for: counting the number of occurrences of a certain event, generate time intervals for task control, track elapsed time between two events, etc. Counters are made of flip flops and combinatorial logic. Common design strategies include using the Finite State Machines (FSM) method or a synchronous accumulator. . Synchronous counters change their output on the clock edge (rising or falling). Each flip flop shares the same clock input signal. If the initial count is zero, each flip flop shares the 푟푒푠푒푡푛 input signal.

COUNTER CLASSIFICATION: a) Binary counter: An 푛 − 푏푖푡 counter counts from 0 to 2푛 − 1. The figure depicts a 2-bit counter.

resetn

D Q Q0 clk

resetn

D Q Q1 Q 00 00 01 10 11 00 01 10 11

clk

b) Modulus counter: A counter 푚표푑푢푙표 − 푁 counts from 0 to N-1. Special case: BCD (or decade) counter: Counts from 0 to 9. resetn clk Q 4 resetn

clk Q 0000 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001

BCD counter c) Up/down counter: Counts both up and down, under command of a control input. d) Parallel load counter: The count can be given an arbitrary value. e) Counter with enable: If enable = 0, the count stops. If enable = 1, the counter counts. This is usually done by connecting the enable inputs of the flip flops to a single enable. f) Ring counter: Also called one-hot counter (only one bit is 1 at a time). It can be constructed using a shift register. The output of the last stage is fed back to the input to the first stage, which creates a ring-like structure. The asynchronous signal startn sets the initial count to 100…000 (first bit set to 1). Example (4-bits): 1000, 0100, 0010, 0001, 1000, … The figure below depicts an 푛 − 푏푖푡 ring counter.

Qn-1 Qn-2 Qn-3 Q0

startn

D Q D Q D Q ... D Q

prn clk

g) Johnson counter: Also called twisted ring counter. It can be constructed using a shift register, where the 푄̅ output of the last flip flop is fed back to the first stage. The result is a counter where only a single bit has a different value for two consecutive counts. All the flip flops share the asynchronous signal ‘resetn’, which sets the initial count to 000…000. Example (4 bits): 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000, … The figure below depicts an 푛 − 푏푖푡 Johnson counter.

Qn-1 Qn-2 Qn-3 Q0

resetn

D Q D Q D Q ... D Q

clk

9 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

COUNTER DESIGN USING AN ACCUMULATOR: . The figure shows a counter modulo-200 that uses a register, and adder, a comparator, and logic gates. . 푄: count. 푧: output signal asserted only when the maximum count (199) is reached.

00000001 a7 8 8 b7

a6 b6 + a5 resetn 4 b5 a E 4 b E 11000111 4 sclr A=B sclr 8 a B 3 clock b3 a sclr: synchronous clear 8 = 199? 2 If E=sclr=1, then Q = 0 Q A b2 A=B a 1 b z 1 a 0 b0 RANDOM ACCESS MEMORY EMULATOR . The following sequential circuit represents a memory with 8 addresses, where each address holds a 4-bit data. The memory positions are implemented by 4-bit registers. The reset and clock signals are shared by all the registers. Data is written or read onto/from one of the registers (selected by the signal 푎푑푑푟푒푠푠).

. Writing onto memory (푤푟_푟푑 = 1): The 4-bit input data (D_in) is written into one of the 8 registers. The address signal selects which register is to be written. Here, the 7-segment display must show 0. For example: if address = “101”, then D_in is written into register 5.

. Reading from memory (푤푟_푟푑 = 0): The MUX output appears on the 7-segment display (hexadecimal value). The address signal selects the register from which data is read. For example: If address = “010”, then data in register 2 must appear on the 7-segment display. If data in register 2 is ‘1010’, then the symbol ‘A’ appears on the 7-segment display.

resetn wr_rd E 4 4 Din D 0 Q

D 1 Q clock E D 2 Q

E E 3 address D 3 Q Decoder 4 Decoder: HEX to 7

E MUX segments D 4 Q wr_rd E

E 7 D 5 Q 3

D 6 Q

E 4 D 7 Q

10 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

LINEAR FEEDBACK SHIFT REGISTERS (LFSRS) . LFSRs have a simple and fairly regular structure. Typical components: D-type flip flops, and logic gates. . Advantages: very little hardware and high speed operation. . Inputs to flip flops are linear functions of the previous state. . Despite the simple appearance, LFSRs are based on rather complex mathematical theory and have interesting applications in the area of digital system testing, cryptography, and fault-tolerant computing. . Typical applications: Error correction/detection, pseudo random number generators, fast counters. . A generic 4-bit LFSR is depicted below:

Q3 Q2 Q1 Q0 resetn

x D Q D Q D Q D Q

E E E E E

clk

LINEAR FUNCTION

APPLICATION: CYCLIC REDUNDANCY CHECK (CRC) . This error-detection code is used in digital communications (e.g.: Ethernet, CAN), and storage devices (e.g.: RAMs).

Communication system . 푘-bit message: 푀 = 푚푘−1푚푘−2 … 푚1푚0. . CRC code: 푅 = 푟푛−1푟푛−2 … 푟1푟0. . Stream sent: 푚푘−1푚푘−2 … 푚1푚0푟푛−1푟푛−2 … 푟1푟0

Transmitted bits CRC CRC error Generator Checker

. Associated polynomials: 푘−1 푘−2 1 0  푀(푥) = 푚푘−1푥 + 푚푘−2푥 + ⋯ + 푚1푥 + 푚0푥 . Order: 푘 − 1 푛−1 푛−2 1 0  푅(푥) = 푟푛−1푥 + 푟푛−2푥 + ⋯ + 푟1푥 + 푟0푥 . Order: 푛 − 1 푥푛푀(푥) . The CRC code is calculated as a remainder: 푅(푥) = 푟푒푚푎푖푛푑푒푟 ( ) 퐺(푥) 푛 푛−1 1 0 . 퐺(푥) = 푔푛푥 + 푔푛−1푥 + ⋯ + 푔1푥 + 푔0푥 . This is the generating polynomial of order 푛. 퐺 = 푔푛푔푛−1 … 푔1푔0

. Here, when dealing with polynomial operations, we use modulo-2 polynomial arithmetic (Galois field of two elements: GF(2)). The coefficients of the polynomials can only be 0 or 1. The multiplication operation can be implemented as a simple AND gate, and the addition (or subtraction) operation can be implemented by a XOR gate: 푎 ± 푏 = 푎푏, 푎 ∈ {0,1}.  Example: 푥푛 + 푥푛 = 푥푛 − 푥푛 = 0.

푛 . CRC generator: It computes 푅(푥). Its input is 푥 푀(푥) ≡ 푚푘−1푚푘−2 … 푚1푚000 … 0.

. CRC checker: On the receiver side, both the message and CRC code might be corrupted by the channel: 푀′(푥) and 푅′(푥). 푥푛푀′(푥)  So, we must check if 푟푒푚푎푖푛푑푒푟 ( ) = 푅′(푥). If so, we say that the system passed the CRC check. 퐺(푥)  Note that this implies: 푥푛푀′(푥) = 푄’(푥)퐺(푥) + 푅’(푥) → 푥푛푀′(푥) − 푅’(푥) = 푥푛푀′(푥) + 푅’(푥) = 푄’(푥)퐺(푥). In modulo-2 arithmetic, 푅′(푥) = −푅′(푥). It follows that 푥푛푀′(푥) + 푅’(푥) should be divisible by 퐺(푥). 푥푛푀′(푥)+푅′(푥)  The CRC checker tests if 푟푒푚푎푖푛푑푒푟 ( ) = 0. If the remainder is zero, we say that it passed the CRC check. It 퐺(푥) is still possible for 푅’(푥) and 푀’(푥) to make the remainder equal to zero but this is far less likely. 푛 ′ ′  The input to the CRC checker is 푥 푀 (푥) + 푅 (푥) ≡ 푚′푘−1푚′푘−2 … 푚′0푟′푛−1푟′푛−2 … 푟′0.

11 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

. Example: CRC-4 (푛 = 4): 푀 = 11100110, 퐺 = 11001 + + + 푀(푥) = 푥7 + 푥6 + 푥5 + 푥2 + 푥 → 푥푛푀(푥) = 푥4(푥7 + 푥6 + 푥5 + 푥2 + 푥) = 푥11 + 푥10 + 푥9 + 푥6 + 푥5 퐺(푥) = 푥4 + 푥3 + 1 푅(푥) = 푥2 + 푥

CRC circuit . The following LFSR implements 4-bit CRC. Components: flip flops, AND, XOR gates. . Note that 푔4 = 1 is not used. This is because it is common in CRC to have 푔푛 = 1. This is already considered in the design of the circuit. . Example with 푀 = 11100110, 퐺 = 11001:  When integrated into the CRC generator, the input is given by: 푥푛푀(푥) ≡ 111001100000. The output result is 푅 = 0110.  When integrated into the CRC checker, the input is given by: 푥푛푀′(푥) + 푅′(푥) ≡ 111001100110. The result of the circuit is 푟푒푚푎푖푛푑푒푟 = 0000, indicating a valid transmission.

R0 R1 R2 R3

resetn x D Q D Q D Q D Q E E E E E

clk

G0 G1 G2 G3

clk

resetn

R 0000 0000 0001 0011 0111 1110 0101 1011 1110 0101 1010 1101 0011 0110 0110 0110

clk

resetn

R 0000 0000 0001 0011 0111 1110 0101 1011 1110 0101 1010 1100 0000 0000 0000 0000

R0 . Applications: The circuit above can be implemented for any number of bits 푛. For resetn example: CRC-32 (Ethernet), CRC-15 (CAN), and CRC-1 (trivial even parity generator x with 퐺(푥) = 푥 + 1). D Q . This is a serial implementation, i.e., each bit is fed to the circuit at a time. Other E E implementation process some bits in parallel (for CRC-1, the parity generator in Notes clk – Unit 1 processes all the bits at once). . The design of the generating polynomial 퐺(푥) is outside the scope of this class. . These circuits are better implemented in hardware for high speed and low resource utilization. G0

12 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

FINITE STATE MACHINES:

. Sequential circuits are also called Finite State Machines (FSMs), because the functional behavior of these circuits can be represented using a finite number of states (flip flop outputs). . The signal 푟푒푠푒푡푛 sets the flip flops to an initial state. . Classification: - Moore machine: Outputs depend solely on the current state of the flip flops. - Mealy machine: Outputs depend on the current state of the flip flops as well as on the input to the circuit. Only for Mealy Machine

Inputs Outputs Combinatorial Flip n Q(states) Combinatorial Circuit Flops Circuit

clock

resetn

. Any general sequential circuit can be represented by the figure above (Finite State Machine model). . A sequential circuit with certain behavior and/or specification can be formally designed using the Finite State Machine method: drawing a State Diagram and coming up the Excitation Table. . Designing sequential circuits using Finite State Machines is a powerful method in Digital Logic Design.

Example: 2-bit gray-code counter with enable and ‘z’ output: 00, 01, 11, 10, 00, … The output ‘z’ is 1 when the present count is ‘10’. The count is the same as the states encoded in binary. . First step: Draw the State Diagram and State Table. If we were to implement the state machine in VHDL, this is the only step we need.

E/z E PRESENT NEXT NEXT resetn = 0 0/0 STATE STATE COUNT z 1/0 0/0 S1 S2 0 S1 S1 00 0 0 S2 S2 01 0 1/1 1/0 0/0 0 S3 S3 11 0 0 S4 1/0 S4 10 1 0/1 S4 S3 1 S1 S2 01 0 1 S2 S3 11 0 1 S3 S4 10 0 1 S4 S1 00 1

. Second step: State Assignment. We assign unique flip flop states to our state labels (S1, S2, S3, S4). Notice that this is arbitrary. However, we can save resources if we assign each state to the count that we desire. Then, the output ‘count’ is just the flip flops’ outputs.

 S1: Q = 00  S2: Q = 01  S3: Q = 11  S4: Q = 10

13 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

. Third step: Excitation table. Here, we replace the state labels by the flip flop states: PRESENT STATE NEXTSTATE

E Q1(t) Q0(t) Q1(t+1) Q0(t+1) z

0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 1 0 1 0 1

1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 0 1

. Fourth step: Excitation equations and minimization. 푄1(푡 + 1) and 푄0(푡 + 1) are the next state of the flip flops, i.e. these signals are to be connected to the inputs of the flip flops.

Q1(t+1) Q0(t+1) z EQ1 EQ1 EQ1 00 01 11 10 00 01 11 10 00 01 11 10 Q0 Q0 Q0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0

1 0 1 1 1 1 1 1 0 1 1 0 0 0 0

푄1(푡 + 1) = 퐸̅푄1 + 퐸푄0 푄0(푡 + 1) = 퐸푄̅̅1̅ + 퐸̅푄0 푧 = 푄1푄̅̅̅0̅ Output 푧 only depends on the present state. Outputs 푄1, 푄0 are the states and they only depend (in terms of the combinational output circuit) on the present state. Thus, this is a Moore FSM.

. Fifth step: Circuit implementation.

resetn clk clock

resetn D Q Q0

E E

state S1 S1 S2 S3 S3 S4 S4 S1 S2 S2 D Q Q1

Q 00 00 01 11 11 10 10 00 01 01

z z

Example: 2-bit counter with enable and ‘z’ output. The output ‘z’ is 1 when the present count is ‘11’. The count is the same as the states encoded in binary. . First step: Draw the State Diagram and State Table. If we were to implement the state machine in VHDL, this is the only step we need. E/z E PRESENT NEXT NEXT resetn = 0 0/0 STATE STATE COUNT z 1/0 0 S1 S1 00 0 0/0 S2 S1 0 S2 S2 01 0 0 S3 S3 10 0 1/1 1/0 0/0 0 S4 S4 11 1 1/0 1 S1 S2 01 0 S4 S3 0/1 1 S2 S3 10 0 1 S3 S4 11 0 1 S4 S1 00 1 14 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

 S1: Q = 00  S2: Q = 01  S3: Q = 10  S4: Q = 11

. Third step: Excitation table. Here, we replace the state labels by the flip flop states: PRESENT STATE NEXTSTATE

E Q1(t) Q0(t) Q1(t+1) Q0(t+1) z

0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 1 1 1

1 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1

. Fourth step: Excitation equations and minimization. 푄1(푡 + 1) and 푄0(푡 + 1) are the next state of the flip flops, i.e. these signals are to be connected to the inputs of the flip flops.

Q1(t+1) Q0(t+1) z EQ1 EQ1 EQ1 00 01 11 10 00 01 11 10 00 01 11 10 Q0 Q0 Q0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0

1 0 1 0 1 1 1 1 0 0 1 0 1 1 0

푄1(푡 + 1) = 푄1푄̅̅̅0̅ + 퐸̅푄1 + 퐸푄̅̅1̅푄0 푄0(푡 + 1) = 퐸푄̅̅̅0̅ + 퐸̅푄0 푧 = 푄1푄0 Output 푧 only depends on the present state. Outputs 푄1, 푄0 are the states and they only depend (in terms of the combinational output circuit) on the present state. Thus, this is a Moore FSM.

. Fifth step: Circuit implementation.

resetn clock clk

resetn E

D Q Q1

E z

state S1 S1 S2 S3 S3 S4 S4 S1 S2 S2

D Q Q0 Q 00 00 01 10 10 11 11 00 01 01

Note: In these 2-bit counters, the states are represented by the outputs of the flip flops: 푄1, 푄0. They also happen to be the outputs of the FSM. This is common in counters, as the count is usually the same as the flip flop outputs.

15 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

Example: BCD counter. Outputs: 푄(3. .0), 푧. When the count reaches 1001, 푧 becomes 1. Moore FSM

resetn = '0'

S1 S2 S3 S4 S5 Q=0,z=0 Q=1,z=0 Q=2,z=0 Q=3,z=0 Q=4,z=0

S10 S9 S8 S7 S6

Q=9,z=1 Q=8,z=0 Q=7,z=0 Q=6,z=0 Q=5,z=0

Example: FSM. Input: 푤. Output: 푧. This is a Moore FSM as 푧 only depends on the present state.

resetn = 0 w=1 w=0 w=0 w=0 w=0

S1 S2 w=1 S3 w=1 S4 w=0 S5 z=0 z=0 z=0 z=1 z=0 w=1 w=1 w=0 w=0 w=1 w=1

w=1 S9 w=1 S8 w=0 S7 w=0 S6 z=1 z=0 z=0 z=0

clk

rstn

state S1 S1 S2 S9 S8 S9 S1 S2 S3 S2 S3 S4 S5 S4 S3 S4

16 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

ALGORITHMIC STATE MACHINE (ASM) CHARTS: Sequence Detector (with overlap) Gray counter, z=1 when Q=10 010011

x/z E/z resetn = 0 0/0 resetn = 0 0/0 1/0 1/0 0/0 S1 S2 0/0 1/0 S1 S2 S3 1/1 1/0 0/0 1/0 1/1 0/0 0/0 1/0 1/0 S4 S3 0/1 S6 S5 S4 1/0 0/0

0/0

resetn=0 resetn=0 S1 S1

0 1 E x

1 0 S2 S2

0 0 E x

1 1 S3 S3

0 1 E x

1 0 S4 S4 z  1

1 0 1 E x 0 S5

0 x

1 S6

0 1 x z  1

17 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

EXAMPLE: ARBITER CIRCUIT

. Three devices can request access to a certain resource at any time (example: access to a bus made of tri-state buffers, only one tri-state buffer can be enabled at a time). The FSM can only grant access to one device at a time.There should be a priority level among devices. . If the FSM grants access to one device, one must wait until the request signal to that device is deasserted (i.e. set to zero) before granting access to a different device.

req1 DEVICE 1 priority

grant1 resetn req2 DEVICE 2

g1 r1 r2 FINITE STATE g2 r3 MACHINE g3 grant2 clock

CONTROL CIRCUIT

req3 DEVICE 3

grant3

. Algorithmic State Machine (ASM) chart:

resetn=0 S1 g1,g2,g3  0

0 0 0 r1 r2 r3

1 1 1 S2 S3 S4 g1  1 g2  1 g3  1

0 1 1 1 r1 r2 r3

0 0

18 Instructor: Daniel Llamocca ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Computer Hardware Design Winter 2017

Reducing rate of change of a synchronous circuit:

. Here, we use FSM as an example of a synchronous circuit. But we can apply this technique to any synchronous circuit.

. We usually would like to reduce the rate at which FSM transitions occur. A straightforward option is to reduce the frequency of the input clock. But this is a very complicated problem when a high precision clock is required.

. Alternatively, we can reduce the rate at which FSM transitions occur by including an enable signal in our FSM: this means including an enable to every flip flop in the FSM. For any FSM transition to occur, the enable signal has to be ‘1’. Then we assert the enable signal only when we need it. The effect is the same as reducing the frequency of the input clock.

 The figure below depicts a counter modulo-N (from 0 to N-1) connected to a comparator that generates a pulse (output signal ‘z’) of one clock period every time we hit the count ‘N-1’. The number of bits the counter is given by 푛 = ⌈log2 푁⌉. The effect is the same as reducing the frequency of the FSM to 푓⁄푁, where 푓 is the frequency of the clock.

 A modulo-N counter is better designed using VHDL behavioral description, where the count is increased by 1 every clock cycle and ‘z’ is generated by comparing the count to ‘N-1’. A modulo-N counter could be designed by the State Machine method, but this can be very cumbersome if N is a large number. For example, if N = 1000, we need 1000 states.

resetn

E Outputs Inputs FSM

E E Q n

comparator z

Q=N-1? counter 0 to N-1 clock

 As an example, we provide the timing diagram of the counter from 0 to N-1, when N=10. Notice that ‘z’ is only activated when the count reaches “1001”. This ‘z’ signal controls the enable of a state machine, so that the FSM transitions only occur every 10 clock cycles, thereby having the same effect as reducing the frequency by 10.

clk

resetn

Q 0000 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001

. We can apply the same technique not only to FSMs, but also to any sequential circuit. This way, we can reduce the rate of any sequential circuit (e.g. another counter) by including an enable signal of every flip flop in the circuit.

Flip flop timing parameters: . Propagation Delay. . Setup Time: Interval of time before the clock edge where the data must be resetn clk held stable. . Hold Time: Interval of time after the D D Q Q clock where the data must be held D stable. clk . If setup time or hold time are violated, Q the output may become unpredictable, or even worse it might enter into restricted metastability. region

19 Instructor: Daniel Llamocca