FPGA/CPLD CONVERSION S ERVICE ULC

C OST S AVINGS

WITH N O R ISK P LUG AND S AVE

COST REDUCTION In today's market, cost reduction is a must to Equivalent complexity, much smaller MADE EASY maintain competitiveness. New products FPGA, 252 mm² need to be designed fast, before the compe- tition catches up. FPGA/CPLD usage pro- vides early feedback to designers. This allows them to tune the application prior to production. FPGAs provide a flexible combi- nation between the quick design cycle and pre-production phases. For any specific design, the customer may be paying for FPGA resources that are not ULC, 104 mm² used. Programming and associated PROM

costs remain. As soon as the customer’s engineering resources. Atmel’s innovative design is frozen, cost and manufacturability design flow, based on Verify-before-silicon become the important criteria. This is where techniques, allows Atmel to deliver in-system

the Atmel® conversion service helps pur- guaranteed parts. There is no financial obliga- chasing and engineering. Ultimate Logic tion if the ULC does not work in the customer’s

Conversion (ULC) offers a pin-to-pin, drop-in application (sign-off required for 0.18 µm technologies). replacement for the customer’s FPGA, gen- Atmel guarantees a working ULC. erating immediate cost

savings. With more than 19 years experience and Atmel does the work. 1,900 successful conversions, Atmel has the FPGAs can be converted proven ability to convert FPGAs to help with minimum involve- maximize cost reduction. ment of the customer’s

Cost Reduction FPGA replacement, immediate cost savings with no risk

Easy Minimum customer engineering involvement

In-system Guarantee Verify-before-silicon technique*

Risk-Free Charged only if parts work

* for 0.35 µm technologies ULC SAVE A PPLICATION S PACE

On an FPGA device, programming resources removed thereby saving cost. The customer has SAVE SPACE use up to 50% of the total silicon area! With the possibility to use smaller packages to save AND SAVE COST Atmel ULCs, these programming resources are board space and additional cost.

FPGA (®, ®...) Replacement

Set Top Box

We deliver the cost savings

High-end Modem that your application demands!

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Automotive ULC T ECHNOLOGIES

ULC Road Map

WORLD CLASS The extended range of design and manufacturing capability available within Atmel offers cost-effective

TECHNOLOGY solutions for the future.

Complexity Kgates & I/O’s 3000 K ASIC gates 700 I/O’s 1500 K ASIC gates* 1.2V - 0.13µm 700 I/O’s 6 metal layers 1.8V - 0.18 µm I/O: 1.8V 5 Metal Layers 2500 Kbits DPRAM 780 K ASIC gates* I/O: 1.8V/3.3V 700 I/O’s Up to 1195 Kbits DPRAM 2.5V/3.3V - 0.35 µm 4 Metal Layers 1400 K ASIC gates* I/O: 3.3V/5V 700 I/O’s Up to 390 Kbits DPRAM 2.5V/3.3V - 0.35 µm 3 Metal Layers 80 µm I/O buffer pitch I/O: 3.3V/5V

Note: 1 ASIC gate = 4 FPGA gates

1999 2001 2005 2007

Memory Blocks Supported Special IO’s Supported

All Altera® and Xilinx® DPRAM blocks CMOS, TTL, LVCMOS, LVTTL, PECL, and others (Actel®, Quicklogic®, etc.) PCI (33/66 MHz) levels, GTL/GTL+, HSTL, 0.35 µm: up to 390 Kbits DPRAM SSTL2, SSTL3, CCT, AGP, LVDS. and 780 K array gates. 0.18 µm: up to 1195 Kbits DPRAM Power Supply and 1500 K array gates. 0.13 µm: up to 2500 Kbits DPRAM IOs Core and 3000 K array gates. 0.5 µm 3.3, 5V 3.3 ou 5V

0.35 µm 3.3, 5V 2.5 ou 3.3V PLL/DLL

100% compatible with Altera and Xilinx. 0.18 µm 1.8, 2.5, 3.3V 1.5 or 1.8V

Power Consumption Extensive Packaging Capabilities

ULC static consumption is about 70% less than Latest fine pitch BGA (1.0 mm) compatible with Virtex®, APEX™ series. Xilinx and Altera. ULC dynamic consumption is about 30% less Pin Count: from 100 up to 1156. than Virtex, APEX series. Body Size: from 11 x 11 up to 35 x 35. CQFP, PQFP, TQFP, VQFP, JLCC, PLCC, PBGA, Frequency SOIC, TSOP, PDIP, Chip Scale, etc.

0.18 µm, 200 MHz system clock, local clock Lead and Halogen Free, Green following JEDEC speed 350 MHz. standards ULC CONVERSION S ERVICE

Feasibility Study Flow ATMEL DOES THE WORK Atmel performs a feasibility study on every design before the final conversion and verification work is started. This allows Atmel to confirm the die size, package and conversion lead-time, and also discuss any technical issues with the customer. For the feasibility study, Atmel requires:

O Preferred code RTL synthetisable O Circuit pinout

O Test bench O ULC checklist completed

FPGA Netlist Customer Pinout

Retarget/Optimization ULC Checklist (timing, power) Atmel Bonding Diagram

Synthesis (Leonardo®, ®, etc.)

Atmel Netlist

Pre-Layout Design Rule Check Functional Simulations ATPG ModelSim® (Mentor®) DFT Advisor (Mentor)

Conversion Flow

After receiving the initial purchase order, the ULC design team proceeds with conversion and verification of the programmable logic device to a ULC.

Atmel Netlist Formal Proof Scan, JTAG Insertion

Physical Synthesis Adjust timing including clock tree

GateEnsemble® (Cadence®)

Atmel Netlist + Delays

Static Timing Analysis Power Analysis Functional Simulations Prime Time® (Synopsys) ModelSim (Mentor)

Functional and Timing Comparison

Tester ( Nextest Maverick®)

First Article Delivery

ULCs are manufactured and prototypes are delivered for validation on the application. After customer approval, full production is started. Pre-production parts are available upon request. ULC S UPPORT

CUSTOMER Conversion Centers Near Customers SATISFACTION USA: San Jose - CA Europe: Nantes - France Eching - Germany Camberley - UK Milan - Italy Asia Pacific: Nantes - France

Optional Improvements:

O Multiple FPGAs merge in a single ULC

O Stack Die Capability: Atmel can house any external memory used along with any FPGA or ASIC into a single ULC package.

O ASIC obsolescence replacement

O JTAG insertion

Die Stacking Technology Customer Service

Dedicated to ULC Product Line

O Close customer interface and support O Delivery Plan Agreement and Consignment

O 98% First Pass Success on conversions done stock available for Key Accounts since 1998

Field Application Support

Dedicated ULC engineers are available to interface with customers on technical issues.

Quality and Test

O 100% of Atmel parts are tested

O Optimized fault coverage

O Quality and reliability monitoring

Obsolete ASICs

Atmel also converts ASICs into ULCs with similar conditions for customers who want to develop a second source or avoid process obsolescence with their current ASIC vendor. FPGA/CPLD S UPPORTED

FPGA CPLD VISIT US AT Altera FLEX®10K Cyclone™ MAX®7000/A/B/S MAX5000 WWW.ATMEL.COM FLEX6000 Cyclone™ II MAX9000 MAX3000/A FLEX8000 APEXII ® APEX20K

Stratix® II APEX20KC

ACEX® 1K Xilinx XC4000E/EX/XL/XV/XLA XC9500 XC9500XV/XL XC3000 XC7000 XC5200 CoolRunner® XPLA2/XPLA3 Spartan® & Spartan XL CoolRunnerII SpartanII, SpartanIIE & SpartanIIIE CoolRunnerIIA Virtex, VirtexE, Virtex 4 & VirtexII Actel SX & SX-A MX Series eX & AX ProASIC ProASIC3 ProASIC3E Lattice® Lattice ECP ispXPLD Lattice EC ispLSI Lattice XP ispMACH5000 ISP XPGA ipsMACH4000 ORCA ipsMACH4A QuickLogic pASIC1/2/3 Eclipse Eclipse Plus QuickRAM Cypress® Flash370 Ultra37000 Quantum 38k MAX340 Delta39K SPLD

New FPGA/CPLDs are continually being intro- Xilinx 45% Altera 45% duced by programmable logic vendors. Others 1%

If the device or version of the device you are inter- Lattice 3% ested in converting is not listed above, contact Actel 6% your local Atmel sales representative or sales office.

Percentage of the 1,900 successful conversions per FPGA/CPLD vendors. Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA TEL.: 1 (408) 441-0311 FAX.: 1 (408) 487-2600

Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL.: (41) 26-426-5555 FAX.: (41) 26-426-5500

Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong TEL.: (852) 2721-9778 FAX.: (852) 2722-1369

Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL.: (81) 3-3523-3551 FAX.: (81) 3-3523-7581

Product Contact La Chantrerie BP 70602 44306 Nantes Cedex 3 France TEL.: (33) 2 40 18 18 18 FAX.: (33) 2 40 18 19 60

Web Site http://www.atmel.com

Literature Requests www.atmel.com/literature

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