University of California s19

UNIVERSITY OF CALIFORNIA

College of Engineering

Department of Electrical Engineering and Computer Sciences

Last modified on October 29, 2002 by Leland Chang ()

Borivoje Nikolic Homework #8 EECS 141

Due Tuesday, November 5th, 5pm @ 275 Cory

Problem 1 – Conditional Sum Adder

Here is a neat adder structure called the conditional sum adder. Shown below is a 4-bit version of the circuit. Note that in the diagram, multiplexors are represented by switch-controlled arrows.

Using a pass-transistor implementation, the circuit schematic for each adder cell can be:

a)  Derive Boolean equations for the four outputs of the one-bit conditional adder cell

b)  Based on your results to part a), describe how the 4-bit adder works.

c)  Derive an expression for the propagation delay of the adder as a function of the number of Bits, N. Assume that the delay through each conditional cell is tcell and that the delay of a MUX is tMUX.

Problem 2 – Variable-Block Carry-Skip Adder

The carry-skip adder is a pretty good circuit. However, upon closer inspection, you notice that if all the skip blocks are of the same size, the latter blocks will finish switching quickly and then sit idle for a while waiting for the carry signal to pass through all the bypass multiplexors. For example, in the diagram of a 32-bit carry-skip adder below, bits the carry-out for bits 4-7 will be ready at the same time as the carry-out for bits 0-3. This second block will sit around doing nothing while MUX1 does its job.

To speed up the circuit, we could vary the size of the skip block. Intuitively, we should then be able to reduce the size of the first skip block and make each subsequent block increasingly larger. Because the critical path includes the last skip block, we must also start to taper down the size of each block as we approach the end. To obtain the optimal size of all the skip blocks, you realize that some really smart guy has already done all the mathematical derivations…which means that you don’t have to do it yourself. After talking to this really smart guy, you know that the optimal configuration for a 32-bit adder is (under the assumption that tMUX = 2tprop):

Estimate the worst-case delay for the simple 32-bit carry-skip adder in the first diagram and then estimate the amount of delay improvement with this new variable-block scheme. Assume that the setup (creation of propagate and generate signals) takes tsetup, each bit of carry propagation takes tprop (i.e. a skip block of m bits has a delay of m*tprop), a MUX has a delay of tMUX, and the sum generation has a delay of tsum. Leave your answers in terms of tsetup, tprop, tMUX, and tsum.