2778 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 8, AUGUST 2016 Noise Coupling Models in Heterogeneous 3-D ICs Boris Vaisband, Student Member, IEEE, and Eby G. Friedman, Fellow, IEEE Abstract— Models of coupling noise from an aggressor module to a victim module by way of through silicon vias (TSVs) within heterogeneous 3-D integrated circuits (ICs) are presented in this paper. Existing TSV models are enhanced for different substrate materials within heterogeneous 3-D ICs. Each model is adapted to each substrate material according to the local noise coupling characteristics. The 3-D noise coupling system is evaluated for isolation efficiency over frequencies of up to 100 GHz. Isolation improvement techniques, such as reducing the ground network inductance and increasing the distance between the aggressor and victim modules, are quantified in terms of noise improvements. A maximum improvement of 73.5 dB for different ground network impedances and a difference of 38.5 dB in isolation efficiency for greater separation between the aggressor and victim modules are demonstrated. Compact, accurate, and computationally efficient models are extracted from the transfer function for each of the heterogeneous substrate materials. The reduced transfer functions are used to explore different manufacturing and design parameters to evaluate coupling noise across multiple 3-D planes. Index Terms— 3-D integrated circuit (IC), heterogeneous 3-D system, noise coupling, substrate coupling, through silicon via (TSV) noise coupling model. Fig. 1. Heterogeneous 3-D IC. I. INTRODUCTION OISE coupling is of increasing importance within the TABLE I integrated circuits (ICs) community [1]–[6]. This issue N COMMON CIRCUITS AND COMPATIBLE SUBSTRATE TYPES is of fundamental concern in 3-D circuits, where signals are distributed among multiple different layers using through silicon vias (TSVs), creating an electronic storm within the 3-D system. Different types of signals (power, clock, and data) can propagate within these vertical interconnects. Different TSV processes are used in 3-D integration, including via-first, via-middle, and via-last [7]. In each of these processes, the TSV penetrates the substrate of a layer and connects to either the first or last metal within that layer. TSVs, a seminal component of 3-D technology, are short vertical intercon- nections (e.g., 20 μm in length and 2 μm in diameter [8]) between the different layers that can alleviate global signaling substrate of each layer. This noise propagates through the issues [9]. The TSVs, however, also pose novel obstacles. substrate and affects the victim circuits surrounding a TSV. In particular, the noise is coupled through the TSV into the Modern applications employ diverse functionalities. Mobile devices are capable of sensing light, capturing images and Manuscript received May 7, 2015; revised September 9, 2015, November 30, 2015, and February 10, 2016; accepted February 18, 2016. videos, high-performance processing, storing large amounts of Date of publication March 15, 2016; date of current version July 22, 2016. data, and much more. A 3-D structure is an effective platform This work was supported in part by the Binational Science Foundation for integrating these heterogeneous circuits within a single under Grant 2012139, in part by the National Science Foundation under Grant CCF-1329374, in part by the Intelligence Advanced Research Projects system, as shown in Fig. 1. Each layer of a 3-D IC is typically Activity under Grant W911NF-14-C-0089, and in part by Grants from Cisco independently optimized and often designed using different Systems and Intel. The associate editor coordinating the review of this substrate materials for different applications. Common circuits manuscript and approving it for publication was Prof. Ibrahim M. Elfadel. The authors are with the Department of Electrical and Computer Engi- and compatible substrate materials are listed in Table I. The neering, University of Rochester, Rochester, NY 14627 USA (e-mail: electrical resistivity and the thermal conductivity of each [email protected]; [email protected]). substrate material are also listed. Some commonly used mate- Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. rials in modern ICs are silicon (Si), gallium arsenide (GaAs), Digital Object Identifier 10.1109/TVLSI.2016.2535370 germanium (Ge), and mercury cadmium (MerCad) 1063-8210 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. VAISBAND AND FRIEDMAN: NOISE COUPLING MODELS IN HETEROGENEOUS 3-D ICs 2779 TABLE II COMPARISON OF LUMPED,DISTRIBUTED, AND SHORT-CIRCUIT MODELS FOR Si, GaAs, AND Ge SUBSTRATES FOR DIFFERENT VALUES OF INDUCTANCE OF THE GROUND NETWORK telluride (HgCdTe) [10]–[12]. Noise coupling from the TSVs into the victim layers for these common substrates is discussed here. Previous work has addressed noise coupling from TSVs into the substrate in homogeneous circuits (processor/memory stacks), typically on a silicon substrate [13], [14]. The purpose of this paper is to provide noise coupling models for heterogeneous 3-D systems composed of different substrate materials. It is suggested here to change the acronym TSV from TSV to through-substrate-via, since the substrate penetrated by the vertical interconnect in a heterogeneous 3-D system can be composed of different types of materials. A similar example is Fig. 2. Noise coupling from a TSV to a victim through a silicon substrate the acronym MOS that stands for metal–oxide–semiconductor as (a) previously proposed in [13], and (b) proposed in this paper. and not for metal–oxide–silicon. The rest of this paper is organized as follows. Through- The number of distributed sections of the TSV is Ntsv,the substrate-via models are proposed in Section II. A frequency resistivity of the conductive material within the TSV is ρc,and analysis of the isolation efficiency and isolation improvement the depth (length) and the diameter of the TSV are D and W, techniques, as well as extraction of the transfer function respectively. With a copper resistivity of 2.8 μ · cm [17], of the noise coupling system, are discussed in Section III. a depth of 20 μm, and a diameter of 2 μm [8], a resistance Design methods to lower coupling noise between layers are of 0.18 for (1/Ntsv) = 1 is produced. This resistance is provided in Section IV. Finally, some conclusions are drawn relatively small as compared with the resistance of a typical in Section V. digital buffer [18]. It is proposed, therefore, to use a lumped RC model for the TSV [1], [19], as shown in Fig. 2(b). II. THROUGH-SUBSTRATE-VIA MODELS Another important aspect is the model of the ground network. Existing models for noise coupling from TSVs to victim The victim device is commonly connected to the ground circuits in 3-D ICs [13]–[15] have to date only addressed network through the bulk contact; the inductive behavior of homogeneous systems. In these models, the layers are exclu- this network, therefore, also has to be considered. sively silicon, including dual-well bulk CMOS and partially A comparison of a lumped model versus a distributed model depleted silicon-on-insulator [14]. The noise coupling model with three sections is listed in Table II for Si, GaAs, and Ge. proposed in [13] is shown in Fig. 2(a). A distributed RC model For Ge, a third short-circuit model [shown in Fig. 3(a)] is also composed of four sections is used to characterize the compared. This model completely omits the resistors of the TSV impedance and capacitive coupling into the silicon substrate, since the resistance of the substrate is negligible and substrate. The substrate is modeled using distributed lateral the model, therefore, only exhibits a coupling capacitance from and vertical resistors. The ground network is modeled as a the TSV to the substrate [19]. The models have been evaluated resistive–inductive impedance [16]. using SPICE. A 10-ps input ramp from 0 to 1 V (Vpulse) is Silicon is the most common substrate material for ICs and applied to simulate switching the aggressive digital circuits. is used for many applications. The model shown in Fig. 2(a) The voltage is evaluated at the victim device node. Both the suggests the use of a distributed model for the RC impedances. peak noise voltage and the settling time (2% of the final value) The resistance of a TSV, based on the following expres- have been recorded for three different inductance values of the sion [13], is ground network. Note that unlike coupling between adjacent 1 ρ D R = · c . interconnects where the analysis of the propagating waves is tsv 2 (1) Ntsv π(W/2) required [6], in this paper, coupling from a signal propagating 2780 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 8, AUGUST 2016 The analysis is limited to frequencies of up to 100 GHz to maintain a near field coupling mode. Noise isolation improve- ment techniques are also suggested. The model is simulated in SPICE, and the transfer function of the system is extracted based on the characteristics of each substrate material. In Section IV, the extracted transfer functions are simulated in MATLAB and compared with SPICE. Note that due to similar electrical properties of HgCdTe and Si, only Si, GaAs, and Ge as the substrate materials are considered. A. Isolation Efficiency of Noise Coupled System Fig. 3. Noise coupling from a TSV to a victim through (a) short-circuit Ge substrate model, and (b) open-circuit GaAs substrate model. Isolation efficiency is the magnitude of the signal observed at the victim for a 1 V aggressor signal (in decibel). The within an aggressor TSV to the substrate is described.