Implementation of Space Vector Pulse Width Modulation on System on Programmable Chip by Vincent Luong A project presented to Ryerson University in a requirement for the degree of Master of Engineering in the Electrical and Computer Engineering program Toronto, Ontario, Canada, 2010 I PROPfiflr.Y Of RYER~O;~ UNWil1SlTY LfBRAlrl Declaration I hereby declare that I am the sole author ofthis thesis report. I authorize Ryerson University to make copies ofthis thesis by any means, in whole or in part, for the purpose of scholarly research. Signature: II Acknowledgements I would like to express my sincere gratitude to my supervisor Professor Richard Cheung for his guidance. His tremendous patient and constant encouragement has helped me accomplishing what I thought to be beyond my ability. I am grateful to my wife and sons for their love and support. Because of my study, many weekend activities were cancelled. I give thanks to my Lord Jesus for everything I have. To Him all glory belongs! III Abstract For years, DSP has been the dominant tool in implementing gate switching for power inverter. It is a powerful and reliable technology in carrying out complex switching schemes. DSP is still expensive due to its intensive use of resource in chip fabrication. There is no flexibility in making change on hardware once a DSP chip is selected. It is also time consuming in a design development because the learning curve of the DSP is stiff. Recently, a new approach to the problem has emerged. It is called embedded system design. Basically, it is a FPGA system combined with a RISC type microprocessor. This is a robust combination that allows users to pick and choose any functional peripheral devices only as needed. Once the complete hardware platform is decided upon, the circuit is configured and down loaded to a chip. Software codes are then written to run the application. The hardware system is reconfigurable. Designers can always go back to change the hardware with ease in order to improve the performance and to meet the target cost. This is an attempt to utilize the embedded system design also called System on Programmable Chip (SOPC) to perform Space Vector Modulation (SVM) gate switching strategy. The Altera Nios II IDE tool is selected for this task. IV Table of Content Chapter I Introduction .......................................................................... 1 1.1 Objective .............................................................................. .1 1.2 Background ............................................................................. 1 1.3 Methodologies .........................................................................4 1.4 ProposaL ................................................................................ 6 Chapter II Principal of Space Vector Modulation ........................................8 2.1 Switching State ........................................................................ 9 2.2 Space Vector ........................................................................... 10 2.3 Dwell Time Calculation ............................................................. 13 2.4 Modulation Index ..................................................................... 15 2.5 Switching Sequence .................................................................. .16 Chapter III SVP~ Matlab Simulation ................................................... 20 3.1 Specification .......................................................................... 20 3.2 Simulating Scheme .................................................................. 21 3.3 Result ................................................................................... 21 3.4 Observation ........................................................................... 27 Chapter IV SVPWM Realization by SOPC •••••.••••••••••.••••••••••••••••••••••••••••.•• 28 4.1 Target Board .......................................................................... 28 4.2 Embedded Processor ..................................................................29 4.3 System Development Flow .......................................................... 30 4}.1 Hardware Development Tasks ..........................................32 4.3.2 Software Development Tasks ...........................................34 4.3.3 Refining Hardware and Software ..................................... 35 4.4 Creating The Design ................................................................. 35 4.5 Design Result ......................................................................... 52 4.6 Future Work: Multiple Processors System ............................................. 54 Chapter V Conclusion ...........................................................................57 Appendix A Matlab Simulink Block Diagram ............................................59 Appendix B Software Codes in C Programming Language............................. 62 References ..........................................................................................71 V Lists of Figures Figure 2-1 Simplified Schematic of an Inverter .......................................... 8 Figure 2.1-1 Switching State Definition ................................................... 9 Figure 2.1-2 All Switching State Combination ............................................ 10 Figure 2.2-1 Space Vector Diagram ........................................................ 11 Figure 2.3-1 Dwell Time and Voltage Vectors ........................................... 14 Figure 2.5-1 Switching Sequence in Sector I ............................................. 17 Figure 2.5-2 Switching Sequence in All Six Sectors .................................... 18 Figure 3.2-1 Simulation Logic Flow .......................................................20 Figure 3.3-1 Simulation output at f=60Hz, fsw=900Hz, tIla=0.7 ....................... 21 Figure 3.3-2 Simulation output at f=60Hz, fsw=900Hz, tIla=O.5 ....................... 22 Figure 3.3-3 Simulation output at f=60Hz, fsw=900Hz, tIla=O.2 ....................... 23 Figure 3.3-4 Simulation output at f=30Hz, fsw=900Hz, tIla=0.9 ....................... 24 Figure 3.3-5 Simulation output at f=10Hz, fsw=900Hz, tIla=0.9 ....................... 25 Figure 3.3-1 Table of Simulation output and Its Load Current THD ..................26 Figure 4.1-1 Target Board ...................................................................28 Figure 4.3-1 Embedded System Design Flow ........................................... .30 Figure 4.3.1-1 Preliminary Design Block .................................................32 Figure 4.3.2-1 Software Algorithm ....................................................... .33 Figure 4.4-1 SOPC Builder GUI ........................................................... 35 Figure 4.4-2 On-chip Memory MegaWizard ............................................ .36 Figure 4.4-3 NIOS II Processor Core GUI ............................................... 37 Figure 4.4-4 Floating Point GUI .............................................. ;............. .38 Figure 4.4-5 Serial Communication GUI ................................................ 38 Figure 4.4-7 Interval Timer MegaWizard ...............................................39 Figure 4.4-8 PIO MegaWizard ............................................................40 Figure 4.4-9 System ID Peripheral Interface Box ..................................... .41 Figure 4.4-10 Content of Complete System ............................................ .42 Figure 4.4.5-1 System Module .............................................................43 Figure 4.4.5-2 FPGA Pin Assignment MegaWizard .................................. .43 Figure 4.4.7-1 Software Main Flow Chart .............................................. .44 Figure 4.4.7-2 Flow Chart of Some Subroutines ....................................... .45 Figure 4.4.7-3 Overview of Switching Pattern, Timing Sequence and Interrupt Timers ...................................................................................................................... 48 Figure 4.5-1 Waveforms of Software Simulation and Hardware Output ............ 52 Figure 4.5-2 Matlab Simulation Waveforms ............................................ 53 Figure 4.6-1 Multiple Processors in Open Loop Control System .................... 55 VI VII VIII Chapter I Introduction 1.1 Objective The focus ofthis report is on the implementation of space vector modulation for induction load or motor using System on Programmable Chip (SOPC) method. The advantages of the induction motor over the DC motor will mentioned, two main pulse width modulation schemes will be discussed, different ways to apply the scheme will be examined before heading to the proposal. 1.2 Back Ground The fIrst induction motor was invented by Nicola Tesla in 1888. To this day, it still remains the most rugged, reliable, less expensive to build and the least maintenance required machine. In comparison with a DC motor, the DC one relies on built in permanent magnets for flux generation in order for the machine to run. The induction motor produces its flux through the supply voltages. Hence, the induction machine is lighter in term ofweigh and output power ratio. In addition, the rotor ofthe DC machine brings about a turning force as the current carrying conductor is placed inside the magnetic fIeld. This conductor is connected to the power source through some kind brushing mechanism. Over times, this connector gets corroded due to wear and tear that affects the performance of the motor.